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authorStefan Reinauer <stepan@coresystems.de>2010-10-01 12:24:57 +0000
committerStefan Reinauer <stepan@openbios.org>2010-10-01 12:24:57 +0000
commitf11b81d18d36ecf732452a861d79ecd75f380adc (patch)
tree6918c9bbf9a4ee4b3cf470b243c2e2ebdb848603 /src
parent6c05bf411456a4166be9ad7d1775f5a3aa37ef9a (diff)
fix VIA C7 code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/via/car/cache_as_ram.inc6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 6389a3833f..6bd2c0f393 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -100,7 +100,8 @@ clear_fixed_var_mtrr_out:
*/
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
@@ -243,7 +244,8 @@ testok:
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
movl $MTRRphysBase_MSR(3), %ecx
xorl %edx, %edx
- movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(3), %ecx