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authorAaron Durbin <adurbin@chromium.org>2020-06-18 14:45:55 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-06-22 12:02:04 +0000
commitd9196d0696d3918f98870d0ba419f9d50e71c902 (patch)
tree484d6f1c386e657da171adf86722c3adaac93621 /src
parentae758fa41d887337dbdefbbe0be69053891386c0 (diff)
soc/amd/picasso: don't increment boot count twice
The FSP-M path increments the boot count already. Therefore, remove the double increment. BUG=b:159359278 Change-Id: I96cabce58d7114f708cad157600f0ccd3aa8a536 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42546 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/picasso/romstage.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 83243d386d..ce8ab5da04 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -81,7 +81,6 @@ asmlinkage void car_stage_entry(void)
post_code(0x41);
s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
mainboard_romstage_entry_s3(s3_resume);
- elog_boot_notify(s3_resume);
post_code(0x42);
u32 val = cpuid_eax(1);