diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-05 18:45:22 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-09 23:10:40 +0200 |
| commit | c9bf8bfabfeb75500ea0f3b4a0bfb5ce5485ae23 (patch) | |
| tree | 6560caaf5b51b7542473a8c86bf3217d3c6d4e52 /src | |
| parent | 9048384defbe752e03c4e2b9cc995820c60d0cd2 (diff) | |
util/checklist: Add bootblock support
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK
selected.
TEST=Build and run with Galileo Gen2
Change-Id: I922f761c31e95efde0975d8572c47084b91b2879
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15130
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat | 77 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat | 6 |
2 files changed, 11 insertions, 72 deletions
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat index 8a4325f4e0..4055a3c6c1 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -1,77 +1,10 @@ -arch_segment_loaded -backup_top_of_ram +bootblock_c_entry bootblock_mainboard_early_init bootblock_mainboard_init +bootblock_main_with_timestamp +bootblock_pre_c_entry +bootblock_protected_mode_entry bootblock_soc_early_init bootblock_soc_init -boot_device_init -car_mainboard_post_console_init -car_mainboard_pre_console_init -car_soc_post_console_init -car_soc_pre_console_init -cbfs_master_header_locator -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -fill_power_state -fw_cfg_acpi_tables -get_sw_write_protect_state -get_top_of_ram -gpio_acpi_path -init_timer -lb_board -lb_framebuffer -mainboard_add_dimm_info -mainboard_check_ec_image -mainboard_io_trap_handler -mainboard_memory_init_params -mainboard_post -mainboard_romstage_entry -mainboard_save_dimm_info -mainboard_silicon_init_params -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -mainboard_suspend_resume -map_oprom_vendev -mirror_payload -mrc_cache_get_current -mrc_cache_stash_data -northbridge_smi_handler -nvm_mmio_to_flash_offset -platform_prog_run -platform_segment_loaded -raminit -ramstage_cache_invalid -report_memory_config -save_chromeos_gpios -setup_stack_and_mtrrs -smbios_mainboard_bios_version -smbios_mainboard_manufacturer -smbios_mainboard_product_name -smbios_mainboard_serial_number -smbios_mainboard_set_uuid -smbios_mainboard_version -smm_disable_busmaster -soc_after_ram_init -soc_after_silicon_init -soc_display_memory_init_params -soc_display_silicon_init_params -soc_fill_acpi_wake -soc_memory_init_params -soc_pre_ram_init -soc_silicon_init_params -soc_skip_ucode_update -southbridge_smi_handler -stage_cache_add -stage_cache_load_stage -timestamp_get -timestamp_tick_freq_mhz tsc_freq_mhz -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -vboot_platform_prepare_reboot -verstage_mainboard_init -wifi_regulatory_domain -write_smp_table +uart_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat new file mode 100644 index 0000000000..fc0e872fd9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat @@ -0,0 +1,6 @@ +bootblock_c_entry +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +uart_init |