coreboot t132: Enable loading of romstage from CBFS media

Add proper Kconfig options and initialize cbfs media to enable loading of
romstage

BUG=None
BRANCH=None
TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer
for romstage

Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205762
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78
Reviewed-on: http://review.coreboot.org/8572
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

4 files changed, 42 insertions, 2 deletions

diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 5f7ae163d0..b3dd3de3f7 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -56,4 +56,20 @@ config RUSH_BCT_CFG_EMMC
 
 endchoice
 
+config BOOT_MEDIA_SPI_BUS
+	int "SPI bus with boot media ROM"
+	range 1 6
+	depends on RUSH_BCT_CFG_SPI
+	default 4
+	help
+	  Which SPI bus the boot media is connected to.
+
+config BOOT_MEDIA_SPI_CHIP_SELECT
+	int "Chip select for SPI boot media"
+	range 0 3
+	depends on RUSH_BCT_CFG_SPI
+	default 0
+	help
+	  Which chip select to use for boot media.
+
 endif # BOARD_GOOGLE_RUSH
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 23f7c6e7f2..4dc71fe2c5 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -54,4 +54,12 @@ config STACK_BOTTOM
 	hex
 	default 0x4001c000
 
+config CBFS_CACHE_ADDRESS
+	hex "memory address to put CBFS cache data"
+	default 0x40006000
+
+config CBFS_CACHE_SIZE
+	hex "size of CBFS cache data"
+	default 0x00016000
+
 endif
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c
index 46b7b3ab56..62e5228829 100644
--- a/src/soc/nvidia/tegra132/bootblock.c
+++ b/src/soc/nvidia/tegra132/bootblock.c
@@ -24,12 +24,15 @@
 #include <console/console.h>
 #include <soc/clock.h>
 #include <soc/nvidia/tegra/apbmisc.h>
+#include <arch/stages.h>
 
 #include "pinmux.h"
 #include "power.h"
 
 void main(void)
 {
+	void *entry;
+
 	// enable pinmux clamp inputs
 	clamp_tristate_inputs();
 
@@ -65,5 +68,14 @@ void main(void)
 
 	printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n");
 
-	while(1);
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
+
+	if (entry) {
+		printk(BIOS_INFO, "T132 bootblock: jumping to romstage\n");
+		stage_exit(entry);
+	} else {
+		printk(BIOS_INFO, "T132 bootblock: fallback/romstage not found\n");
+	}
+
+	hlt();
 }
diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c
index ac4a5570e6..7b75f7c8c1 100644
--- a/src/soc/nvidia/tegra132/cbfs.c
+++ b/src/soc/nvidia/tegra132/cbfs.c
@@ -20,7 +20,11 @@
 
 #include <cbfs.h>  /* This driver serves as a CBFS media source. */
 
+#include "spi.h"
+
 int init_default_cbfs_media(struct cbfs_media *media)
 {
-        return 0;
+	return initialize_tegra_spi_cbfs_media(media,
+		(void*)CONFIG_CBFS_CACHE_ADDRESS,
+		CONFIG_CBFS_CACHE_SIZE);
 }