cpu/intel/common: Fill cpu voltage in SMBIOS tables

Introduce a weak function to let the platform code provide the processor
voltage in 100mV units.

Implement the function on Intel platforms using the MSR_PERF_STATUS msr.
On other platforms the processor voltage still reads as unknown.

Tested on Intel CFL. The CPU voltage is correctly advertised.

Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

6 files changed, 28 insertions, 0 deletions

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index dc676cf141..da77284d37 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -493,6 +493,12 @@ unsigned int __weak smbios_cache_conf_operation_mode(u8 level)
 	return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */
 }
 
+/* Returns the processor voltage in 100mV units */
+unsigned int __weak smbios_cpu_get_voltage(void)
+{
+	return 0; /* Unknown */
+}
+
 static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache)
 {
 	size_t max_logical_cpus_sharing_cache = 0;
@@ -595,6 +601,7 @@ static int smbios_write_type3(unsigned long *current, int handle)
 
 static int smbios_write_type4(unsigned long *current, int handle)
 {
+	unsigned int cpu_voltage;
 	struct cpuid_result res;
 	struct smbios_type4 *t = (struct smbios_type4 *)*current;
 	int len = sizeof(struct smbios_type4);
@@ -686,6 +693,9 @@ static int smbios_write_type4(unsigned long *current, int handle)
 		}
 	}
 	t->processor_characteristics = characteristics | smbios_processor_characteristics();
+	cpu_voltage = smbios_cpu_get_voltage();
+	if (cpu_voltage > 0)
+		t->voltage = 0x80 | cpu_voltage;
 
 	*current += len;
 	return len;
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig
index 01f2721b59..7f9033cf65 100644
--- a/src/cpu/intel/common/Kconfig
+++ b/src/cpu/intel/common/Kconfig
@@ -32,6 +32,9 @@ config CPU_INTEL_COMMON_TIMEBASE
 
 endif
 
+config CPU_INTEL_COMMON_VOLTAGE
+	bool
+
 config CPU_INTEL_COMMON_SMM
 	bool
 	default y if CPU_INTEL_COMMON
diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index 8b81a121d3..530ecee009 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1,5 +1,6 @@
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c
 
 ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
 bootblock-y += fsb.c
diff --git a/src/cpu/intel/common/voltage.c b/src/cpu/intel/common/voltage.c
new file mode 100644
index 0000000000..38951a06db
--- /dev/null
+++ b/src/cpu/intel/common/voltage.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/msr.h>
+#include <smbios.h>
+
+/* This is not an architectural MSR. */
+#define MSR_PERF_STATUS 0x198
+
+unsigned int smbios_cpu_get_voltage(void)
+{
+	return (rdmsr(MSR_PERF_STATUS).hi & 0xffff) * 10 / 8192;
+}
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index fbfa71456b..0d3d132006 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 	select HAVE_ASAN_IN_ROMSTAGE
+	select CPU_INTEL_COMMON_VOLTAGE
 
 config SMM_TSEG_SIZE
 	hex
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 6a19655b31..4ddf4384dc 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -40,6 +40,7 @@ const char *smbios_system_sku(void);
 
 unsigned int smbios_cpu_get_max_speed_mhz(void);
 unsigned int smbios_cpu_get_current_speed_mhz(void);
+unsigned int smbios_cpu_get_voltage(void);
 
 const char *smbios_mainboard_manufacturer(void);
 const char *smbios_mainboard_product_name(void);