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authorFurquan Shaikh <furquan@google.com>2017-12-17 20:31:18 -0800
committerFurquan Shaikh <furquan@google.com>2017-12-19 02:38:29 +0000
commit9c12e90819c3a7955adf9de2fa82cc652ae6a76f (patch)
treeba59c976eff3f66aafe67ce906cfa4dd8616d3e8 /src
parentf7cd2eb55d8e6440b42b924a82a7025344056cc3 (diff)
mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1
Similar to other KBL projects, this change enables AER and LTR for root port 1 on poppy. BUG=b:65570878 Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index ac3bd1dc45..46b0946c2b 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -157,6 +157,10 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
+ # RP 1, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ # RP 1, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port