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authorWolfgang Kamp <wmkamp@datakamp.de>2013-03-11 16:35:42 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-15 17:51:48 +0100
commit9ae1eb6961b483c9905423fb113100a8038b4507 (patch)
tree68d440ec8ed012778e4ef8404c41bd666d4e310a /src
parent8d629c14eb776ce6e243218bb554a335dc0f3672 (diff)
Super I/O W83627DHG: Enable UART B by redirecting pins
Pins 78-85 are set to GPIO after power on or reset. To enable UART B the pins must be redirected to it. Look at W83627DHG databook version 1.4 page 185 Chip (global) Control Register CR2C. Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845 Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de> Reviewed-on: http://review.coreboot.org/2626 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/superio/winbond/w83627dhg/superio.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 26f2921300..bbde26a67e 100644
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -37,6 +37,17 @@ void pnp_exit_ext_func_mode(device_t dev)
outb(0xaa, dev->path.pnp.port);
}
+static void w83627dhg_enable_UR2(device_t dev)
+{
+ u8 reg8;
+
+ pnp_enter_ext_func_mode(dev);
+ reg8 = pnp_read_config(dev, 0x2c);
+ reg8 |= (0x3);
+ pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B
+ pnp_exit_ext_func_mode(dev);
+}
+
static void w83627dhg_init(device_t dev)
{
struct superio_winbond_w83627dhg_config *conf = dev->chip_info;
@@ -45,6 +56,9 @@ static void w83627dhg_init(device_t dev)
return;
switch(dev->path.pnp.device) {
+ case W83627DHG_SP2:
+ w83627dhg_enable_UR2(dev);
+ break;
case W83627DHG_KBC:
pc_keyboard_init(&conf->keyboard);
break;