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authorSubrata Banik <subrata.banik@intel.com>2019-05-17 14:39:36 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-05-20 14:50:28 +0000
commit97ae7430a80c00b3f53465727880d74d7ebfe7aa (patch)
tree2fcff4338579446d6b2fb260b6687a5de57c27c4 /src
parent76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8 (diff)
mb/google/dragonegg: Override FSP default GPIO PM configuration
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
index 257ad1dd15..f820924280 100644
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -167,6 +167,16 @@ chip soc/intel/icelake
},
}"
+ # GPIO PM programming
+ register "gpio_override_pm" = "1"
+
+ # GPIO community PM configuration
+ register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
+ register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device