diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2014-06-05 08:50:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-05 10:39:22 +0200 |
| commit | 8aeab56b102be493b7a592d45bb3646f8230e7be (patch) | |
| tree | 22673556bb99706a33b26f996cfcccf8e6fd0317 /src | |
| parent | 9238c11be4f8e0909b0ad1ecfdebf891337bb1a0 (diff) | |
lenovo/x60/i915.c: Use define for `BSM`
Although it builds without any further changes, including the header
src/northbridge/intel/i945/i945.h
where `BSM` is defined, would be useful. Unfortunately that conflicts
with the already included header `southbridge/intel/bd82x6x/pch.h`,
so it is left as is.
Change-Id: I7c0a795338c34038169e082446907987364a0e88
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5932
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/x60/i915.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0baaa1..8fbd2a14fc 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase) PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED; - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; PGETBL_save |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); |