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authorGreg Watson <jarrah@users.sourceforge.net>2003-10-12 21:19:22 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2003-10-12 21:19:22 +0000
commit85862124fd6b069f21b4dbfd6bd7dade740ae82f (patch)
tree92f992c4216624780498b575206cac1a260754b6 /src
parentf610d2466cb182fcc798bcbf99c1f12072144b2c (diff)
cache ram startup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/arch/ppc/init/crt0.S.lb103
1 files changed, 81 insertions, 22 deletions
diff --git a/src/arch/ppc/init/crt0.S.lb b/src/arch/ppc/init/crt0.S.lb
index be54d03d20..ea4ea925dd 100644
--- a/src/arch/ppc/init/crt0.S.lb
+++ b/src/arch/ppc/init/crt0.S.lb
@@ -11,6 +11,8 @@
_start:
b system_reset
+.section ".rom.exception_vectors", "ax", @progbits
+
%%EXCEPTION_VECTOR_TABLE%%
.section ".rom.data", "a", @progbits
@@ -18,38 +20,95 @@ _start:
system_reset:
-%%EARLY_INIT%%
+ /*
+ * Do processor family initialization
+ */
+%%FAMILY_INIT%%
+
+ /*
+ * Do processor specific initialization
+ */
+%%PROCESSOR_INIT%%
+
+#if USE_DCACHE_RAM == 1
+#define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
+ /*
+ * Setup stack in cache
+ */
+ lis r1, DCACHE_RAM_END@ha
+ addi r1, r1, DCACHE_RAM_END@l
+ stwu r0,-64(r1)
+ stwu r1,-24(r1)
+
+ /*
+ * Clear stack
+ */
+ lis r4, DCACHE_RAM_BASE@ha
+ addi r4, r4, DCACHE_RAM_BASE@l
+ lis r7, DCACHE_RAM_END@ha
+ addi r7, r7, DCACHE_RAM_END@l
+ lis r5, 0
+1: stwx r5, 0, r4
+ addi r4, r4, 4
+ cmp 0, 0, r4, r7
+ ble 1b
+ sync
+
+ /*
+ * Set up the EABI pointers, before we enter any C code
+ */
+ lis r13, _SDA_BASE_@ha
+ addi r13, r13, _SDA_BASE_@l
+ lis r2, _SDA2_BASE_@ha
+ addi r2, r2, _SDA2_BASE_@l
-start_payload:
/*
- * Relocate payload (text & data) to ram
+ * load start address into SRR0 for rfi
*/
- lis r3, _liseg@ha
- addi r3, r3, _liseg@l
- lis r4, _iseg@ha
- addi r4, r4, _iseg@l
+ lis r3, ppc_main@ha
+ addi r3, r3, ppc_main@l
+ mtspr SRR0, r3
/*
- * Skip if they're the same
+ * load the current MSR into SRR1 so that it will be copied
+ * back into MSR on rfi
*/
- cmp 0, 0, r3, r4
- beq 1f
+ mfmsr r4
+ mtspr SRR1, r4 // load SRR1 with r4
- lis r7, _eliseg@ha
- addi r7, r7, _eliseg@l
+ /*
+ * If something returns after rfi then die
+ */
+ lis r3, dead@ha
+ addi r3, r3, dead@l
+ mtlr r3
-2:
- lwzx r5, 0, r3
- stwx r5, 0, r4
- addi r3, r3, 4
- addi r4, r4, 4
- cmp 0, 0, r3, r7
- ble 2b
+ /*
+ * Complete rest of initialization in C (ppc_main)
+ */
+ rfi
+#endif /* USE_DCACHE_RAM */
-1:
/*
- * Start payload
+ * Stop here if something goes wrong
*/
- b _iseg
+dead:
+ b dead
+ /*NOTREACHED*/
+
+/* Remove need for ecrti.o and ectrn.o */
+.globl __init
+__init:
+.globl __fini
+__fini:
+.globl __CTOR_LIST__
+__CTOR_LIST__:
+.globl __CTOR_END__
+__CTOR_END__:
+.globl __DTOR_LIST__
+__DTOR_LIST__:
+.globl __DTOR_END__
+__DTOR_END__:
+ blr
%%NORTHBRIDGE_INIT%%