diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-04-08 17:14:36 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-11 11:28:09 +0000 |
| commit | 7fc25c013b91f26933705549d65e29b0301ff51d (patch) | |
| tree | e672d96e174b3329eb217cbab3d873ca51f1f409 /src | |
| parent | 67d630945ba6d70b630065f1a4dd8ce8a67ae5d2 (diff) | |
mb/google/sarien: Reserve gpio pins for D3 cold control
Based on HW change, reserve gpio pins for D3 cold control.
A13,A15 for Card reader
H13 for M.2 SSD
BUG=b:123263562
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/gpio.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index ff311b1293..19fd45cdea 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -31,9 +31,9 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* BM_BUSY# */ PAD_NC(GPP_A12, NONE), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -197,8 +197,8 @@ static const struct pad_config gpio_table[] = { /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* /D3 cold RST */ +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), |