nb/intel/haswell: Put DMIBAR/EPBAR registers into separate files

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ib68d8b88b0d79cb33d42f9e21cfb0e57abae75e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45355
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 82 insertions, 66 deletions

diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 136701cca2..44ea9b9858 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -61,23 +61,7 @@
 #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
 #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))
 
-#define EPPVCCAP1	0x004	/* 32bit */
-#define EPPVCCAP2	0x008	/* 32bit */
-
-#define EPVC0RCAP	0x010	/* 32bit */
-#define EPVC0RCTL	0x014	/* 32bit */
-#define EPVC0RSTS	0x01a	/* 16bit */
-
-#define EPVC1RCAP	0x01c	/* 32bit */
-#define EPVC1RCTL	0x020	/* 32bit */
-#define EPVC1RSTS	0x026	/* 16bit */
-
-#define EPESD		0x044	/* 32bit */
-
-#define EPLE1D		0x050	/* 32bit */
-#define EPLE1A		0x058	/* 64bit */
-#define EPLE2D		0x060	/* 32bit */
-#define EPLE2A		0x068	/* 64bit */
+#include "registers/epbar.h"
 
 /*
  * DMIBAR
@@ -87,55 +71,7 @@
 #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
 #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))
 
-#define DMIVCECH	0x000	/* 32bit */
-#define DMIPVCCAP1	0x004	/* 32bit */
-#define DMIPVCCAP2	0x008	/* 32bit */
-#define DMIPVCCCTL	0x00c	/* 16bit */
-
-#define DMIVC0RCAP	0x010	/* 32bit */
-#define DMIVC0RCTL	0x014	/* 32bit */
-#define DMIVC0RSTS	0x01a	/* 16bit */
-#define  VC0NP		(1 << 1)
-
-#define DMIVC1RCAP	0x01c	/* 32bit */
-#define DMIVC1RCTL	0x020	/* 32bit */
-#define DMIVC1RSTS	0x026	/* 16bit */
-#define  VC1NP		(1 << 1)
-
-#define DMIVCPRCAP	0x028	/* 32bit */
-#define DMIVCPRCTL	0x02c	/* 32bit */
-#define DMIVCPRSTS	0x032	/* 16bit */
-#define  VCPNP		(1 << 1)
-
-#define DMIVCMRCAP	0x034	/* 32bit */
-#define DMIVCMRCTL	0x038	/* 32bit */
-#define DMIVCMRSTS	0x03e	/* 16bit */
-#define  VCMNP		(1 << 1)
-
-#define DMIRCLDECH	0x040	/* 32bit */
-#define DMIESD		0x044	/* 32bit */
-
-#define DMILE1D		0x050	/* 32bit */
-#define DMILE1A		0x058	/* 64bit */
-#define DMILE2D		0x060	/* 32bit */
-#define DMILE2A		0x068	/* 64bit */
-
-#define DMILCAP		0x084	/* 32bit */
-#define DMILCTL		0x088	/* 16bit */
-#define DMILSTS		0x08a	/* 16bit */
-
-#define DMILCTL2	0x098	/* 16bit */
-#define DMILSTS2	0x09c	/* 16bit */
-
-#define DMIUESTS	0x1c4	/* 32bit */
-#define DMICESTS	0x1d0	/* 32bit */
-
-#define DMICC		0x208	/* 32bit */
-
-#define DMIL0SLAT	0x22c	/* 32bit */
-#define DMILLTC		0x238	/* 32bit */
-
-#define DMI_AFE_PM_TMR	0xc28	/* 32bit */
+#include "registers/dmibar.h"
 
 #ifndef __ASSEMBLER__
 
diff --git a/src/northbridge/intel/haswell/registers/dmibar.h b/src/northbridge/intel/haswell/registers/dmibar.h
new file mode 100644
index 0000000000..9d523825a7
--- /dev/null
+++ b/src/northbridge/intel/haswell/registers/dmibar.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __HASWELL_REGISTERS_DMIBAR_H__
+#define __HASWELL_REGISTERS_DMIBAR_H__
+
+#define DMIVCECH	0x000	/* 32bit */
+#define DMIPVCCAP1	0x004	/* 32bit */
+#define DMIPVCCAP2	0x008	/* 32bit */
+#define DMIPVCCCTL	0x00c	/* 16bit */
+
+#define DMIVC0RCAP	0x010	/* 32bit */
+#define DMIVC0RCTL	0x014	/* 32bit */
+#define DMIVC0RSTS	0x01a	/* 16bit */
+#define  VC0NP		(1 << 1)
+
+#define DMIVC1RCAP	0x01c	/* 32bit */
+#define DMIVC1RCTL	0x020	/* 32bit */
+#define DMIVC1RSTS	0x026	/* 16bit */
+#define  VC1NP		(1 << 1)
+
+#define DMIVCPRCAP	0x028	/* 32bit */
+#define DMIVCPRCTL	0x02c	/* 32bit */
+#define DMIVCPRSTS	0x032	/* 16bit */
+#define  VCPNP		(1 << 1)
+
+#define DMIVCMRCAP	0x034	/* 32bit */
+#define DMIVCMRCTL	0x038	/* 32bit */
+#define DMIVCMRSTS	0x03e	/* 16bit */
+#define  VCMNP		(1 << 1)
+
+#define DMIRCLDECH	0x040	/* 32bit */
+#define DMIESD		0x044	/* 32bit */
+
+#define DMILE1D		0x050	/* 32bit */
+#define DMILE1A		0x058	/* 64bit */
+#define DMILE2D		0x060	/* 32bit */
+#define DMILE2A		0x068	/* 64bit */
+
+#define DMILCAP		0x084	/* 32bit */
+#define DMILCTL		0x088	/* 16bit */
+#define DMILSTS		0x08a	/* 16bit */
+
+#define DMILCTL2	0x098	/* 16bit */
+#define DMILSTS2	0x09c	/* 16bit */
+
+#define DMIUESTS	0x1c4	/* 32bit */
+#define DMICESTS	0x1d0	/* 32bit */
+
+#define DMICC		0x208	/* 32bit */
+
+#define DMIL0SLAT	0x22c	/* 32bit */
+#define DMILLTC		0x238	/* 32bit */
+
+#define DMI_AFE_PM_TMR	0xc28	/* 32bit */
+
+#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */
diff --git a/src/northbridge/intel/haswell/registers/epbar.h b/src/northbridge/intel/haswell/registers/epbar.h
new file mode 100644
index 0000000000..963ceaddf4
--- /dev/null
+++ b/src/northbridge/intel/haswell/registers/epbar.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __HASWELL_REGISTERS_EPBAR_H__
+#define __HASWELL_REGISTERS_EPBAR_H__
+
+#define EPPVCCAP1	0x004	/* 32bit */
+#define EPPVCCAP2	0x008	/* 32bit */
+
+#define EPVC0RCAP	0x010	/* 32bit */
+#define EPVC0RCTL	0x014	/* 32bit */
+#define EPVC0RSTS	0x01a	/* 16bit */
+
+#define EPVC1RCAP	0x01c	/* 32bit */
+#define EPVC1RCTL	0x020	/* 32bit */
+#define EPVC1RSTS	0x026	/* 16bit */
+
+#define EPESD		0x044	/* 32bit */
+
+#define EPLE1D		0x050	/* 32bit */
+#define EPLE1A		0x058	/* 64bit */
+#define EPLE2D		0x060	/* 32bit */
+#define EPLE2A		0x068	/* 64bit */
+
+#endif /* __HASWELL_REGISTERS_EPBAR_H__ */