diff options
| author | Shelley Chen <shchen@google.com> | 2019-11-21 01:20:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-22 10:40:01 +0000 |
| commit | 5a0edcbde1537ad9d4d94b0e5f355454c8e597cf (patch) | |
| tree | 24f4f33ce4dbea9c5b76ca67a1644676f556b1b1 /src | |
| parent | 61e3d01739fd5e7c85c084cb6c0cd0e7cb5fc89c (diff) | |
mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOs
Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding
explicit configuration for Kohaku in the event that MEM_STRAP is set
differently in the baseboard gpio file.
BUG=b:144895517
BRANCH=hatch
TEST=None
./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/gpio.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 87c586d5a2..61d3375d6d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -55,6 +55,14 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E23, NONE), /* F1 : GPP_F1 ==> NC */ PAD_NC(GPP_F1, NONE), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* G0 : GPP_G0 ==> NC */ PAD_NC(GPP_G0, NONE), /* G1 : GPP_G1 ==> NC */ @@ -111,6 +119,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) |