soc/marvell/armada38x: Remove unused SoC armada38x

No mainboard is actually using this SoC. Remove the code for this SoC for now. BUG=b:38430839 Change-Id: Ia35986dffda8bbd76305ef5abab6ae81cc154b0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19824 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
author: Furquan Shaikh <furquan@chromium.org> 2017-05-22 14:32:30 -0700
committer: Furquan Shaikh <furquan@google.com> 2017-05-24 04:43:23 +0200
commit: 53bbf87a4c145d6394935f315b06ffc81c939b47 (patch)
tree: 1b84cee23366fa73efc6bb5186caff056f679d9f /src
parent: 12eca76469670d444897e67368a0d0a70787ad52 (diff)
18 files changed, 0 insertions, 2895 deletions
diff --git a/src/soc/marvell/armada38x/Kconfig b/src/soc/marvell/armada38x/Kconfig
deleted file mode 100644
index 20f9d09c89..0000000000
--- a/src/soc/marvell/armada38x/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-config SOC_MARVELL_ARMADA38X
-	bool
-	default n
-	select ARCH_BOOTBLOCK_ARMV7
-	select ARCH_VERSTAGE_ARMV7
-	select ARCH_ROMSTAGE_ARMV7
-	select ARCH_RAMSTAGE_ARMV7
-	select HAVE_UART_SPECIAL
-	select BOOTBLOCK_CONSOLE
-	select BOOTBLOCK_CUSTOM
-	select GENERIC_UDELAY
-	select UART_OVERRIDE_REFCLK
-
-if SOC_MARVELL_ARMADA38X
-
-config VBOOT
-	select VBOOT_RETURN_FROM_VERSTAGE
-
-config BOOTBLOCK_CPU_INIT
-	string
-	default "soc/marvell/armada38x/bootblock.c"
-	help
-	  CPU/SoC-specific bootblock code. This is useful if the
-	  bootblock must load microcode or copy data from ROM before
-	  searching for the bootblock.
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	default 0xf1012000
-endif
diff --git a/src/soc/marvell/armada38x/Makefile.inc b/src/soc/marvell/armada38x/Makefile.inc
deleted file mode 100644
index c55bfff6e3..0000000000
--- a/src/soc/marvell/armada38x/Makefile.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-ifeq ($(CONFIG_SOC_MARVELL_ARMADA38X),y)
-
-bootblock-y += bootblock.c
-bootblock-y += bootblock_asm.S
-bootblock-y += spi.c
-bootblock-y += gpio.c
-bootblock-y += monotonic_timer.c
-bootblock-y += clock.c
-ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
-bootblock-$(CONFIG_DRIVERS_UART) += uart.c
-endif
-
-verstage-$(CONFIG_DRIVERS_UART) += uart.c
-verstage-y += monotonic_timer.c
-verstage-y += spi.c
-verstage-y += gpio.c
-verstage-y += i2c.c
-verstage-y += clock.c
-
-romstage-y += spi.c
-romstage-y += gpio.c
-romstage-y += cbmem.c
-romstage-y += monotonic_timer.c
-romstage-$(CONFIG_DRIVERS_UART) += uart.c
-romstage-y += clock.c
-
-ramstage-y += spi.c
-ramstage-y += gpio.c
-ramstage-y += cbmem.c
-ramstage-y += monotonic_timer.c
-ramstage-y += soc.c
-ramstage-$(CONFIG_DRIVERS_UART) += uart.c
-ramstage-y += clock.c
-
-CPPFLAGS_common += -Isrc/soc/marvell/armada38x/include/ -Isrc/commonlib/include/commonlib/
-
-BIN_HDR = 3rdparty/cpu/marvell/armada38x/bin_hdr.bin
-DOIMAGE = $(objutil)/marvell/doimage_mv/doimage
-
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(DOIMAGE)
-	@chmod a+x $(DOIMAGE)
-	$(DOIMAGE) -T flash -D 0 -E 0 -G $(BIN_HDR) $< $@
-	rm $<
-endif
diff --git a/src/soc/marvell/armada38x/bootblock.c b/src/soc/marvell/armada38x/bootblock.c
deleted file mode 100644
index 8c125b5bb6..0000000000
--- a/src/soc/marvell/armada38x/bootblock.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <arch/io.h>
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/hlt.h>
-#include <bootblock_common.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <delay.h>
-#include <arch/stages.h>
-#include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/common.h>
-
-#define CLOCK_BIT_SATA23	BIT30
-#define CLOCK_BIT_PNC		BIT29
-#define CLOCK_BIT_TDM		BIT25
-#define CLOCK_BIT_CRYPTO0_GATE	BIT23
-#define CLOCK_BIT_CRYPTO1_GATE	BIT21
-#define CLOCK_BIT_CRYPTO1_Z	BIT16
-#define CLOCK_BIT_SATA01	BIT15
-#define CLOCK_BIT_CRYPTO0_Z	BIT14
-#define CLOCK_BIT_BM		BIT13
-#define CLOCK_BIT_PCIE2		BIT6
-#define CLOCK_BIT_PCIE1		BIT5
-#define CLOCK_BIT_GBE0		BIT4
-#define CLOCK_BIT_GBE1		BIT3
-#define CLOCK_BIT_GBE2		BIT2
-#define CLOCK_BIT_AUDIO		BIT0
-
-#define A38x_MPP0_7_OFFSET 0x18000
-#define A38x_MPP8_15_OFFSET 0x18004
-#define A38x_MPP16_23_OFFSET 0x18008
-#define A38x_MPP24_31_OFFSET 0x1800c
-#define A38x_MPP32_39_OFFSET 0x18010
-#define A38x_MPP40_47_OFFSET 0x18014
-#define A38x_MPP48_55_OFFSET 0x18018
-#define A38x_MPP56_63_OFFSET 0x1801c
-
-#define A38X_GPP_OUT_ENA_OFFSET_LOW 0x18104
-#define A38X_GPP_OUT_ENA_OFFSET_MID 0x18144
-
-#define A38X_GPP_OUT_VALUE_OFFSET_LOW	0x18100
-#define A38X_GPP_OUT_VALUE_OFFSET_MID	0x18140
-
-#define A38x_CUBE_BOARD_MPP0_7 0x00001111
-#define A38x_CUBE_BOARD_MPP8_15 0x46200000
-#define A38x_CUBE_BOARD_MPP16_23 0x00400444
-#define A38x_CUBE_BOARD_MPP24_31 0x00043300
-#define A38x_CUBE_BOARD_MPP32_39 0x44400000
-#define A38x_CUBE_BOARD_MPP40_47 0x00000004
-#define A38x_CUBE_BOARD_MPP48_55 0x00444444
-#define A38x_CUBE_BOARD_MPP56_63 0x00004444
-
-/* Set bit x to enable GPIO output mode for MPP x */
-#define A38x_CUBE_BOARD_0_GPP_OUT_ENA_LOW ~(BIT4 | BIT6)
-/* MID group is for MPP32 ~ MPP63 e.g BIT3 corresponds to MPP35 */
-#define A38x_CUBE_BOARD_0_GPP_OUT_ENA_MID ~(BIT3)
-
-#define A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_LOW (BIT4)
-/* MID group is for MPP32 ~ MPP63 e.g BIT3 corresponds to MPP35 */
-#define A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_MID (BIT3)
-
-#define A38X_POWER_MANAGEMENT_CLOCK_GATING_CONTROL 0x18220
-
-#define A38x_SOC_IO_ERR_CTRL_OFFSET 0x20200
-#define A38x_SOC_WIN_CTRL_OFFSET 0x20250
-#define A38x_SOC_WIN_BASE_OFFSET 0x20254
-
-#define A38x_CUBE_BOARD_SOC_IO_ERR_CTRL 0x00000000
-#define A38x_CUBE_BOARD_SOC_WIN_CTRL 0x1ff00001
-#define A38x_CUBE_BOARD_SOC_BASE_CTRL 0xe0000000
-
-#define DRAM_START ((uintptr_t)_dram / MiB)
-#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
-/* DMA memory for drivers */
-#define DMA_START ((uintptr_t)_dma_coherent / MiB)
-#define DMA_SIZE (_dma_coherent_size / MiB)
-
-static void setup_pinmux(void)
-{
-	/* Hard coded pin mux configuration */
-	mrvl_reg_write(A38x_MPP0_7_OFFSET, A38x_CUBE_BOARD_MPP0_7);
-	mrvl_reg_write(A38x_MPP8_15_OFFSET, A38x_CUBE_BOARD_MPP8_15);
-	mrvl_reg_write(A38x_MPP16_23_OFFSET, A38x_CUBE_BOARD_MPP16_23);
-	mrvl_reg_write(A38x_MPP24_31_OFFSET, A38x_CUBE_BOARD_MPP24_31);
-	mrvl_reg_write(A38x_MPP32_39_OFFSET, A38x_CUBE_BOARD_MPP32_39);
-	mrvl_reg_write(A38x_MPP40_47_OFFSET, A38x_CUBE_BOARD_MPP40_47);
-	mrvl_reg_write(A38x_MPP48_55_OFFSET, A38x_CUBE_BOARD_MPP48_55);
-	mrvl_reg_write(A38x_MPP56_63_OFFSET, A38x_CUBE_BOARD_MPP56_63);
-}
-
-static void setup_gpp_out_value(void)
-{
-	mrvl_reg_write(
-		A38X_GPP_OUT_VALUE_OFFSET_LOW,
-			A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_LOW);
-	mrvl_reg_write(
-		A38X_GPP_OUT_VALUE_OFFSET_MID,
-			A38x_CUSTOMER_BOARD_0_GPP_OUT_VAL_MID);
-}
-
-static void setup_gpp_out_enable(void)
-{
-	mrvl_reg_write(
-		A38X_GPP_OUT_ENA_OFFSET_LOW,
-			A38x_CUBE_BOARD_0_GPP_OUT_ENA_LOW);
-	mrvl_reg_write(
-		A38X_GPP_OUT_ENA_OFFSET_MID,
-			A38x_CUBE_BOARD_0_GPP_OUT_ENA_MID);
-}
-
-/* This function disable unused periperal clocks */
-static void setup_peripherals_clocks(void)
-{
-	mrvl_reg_bit_reset(
-		A38X_POWER_MANAGEMENT_CLOCK_GATING_CONTROL, (
-			CLOCK_BIT_SATA23 | CLOCK_BIT_PNC | CLOCK_BIT_TDM |
-			CLOCK_BIT_CRYPTO0_GATE | CLOCK_BIT_CRYPTO1_GATE |
-			CLOCK_BIT_CRYPTO1_Z | CLOCK_BIT_SATA01 |
-			CLOCK_BIT_CRYPTO0_Z | CLOCK_BIT_BM |
-			CLOCK_BIT_PCIE2 | CLOCK_BIT_PCIE1 |
-			CLOCK_BIT_GBE0 | CLOCK_BIT_GBE1 |
-			CLOCK_BIT_GBE2 | CLOCK_BIT_AUDIO
-		)
-	);
-}
-
-static void setup_win_regs(void)
-{
-	mrvl_reg_write(A38x_SOC_IO_ERR_CTRL_OFFSET,
-			A38x_CUBE_BOARD_SOC_IO_ERR_CTRL);
-	mrvl_reg_write(A38x_SOC_WIN_CTRL_OFFSET, A38x_CUBE_BOARD_SOC_WIN_CTRL);
-	mrvl_reg_write(A38x_SOC_WIN_BASE_OFFSET, A38x_CUBE_BOARD_SOC_BASE_CTRL);
-}
-
-void main(void)
-{
-	if (CONFIG_BOOTBLOCK_CONSOLE) {
-		console_init();
-		exception_init();
-	}
-
-	init_timer();
-
-	/* enable mmu */
-	mmu_init();
-	mmu_config_range(0, 4096, DCACHE_OFF);
-	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
-	mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
-	dcache_mmu_enable();
-
-	bootblock_mainboard_init();
-
-	setup_pinmux();
-	setup_gpp_out_value();
-	setup_gpp_out_enable();
-	setup_win_regs();
-	setup_peripherals_clocks();
-	run_romstage();
-}
diff --git a/src/soc/marvell/armada38x/bootblock_asm.S b/src/soc/marvell/armada38x/bootblock_asm.S
deleted file mode 100644
index 7bb7ccf504..0000000000
--- a/src/soc/marvell/armada38x/bootblock_asm.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/asm.h>
-
-.arm
-	/*
-	 * Just in case the maskrom or the vendor basic firmware passes on a
-	 * parameter when calling the bootblock, store it here for handling by C
-	 * code.
-	 */
-	.section .bss, "aw" @nobits
-	.global maskrom_param
-	.align 4
-maskrom_param:
-	.word 0
-
-ENTRY(_start)
-	/*
-	 * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
-	 * aborts may happen early and crash before the abort handlers are
-	 * installed, but at least the problem will show up near the code that
-	 * causes it.
-	 */
-	msr	cpsr_cxf, #0xdf
-	bl	_thumb_start
-ENDPROC(_start)
-
-.thumb
-ENTRY(_thumb_start)
-
-	/* Preserve the maskrom passed value, if any */
-	mov	r10, r0
-
-	/* Disable L2 Cache */
-        ldr r1, =0x0
-        ldr r0, =0xD0008100
-        str r1, [r0]
-
-        /* Disable windows that overlap with 0xF1000000 */
-        /* By default, window #12 overlaps with 0xF1000000 */
-        mov  r1, #0
-        ldr  r0, =0xD00200B0
-        str  r1, [r0]
-        /* Set Registers Base address. */
-        ldr  r1, =0xf1000000
-        ldr  r0, =0xD0020080
-        str  r1, [r0]
-        /* Update SCU (peripheral) register Base address with
-	 * correct INTER_REG_BASE
-	 */
-        ldr r2, = 0xC000                /* SCU offset = 0xC000 */
-        add r1, r1, r2                  /* r1 = INTER_REG_BASE + SCU_OFFSET */
-        mcr p15, 4, r1, c15, c0, 0      /* Write SCU base register */
-
-	bl	arm_init_caches
-
-	/*
-	 * From Cortex-A Series Programmer's Guide:
-	 * Only CPU 0 performs initialization. Other CPUs go into WFI
-	 * to do this, first work out which CPU this is
-	 * this code typically is run before any other initialization step
-	 */
-	mrc p15, 0, r1, c0, c0, 5	@ Read Multiprocessor Affinity Register
-	and r1, r1, #0x3 @ Extract CPU ID bits
-	cmp r1, #0
-	bne wait_for_interrupt		@ If this is not core0, wait
-
-	/*
-	 * Initialize the stack to a known value. This is used to check for
-	 * stack overflow later in the boot process.
-	 */
-	ldr	r0, =_stack
-	ldr	r1, =_estack
-	ldr	r2, =0xdeadbeef
-init_stack_loop:
-	str	r2, [r0]
-	add	r0, #4
-	cmp	r0, r1
-	bne	init_stack_loop
-
-        ldr     r0, =_bss
-        ldr     r1, =_ebss
-        mov     r2, #0x00000000         /* prepare zero to clear BSS */
-clbss_l:
-	str     r2, [r0]
-	add     r0, #4
-	cmp     r0, r1
-	bne     clbss_l
-
-call_bootblock:
-
-	/* Restore parameter passed in by maskrom/vendor firmware. */
-	ldr	r0, =maskrom_param
-	str	r10, [r0]
-
-	/* Set stackpointer in internal RAM to call bootblock main() */
-	ldr	sp, =_estack
-	ldr	r0,=0x00000000
-	 /*
-	  * The current design of cpu_info places the struct at the top of the
-	  * stack. Free enough space to accommodate for that, but make sure it's
-	  * 8-byte aligned for ABI compliance.
-	  */
-	sub	sp, sp, #16
-	bl	main
-
-wait_for_interrupt:
-	wfi
-	mov	pc, lr			@ back to my caller
-ENDPROC(_thumb_start)
diff --git a/src/soc/marvell/armada38x/cbmem.c b/src/soc/marvell/armada38x/cbmem.c
deleted file mode 100644
index 94719b8ca0..0000000000
--- a/src/soc/marvell/armada38x/cbmem.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <soc/soc_services.h>
-
-void *cbmem_top(void)
-{
-	return (void *)_memlayout_cbmem_top;
-}
diff --git a/src/soc/marvell/armada38x/clock.c b/src/soc/marvell/armada38x/clock.c
deleted file mode 100644
index 579e1a3d2b..0000000000
--- a/src/soc/marvell/armada38x/clock.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/common.h>
-#include <soc/clock.h>
-
-uint32_t mv_tclk_get(void)
-{
-	uint32_t tclk_reg_value;
-	uint32_t tclk;
-
-	tclk_reg_value = (mrvl_reg_read(MPP_SAMPLE_AT_RESET));
-	tclk_reg_value = ((tclk_reg_value & (1 << 15)) >> 15);
-	switch (tclk_reg_value) {
-	case 0:
-		tclk = MV_BOARD_TCLK_250MHZ;
-	case 1:
-		tclk = MV_BOARD_TCLK_200MHZ;
-	default:
-		tclk = MV_BOARD_TCLK_250MHZ;
-	}
-	return tclk;
-}
diff --git a/src/soc/marvell/armada38x/gpio.c b/src/soc/marvell/armada38x/gpio.c
deleted file mode 100644
index 1c5a4c78c6..0000000000
--- a/src/soc/marvell/armada38x/gpio.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Marvell Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <soc/common.h>
-#include <console/console.h>
-
-#define MV_GPIO_MAX_NUM 59
-
-#define MV_GPP_IN 0xFFFFFFFF /* GPP input */
-#define MV_GPP_OUT 0 /* GPP output */
-
-#define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit)*0x40))
-#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
-#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
-#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
-
-static void gpp_reg_set(u32 group, u32 reg_offs, u32 mask, u32 value);
-static int mv_gpp_type_set(u32 group, u32 mask, u32 value);
-static u32 mv_gpp_value_get(u32 group, u32 mask);
-static int mv_gpp_value_set(u32 group, u32 mask, u32 value);
-
-void gpp_reg_set(u32 group, u32 reg_offs, u32 mask, u32 value)
-{
-	u32 gpp_data;
-
-	gpp_data = mrvl_reg_read(reg_offs);
-	gpp_data &= ~mask;
-	gpp_data |= (value & mask);
-	mrvl_reg_write(reg_offs, gpp_data);
-}
-
-int mv_gpp_type_set(u32 group, u32 mask, u32 value)
-{
-	gpp_reg_set(group, GPP_DATA_OUT_EN_REG(group), mask, value);
-	return MV_OK;
-}
-
-u32 mv_gpp_value_get(u32 group, u32 mask)
-{
-	u32 gpp_data;
-
-	gpp_data = mrvl_reg_read(GPP_DATA_IN_REG(group));
-	gpp_data &= mask;
-	return gpp_data;
-}
-
-int mv_gpp_value_set(u32 group, u32 mask, u32 value)
-{
-	u32 out_enable;
-
-	/* verify that the gpp pin is configured as output*/
-	/* Note that in the register out enabled -> bit = '0'.*/
-	out_enable = ~(mrvl_reg_read(GPP_DATA_OUT_EN_REG(group)));
-	if ((out_enable & mask) != mask) {
-		printk(BIOS_ERR,
-			"Mask and out_enable mismatch(mask:0x%x, out_enable:0x%x).\n",
-			mask, (out_enable & mask));
-		return MV_ERROR;
-	}
-	gpp_reg_set(group, GPP_DATA_OUT_REG(group), mask, value);
-	return MV_OK;
-}
-
-static inline int gpio_not_valid(gpio_t gpio)
-{
-	return (gpio > MV_GPIO_MAX_NUM);
-}
-
-int gpio_get(gpio_t gpio)
-{
-	u32 group = 0;
-	u32 gpp_data;
-
-	if (gpio_not_valid(gpio))
-		return MV_BAD_PARAM;
-	if (gpio >= 32) {
-		group = 1;
-		gpio -= 32;
-	}
-
-	mv_gpp_type_set(group, (1 << gpio), MV_GPP_IN & (1 << gpio));
-	gpp_data = mv_gpp_value_get(group, (1 << gpio));
-	return (gpp_data != 0);
-}
-
-void gpio_set(gpio_t gpio, int value)
-{
-	u32 group = 0;
-
-	if (gpio_not_valid(gpio))
-		return;
-	if (gpio >= 32) {
-		group = 1;
-		gpio -= 32;
-	}
-
-	mv_gpp_type_set(group, (1 << gpio), MV_GPP_OUT & (1 << gpio));
-	mv_gpp_value_set(group, (1 << gpio), (value ? (1 << gpio) : 0));
-}
diff --git a/src/soc/marvell/armada38x/i2c.c b/src/soc/marvell/armada38x/i2c.c
deleted file mode 100644
index 723d3b4b1d..0000000000
--- a/src/soc/marvell/armada38x/i2c.c
+++ /dev/null
@@ -1,1251 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Marvell Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/i2c.h>
-#include <soc/common.h>
-#include <soc/i2c.h>
-#include <soc/clock.h>
-#include <helpers.h>
-
-#undef MV_DEBUG
-//#define MV_DEBUG
-#ifdef MV_DEBUG
-#define DB(x) x
-#else
-#define DB(x)
-#endif
-#define mv_os_printf(args...) printk(BIOS_INFO, args)
-
-/* The TWSI interface supports both 7-bit and 10-bit addressing.            */
-/* This enumerator describes addressing type.                               */
-typedef enum _mv_twsi_addr_type {
-	ADDR7_BIT, /* 7 bit address    */
-	ADDR10_BIT /* 10 bit address   */
-} MV_TWSI_ADDR_TYPE;
-
-/* This structure describes TWSI address.                                   */
-typedef struct _mv_twsi_addr {
-	uint32_t address;       /* address          */
-	MV_TWSI_ADDR_TYPE type; /* Address type     */
-} MV_TWSI_ADDR;
-
-/* This structure describes a TWSI slave.                                   */
-typedef struct _mv_twsi_slave {
-	MV_TWSI_ADDR slave_addr;
-	int valid_offset; /* whether the slave has offset (i.e. Eeprom  etc.) */
-	uint32_t offset;  /* offset in the slave. */
-	int more_than256; /* whether the ofset is bigger then 256 */
-} MV_TWSI_SLAVE;
-
-/* This enumerator describes TWSI protocol commands.                        */
-typedef enum _mv_twsi_cmd {
-	MV_TWSI_WRITE, /* TWSI write command - 0 according to spec   */
-	MV_TWSI_READ   /* TWSI read command  - 1 according to spec */
-} MV_TWSI_CMD;
-
-static void twsi_int_flg_clr(uint8_t chan_num);
-static uint8_t twsi_main_int_get(uint8_t chan_num);
-static void twsi_ack_bit_set(uint8_t chan_num);
-static uint32_t twsi_sts_get(uint8_t chan_num);
-static void twsi_reset(uint8_t chan_num);
-static int twsi_addr7_bit_set(uint8_t chan_num,
-			      uint32_t device_address,
-			      MV_TWSI_CMD command);
-static int twsi_addr10_bit_set(uint8_t chan_num,
-			       uint32_t device_address,
-			       MV_TWSI_CMD command);
-static int twsi_data_transmit(uint8_t chan_num,
-			      uint8_t *p_block,
-			      uint32_t block_size);
-static int twsi_data_receive(uint8_t chan_num,
-			     uint8_t *p_block,
-			     uint32_t block_size);
-static int twsi_target_offs_set(uint8_t chan_num,
-				uint32_t offset,
-				uint8_t more_than256);
-static int mv_twsi_start_bit_set(uint8_t chan_num);
-static int mv_twsi_stop_bit_set(uint8_t chan_num);
-static int mv_twsi_addr_set(uint8_t chan_num,
-			    MV_TWSI_ADDR *twsi_addr,
-			    MV_TWSI_CMD command);
-static uint32_t mv_twsi_init(uint8_t chan_num,
-			     uint32_t frequency,
-			     uint32_t Tclk,
-			     MV_TWSI_ADDR *twsi_addr,
-			     uint8_t general_call_enable);
-static int mv_twsi_read(uint8_t chan_num,
-			MV_TWSI_SLAVE *twsi_slave,
-			uint8_t *p_block,
-			uint32_t block_size);
-static int mv_twsi_write(uint8_t chan_num,
-			 MV_TWSI_SLAVE *twsi_slave,
-			 uint8_t *p_block,
-			 uint32_t block_size);
-static uint32_t who_am_i(void);
-static int i2c_init(unsigned bus);
-static void i2c_reset(unsigned bus);
-
-static int m_initialized[MAX_I2C_NUM] = {0, 0};
-
-static uint8_t twsi_timeout_chk(uint32_t timeout, const char *p_string)
-{
-	if (timeout >= TWSI_TIMEOUT_VALUE) {
-		DB(mv_os_printf("%s", p_string));
-		return MV_TRUE;
-	}
-	return MV_FALSE;
-}
-
-/*******************************************************************************
-* mv_twsi_start_bit_set - Set start bit on the bus
-*
-* DESCRIPTION:
-*       This routine sets the start bit on the TWSI bus.
-*       The routine first checks for interrupt flag condition, then it sets
-*       the start bit  in the TWSI Control register.
-*       If the interrupt flag condition check previously was set, the function
-*       will clear it.
-*       The function then wait for the start bit to be cleared by the HW.
-*       Then it waits for the interrupt flag to be set and eventually, the
-*       TWSI status is checked to be 0x8 or 0x10(repeated start bit).
-*
-* INPUT:
-*       chan_num - TWSI channel.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_OK if start bit was set successfuly on the bus.
-*       MV_FAIL if start_bit not set or status does not indicate start
-*       condition trasmitted.
-*
-*******************************************************************************/
-static int mv_twsi_start_bit_set(uint8_t chan_num)
-{
-	uint8_t is_int_flag = MV_FALSE;
-	uint32_t timeout, temp;
-
-	DB(mv_os_printf("TWSI: mv_twsi_start_bit_set\n"));
-	/* check Int flag */
-	if (twsi_main_int_get(chan_num))
-		is_int_flag = MV_TRUE;
-	/* set start Bit */
-	mrvl_reg_bit_set(TWSI_CONTROL_REG(chan_num), TWSI_CONTROL_START_BIT);
-
-	/* in case that the int flag was set before i.e. repeated start bit */
-	if (is_int_flag) {
-		DB(mv_os_printf(
-		    "TWSI: mv_twsi_start_bit_set repeated start Bit\n"));
-		twsi_int_flg_clr(chan_num);
-	}
-
-	/* wait for interrupt */
-	timeout = 0;
-	while (!twsi_main_int_get(chan_num) && (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(timeout,
-			     (const char *)"TWSI: Start Clear bit time_out.\n"))
-		return MV_TIMEOUT;
-
-	/* check that start bit went down */
-	if ((mrvl_reg_read(TWSI_CONTROL_REG(chan_num)) &
-	     TWSI_CONTROL_START_BIT) != 0) {
-		mv_os_printf("TWSI: start bit didn't go down\n");
-		return MV_FAIL;
-	}
-
-	/* check the status */
-	temp = twsi_sts_get(chan_num);
-	if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == temp) ||
-	    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA == temp)) {
-		DB(mv_os_printf("TWSI: Lost Arb, status %x\n", temp));
-		return MV_RETRY;
-	} else if ((temp != TWSI_START_CON_TRA) &&
-		   (temp != TWSI_REPEATED_START_CON_TRA)) {
-		mv_os_printf("TWSI: status %x after Set Start Bit.\n", temp);
-		return MV_FAIL;
-	}
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* mv_twsi_stop_bit_set - Set stop bit on the bus
-*
-* DESCRIPTION:
-*       This routine set the stop bit on the TWSI bus.
-*       The function then wait for the stop bit to be cleared by the HW.
-*       Finally the function checks for status of 0xF8.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_TRUE is stop bit was set successfuly on the bus.
-*
-*******************************************************************************/
-static int mv_twsi_stop_bit_set(uint8_t chan_num)
-{
-	uint32_t timeout, temp;
-
-	/* Generate stop bit */
-	mrvl_reg_bit_set(TWSI_CONTROL_REG(chan_num), TWSI_CONTROL_STOP_BIT);
-
-	twsi_int_flg_clr(chan_num);
-
-	/* wait for stop bit to come down */
-	timeout = 0;
-	while (((mrvl_reg_read(TWSI_CONTROL_REG(chan_num)) &
-		 TWSI_CONTROL_STOP_BIT) != 0) &&
-	       (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(timeout,
-			     (const char *)"TWSI: ERROR - Stop bit timeout\n"))
-		return MV_TIMEOUT;
-
-	/* check that the stop bit went down */
-	if ((mrvl_reg_read(TWSI_CONTROL_REG(chan_num)) &
-	     TWSI_CONTROL_STOP_BIT) != 0) {
-		mv_os_printf(
-		    "TWSI: ERROR - stop bit not went down\n");
-		return MV_FAIL;
-	}
-
-	/* check the status */
-	temp = twsi_sts_get(chan_num);
-	if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == temp) ||
-	    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA == temp)) {
-		DB(mv_os_printf("TWSI: Lost Arb, status %x\n", temp));
-		return MV_RETRY;
-	} else if (temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0) {
-		mv_os_printf(
-		    "TWSI: ERROR - status %x after Stop Bit\n",
-		    temp);
-		return MV_FAIL;
-	}
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* twsi_main_int_get - Get twsi bit from main Interrupt cause.
-*
-* DESCRIPTION:
-*       This routine returns the twsi interrupt flag value.
-*
-* INPUT:
-*       None.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_TRUE is interrupt flag is set, MV_FALSE otherwise.
-*
-*******************************************************************************/
-static uint32_t who_am_i(void)
-{
-	return (read_mpidr() & 0x1);
-}
-
-static uint8_t twsi_main_int_get(uint8_t chan_num)
-{
-	uint32_t temp;
-
-	/* get the int flag bit */
-	temp = mrvl_reg_read(MV_TWSI_CPU_MAIN_INT_CAUSE(chan_num, who_am_i()));
-	if (temp & (1 << CPU_MAIN_INT_TWSI_OFFS(chan_num)))
-		return MV_TRUE;
-
-	return MV_FALSE;
-}
-
-/*******************************************************************************
-* twsi_int_flg_clr - Clear Interrupt flag.
-*
-* DESCRIPTION:
-*       This routine clears the interrupt flag. It does NOT poll the interrupt
-*       to make sure the clear. After clearing the interrupt, it waits for at
-*       least 1 miliseconds.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void twsi_int_flg_clr(uint8_t chan_num)
-{
-	/* wait for 1ms to prevent TWSI register write after write problems */
-	mdelay(1);
-	/* clear the int flag bit */
-	mrvl_reg_bit_reset(
-		TWSI_CONTROL_REG(chan_num), TWSI_CONTROL_INT_FLAG_SET);
-	/* wait for 1 mili sec for the clear to take effect */
-	mdelay(1);
-}
-
-/*******************************************************************************
-* twsi_ack_bit_set - Set acknowledge bit on the bus
-*
-* DESCRIPTION:
-*       This routine set the acknowledge bit on the TWSI bus.
-*
-* INPUT:
-*       None.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void twsi_ack_bit_set(uint8_t chan_num)
-{
-	/*Set the Ack bit */
-	mrvl_reg_bit_set(TWSI_CONTROL_REG(chan_num), TWSI_CONTROL_ACK);
-	/* Add delay of 1ms */
-	mdelay(1);
-}
-
-/*******************************************************************************
-* twsi_init - Initialize TWSI interface
-*
-* DESCRIPTION:
-*       This routine:
-*	-Reset the TWSI.
-*	-Initialize the TWSI clock baud rate according to given frequency
-*	 parameter based on Tclk frequency and enables TWSI slave.
-*       -Set the ack bit.
-*	-Assign the TWSI slave address according to the TWSI address Type.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       frequency - TWSI frequency in KHz. (up to 100_kHZ)
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       Actual frequency.
-*
-*******************************************************************************/
-static uint32_t mv_twsi_init(uint8_t chan_num,
-			     uint32_t frequency,
-			     uint32_t Tclk,
-			     MV_TWSI_ADDR *p_twsi_addr,
-			     uint8_t general_call_enable)
-{
-	uint32_t n, m, freq, margin, min_margin = 0xffffffff;
-	uint32_t power;
-	uint32_t actual_freq = 0, actual_n = 0, actual_m = 0, val;
-
-	if (frequency > 100000)
-		die("TWSI frequency is too high!");
-
-	DB(mv_os_printf("TWSI: mv_twsi_init - Tclk = %d freq = %d\n", Tclk,
-			frequency));
-	/* Calucalte N and M for the TWSI clock baud rate */
-	for (n = 0; n < 8; n++) {
-		for (m = 0; m < 16; m++) {
-			power = 2 << n; /* power = 2^(n+1) */
-			freq = Tclk / (10 * (m + 1) * power);
-			margin = ABS(frequency - freq);
-
-			if ((freq <= frequency) && (margin < min_margin)) {
-				min_margin = margin;
-				actual_freq = freq;
-				actual_n = n;
-				actual_m = m;
-			}
-		}
-	}
-	DB(mv_os_printf("TWSI: mv_twsi_init - act_n %u act_m %u act_freq %u\n",
-			actual_n, actual_m, actual_freq));
-	/* Reset the TWSI logic */
-	twsi_reset(chan_num);
-
-	/* Set the baud rate */
-	val = ((actual_m << TWSI_BAUD_RATE_M_OFFS) |
-	       actual_n << TWSI_BAUD_RATE_N_OFFS);
-	mrvl_reg_write(TWSI_STATUS_BAUDE_RATE_REG(chan_num), val);
-
-	/* Enable the TWSI and slave */
-	mrvl_reg_write(TWSI_CONTROL_REG(chan_num),
-		       TWSI_CONTROL_ENA | TWSI_CONTROL_ACK);
-
-	/* set the TWSI slave address */
-	if (p_twsi_addr->type == ADDR10_BIT) {
-		/* writing the 2 most significant bits of the 10 bit address */
-		val = ((p_twsi_addr->address & TWSI_SLAVE_ADDR_10_BIT_MASK) >>
-		       TWSI_SLAVE_ADDR_10_BIT_OFFS);
-		/* bits 7:3 must be 0x11110 */
-		val |= TWSI_SLAVE_ADDR_10_BIT_CONST;
-		/* set GCE bit */
-		if (general_call_enable)
-			val |= TWSI_SLAVE_ADDR_GCE_ENA;
-		/* write slave address */
-		mrvl_reg_write(TWSI_SLAVE_ADDR_REG(chan_num), val);
-
-		/* writing the 8 least significant bits of the 10 bit address */
-		val = (p_twsi_addr->address << TWSI_EXTENDED_SLAVE_OFFS) &
-		      TWSI_EXTENDED_SLAVE_MASK;
-		mrvl_reg_write(TWSI_EXTENDED_SLAVE_ADDR_REG(chan_num), val);
-	} else {
-		/* set the 7 Bits address */
-		mrvl_reg_write(TWSI_EXTENDED_SLAVE_ADDR_REG(chan_num), 0x0);
-		val = (p_twsi_addr->address << TWSI_SLAVE_ADDR_7_BIT_OFFS) &
-		      TWSI_SLAVE_ADDR_7_BIT_MASK;
-		mrvl_reg_write(TWSI_SLAVE_ADDR_REG(chan_num), val);
-	}
-
-	/* unmask twsi int */
-	mrvl_reg_bit_set(TWSI_CONTROL_REG(chan_num), TWSI_CONTROL_INT_ENA);
-
-	/* unmask twsi int in Interrupt source control register */
-	mrvl_reg_bit_set(CPU_INT_SOURCE_CONTROL_REG(
-			CPU_MAIN_INT_CAUSE_TWSI(chan_num)), (
-				1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS));
-
-	/* Add delay of 1ms */
-	mdelay(1);
-
-	return actual_freq;
-}
-
-/*******************************************************************************
-* twsi_sts_get - Get the TWSI status value.
-*
-* DESCRIPTION:
-*       This routine returns the TWSI status value.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       uint32_t - the TWSI status.
-*
-*******************************************************************************/
-static uint32_t twsi_sts_get(uint8_t chan_num)
-{
-	return mrvl_reg_read(TWSI_STATUS_BAUDE_RATE_REG(chan_num));
-}
-
-/*******************************************************************************
-* twsi_reset - Reset the TWSI.
-*
-* DESCRIPTION:
-*       Resets the TWSI logic and sets all TWSI registers to their reset values.
-*
-* INPUT:
-*      chan_num - TWSI channel
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       None
-*
-*******************************************************************************/
-static void twsi_reset(uint8_t chan_num)
-{
-	/* Reset the TWSI logic */
-	mrvl_reg_write(TWSI_SOFT_RESET_REG(chan_num), 0);
-
-	/* wait for 2 mili sec */
-	mdelay(2);
-}
-
-/*******************************************************************************
-* mv_twsi_addr_set - Set address on TWSI bus.
-*
-* DESCRIPTION:
-*       This function Set address (7 or 10 Bit address) on the Twsi Bus.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       p_twsi_addr - twsi address.
-*	command	 - read / write .
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_OK - if setting the address completed successfully.
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int mv_twsi_addr_set(uint8_t chan_num,
-			    MV_TWSI_ADDR *p_twsi_addr,
-			    MV_TWSI_CMD command)
-{
-	DB(mv_os_printf(
-	    "TWSI: mv_twsi_addr7_bit_set addr %x , type %d, cmd is %s\n",
-	    p_twsi_addr->address, p_twsi_addr->type,
-	    ((command == MV_TWSI_WRITE) ? "Write" : "Read")));
-	/* 10 Bit address */
-	if (p_twsi_addr->type == ADDR10_BIT)
-		return twsi_addr10_bit_set(chan_num, p_twsi_addr->address,
-					   command);
-	/* 7 Bit address */
-	else
-		return twsi_addr7_bit_set(chan_num, p_twsi_addr->address,
-					  command);
-}
-
-/*******************************************************************************
-* twsi_addr10_bit_set - Set 10 Bit address on TWSI bus.
-*
-* DESCRIPTION:
-*       There are two address phases:
-*       1) Write '11110' to data register bits [7:3] and 10-bit address MSB
-*          (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1)
-*bit
-*          to the Data register. Then it clears interrupt flag which drive
-*          the address on the TWSI bus. The function then waits for interrupt
-*          flag to be active and status 0x18 (write) or 0x40 (read) to be set.
-*       2) write the rest of 10-bit address to data register and clears
-*          interrupt flag which drive the address on the TWSI bus. The
-*          function then waits for interrupt flag to be active and status
-*          0xD0 (write) or 0xE0 (read) to be set.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       device_address - twsi address.
-*	command	 - read / write .
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_OK - if setting the address completed successfully.
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int twsi_addr10_bit_set(uint8_t chan_num,
-			       uint32_t device_address,
-			       MV_TWSI_CMD command)
-{
-	uint32_t val, timeout;
-
-	/* writing the 2 most significant bits of the 10 bit address */
-	val = ((device_address & TWSI_DATA_ADDR_10_BIT_MASK) >>
-	       TWSI_DATA_ADDR_10_BIT_OFFS);
-	/* bits 7:3 must be 0x11110 */
-	val |= TWSI_DATA_ADDR_10_BIT_CONST;
-	/* set command */
-	val |= command;
-	mrvl_reg_write(TWSI_DATA_REG(chan_num), val);
-	/* WA add a delay */
-	mdelay(1);
-
-	/* clear Int flag */
-	twsi_int_flg_clr(chan_num);
-
-	/* wait for Int to be Set */
-	timeout = 0;
-	while (!twsi_main_int_get(chan_num) && (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(
-		timeout, (const char *)"TWSI: addr (10_bit) Int time_out.\n"))
-		return MV_TIMEOUT;
-
-	/* check the status */
-	val = twsi_sts_get(chan_num);
-	if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == val) ||
-	    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA == val)) {
-		DB(mv_os_printf("TWSI: Lost Arb, status %x\n", val));
-		return MV_RETRY;
-	} else if (((val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) &&
-		    (command == MV_TWSI_READ)) ||
-		   ((val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) &&
-		    (command == MV_TWSI_WRITE))) {
-		mv_os_printf("TWSI: status %x 1st addr (10 Bit) in %s mode.\n",
-			     val,
-			     ((command == MV_TWSI_WRITE) ? "Write" : "Read"));
-		return MV_FAIL;
-	}
-
-	/* set  8 LSB of the address */
-	val = (device_address << TWSI_DATA_ADDR_7_BIT_OFFS) &
-	      TWSI_DATA_ADDR_7_BIT_MASK;
-	mrvl_reg_write(TWSI_DATA_REG(chan_num), val);
-
-	/* clear Int flag */
-	twsi_int_flg_clr(chan_num);
-
-	/* wait for Int to be Set */
-	timeout = 0;
-	while (!twsi_main_int_get(chan_num) && (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(timeout,
-			     (const char *)"TWSI: 2nd (10 Bit) Int tim_out.\n"))
-		return MV_TIMEOUT;
-
-	/* check the status */
-	val = twsi_sts_get(chan_num);
-	if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == val) ||
-	    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA == val)) {
-		DB(mv_os_printf("TWSI: Lost Arb, status %x\n", val));
-		return MV_RETRY;
-	} else if (((val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) &&
-		    (command == MV_TWSI_READ)) ||
-		   ((val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) &&
-		    (command == MV_TWSI_WRITE))) {
-		mv_os_printf("TWSI: status %x 2nd addr(10 Bit) in %s mode.\n",
-			     val,
-			     ((command == MV_TWSI_WRITE) ? "Write" : "Read"));
-		return MV_FAIL;
-	}
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* twsi_addr7_bit_set - Set 7 Bit address on TWSI bus.
-*
-* DESCRIPTION:
-*       This function writes 7 bit address plus a write or read bit to the
-*       Data register. Then it clears interrupt flag which drive the address on
-*       the TWSI bus. The function then waits for interrupt flag to be active
-*       and status 0x18 (write) or 0x40 (read) to be set.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       device_address - twsi address.
-*	command	 - read / write .
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_OK - if setting the address completed successfully.
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int twsi_addr7_bit_set(uint8_t chan_num,
-			      uint32_t device_address,
-			      MV_TWSI_CMD command)
-{
-	uint32_t val, timeout;
-
-	/* set the address */
-	val = (device_address << TWSI_DATA_ADDR_7_BIT_OFFS) &
-	      TWSI_DATA_ADDR_7_BIT_MASK;
-	/* set command */
-	val |= command;
-	mrvl_reg_write(TWSI_DATA_REG(chan_num), val);
-	/* WA add a delay */
-	mdelay(1);
-
-	/* clear Int flag */
-	twsi_int_flg_clr(chan_num);
-
-	/* wait for Int to be Set */
-	timeout = 0;
-	while (!twsi_main_int_get(chan_num) && (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(
-		timeout, (const char *)"TWSI: Addr (7 Bit) int time_out.\n"))
-		return MV_TIMEOUT;
-
-	/* check the status */
-	val = twsi_sts_get(chan_num);
-	if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == val) ||
-	    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA == val)) {
-		DB(mv_os_printf("TWSI: Lost Arb, status %x\n", val));
-		return MV_RETRY;
-	} else if (((val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) &&
-		    (command == MV_TWSI_READ)) ||
-		   ((val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) &&
-		    (command == MV_TWSI_WRITE))) {
-		/* only in debug, since in boot we try to read the SPD of both
-		   DRAM, and we don't
-		   want error messeges in case DIMM doesn't exist. */
-		DB(mv_os_printf(
-		    "TWSI: status %x addr (7 Bit) in %s mode.\n", val,
-		    ((command == MV_TWSI_WRITE) ? "Write" : "Read")));
-		return MV_FAIL;
-	}
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* twsi_data_write - Trnasmit a data block over TWSI bus.
-*
-* DESCRIPTION:
-*       This function writes a given data block to TWSI bus in 8 bit
-*       granularity.
-*	first The function waits for interrupt flag to be active then
-*       For each 8-bit data:
-*        The function writes data to data register. It then clears
-*        interrupt flag which drives the data on the TWSI bus.
-*        The function then waits for interrupt flag to be active and status
-*        0x28 to be set.
-*
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       p_block - Data block.
-*	block_size - number of chars in p_block.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_OK - if transmiting the block completed successfully,
-*	MV_BAD_PARAM - if p_block is NULL,
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int twsi_data_transmit(uint8_t chan_num,
-			      uint8_t *p_block,
-			      uint32_t block_size)
-{
-	uint32_t timeout, temp, block_size_wr = block_size;
-
-	if (NULL == p_block)
-		return MV_BAD_PARAM;
-
-	/* wait for Int to be Set */
-	timeout = 0;
-	while (!twsi_main_int_get(chan_num) && (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(timeout,
-			     (const char *)"TWSI: Read Data Int time_out.\n"))
-		return MV_TIMEOUT;
-
-	while (block_size_wr) {
-		/* write the data */
-		mrvl_reg_write(TWSI_DATA_REG(chan_num), (uint32_t)*p_block);
-		DB(mv_os_printf(
-		    "TWSI: twsi_data_transmit place = %d write %x\n",
-		    block_size - block_size_wr, *p_block));
-		p_block++;
-		block_size_wr--;
-
-		twsi_int_flg_clr(chan_num);
-
-		/* wait for Int to be Set */
-		timeout = 0;
-		while (!twsi_main_int_get(chan_num) &&
-		       (timeout++ < TWSI_TIMEOUT_VALUE))
-			;
-
-		/* check for timeout */
-		if (MV_TRUE == twsi_timeout_chk(
-				   timeout, (const char *)"TWSI: time_out.\n"))
-			return MV_TIMEOUT;
-
-		/* check the status */
-		temp = twsi_sts_get(chan_num);
-		if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == temp) ||
-		    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA ==
-		     temp)) {
-			DB(mv_os_printf("TWSI: Lost Arb, status %x\n", temp));
-			return MV_RETRY;
-		} else if (temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) {
-			mv_os_printf("TWSI: status %x in write trans\n", temp);
-			return MV_FAIL;
-		}
-	}
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* twsi_data_receive - Receive data block from TWSI bus.
-*
-* DESCRIPTION:
-*       This function receive data block from TWSI bus in 8bit granularity
-*       into p_block buffer.
-*	first The function waits for interrupt flag to be active then
-*       For each 8-bit data:
-*        It clears the interrupt flag which allows the next data to be
-*        received from TWSI bus.
-*	 The function waits for interrupt flag to be active,
-*	 and status reg is 0x50.
-*	 Then the function reads data from data register, and copies it to
-*	 the given buffer.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       block_size - number of bytes to read.
-*
-* OUTPUT:
-*       p_block - Data block.
-*
-* RETURN:
-*       MV_OK - if receive transaction completed successfully,
-*	MV_BAD_PARAM - if p_block is NULL,
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int twsi_data_receive(uint8_t chan_num,
-			     uint8_t *p_block,
-			     uint32_t block_size)
-{
-	uint32_t timeout, temp, block_size_rd = block_size;
-
-	if (NULL == p_block)
-		return MV_BAD_PARAM;
-
-	/* wait for Int to be Set */
-	timeout = 0;
-	while (!twsi_main_int_get(chan_num) && (timeout++ < TWSI_TIMEOUT_VALUE))
-		;
-
-	/* check for timeout */
-	if (MV_TRUE ==
-	    twsi_timeout_chk(timeout,
-			     (const char *)"TWSI: Read Data int Time out .\n"))
-		return MV_TIMEOUT;
-
-	while (block_size_rd) {
-		if (block_size_rd == 1)
-			/* clear ack and Int flag */
-			mrvl_reg_bit_reset(
-				TWSI_CONTROL_REG(chan_num), TWSI_CONTROL_ACK);
-
-		twsi_int_flg_clr(chan_num);
-		/* wait for Int to be Set */
-		timeout = 0;
-		while ((!twsi_main_int_get(chan_num)) &&
-		       (timeout++ < TWSI_TIMEOUT_VALUE))
-			;
-
-		/* check for timeout */
-		if (MV_TRUE ==
-		    twsi_timeout_chk(timeout, (const char *)"TWSI: Timeout.\n"))
-			return MV_TIMEOUT;
-
-		/* check the status */
-		temp = twsi_sts_get(chan_num);
-		if ((TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA == temp) ||
-		    (TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA ==
-		     temp)) {
-			DB(mv_os_printf("TWSI: Lost Arb, status %x\n", temp));
-			return MV_RETRY;
-		} else if ((temp != TWSI_M_REC_RD_DATA_ACK_TRA) &&
-			   (block_size_rd != 1)) {
-			mv_os_printf("TWSI: status %x in read trans\n", temp);
-			return MV_FAIL;
-		} else if ((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) &&
-			   (block_size_rd == 1)) {
-			mv_os_printf("TWSI: status %x in Rd Terminate\n", temp);
-			return MV_FAIL;
-		}
-
-		/* read the data */
-		*p_block = (uint8_t)mrvl_reg_read(TWSI_DATA_REG(chan_num));
-		DB(mv_os_printf("TWSI: twsi_data_receive  place %d read %x\n",
-				block_size - block_size_rd, *p_block));
-		p_block++;
-		block_size_rd--;
-	}
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* twsi_target_offs_set - Set TWST target offset on TWSI bus.
-*
-* DESCRIPTION:
-*       The function support TWSI targets that have inside address space (for
-*       example EEPROMs). The function:
-*       1) Convert the given offset into p_block and size.
-*		in case the offset should be set to a TWSI slave which support
-*		more then 256 bytes offset, the offset setting will be done
-*		in 2 transactions.
-*       2) Use twsi_data_transmit to place those on the bus.
-*
-* INPUT:
-*	chan_num - TWSI channel
-*       offset - offset to be set on the EEPROM device.
-*	more_than256 - whether the EEPROM device support more then 256 byte
-*offset.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       MV_OK - if setting the offset completed successfully.
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int twsi_target_offs_set(uint8_t chan_num,
-				uint32_t offset,
-				uint8_t more_than256)
-{
-	uint8_t off_block[2];
-	uint32_t off_size;
-
-	if (more_than256 == MV_TRUE) {
-		off_block[0] = (offset >> 8) & 0xff;
-		off_block[1] = offset & 0xff;
-		off_size = 2;
-	} else {
-		off_block[0] = offset & 0xff;
-		off_size = 1;
-	}
-	DB(mv_os_printf(
-	    "TWSI: twsi_target_offs_set off_size = %x addr1 = %x addr2 = %x\n",
-	    off_size, off_block[0], off_block[1]));
-	return twsi_data_transmit(chan_num, off_block, off_size);
-}
-
-/*******************************************************************************
-* mv_twsi_read - Read data block from a TWSI Slave.
-*
-* DESCRIPTION:
-*       The function calls the following functions:
-*       -) mv_twsi_start_bit_set();
-*	if (EEPROM device)
-*	-) mv_twsi_addr_set(w);
-*	-) twsi_target_offs_set();
-*	-) mv_twsi_start_bit_set();
-*	-) mv_twsi_addr_set(r);
-*	-) twsi_data_receive();
-*	-) mv_twsi_stop_bit_set();
-*
-* INPUT:
-*	chan_num - TWSI channel
-*	p_twsi_slave - Twsi Slave structure.
-*	block_size - number of bytes to read.
-*
-* OUTPUT:
-*	p_block - Data block.
-*
-* RETURN:
-*	MV_OK - if EEPROM read transaction completed successfully,
-*	MV_BAD_PARAM - if p_block is NULL,
-*	MV_FAIL otherwmise.
-*
-*******************************************************************************/
-static int mv_twsi_read(uint8_t chan_num,
-			MV_TWSI_SLAVE *p_twsi_slave,
-			uint8_t *p_block,
-			uint32_t block_size)
-{
-	int rc;
-	int ret = MV_FAIL;
-	uint32_t counter = 0;
-
-	if ((NULL == p_block) || (NULL == p_twsi_slave))
-		return MV_BAD_PARAM;
-
-	do {
-		/* wait for 1 mili sec for the clear to take effect */
-		if (counter > 0)
-			mdelay(1);
-		ret = mv_twsi_start_bit_set(chan_num);
-
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			mv_twsi_stop_bit_set(chan_num);
-			DB(mv_os_printf(
-			    "mv_twsi_read:mv_twsi_start_bit_set failed\n"));
-			return MV_FAIL;
-		}
-
-		DB(mv_os_printf(
-		    "TWSI: mv_twsi_eeprom_read after mv_twsi_start_bit_set\n"));
-
-		/* in case offset exsist (i.e. eeprom ) */
-		if (MV_TRUE == p_twsi_slave->valid_offset) {
-			rc = mv_twsi_addr_set(chan_num,
-					      &(p_twsi_slave->slave_addr),
-					      MV_TWSI_WRITE);
-			if (MV_RETRY == rc)
-				continue;
-			else if (MV_OK != rc) {
-				mv_twsi_stop_bit_set(chan_num);
-				DB(mv_os_printf(
-				    "mv_twsi_addr_set(%d,0x%x,%d) rc=%d\n",
-				    chan_num,
-				    (uint32_t) &(p_twsi_slave->slave_addr),
-				    MV_TWSI_WRITE, rc));
-				return MV_FAIL;
-			}
-
-			ret =
-			    twsi_target_offs_set(chan_num, p_twsi_slave->offset,
-						 p_twsi_slave->more_than256);
-			if (MV_RETRY == ret)
-				continue;
-			else if (MV_OK != ret) {
-				mv_twsi_stop_bit_set(chan_num);
-				DB(mv_os_printf(
-				    "TWSI: twsi_target_offs_set Failed\n"));
-				return MV_FAIL;
-			}
-			DB(mv_os_printf("TWSI: after twsi_target_offs_set\n"));
-			ret = mv_twsi_start_bit_set(chan_num);
-			if (MV_RETRY == ret)
-				continue;
-			else if (MV_OK != ret) {
-				mv_twsi_stop_bit_set(chan_num);
-				DB(mv_os_printf(
-				    "TWSI: mv_twsi_start_bit_set failed\n"));
-				return MV_FAIL;
-			}
-			DB(mv_os_printf("TWSI: after mv_twsi_start_bit_set\n"));
-		}
-		ret = mv_twsi_addr_set(chan_num, &(p_twsi_slave->slave_addr),
-				       MV_TWSI_READ);
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			mv_twsi_stop_bit_set(chan_num);
-			DB(mv_os_printf(
-			    "mv_twsi_read: mv_twsi_addr_set 2 Failed\n"));
-			return MV_FAIL;
-		}
-		DB(mv_os_printf(
-		    "TWSI: mv_twsi_eeprom_read after mv_twsi_addr_set\n"));
-
-		ret = twsi_data_receive(chan_num, p_block, block_size);
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			mv_twsi_stop_bit_set(chan_num);
-			DB(mv_os_printf(
-			    "mv_twsi_read: twsi_data_receive Failed\n"));
-			return MV_FAIL;
-		}
-		DB(mv_os_printf(
-		    "TWSI: mv_twsi_eeprom_read after twsi_data_receive\n"));
-
-		ret = mv_twsi_stop_bit_set(chan_num);
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			DB(mv_os_printf(
-			    "mv_twsi_read: mv_twsi_stop_bit_set 3 Failed\n"));
-			return MV_FAIL;
-		}
-		counter++;
-	} while ((MV_RETRY == ret) && (counter < MAX_RETRY_CNT));
-
-	if (counter == MAX_RETRY_CNT)
-		DB(mv_os_printf("mv_twsi_write: Retry Expire\n"));
-
-	twsi_ack_bit_set(chan_num);
-
-	DB(mv_os_printf(
-	    "TWSI: mv_twsi_eeprom_read after mv_twsi_stop_bit_set\n"));
-
-	return MV_OK;
-}
-
-/*******************************************************************************
-* mv_twsi_write - Write data block to a TWSI Slave.
-*
-* DESCRIPTION:
-*       The function calls the following functions:
-*       -) mv_twsi_start_bit_set();
-*       -) mv_twsi_addr_set();
-*	-)if (EEPROM device)
-*	-) twsi_target_offs_set();
-*       -) twsi_data_transmit();
-*       -) mv_twsi_stop_bit_set();
-*
-* INPUT:
-*	chan_num - TWSI channel
-*	eeprom_address - eeprom address.
-*       block_size - number of bytes to write.
-*	p_block - Data block.
-*
-* OUTPUT:
-*	None
-*
-* RETURN:
-*       MV_OK - if EEPROM read transaction completed successfully.
-*	MV_BAD_PARAM - if p_block is NULL,
-*	MV_FAIL otherwmise.
-*
-* NOTE: Part of the EEPROM, required that the offset will be aligned to the
-*	max write burst supported.
-*******************************************************************************/
-static int mv_twsi_write(uint8_t chan_num,
-			 MV_TWSI_SLAVE *p_twsi_slave,
-			 uint8_t *p_block,
-			 uint32_t block_size)
-{
-	int ret = MV_FAIL;
-	uint32_t counter = 0;
-
-	if ((NULL == p_block) || (NULL == p_twsi_slave))
-		return MV_BAD_PARAM;
-
-	do {
-		if (counter >
-		    0) /* wait for 1 mili sec for the clear to take effect */
-			mdelay(1);
-		ret = mv_twsi_start_bit_set(chan_num);
-
-		if (MV_RETRY == ret)
-			continue;
-
-		else if (MV_OK != ret) {
-			mv_twsi_stop_bit_set(chan_num);
-			DB(mv_os_printf(
-			    "mv_twsi_write: mv_twsi_start_bit_set failed\n"));
-			return MV_FAIL;
-		}
-
-		ret = mv_twsi_addr_set(chan_num, &(p_twsi_slave->slave_addr),
-				       MV_TWSI_WRITE);
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			mv_twsi_stop_bit_set(chan_num);
-			DB(mv_os_printf(
-			    "mv_twsi_write: mv_twsi_addr_set failed\n"));
-			return MV_FAIL;
-		}
-
-		/* in case offset exsist (i.e. eeprom ) */
-		if (MV_TRUE == p_twsi_slave->valid_offset) {
-			ret =
-			    twsi_target_offs_set(chan_num, p_twsi_slave->offset,
-						 p_twsi_slave->more_than256);
-			if (MV_RETRY == ret)
-				continue;
-			else if (MV_OK != ret) {
-				mv_twsi_stop_bit_set(chan_num);
-				DB(mv_os_printf(
-				    "TWSI: twsi_target_offs_set failed\n"));
-				return MV_FAIL;
-			}
-		}
-
-		ret = twsi_data_transmit(chan_num, p_block, block_size);
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			mv_twsi_stop_bit_set(chan_num);
-			DB(mv_os_printf(
-			    "mv_twsi_write: twsi_data_transmit failed\n"));
-			return MV_FAIL;
-		}
-		ret = mv_twsi_stop_bit_set(chan_num);
-		if (MV_RETRY == ret)
-			continue;
-		else if (MV_OK != ret) {
-			DB(mv_os_printf(
-			    "mv_twsi_write: failed to set stopbit\n"));
-			return MV_FAIL;
-		}
-		counter++;
-	} while ((MV_RETRY == ret) && (counter < MAX_RETRY_CNT));
-
-	if (counter == MAX_RETRY_CNT)
-		DB(mv_os_printf("mv_twsi_write: Retry Expire\n"));
-
-	return MV_OK;
-}
-
-static int i2c_init(unsigned bus)
-{
-	if (bus >= MAX_I2C_NUM)
-		return 1;
-
-	if (!m_initialized[bus]) {
-		/* TWSI init */
-		MV_TWSI_ADDR slave;
-
-		slave.type = ADDR7_BIT;
-		slave.address = 0;
-		mv_twsi_init(bus, TWSI_SPEED, mv_tclk_get(), &slave, 0);
-		m_initialized[bus] = 1;
-	}
-
-	return 0;
-}
-
-static void i2c_reset(unsigned bus)
-{
-	if (bus < MAX_I2C_NUM)
-		m_initialized[bus] = 0;
-}
-
-int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count)
-{
-	struct i2c_seg *seg = segments;
-	int ret = 0;
-	MV_TWSI_SLAVE twsi_slave;
-
-	if (i2c_init(bus))
-		return 1;
-
-	while (!ret && seg_count--) {
-		twsi_slave.slave_addr.address = seg->chip;
-		twsi_slave.slave_addr.type = ADDR7_BIT;
-		twsi_slave.more_than256 = MV_FALSE;
-		twsi_slave.valid_offset = MV_FALSE;
-		if (seg->read)
-			ret =
-			    mv_twsi_read(bus, &twsi_slave, seg->buf, seg->len);
-		else
-			ret =
-			    mv_twsi_write(bus, &twsi_slave, seg->buf, seg->len);
-		seg++;
-	}
-
-	if (ret) {
-		i2c_reset(bus);
-		DB(mv_os_printf("mv_twsi_read/mv_twsi_write failed\n"));
-		return 1;
-	}
-
-	return 0;
-}
diff --git a/src/soc/marvell/armada38x/include/soc/clock.h b/src/soc/marvell/armada38x/include/soc/clock.h
deleted file mode 100644
index 82af93724b..0000000000
--- a/src/soc/marvell/armada38x/include/soc/clock.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_ARMADA38X_CLOCK_H_
-#define __SOC_MARVELL_ARMADA38X_CLOCK_H_
-
-uint32_t mv_tclk_get(void);
-
-#endif  // __SOC_MARVELL_ARMADA38X_CLOCK_H_
diff --git a/src/soc/marvell/armada38x/include/soc/common.h b/src/soc/marvell/armada38x/include/soc/common.h
deleted file mode 100644
index 3a8799cf7e..0000000000
--- a/src/soc/marvell/armada38x/include/soc/common.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Marvell Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_ARMADA38X_COMMON_H_
-#define __SOC_MARVELL_ARMADA38X_COMMON_H_
-
-#include <types.h>
-#include <arch/io.h>
-
-#define INTER_REGS_BASE 0xF1000000
-
-#define MV_TRUE (1)
-#define MV_FALSE (0)
-
-/* The following is a list of Marvell status    */
-#define MV_ERROR (-1)
-#define MV_OK (0)
-#define MV_FAIL (1)
-#define MV_BAD_VALUE (2)
-#define MV_OUT_OF_RANGE (3)
-#define MV_BAD_PARAM (4)
-#define MV_BAD_PTR (5)
-#define MV_BAD_SIZE (6)
-#define MV_BAD_STATE (7)
-#define MV_SET_ERROR (8)
-#define MV_GET_ERROR (9)
-#define MV_CREATE_ERROR (10)
-#define MV_NOT_FOUND (11)
-#define MV_NO_MORE (12)
-#define MV_NO_SUCH (13)
-#define MV_TIMEOUT (14)
-#define MV_NO_CHANGE (15)
-#define MV_NOT_SUPPORTED (16)
-#define MV_NOT_IMPLEMENTED (17)
-#define MV_NOT_INITIALIZED (18)
-#define MV_NO_RESOURCE (19)
-#define MV_FULL (20)
-#define MV_EMPTY (21)
-#define MV_INIT_ERROR (22)
-#define MV_HW_ERROR (23)
-#define MV_TX_ERROR (24)
-#define MV_RX_ERROR (25)
-#define MV_NOT_READY (26)
-#define MV_ALREADY_EXIST (27)
-#define MV_OUT_OF_CPU_MEM (28)
-#define MV_NOT_STARTED (29)
-#define MV_BUSY (30)
-#define MV_TERMINATE (31)
-#define MV_NOT_ALIGNED (32)
-#define MV_NOT_ALLOWED (33)
-#define MV_WRITE_PROTECT (34)
-#define MV_DROPPED (35)
-#define MV_STOLEN (36)
-#define MV_CONTINUE (37)
-#define MV_RETRY (38)
-
-#define MV_INVALID (int)(-1)
-
-#define MV_BOARD_TCLK_200MHZ 200000000
-#define MV_BOARD_TCLK_250MHZ 250000000
-
-#define MPP_SAMPLE_AT_RESET (0x18600)
-
-#define MV_6810_DEV_ID 0x6810
-
-#define BIT0        0x00000001
-#define BIT1        0x00000002
-#define BIT2        0x00000004
-#define BIT3        0x00000008
-#define BIT4        0x00000010
-#define BIT5        0x00000020
-#define BIT6        0x00000040
-#define BIT7        0x00000080
-#define BIT8        0x00000100
-#define BIT9        0x00000200
-#define BIT10       0x00000400
-#define BIT11       0x00000800
-#define BIT12       0x00001000
-#define BIT13       0x00002000
-#define BIT14       0x00004000
-#define BIT15       0x00008000
-#define BIT16       0x00010000
-#define BIT17       0x00020000
-#define BIT18       0x00040000
-#define BIT19       0x00080000
-#define BIT20       0x00100000
-#define BIT21       0x00200000
-#define BIT22       0x00400000
-#define BIT23       0x00800000
-#define BIT24       0x01000000
-#define BIT25       0x02000000
-#define BIT26       0x04000000
-#define BIT27       0x08000000
-#define BIT28       0x10000000
-#define BIT29       0x20000000
-#define BIT30       0x40000000
-#define BIT31       0x80000000
-
-static inline uint32_t mrvl_reg_read(uint32_t offset)
-{
-	return read32((void *)(INTER_REGS_BASE + offset));
-}
-static inline void mrvl_reg_write(uint32_t offset, uint32_t val)
-{
-	write32((void *)(INTER_REGS_BASE + offset), val);
-}
-static inline void mrvl_reg_bit_set(uint32_t offset, uint32_t bit_mask)
-{
-	mrvl_reg_write(offset, (mrvl_reg_read(offset) | bit_mask));
-}
-static inline void mrvl_reg_bit_reset(uint32_t offset, uint32_t bit_mask)
-{
-	mrvl_reg_write(offset, (mrvl_reg_read(offset) & (~bit_mask)));
-}
-
-#endif  // __SOC_MARVELL_ARMADA38X_COMMON_H__
diff --git a/src/soc/marvell/armada38x/include/soc/gpio.h b/src/soc/marvell/armada38x/include/soc/gpio.h
deleted file mode 100644
index e3cd7c0602..0000000000
--- a/src/soc/marvell/armada38x/include/soc/gpio.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_ARMADA38X_GPIO_H_
-#define __SOC_MARVELL_ARMADA38X_GPIO_H_
-
-#include <types.h>
-
-typedef u32 gpio_t;
-
-#endif  // __SOC_MARVELL_ARMADA38X_GPIO_H__
diff --git a/src/soc/marvell/armada38x/include/soc/i2c.h b/src/soc/marvell/armada38x/include/soc/i2c.h
deleted file mode 100644
index 7de29534b6..0000000000
--- a/src/soc/marvell/armada38x/include/soc/i2c.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Marvell Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_ARMADA38X_I2C_H_
-#define __SOC_MARVELL_ARMADA38X_I2C_H_
-
-#include <types.h>
-
-#define TWSI_SPEED 100000
-
-#define MAX_I2C_NUM 2
-#define MAX_RETRY_CNT 1000
-#define TWSI_TIMEOUT_VALUE 0x500
-
-#define MV_TWSI_SLAVE_REGS_OFFSET(chan_num) (0x11000 + (chan_num * 0x100))
-#define MV_TWSI_SLAVE_REGS_BASE(unit) (MV_TWSI_SLAVE_REGS_OFFSET(unit))
-#define TWSI_SLAVE_ADDR_REG(chan_num) (MV_TWSI_SLAVE_REGS_BASE(chan_num) + 0x00)
-
-#define MV_CPUIF_REGS_OFFSET(cpu) (0x21800 + (cpu)*0x100)
-#define MV_CPUIF_REGS_BASE(cpu) (MV_CPUIF_REGS_OFFSET(cpu))
-#define CPU_MAIN_INT_CAUSE_REG(vec, cpu) \
-	(MV_CPUIF_REGS_BASE(cpu) + 0x80 + (vec * 0x4))
-#define CPU_MAIN_INT_TWSI_OFFS(i) (2 + i)
-#define CPU_MAIN_INT_CAUSE_TWSI(i) (31 + i)
-#define TWSI_CPU_MAIN_INT_CAUSE_REG(cpu) CPU_MAIN_INT_CAUSE_REG(1, (cpu))
-#define MV_TWSI_CPU_MAIN_INT_CAUSE(ch_num, cpu) TWSI_CPU_MAIN_INT_CAUSE_REG(cpu)
-
-#define MV_MBUS_REGS_OFFSET (0x20000)
-#define MV_CPUIF_SHARED_REGS_BASE (MV_MBUS_REGS_OFFSET)
-#define CPU_INT_SOURCE_CONTROL_REG(i) \
-	(MV_CPUIF_SHARED_REGS_BASE + 0xB00 + (i * 0x4))
-
-#define CPU_INT_SOURCE_CONTROL_IRQ_OFFS 28
-#define CPU_INT_SOURCE_CONTROL_IRQ_MASK (1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS)
-
-#define TWSI_SLAVE_ADDR_GCE_ENA BIT(0)
-#define TWSI_SLAVE_ADDR_7_BIT_OFFS 0x1
-#define TWSI_SLAVE_ADDR_7_BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7_BIT_OFFS)
-#define TWSI_SLAVE_ADDR_10_BIT_OFFS 0x7
-#define TWSI_SLAVE_ADDR_10_BIT_MASK 0x300
-#define TWSI_SLAVE_ADDR_10_BIT_CONST 0xF0
-
-#define TWSI_DATA_REG(chan_num) (MV_TWSI_SLAVE_REGS_BASE(chan_num) + 0x04)
-#define TWSI_DATA_COMMAND_OFFS 0x0
-#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS)
-#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS)
-#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS)
-#define TWSI_DATA_ADDR_7_BIT_OFFS 0x1
-#define TWSI_DATA_ADDR_7_BIT_MASK (0xFF << TWSI_DATA_ADDR_7_BIT_OFFS)
-#define TWSI_DATA_ADDR_10_BIT_OFFS 0x7
-#define TWSI_DATA_ADDR_10_BIT_MASK 0x300
-#define TWSI_DATA_ADDR_10_BIT_CONST 0xF0
-
-#define TWSI_CONTROL_REG(chan_num) (MV_TWSI_SLAVE_REGS_BASE(chan_num) + 0x08)
-#define TWSI_CONTROL_ACK BIT(2)
-#define TWSI_CONTROL_INT_FLAG_SET BIT(3)
-#define TWSI_CONTROL_STOP_BIT BIT(4)
-#define TWSI_CONTROL_START_BIT BIT(5)
-#define TWSI_CONTROL_ENA BIT(6)
-#define TWSI_CONTROL_INT_ENA BIT(7)
-
-#define TWSI_STATUS_BAUDE_RATE_REG(chan_num) \
-	(MV_TWSI_SLAVE_REGS_BASE(chan_num) + 0x0c)
-#define TWSI_BAUD_RATE_N_OFFS 0
-#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS)
-#define TWSI_BAUD_RATE_M_OFFS 3
-#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS)
-
-#define TWSI_EXTENDED_SLAVE_ADDR_REG(chan_num) \
-	(MV_TWSI_SLAVE_REGS_BASE(chan_num) + 0x10)
-#define TWSI_EXTENDED_SLAVE_OFFS 0
-#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS)
-
-#define TWSI_SOFT_RESET_REG(chan_num) (MV_TWSI_SLAVE_REGS_BASE(chan_num) + 0x1c)
-
-#define TWSI_BUS_ERROR 0x00
-#define TWSI_START_CON_TRA 0x08
-#define TWSI_REPEATED_START_CON_TRA 0x10
-#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18
-#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20
-#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28
-#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30
-#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38
-#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40
-#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48
-#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50
-#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58
-#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60
-#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68
-#define TWSI_GNL_CALL_REC_ACK_TRA 0x70
-#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78
-#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80
-#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88
-#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90
-#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98
-#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0
-#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8
-#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0
-#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8
-#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0
-#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8
-#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0
-#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8
-#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0
-#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8
-#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8
-
-#endif  // __SOC_MARVELL_ARMADA38X_I2C_H__
diff --git a/src/soc/marvell/armada38x/include/soc/memlayout.ld b/src/soc/marvell/armada38x/include/soc/memlayout.ld
deleted file mode 100644
index b7f34eac71..0000000000
--- a/src/soc/marvell/armada38x/include/soc/memlayout.ld
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	DRAM_START(0x00000000)
-	BOOTBLOCK(0x00000000, 24K)
-	RAMSTAGE(0x00800000, 128K)
-	CBFS_CACHE(0x12006000, 80K)
-	STACK(0x1201c000, 16K)
-
-	VERSTAGE(0x1202c000, 96K)
-	ROMSTAGE(0x12044000, 96K)
-	VBOOT2_WORK(0x1205c000, 16K)
-	DMA_COHERENT(0x12100000, 2M)
-	SYMBOL(memlayout_cbmem_top, 0x1F400000)
-	TTB(0x1FF00000, 16K)
-	TTB_SUBTABLES(0x1FF04000, 2K)
-}
diff --git a/src/soc/marvell/armada38x/include/soc/soc_services.h b/src/soc/marvell/armada38x/include/soc/soc_services.h
deleted file mode 100644
index 2659961c29..0000000000
--- a/src/soc/marvell/armada38x/include/soc/soc_services.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_ARMADA38X_SOC_SERVICES_H_
-#define __SOC_MARVELL_ARMADA38X_SOC_SERVICES_H_
-
-#include <types.h>
-
-extern u8 _memlayout_cbmem_top[];
-
-#endif /*__SOC_MARVELL_ARMADA38X_SOC_SERVICES_H_*/
diff --git a/src/soc/marvell/armada38x/monotonic_timer.c b/src/soc/marvell/armada38x/monotonic_timer.c
deleted file mode 100644
index 49fa6cd76f..0000000000
--- a/src/soc/marvell/armada38x/monotonic_timer.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <timer.h>
-#include <delay.h>
-
-#define TIMER_CTRL_REG 0xf1020300
-#define TIMER_RELOAD_REG 0xf1020310
-#define TIMER_REG 0xf1020314
-#define TIMER_RELOAD_VALUE 0xffffffff
-
-#define MHZ_NUM 25
-
-void init_timer(void)
-{
-	unsigned int reg;
-
-	/* Set the reload timer */
-	write32((void *)TIMER_RELOAD_REG, TIMER_RELOAD_VALUE);
-	/* Set the initial value to TIMER_RELOAD_VALUE - 1
-	 * (instead of TIMER_RELOAD_VALUE) to avoid 'fake'
-	 * overflow being detected in timer_monotonic_get
-	 * if it's called close enough with 'this' function */
-	write32((void *)TIMER_REG, TIMER_RELOAD_VALUE - 1);
-	reg = read32((const void *)TIMER_CTRL_REG);
-	/* Let it start counting */
-	reg |= 0x3;
-	write32((void *)TIMER_CTRL_REG, reg);
-}
-
-void timer_monotonic_get(struct mono_time *mt)
-{
-	static uint64_t total_ticks = 0;
-	uint64_t overflow = 0;
-	uint32_t current_ticks =
-		TIMER_RELOAD_VALUE - read32((const void *)TIMER_REG);
-
-	/* Assuming at most one overflow happened since last call */
-	if (current_ticks <= total_ticks)
-		overflow = 1ULL << 32;
-
-	total_ticks = (((total_ticks + overflow) >> 32) << 32) + current_ticks;
-	mono_time_set_usecs(mt, total_ticks / MHZ_NUM);
-}
diff --git a/src/soc/marvell/armada38x/soc.c b/src/soc/marvell/armada38x/soc.c
deleted file mode 100644
index d049391b8e..0000000000
--- a/src/soc/marvell/armada38x/soc.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <symbols.h>
-
-#define RESERVED_SIZE_KB (1 * KiB)
-
-static void soc_enable(device_t dev)
-{
-	/* Reserve bottom 1M bytes for MMU/TTB */
-	reserved_ram_resource(dev, 0, ((uintptr_t)_dram / KiB +
-	    (CONFIG_DRAM_SIZE_MB * KiB - RESERVED_SIZE_KB)),
-	    RESERVED_SIZE_KB);
-	ram_resource(dev, 0, (uintptr_t)_dram / KiB,
-		     (CONFIG_DRAM_SIZE_MB * KiB) - RESERVED_SIZE_KB);
-}
-
-static void soc_init(device_t dev)
-{
-	printk(BIOS_INFO, "CPU: Armada 38X\n");
-}
-
-static struct device_operations soc_ops = {
-	.read_resources = DEVICE_NOOP,
-	.set_resources = DEVICE_NOOP,
-	.enable_resources = soc_enable,
-	.init = soc_init,
-	.scan_bus = 0,
-};
-
-static void enable_armada38x_dev(device_t dev)
-{
-	dev->ops = &soc_ops;
-}
-
-struct chip_operations soc_marvell_armada38x_ops = {
-	CHIP_NAME("SOC Marvell Armada 38x")
-	.enable_dev = enable_armada38x_dev,
-};
diff --git a/src/soc/marvell/armada38x/spi.c b/src/soc/marvell/armada38x/spi.c
deleted file mode 100644
index 47631f4c69..0000000000
--- a/src/soc/marvell/armada38x/spi.c
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Marvell Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <delay.h>
-#include <spi_flash.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include <console/console.h>
-#include <soc/common.h>
-#include <soc/clock.h>
-
-/******************************************************************************
-base type define
-*******************************************************************************/
-#define MV_SPI_REG_READ mrvl_reg_read
-#define MV_SPI_REG_WRITE mrvl_reg_write
-#define MV_SPI_REG_BIT_SET mrvl_reg_bit_set
-#define MV_SPI_REG_BIT_RESET mrvl_reg_bit_reset
-
-#define MV_SPI_REGS_OFFSET(unit) (0x10600 + (unit * 0x80))
-#define MV_SPI_REGS_BASE(unit) (MV_SPI_REGS_OFFSET(unit))
-#define MV_SPI_IF_CONFIG_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x04)
-#define MV_SPI_SPR_OFFSET 0
-#define MV_SPI_SPR_MASK (0xF << MV_SPI_SPR_OFFSET)
-#define MV_SPI_SPPR_0_OFFSET 4
-#define MV_SPI_SPPR_0_MASK (0x1 << MV_SPI_SPPR_0_OFFSET)
-#define MV_SPI_SPPR_HI_OFFSET 6
-#define MV_SPI_SPPR_HI_MASK (0x3 << MV_SPI_SPPR_HI_OFFSET)
-
-#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */
-#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET)
-
-#define MV_SPI_IF_CTRL_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x00)
-#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */
-#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET)
-
-#define MV_SPI_CS_NUM_OFFSET 2
-#define MV_SPI_CS_NUM_MASK (0x7 << MV_SPI_CS_NUM_OFFSET)
-#define MV_SPI_CPOL_OFFSET 11
-#define MV_SPI_CPOL_MASK (0x1 << MV_SPI_CPOL_OFFSET)
-#define MV_SPI_CPHA_OFFSET 12
-#define MV_SPI_CPHA_MASK (0x1 << MV_SPI_CPHA_OFFSET)
-#define MV_SPI_TXLSBF_OFFSET 13
-#define MV_SPI_TXLSBF_MASK (0x1 << MV_SPI_TXLSBF_OFFSET)
-#define MV_SPI_RXLSBF_OFFSET 14
-#define MV_SPI_RXLSBF_MASK (0x1 << MV_SPI_RXLSBF_OFFSET)
-
-/* SPI transfer flags */
-#define SPI_XFER_BEGIN 0x01
-#define SPI_XFER_END 0x02
-
-#define MV_SPI_INT_CAUSE_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x10)
-#define MV_SPI_DATA_OUT_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x08)
-#define MV_SPI_WAIT_RDY_MAX_LOOP 100000
-#define MV_SPI_DATA_IN_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x0c)
-
-#define MV_SPI_TMNG_PARAMS_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x18)
-#define MV_SPI_TMISO_SAMPLE_OFFSET 6
-#define MV_SPI_TMISO_SAMPLE_MASK (0x3 << MV_SPI_TMISO_SAMPLE_OFFSET)
-
-#define CONFIG_ENV_SPI_MAX_HZ 50000000
-#define CONFIG_SF_DEFAULT_SPEED CONFIG_ENV_SPI_MAX_HZ
-
-#define CMD_READ_ARRAY_FAST 0x0b
-
-/******************************************************************************
-base type define end
-*******************************************************************************/
-
-/******************************************************************************
-struct define
-*******************************************************************************/
-typedef enum {
-	SPI_TYPE_FLASH = 0,
-	SPI_TYPE_SLIC_ZARLINK_SILABS,
-	SPI_TYPE_SLIC_LANTIQ,
-	SPI_TYPE_SLIC_ZSI,
-	SPI_TYPE_SLIC_ISI
-} MV_SPI_TYPE;
-
-typedef struct {
-	unsigned short ctrl_model;
-	unsigned int tclk;
-} MV_SPI_HAL_DATA;
-
-typedef struct {
-	int clock_pol_low;
-	enum { SPI_CLK_HALF_CYC, SPI_CLK_BEGIN_CYC } clock_phase;
-	int tx_msb_first;
-	int rx_msb_first;
-} MV_SPI_IF_PARAMS;
-
-typedef struct {
-	/* Does this device support 16 bits access */
-	int en16_bit;
-	/* should we assert / disassert CS for each byte we read / write */
-	int byte_cs_asrt;
-	int clock_pol_low;
-	unsigned int baud_rate;
-	unsigned int clk_phase;
-} MV_SPI_TYPE_INFO;
-
-/******************************************************************************
-struct define end
-*******************************************************************************/
-
-/******************************************************************************
-param define
-*******************************************************************************/
-static MV_SPI_HAL_DATA spi_hal_data;
-static MV_SPI_TYPE_INFO *curr_spi_info = NULL;
-static MV_SPI_TYPE_INFO spi_types[] = { {.en16_bit = MV_TRUE,
-				       .clock_pol_low = MV_TRUE,
-				       .byte_cs_asrt = MV_FALSE,
-				       .baud_rate = (20 << 20), /*  20_m */
-				       .clk_phase = SPI_CLK_BEGIN_CYC},
-				      {.en16_bit = MV_FALSE,
-				       .clock_pol_low = MV_TRUE,
-				       .byte_cs_asrt = MV_TRUE,
-				       .baud_rate = 0x00800000,
-				       .clk_phase = SPI_CLK_BEGIN_CYC},
-				      {.en16_bit = MV_FALSE,
-				       .clock_pol_low = MV_TRUE,
-				       .byte_cs_asrt = MV_FALSE,
-				       .baud_rate = 0x00800000,
-				       .clk_phase = SPI_CLK_BEGIN_CYC},
-				      {.en16_bit = MV_FALSE,
-				       .clock_pol_low = MV_TRUE,
-				       .byte_cs_asrt = MV_TRUE,
-				       .baud_rate = 0x00800000,
-				       .clk_phase = SPI_CLK_HALF_CYC},
-				      {.en16_bit = MV_FALSE,
-				       .clock_pol_low = MV_FALSE,
-				       .byte_cs_asrt = MV_TRUE,
-				       .baud_rate = 0x00200000,
-				       .clk_phase = SPI_CLK_HALF_CYC} };
-
-/******************************************************************************
-param define end
-*******************************************************************************/
-
-static int mv_spi_baud_rate_set(unsigned char spi_id,
-			unsigned int serial_baud_rate);
-static void mv_spi_cs_deassert(unsigned char spi_id);
-static int mv_spi_cs_set(unsigned char spi_id, unsigned char cs_id);
-static int mv_spi_if_config_set(unsigned char spi_id,
-			MV_SPI_IF_PARAMS *if_params);
-static int mv_spi_params_set(unsigned char spi_id,
-			  unsigned char cs_id,
-			  MV_SPI_TYPE type);
-static int mv_spi_init(unsigned char spi_id,
-		     unsigned char cs_id,
-		     unsigned int serial_baud_rate,
-		     MV_SPI_HAL_DATA *hal_data);
-static int mv_spi_sys_init(unsigned char spi_id,
-		    unsigned char cs_id,
-		    unsigned int serial_baud_rate);
-static void mv_spi_cs_assert(unsigned char spi_id);
-static int mv_spi_8bit_data_tx_rx(unsigned char spi_id,
-			     unsigned char tx_data,
-			     unsigned char *p_rx_data);
-
-int mv_spi_baud_rate_set(unsigned char spi_id, unsigned int serial_baud_rate)
-{
-	unsigned int spr, sppr;
-	unsigned int divider;
-	unsigned int best_spr = 0, best_sppr = 0;
-	unsigned char exact_match = 0;
-	unsigned int min_baud_offset = 0xFFFFFFFF;
-	unsigned int cpu_clk = spi_hal_data.tclk; /*mv_cpu_pclk_get();*/
-	unsigned int temp_reg;
-
-	assert(cpu_clk != serial_baud_rate);
-	/* Find the best prescale configuration - less or equal */
-	for (spr = 1; spr <= 15; spr++) {
-		for (sppr = 0; sppr <= 7; sppr++) {
-			divider = spr * (1 << sppr);
-			/* check for higher - irrelevant */
-			if ((cpu_clk / divider) > serial_baud_rate)
-				continue;
-
-			/* check for exact fit */
-			if ((cpu_clk / divider) == serial_baud_rate) {
-				best_spr = spr;
-				best_sppr = sppr;
-				exact_match = 1;
-				break;
-			}
-
-			/* check if this is better than the previous one */
-			if ((serial_baud_rate - (cpu_clk / divider)) <
-			    min_baud_offset) {
-				min_baud_offset =
-				    serial_baud_rate - cpu_clk / divider;
-				best_spr = spr;
-				best_sppr = sppr;
-			}
-		}
-
-		if (exact_match == 1)
-			break;
-	}
-
-	if (best_spr == 0) {
-		printk(BIOS_INFO, "%s ERROR: SPI baud rate prescale error!\n",
-		       __func__);
-		return MV_OUT_OF_RANGE;
-	}
-
-	/* configure the Prescale */
-	temp_reg = MV_SPI_REG_READ(MV_SPI_IF_CONFIG_REG(spi_id)) &
-		  ~(MV_SPI_SPR_MASK | MV_SPI_SPPR_0_MASK | MV_SPI_SPPR_HI_MASK);
-	temp_reg |= ((best_spr << MV_SPI_SPR_OFFSET) |
-		    ((best_sppr & 0x1) << MV_SPI_SPPR_0_OFFSET) |
-		    ((best_sppr >> 1) << MV_SPI_SPPR_HI_OFFSET));
-	MV_SPI_REG_WRITE(MV_SPI_IF_CONFIG_REG(spi_id), temp_reg);
-
-	return MV_OK;
-}
-
-void mv_spi_cs_deassert(unsigned char spi_id)
-{
-	MV_SPI_REG_BIT_RESET(MV_SPI_IF_CTRL_REG(spi_id), MV_SPI_CS_ENABLE_MASK);
-}
-
-int mv_spi_cs_set(unsigned char spi_id, unsigned char cs_id)
-{
-	unsigned int ctrl_reg;
-	static unsigned char last_cs_id = 0xFF;
-	static unsigned char last_spi_id = 0xFF;
-
-	if (cs_id > 7)
-		return MV_BAD_PARAM;
-
-	if ((last_spi_id == spi_id) && (last_cs_id == cs_id))
-		return MV_OK;
-
-	ctrl_reg = MV_SPI_REG_READ(MV_SPI_IF_CTRL_REG(spi_id));
-	ctrl_reg &= ~MV_SPI_CS_NUM_MASK;
-	ctrl_reg |= (cs_id << MV_SPI_CS_NUM_OFFSET);
-	MV_SPI_REG_WRITE(MV_SPI_IF_CTRL_REG(spi_id), ctrl_reg);
-
-	last_spi_id = spi_id;
-	last_cs_id = cs_id;
-
-	return MV_OK;
-}
-
-int mv_spi_if_config_set(unsigned char spi_id, MV_SPI_IF_PARAMS *if_params)
-{
-	unsigned int ctrl_reg;
-
-	ctrl_reg = MV_SPI_REG_READ(MV_SPI_IF_CONFIG_REG(spi_id));
-
-	/* Set Clock Polarity */
-	ctrl_reg &= ~(MV_SPI_CPOL_MASK | MV_SPI_CPHA_MASK | MV_SPI_TXLSBF_MASK |
-		     MV_SPI_RXLSBF_MASK);
-	if (if_params->clock_pol_low)
-		ctrl_reg |= MV_SPI_CPOL_MASK;
-
-	if (if_params->clock_phase == SPI_CLK_BEGIN_CYC)
-		ctrl_reg |= MV_SPI_CPHA_MASK;
-
-	if (if_params->tx_msb_first)
-		ctrl_reg |= MV_SPI_TXLSBF_MASK;
-
-	if (if_params->rx_msb_first)
-		ctrl_reg |= MV_SPI_RXLSBF_MASK;
-
-	MV_SPI_REG_WRITE(MV_SPI_IF_CONFIG_REG(spi_id), ctrl_reg);
-
-	return MV_OK;
-}
-
-int mv_spi_params_set(unsigned char spi_id,
-		unsigned char cs_id,
-		MV_SPI_TYPE type)
-{
-	MV_SPI_IF_PARAMS if_params;
-
-	if (MV_OK != mv_spi_cs_set(spi_id, cs_id)) {
-		printk(BIOS_INFO, "Error, setting SPI CS failed\n");
-		return MV_ERROR;
-	}
-
-	if (curr_spi_info != (&(spi_types[type]))) {
-		curr_spi_info = &(spi_types[type]);
-		mv_spi_baud_rate_set(spi_id, curr_spi_info->baud_rate);
-
-		if_params.clock_pol_low = curr_spi_info->clock_pol_low;
-		if_params.clock_phase = curr_spi_info->clk_phase;
-		if_params.tx_msb_first = MV_FALSE;
-		if_params.rx_msb_first = MV_FALSE;
-		mv_spi_if_config_set(spi_id, &if_params);
-	}
-
-	return MV_OK;
-}
-
-int mv_spi_init(unsigned char spi_id,
-	      unsigned char cs_id,
-	      unsigned int serial_baud_rate,
-	      MV_SPI_HAL_DATA *hal_data)
-{
-	int ret;
-	unsigned int timing_reg;
-
-	spi_hal_data.ctrl_model = hal_data->ctrl_model;
-	spi_hal_data.tclk = hal_data->tclk;
-
-	/* Set the serial clock */
-	ret = mv_spi_baud_rate_set(spi_id, serial_baud_rate);
-	if (ret != MV_OK)
-		return ret;
-
-	/* Configure the default SPI mode to be 8bit */
-	MV_SPI_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG(spi_id),
-			   MV_SPI_BYTE_LENGTH_MASK);
-
-	timing_reg = MV_SPI_REG_READ(MV_SPI_TMNG_PARAMS_REG(spi_id));
-	timing_reg &= ~MV_SPI_TMISO_SAMPLE_MASK;
-	timing_reg |= (0x2) << MV_SPI_TMISO_SAMPLE_OFFSET;
-	MV_SPI_REG_WRITE(MV_SPI_TMNG_PARAMS_REG(spi_id), timing_reg);
-
-	/* Verify that the CS is deasserted */
-	mv_spi_cs_deassert(spi_id);
-
-	mv_spi_params_set(spi_id, cs_id, SPI_TYPE_FLASH);
-
-	return MV_OK;
-}
-
-int mv_spi_sys_init(unsigned char spi_id,
-		unsigned char cs_id,
-		unsigned int serial_baud_rate)
-{
-	MV_SPI_HAL_DATA hal_data;
-
-	hal_data.ctrl_model = MV_6810_DEV_ID;
-	hal_data.tclk = mv_tclk_get();
-
-	return mv_spi_init(spi_id, cs_id, serial_baud_rate, &hal_data);
-}
-
-void mv_spi_cs_assert(unsigned char spi_id)
-{
-	MV_SPI_REG_BIT_SET(MV_SPI_IF_CTRL_REG(spi_id), MV_SPI_CS_ENABLE_MASK);
-}
-
-int mv_spi_8bit_data_tx_rx(unsigned char spi_id,
-		      unsigned char tx_data,
-		      unsigned char *p_rx_data)
-{
-	unsigned int i;
-	int ready = MV_FALSE;
-
-	if (curr_spi_info->byte_cs_asrt)
-		mv_spi_cs_assert(spi_id);
-
-	/* First clear the bit in the interrupt cause register */
-	MV_SPI_REG_WRITE(MV_SPI_INT_CAUSE_REG(spi_id), 0x0);
-
-	/* Transmit data */
-	MV_SPI_REG_WRITE(MV_SPI_DATA_OUT_REG(spi_id), tx_data);
-
-	/* wait with timeout for memory ready */
-	for (i = 0; i < MV_SPI_WAIT_RDY_MAX_LOOP; i++) {
-		if (MV_SPI_REG_READ(MV_SPI_INT_CAUSE_REG(spi_id))) {
-			ready = MV_TRUE;
-			break;
-		}
-	}
-
-	if (!ready) {
-		if (curr_spi_info->byte_cs_asrt) {
-			mv_spi_cs_deassert(spi_id);
-			/* WA to compansate Zarlink SLIC CS off time */
-			udelay(4);
-		}
-		return MV_TIMEOUT;
-	}
-
-	/* check that the RX data is needed */
-	if (p_rx_data)
-		*p_rx_data = MV_SPI_REG_READ(MV_SPI_DATA_IN_REG(spi_id));
-
-	if (curr_spi_info->byte_cs_asrt) {
-		mv_spi_cs_deassert(spi_id);
-		/* WA to compansate Zarlink SLIC CS off time */
-		udelay(4);
-	}
-
-	return MV_OK;
-}
-
-static int mrvl_spi_xfer(const struct spi_slave *slave,
-			 size_t bitlen,
-			 const void *dout,
-			 void *din)
-{
-	int ret;
-	unsigned char *pdout = (unsigned char *)dout;
-	unsigned char *pdin = (unsigned char *)din;
-	int tmp_bitlen = bitlen;
-	unsigned char tmp_dout = 0;
-
-	/* Verify that the SPI mode is in 8bit mode */
-	MV_SPI_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG(slave->bus),
-			 MV_SPI_BYTE_LENGTH_MASK);
-
-	while (tmp_bitlen > 0) {
-		if (pdout)
-			tmp_dout = (*pdout) & 0xff;
-
-		/* Transmitted and wait for the transfer to be completed */
-		ret = mv_spi_8bit_data_tx_rx(slave->bus, tmp_dout, pdin);
-		if (ret != MV_OK)
-			return ret;
-
-		/* increment the pointers */
-		if (pdin)
-			pdin++;
-		if (pdout)
-			pdout++;
-
-		tmp_bitlen -= 8;
-	}
-	return 0;
-}
-
-static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
-{
-	mv_spi_cs_set(slave->bus, slave->cs);
-	mv_spi_cs_assert(slave->bus);
-	return 0;
-}
-
-static void spi_ctrlr_release_bus(const struct spi_slave *slave)
-{
-	mv_spi_cs_deassert(slave->bus);
-}
-
-static int spi_ctrlr_xfer(const struct spi_slave *slave,
-		       const void *dout,
-		       size_t out_bytes,
-		       void *din,
-		       size_t in_bytes)
-{
-	int ret = -1;
-
-	if (out_bytes)
-		ret = mrvl_spi_xfer(slave, out_bytes * 8, dout, din);
-	else if (in_bytes)
-		ret = mrvl_spi_xfer(slave, in_bytes * 8, dout, din);
-	else
-		die("Unexpected condition in spi_xfer\n");
-	return ret;
-}
-
-static const spi_ctrlr spi_ctrlr = {
-	.claim_bus = spi_ctrlr_claim_bus,
-	.release_bus = spi_ctrlr_release_bus,
-	.xfer = spi_ctrlr_xfer,
-	.max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE,
-};
-
-int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
-{
-	slave->bus = bus;
-	slave->cs = cs;
-	slave->ctrlr = &spi_ctrlr;
-	mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED);
-	return 0;
-}
diff --git a/src/soc/marvell/armada38x/uart.c b/src/soc/marvell/armada38x/uart.c
deleted file mode 100644
index c2800d0543..0000000000
--- a/src/soc/marvell/armada38x/uart.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/uart.h>
-#include <console/console.h>
-#include <drivers/uart/uart8250reg.h>
-#include <boot/coreboot_tables.h>
-#include <stdint.h>
-#include <assert.h>
-#include <soc/common.h>
-#include <soc/clock.h>
-
-struct armada38x_uart {
-	union {
-		uint32_t thr; // Transmit holding register.
-		uint32_t rbr; // Receive buffer register.
-		uint32_t dll; // Divisor latch lsb.
-	};
-	union {
-		uint32_t ier; // Interrupt enable register.
-		uint32_t dlm; // Divisor latch msb.
-	};
-	union {
-		uint32_t iir; // Interrupt identification register.
-		uint32_t fcr; // FIFO control register.
-	};
-	uint32_t lcr; // Line control register.
-	uint32_t mcr; // Modem control register.
-	uint32_t lsr; // Line status register.
-	uint32_t msr; // Modem status register.
-} __attribute__ ((packed));
-
-static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr);
-static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr);
-
-static void armada38x_uart_init(struct armada38x_uart *uart_ptr)
-{
-	const uint8_t line_config = UART8250_LCR_WLS_8;
-	uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
-		uart_platform_refclk(), 16);
-
-	armada38x_uart_tx_flush(uart_ptr);
-	// Disable interrupts.
-	write8(&uart_ptr->ier, 0);
-	// Enable access to divisor latches.
-	write8(&uart_ptr->lcr, UART8250_LCR_DLAB);
-	// Set the divisor.
-	write8(&uart_ptr->dll, divisor & 0xff);
-	write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
-	// Hide divisor latches and program line config.
-	write8(&uart_ptr->lcr, line_config);
-	// Enable FIFOs, and clear receive and transmit.
-	write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
-				   UART8250_FCR_CLEAR_XMIT);
-}
-
-static void armada38x_uart_tx_byte(struct armada38x_uart *uart_ptr,
-					unsigned char data)
-{
-	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))
-		;
-	write8(&uart_ptr->thr, data);
-}
-
-static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr)
-{
-	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))
-		;
-}
-
-static unsigned char armada38x_uart_rx_byte(struct armada38x_uart *uart_ptr)
-{
-	if (!armada38x_uart_tst_byte(uart_ptr))
-		return 0;
-	return read8(&uart_ptr->rbr);
-}
-
-static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr)
-{
-	return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
-}
-
-unsigned int uart_platform_refclk(void)
-{
-	return mv_tclk_get();
-}
-
-uintptr_t uart_platform_base(int idx)
-{
-	/* Default to UART 0 */
-	unsigned int base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
-
-	assert((idx >= 0) && (idx < 2));
-	base += idx * 0x100;
-	return base;
-}
-
-void uart_init(int idx)
-{
-	struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
-
-	armada38x_uart_init(uart_ptr);
-}
-
-void uart_tx_byte(int idx, unsigned char data)
-{
-	struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
-
-	armada38x_uart_tx_byte(uart_ptr, data);
-}
-
-void uart_tx_flush(int idx)
-{
-	struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
-
-	armada38x_uart_tx_flush(uart_ptr);
-}
-
-unsigned char uart_rx_byte(int idx)
-{
-	struct armada38x_uart *uart_ptr = uart_platform_baseptr(idx);
-
-	return armada38x_uart_rx_byte(uart_ptr);
-}
-
-#if ENV_RAMSTAGE
-void uart_fill_lb(void *data)
-{
-	struct lb_serial serial;
-
-	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-	serial.baud = default_baudrate();
-	serial.regwidth = 4;
-	lb_add_serial(&serial, data);
-
-	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
-}
-#endif
author	Furquan Shaikh <furquan@chromium.org>	2017-05-22 14:32:30 -0700
committer	Furquan Shaikh <furquan@google.com>	2017-05-24 04:43:23 +0200
commit	53bbf87a4c145d6394935f315b06ffc81c939b47 (patch)
tree	1b84cee23366fa73efc6bb5186caff056f679d9f /src
parent	12eca76469670d444897e67368a0d0a70787ad52 (diff)