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authorAamir Bohra <aamir.bohra@intel.com>2019-07-08 12:19:30 +0530
committerFurquan Shaikh <furquan@google.com>2019-08-09 18:28:28 +0000
commit4c81167ce419853c03f98d4160a70c493c4c1606 (patch)
treeb81cb232bbbafa7204047e415a737c45ebd439c8 /src
parentbd7b245ff00337099083c96dd9f2ce1c8b5f48da (diff)
src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1263
Change-Id: Ia29769f1fc9947d9e37de2534c9486d21a4c9eae Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h406
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h1238
2 files changed, 848 insertions, 796 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
index cb31f7e131..b623ba0b65 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
@@ -106,15 +106,15 @@ typedef struct {
**/
UINT8 DqsMapCpu2DramCh1[8];
-/** Offset 0x0082 - RcompResister settings
- Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design
- Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide
- the appropriate values.
+/** Offset 0x0082 - RcompResistor settings
+ Indicates RcompResistor settings: CML - 0's means MRC auto configured based on
+ Design Guidelines, otherwise input an Ohmic value per segment. CFL will need to
+ provide the appropriate values.
**/
UINT16 RcompResistor[3];
/** Offset 0x0088 - RcompTarget settings
- RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines,
+ RcompTarget settings: CML - 0's mean MRC auto configured based on Design Guidelines,
otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.
**/
UINT16 RcompTarget[5];
@@ -138,92 +138,102 @@ typedef struct {
**/
UINT8 SmramMask;
-/** Offset 0x0095 - MRC Fast Boot
+/** Offset 0x0095 - Time Measure
+ Time Measure: 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 MrcTimeMeasure;
+
+/** Offset 0x0096 - MRC Fast Boot
Enables/Disable the MRC fast path thru the MRC
$EN_DIS
**/
UINT8 MrcFastBoot;
-/** Offset 0x0096 - Rank Margin Tool per Task
+/** Offset 0x0097 - Rank Margin Tool per Task
This option enables the user to execute Rank Margin Tool per major training step
in the MRC.
$EN_DIS
**/
UINT8 RmtPerTask;
-/** Offset 0x0097 - Training Trace
+/** Offset 0x0098 - Training Trace
This option enables the trained state tracing feature in MRC. This feature will
print out the key training parameters state across major training steps.
$EN_DIS
**/
UINT8 TrainTrace;
-/** Offset 0x0098 - Intel Enhanced Debug
+/** Offset 0x0099
+**/
+ UINT8 UnusedUpdSpace0[3];
+
+/** Offset 0x009C - Intel Enhanced Debug
Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
0 : Disable, 0x400000 : Enable
**/
UINT32 IedSize;
-/** Offset 0x009C - Tseg Size
+/** Offset 0x00A0 - Tseg Size
Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
0x0400000:4MB, 0x01000000:16MB
**/
UINT32 TsegSize;
-/** Offset 0x00A0 - MMIO Size
+/** Offset 0x00A4 - MMIO Size
Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
**/
UINT16 MmioSize;
-/** Offset 0x00A2 - Probeless Trace
+/** Offset 0x00A6 - Probeless Trace
Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
This also requires IED to be enabled.
$EN_DIS
**/
UINT8 ProbelessTrace;
-/** Offset 0x00A3 - GDXC IOT SIZE
+/** Offset 0x00A7 - GDXC IOT SIZE
Size of IOT and MOT is in 8 MB chunks
**/
UINT8 GdxcIotSize;
-/** Offset 0x00A4 - GDXC MOT SIZE
+/** Offset 0x00A8 - GDXC MOT SIZE
Size of IOT and MOT is in 8 MB chunks
**/
UINT8 GdxcMotSize;
-/** Offset 0x00A5 - Spd Address Tabl
+/** Offset 0x00A9 - Spd Address Tabl
Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
if SPD Address is 00
**/
UINT8 SpdAddressTable[4];
-/** Offset 0x00A9 - Internal Graphics Pre-allocated Memory
+/** Offset 0x00AD - Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics.
0x00:0 MB, 0x01:32 MB, 0x02:64 MB
**/
UINT8 IgdDvmt50PreAlloc;
-/** Offset 0x00AA - Internal Graphics
+/** Offset 0x00AE - Internal Graphics
Enable/disable internal graphics.
$EN_DIS
**/
UINT8 InternalGfx;
-/** Offset 0x00AB - Aperture Size
+/** Offset 0x00AF - Aperture Size
Select the Aperture Size.
0:128 MB, 1:256 MB, 2:512 MB
**/
UINT8 ApertureSize;
-/** Offset 0x00AC - Board Type
+/** Offset 0x00B0 - Board Type
MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
Halo, 7=UP Server
0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
**/
UINT8 UserBd;
-/** Offset 0x00AD - SA GV
+/** Offset 0x00B1 - SA GV
System Agent dynamic frequency support and when enabled memory will be training
at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
2=FixedHigh, and 3=Enabled.
@@ -231,7 +241,7 @@ typedef struct {
**/
UINT8 SaGv;
-/** Offset 0x00AE - DDR Frequency Limit
+/** Offset 0x00B2 - DDR Frequency Limit
Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
i.e. divide by 133 or 100
1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,
@@ -239,135 +249,128 @@ typedef struct {
**/
UINT16 DdrFreqLimit;
-/** Offset 0x00B0 - Low Frequency
+/** Offset 0x00B4 - Low Frequency
SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
2400, 2667, 2933 and 0 for Auto.
1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
**/
UINT16 FreqSaGvLow;
-/** Offset 0x00B2 - Mid Frequency
- SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
- 2400, 2667, 2933 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
- UINT16 FreqSaGvMid;
-
-/** Offset 0x00B4 - Rank Margin Tool
+/** Offset 0x00B6 - Rank Margin Tool
Enable/disable Rank Margin Tool.
$EN_DIS
**/
UINT8 RMT;
-/** Offset 0x00B5 - Channel A DIMM Control
+/** Offset 0x00B7 - Channel A DIMM Control
Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmChannel0;
-/** Offset 0x00B6 - Channel B DIMM Control
+/** Offset 0x00B8 - Channel B DIMM Control
Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
**/
UINT8 DisableDimmChannel1;
-/** Offset 0x00B7 - Scrambler Support
+/** Offset 0x00B9 - Scrambler Support
This option enables data scrambling in memory.
$EN_DIS
**/
UINT8 ScramblerSupport;
-/** Offset 0x00B8 - Skip Multi-Processor Initialization
+/** Offset 0x00BA - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. </b>0: Initialize; <b>1: Skip
$EN_DIS
**/
UINT8 SkipMpInit;
-/** Offset 0x00B9 - SPD Profile Selected
+/** Offset 0x00BB - SPD Profile Selected
Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
Profile 1, 3=XMP Profile 2
0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
**/
UINT8 SpdProfileSelected;
-/** Offset 0x00BA - Memory Reference Clock
+/** Offset 0x00BC - Memory Reference Clock
100MHz, 133MHz.
0:133MHz, 1:100MHz
**/
UINT8 RefClk;
-/** Offset 0x00BB
+/** Offset 0x00BD
**/
- UINT8 UnusedUpdSpace0;
+ UINT8 UnusedUpdSpace1;
-/** Offset 0x00BC - Memory Voltage
+/** Offset 0x00BE - Memory Voltage
Memory Voltage Override (Vddq). Default = no override
0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
**/
UINT16 VddVoltage;
-/** Offset 0x00BE - Memory Ratio
+/** Offset 0x00C0 - Memory Ratio
Automatic or the frequency will equal ratio times reference clock. Set to Auto to
recalculate memory timings listed below.
0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
**/
UINT8 Ratio;
-/** Offset 0x00BF - QCLK Odd Ratio
+/** Offset 0x00C1 - QCLK Odd Ratio
Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
$EN_DIS
**/
UINT8 OddRatioMode;
-/** Offset 0x00C0 - tCL
+/** Offset 0x00C2 - tCL
CAS Latency, 0: AUTO, max: 31
**/
UINT8 tCL;
-/** Offset 0x00C1 - tCWL
+/** Offset 0x00C3 - tCWL
Min CAS Write Latency Delay Time, 0: AUTO, max: 34
**/
UINT8 tCWL;
-/** Offset 0x00C2 - tRCD/tRP
+/** Offset 0x00C4 - tRCD/tRP
RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
**/
UINT8 tRCDtRP;
-/** Offset 0x00C3 - tRRD
+/** Offset 0x00C5 - tRRD
Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
**/
UINT8 tRRD;
-/** Offset 0x00C4 - tFAW
+/** Offset 0x00C6 - tFAW
Min Four Activate Window Delay Time, 0: AUTO, max: 63
**/
UINT16 tFAW;
-/** Offset 0x00C6 - tRAS
+/** Offset 0x00C8 - tRAS
RAS Active Time, 0: AUTO, max: 64
**/
UINT16 tRAS;
-/** Offset 0x00C8 - tREFI
+/** Offset 0x00CA - tREFI
Refresh Interval, 0: AUTO, max: 65535
**/
UINT16 tREFI;
-/** Offset 0x00CA - tRFC
+/** Offset 0x00CC - tRFC
Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
**/
UINT16 tRFC;
-/** Offset 0x00CC - tRTP
+/** Offset 0x00CE - tRTP
Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
values: 5, 6, 7, 8, 9, 10, 12
**/
UINT8 tRTP;
-/** Offset 0x00CD - tWR
+/** Offset 0x00CF - tWR
Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
20, 24, 30, 34, 40
0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
@@ -375,63 +378,74 @@ typedef struct {
**/
UINT8 tWR;
-/** Offset 0x00CE - tWTR
+/** Offset 0x00D0 - tWTR
Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
**/
UINT8 tWTR;
-/** Offset 0x00CF - NMode
+/** Offset 0x00D1 - NMode
System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
**/
UINT8 NModeSupport;
-/** Offset 0x00D0 - DllBwEn[0]
+/** Offset 0x00D2 - DllBwEn[0]
DllBwEn[0], for 1067 (0..7)
**/
UINT8 DllBwEn0;
-/** Offset 0x00D1 - DllBwEn[1]
+/** Offset 0x00D3 - DllBwEn[1]
DllBwEn[1], for 1333 (0..7)
**/
UINT8 DllBwEn1;
-/** Offset 0x00D2 - DllBwEn[2]
+/** Offset 0x00D4 - DllBwEn[2]
DllBwEn[2], for 1600 (0..7)
**/
UINT8 DllBwEn2;
-/** Offset 0x00D3 - DllBwEn[3]
+/** Offset 0x00D5 - DllBwEn[3]
DllBwEn[3], for 1867 and up (0..7)
**/
UINT8 DllBwEn3;
-/** Offset 0x00D4 - ISVT IO Port Address
+/** Offset 0x00D6 - ISVT IO Port Address
ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
**/
UINT8 IsvtIoPort;
-/** Offset 0x00D5 - CPU Trace Hub Mode
+/** Offset 0x00D7 - Margin Limit Check
+ Margin Limit Check. Choose level of margin check
+ 0:Disable, 1:L1, 2:L2, 3:Both
+**/
+ UINT8 MarginLimitCheck;
+
+/** Offset 0x00D8 - Margin Limit L2
+ % of L1 check for margin limit check
+**/
+ UINT16 MarginLimitL2;
+
+/** Offset 0x00DA - CPU Trace Hub Mode
Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'
trace hub functionality.
0: Disable, 1:Target Debugger Mode
**/
UINT8 CpuTraceHubMode;
-/** Offset 0x00D6 - CPU Trace Hub Memory Region 0
+/** Offset 0x00DB - CPU Trace Hub Memory Region 0
CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
**/
UINT8 CpuTraceHubMemReg0Size;
-/** Offset 0x00D7 - CPU Trace Hub Memory Region 1
+/** Offset 0x00DC - CPU Trace Hub Memory Region 1
CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
**/
UINT8 CpuTraceHubMemReg1Size;
-/** Offset 0x00D8 - Enable or Disable Peci C10 Reset command
+/** Offset 0x00DD - Enable or Disable Peci C10 Reset command
Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message
to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL,
and <b>1: Enable</b> for all other CPU's
@@ -439,175 +453,171 @@ typedef struct {
**/
UINT8 PeciC10Reset;
-/** Offset 0x00D9 - Enable or Disable Peci Sx Reset command
+/** Offset 0x00DE - Enable or Disable Peci Sx Reset command
Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
$EN_DIS
**/
UINT8 PeciSxReset;
-/** Offset 0x00DA - HECI Timeouts
+/** Offset 0x00DF - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
$EN_DIS
**/
UINT8 HeciTimeouts;
-/** Offset 0x00DB
-**/
- UINT8 UnusedUpdSpace1;
-
-/** Offset 0x00DC - HECI1 BAR address
+/** Offset 0x00E0 - HECI1 BAR address
BAR address of HECI1
**/
UINT32 Heci1BarAddress;
-/** Offset 0x00E0 - HECI2 BAR address
+/** Offset 0x00E4 - HECI2 BAR address
BAR address of HECI2
**/
UINT32 Heci2BarAddress;
-/** Offset 0x00E4 - HECI3 BAR address
+/** Offset 0x00E8 - HECI3 BAR address
BAR address of HECI3
**/
UINT32 Heci3BarAddress;
-/** Offset 0x00E8 - SG dGPU Power Delay
+/** Offset 0x00EC - SG dGPU Power Delay
SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
300=300 microseconds
**/
UINT16 SgDelayAfterPwrEn;
-/** Offset 0x00EA - SG dGPU Reset Delay
+/** Offset 0x00EE - SG dGPU Reset Delay
SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
microseconds
**/
UINT16 SgDelayAfterHoldReset;
-/** Offset 0x00EC - MMIO size adjustment for AUTO mode
+/** Offset 0x00F0 - MMIO size adjustment for AUTO mode
Positive number means increasing MMIO size, Negative value means decreasing MMIO
size: 0 (Default)=no change to AUTO mode MMIO size
**/
UINT16 MmioSizeAdjustment;
-/** Offset 0x00EE - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+/** Offset 0x00F2 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiGen3ProgramStaticEq;
-/** Offset 0x00EF - Enable/Disable PEG 0
+/** Offset 0x00F3 - Enable/Disable PEG 0
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
0:Disable, 1:Enable, 2:AUTO
**/
UINT8 Peg0Enable;
-/** Offset 0x00F0 - Enable/Disable PEG 1
+/** Offset 0x00F4 - Enable/Disable PEG 1
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
0:Disable, 1:Enable, 2:AUTO
**/
UINT8 Peg1Enable;
-/** Offset 0x00F1 - Enable/Disable PEG 2
+/** Offset 0x00F5 - Enable/Disable PEG 2
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
0:Disable, 1:Enable, 2:AUTO
**/
UINT8 Peg2Enable;
-/** Offset 0x00F2 - Enable/Disable PEG 3
+/** Offset 0x00F6 - Enable/Disable PEG 3
Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
0:Disable, 1:Enable, 2:AUTO
**/
UINT8 Peg3Enable;
-/** Offset 0x00F3 - PEG 0 Max Link Speed
+/** Offset 0x00F7 - PEG 0 Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 Peg0MaxLinkSpeed;
-/** Offset 0x00F4 - PEG 1 Max Link Speed
+/** Offset 0x00F8 - PEG 1 Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 Peg1MaxLinkSpeed;
-/** Offset 0x00F5 - PEG 2 Max Link Speed
+/** Offset 0x00F9 - PEG 2 Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 Peg2MaxLinkSpeed;
-/** Offset 0x00F6 - PEG 3 Max Link Speed
+/** Offset 0x00FA - PEG 3 Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 Peg3MaxLinkSpeed;
-/** Offset 0x00F7 - PEG 0 Max Link Width
+/** Offset 0x00FB - PEG 0 Max Link Width
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
**/
UINT8 Peg0MaxLinkWidth;
-/** Offset 0x00F8 - PEG 1 Max Link Width
+/** Offset 0x00FC - PEG 1 Max Link Width
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
Limit Link to x2, (0x3):Limit Link to x4
0:Auto, 1:x1, 2:x2, 3:x4
**/
UINT8 Peg1MaxLinkWidth;
-/** Offset 0x00F9 - PEG 2 Max Link Width
+/** Offset 0x00FD - PEG 2 Max Link Width
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
Limit Link to x2
0:Auto, 1:x1, 2:x2
**/
UINT8 Peg2MaxLinkWidth;
-/** Offset 0x00FA - PEG 3 Max Link Width
+/** Offset 0x00FE - PEG 3 Max Link Width
Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
Limit Link to x2
0:Auto, 1:x1, 2:x2
**/
UINT8 Peg3MaxLinkWidth;
-/** Offset 0x00FB - Power down unused lanes on PEG 0
+/** Offset 0x00FF - Power down unused lanes on PEG 0
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
on the max possible link width
0:No power saving, 1:Auto
**/
UINT8 Peg0PowerDownUnusedLanes;
-/** Offset 0x00FC - Power down unused lanes on PEG 1
+/** Offset 0x0100 - Power down unused lanes on PEG 1
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
on the max possible link width
0:No power saving, 1:Auto
**/
UINT8 Peg1PowerDownUnusedLanes;
-/** Offset 0x00FD - Power down unused lanes on PEG 2
+/** Offset 0x0101 - Power down unused lanes on PEG 2
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
on the max possible link width
0:No power saving, 1:Auto
**/
UINT8 Peg2PowerDownUnusedLanes;
-/** Offset 0x00FE - Power down unused lanes on PEG 3
+/** Offset 0x0102 - Power down unused lanes on PEG 3
(0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
on the max possible link width
0:No power saving, 1:Auto
**/
UINT8 Peg3PowerDownUnusedLanes;
-/** Offset 0x00FF - PCIe ASPM programming will happen in relation to the Oprom
+/** Offset 0x0103 - PCIe ASPM programming will happen in relation to the Oprom
Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
@@ -615,34 +625,34 @@ typedef struct {
**/
UINT8 InitPcieAspmAfterOprom;
-/** Offset 0x0100 - PCIe Disable Spread Spectrum Clocking
+/** Offset 0x0104 - PCIe Disable Spread Spectrum Clocking
PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
0:Normal Operation, 1:Disable SSC
**/
UINT8 PegDisableSpreadSpectrumClocking;
-/** Offset 0x0101 - DMI Gen3 Root port preset values per lane
+/** Offset 0x0105 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
**/
UINT8 DmiGen3RootPortPreset[8];
-/** Offset 0x0109 - DMI Gen3 End port preset values per lane
+/** Offset 0x010D - DMI Gen3 End port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
**/
UINT8 DmiGen3EndPointPreset[8];
-/** Offset 0x0111 - DMI Gen3 End port Hint values per lane
+/** Offset 0x0115 - DMI Gen3 End port Hint values per lane
Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
UINT8 DmiGen3EndPointHint[8];
-/** Offset 0x0119 - DMI Gen3 RxCTLEp per-Bundle control
+/** Offset 0x011D - DMI Gen3 RxCTLEp per-Bundle control
Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
**/
UINT8 DmiGen3RxCtlePeaking[4];
-/** Offset 0x011D - Thermal Velocity Boost Ratio clipping
+/** Offset 0x0121 - Thermal Velocity Boost Ratio clipping
0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
caused by high package temperatures for processors that implement the Intel Thermal
Velocity Boost (TVB) feature
@@ -650,59 +660,59 @@ typedef struct {
**/
UINT8 TvbRatioClipping;
-/** Offset 0x011E - Thermal Velocity Boost voltage optimization
+/** Offset 0x0122 - Thermal Velocity Boost voltage optimization
0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
0: Disabled, 1: Enabled
**/
UINT8 TvbVoltageOptimization;
-/** Offset 0x011F - PEG Gen3 RxCTLEp per-Bundle control
+/** Offset 0x0123 - PEG Gen3 RxCTLEp per-Bundle control
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
**/
UINT8 PegGen3RxCtlePeaking[10];
-/** Offset 0x0129
+/** Offset 0x012D
**/
UINT8 UnusedUpdSpace2[3];
-/** Offset 0x012C - Memory data pointer for saved preset search results
+/** Offset 0x0130 - Memory data pointer for saved preset search results
The reference code will store the Gen3 Preset Search results in the SaDataHob's
PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
**/
UINT32 PegDataPtr;
-/** Offset 0x0130 - PEG PERST# GPIO information
+/** Offset 0x0134 - PEG PERST# GPIO information
The reference code will use the information in this structure in order to reset
PCIe Gen3 devices during equalization, if necessary
**/
UINT8 PegGpioData[28];
-/** Offset 0x014C - PCIe Hot Plug Enable/Disable per port
+/** Offset 0x0150 - PCIe Hot Plug Enable/Disable per port
0(Default): Disable, 1: Enable
**/
UINT8 PegRootPortHPE[4];
-/** Offset 0x0150 - DeEmphasis control for DMI
+/** Offset 0x0154 - DeEmphasis control for DMI
DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
0: -6dB, 1: -3.5dB
**/
UINT8 DmiDeEmphasis;
-/** Offset 0x0151 - Selection of the primary display device
+/** Offset 0x0155 - Selection of the primary display device
0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
**/
UINT8 PrimaryDisplay;
-/** Offset 0x0152 - Selection of iGFX GTT Memory size
+/** Offset 0x0156 - Selection of iGFX GTT Memory size
1=2MB, 2=4MB, 3=8MB, Default is 3
1:2MB, 2:4MB, 3:8MB
**/
UINT16 GttSize;
-/** Offset 0x0154 - Temporary MMIO address for GMADR
+/** Offset 0x0158 - Temporary MMIO address for GMADR
The reference code will use this as Temporary MMIO address space to access GMADR
Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
(GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
@@ -710,7 +720,7 @@ typedef struct {
**/
UINT32 GmAdr;
-/** Offset 0x0158 - Temporary MMIO address for GTTMMADR
+/** Offset 0x015C - Temporary MMIO address for GTTMMADR
The reference code will use this as Temporary MMIO address space to access GTTMMADR
Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
@@ -718,155 +728,155 @@ typedef struct {
**/
UINT32 GttMmAdr;
-/** Offset 0x015C - Selection of PSMI Region size
+/** Offset 0x0160 - Selection of PSMI Region size
0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
**/
UINT8 PsmiRegionSize;
-/** Offset 0x015D - Switchable Graphics GPIO information for PEG 0
+/** Offset 0x0161 - Switchable Graphics GPIO information for PEG 0
Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
**/
UINT8 SaRtd3Pcie0Gpio[24];
-/** Offset 0x0175 - Switchable Graphics GPIO information for PEG 1
+/** Offset 0x0179 - Switchable Graphics GPIO information for PEG 1
Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
**/
UINT8 SaRtd3Pcie1Gpio[24];
-/** Offset 0x018D - Switchable Graphics GPIO information for PEG 2
+/** Offset 0x0191 - Switchable Graphics GPIO information for PEG 2
Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
**/
UINT8 SaRtd3Pcie2Gpio[24];
-/** Offset 0x01A5 - Switchable Graphics GPIO information for PEG 3
+/** Offset 0x01A9 - Switchable Graphics GPIO information for PEG 3
Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
**/
UINT8 SaRtd3Pcie3Gpio[24];
-/** Offset 0x01BD - Enable/Disable MRC TXT dependency
+/** Offset 0x01C1 - Enable/Disable MRC TXT dependency
When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
$EN_DIS
**/
UINT8 TxtImplemented;
-/** Offset 0x01BE - Enable/Disable SA OcSupport
+/** Offset 0x01C2 - Enable/Disable SA OcSupport
Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
$EN_DIS
**/
UINT8 SaOcSupport;
-/** Offset 0x01BF - GT slice Voltage Mode
+/** Offset 0x01C3 - GT slice Voltage Mode
0(Default): Adaptive, 1: Override
0: Adaptive, 1: Override
**/
UINT8 GtVoltageMode;
-/** Offset 0x01C0 - Maximum GTs turbo ratio override
+/** Offset 0x01C4 - Maximum GTs turbo ratio override
0(Default)=Minimal/Auto, 60=Maximum
**/
UINT8 GtMaxOcRatio;
-/** Offset 0x01C1
+/** Offset 0x01C5
**/
UINT8 UnusedUpdSpace3;
-/** Offset 0x01C2 - The voltage offset applied to GT slice
+/** Offset 0x01C6 - The voltage offset applied to GT slice
0(Default)=Minimal, 1000=Maximum
**/
UINT16 GtVoltageOffset;
-/** Offset 0x01C4 - The GT slice voltage override which is applied to the entire range of GT frequencies
+/** Offset 0x01C8 - The GT slice voltage override which is applied to the entire range of GT frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtVoltageOverride;
-/** Offset 0x01C6 - adaptive voltage applied during turbo frequencies
+/** Offset 0x01CA - adaptive voltage applied during turbo frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtExtraTurboVoltage;
-/** Offset 0x01C8 - voltage offset applied to the SA
+/** Offset 0x01CC - voltage offset applied to the SA
0(Default)=Minimal, 1000=Maximum
**/
UINT16 SaVoltageOffset;
-/** Offset 0x01CA - PCIe root port Function number for Switchable Graphics dGPU
+/** Offset 0x01CE - PCIe root port Function number for Switchable Graphics dGPU
Root port Index number to indicate which PCIe root port has dGPU
**/
UINT8 RootPortIndex;
-/** Offset 0x01CB - Realtime Memory Timing
+/** Offset 0x01CF - Realtime Memory Timing
0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
realtime memory timing changes after MRC_DONE.
0: Disabled, 1: Enabled
**/
UINT8 RealtimeMemoryTiming;
-/** Offset 0x01CC - Enable/Disable SA IPU
+/** Offset 0x01D0 - Enable/Disable SA IPU
Enable(Default): Enable SA IPU, Disable: Disable SA IPU
$EN_DIS
**/
UINT8 SaIpuEnable;
-/** Offset 0x01CD - IPU IMR Configuration
+/** Offset 0x01D1 - IPU IMR Configuration
0:IPU Camera, 1:IPU Gen Default is 0
0:IPU Camera, 1:IPU Gen
**/
UINT8 SaIpuImrConfiguration;
-/** Offset 0x01CE - Selection of PSMI Support On/Off
+/** Offset 0x01D2 - Selection of PSMI Support On/Off
0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
$EN_DIS
**/
UINT8 GtPsmiSupport;
-/** Offset 0x01CF - GT unslice Voltage Mode
+/** Offset 0x01D3 - GT unslice Voltage Mode
0(Default): Adaptive, 1: Override
0: Adaptive, 1: Override
**/
UINT8 GtusVoltageMode;
-/** Offset 0x01D0 - voltage offset applied to GT unslice
+/** Offset 0x01D4 - voltage offset applied to GT unslice
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtusVoltageOffset;
-/** Offset 0x01D2 - GT unslice voltage override which is applied to the entire range of GT frequencies
+/** Offset 0x01D6 - GT unslice voltage override which is applied to the entire range of GT frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtusVoltageOverride;
-/** Offset 0x01D4 - adaptive voltage applied during turbo frequencies
+/** Offset 0x01D8 - adaptive voltage applied during turbo frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtusExtraTurboVoltage;
-/** Offset 0x01D6 - Maximum GTus turbo ratio override
+/** Offset 0x01DA - Maximum GTus turbo ratio override
0(Default)=Minimal, 60=Maximum
**/
UINT8 GtusMaxOcRatio;
-/** Offset 0x01D7 - SaPreMemProductionRsvd
+/** Offset 0x01DB - SaPreMemProductionRsvd
Reserved for SA Pre-Mem Production
$EN_DIS
**/
- UINT8 SaPreMemProductionRsvd[4];
+ UINT8 SaPreMemProductionRsvd[3];
-/** Offset 0x01DB - BIST on Reset
+/** Offset 0x01DE - BIST on Reset
Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 BistOnReset;
-/** Offset 0x01DC - Skip Stop PBET Timer Enable/Disable
+/** Offset 0x01DF - Skip Stop PBET Timer Enable/Disable
Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 SkipStopPbet;
-/** Offset 0x01DD - C6DRAM power gating feature
+/** Offset 0x01E0 - C6DRAM power gating feature
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
@@ -874,54 +884,54 @@ typedef struct {
**/
UINT8 EnableC6Dram;
-/** Offset 0x01DE - Over clocking support
+/** Offset 0x01E1 - Over clocking support
Over clocking support; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 OcSupport;
-/** Offset 0x01DF - Over clocking Lock
+/** Offset 0x01E2 - Over clocking Lock
Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 OcLock;
-/** Offset 0x01E0 - Maximum Core Turbo Ratio Override
+/** Offset 0x01E3 - Maximum Core Turbo Ratio Override
Maximum core turbo ratio override allows to increase CPU core frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
**/
UINT8 CoreMaxOcRatio;
-/** Offset 0x01E1 - Core voltage mode
+/** Offset 0x01E4 - Core voltage mode
Core voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 CoreVoltageMode;
-/** Offset 0x01E2 - Program Cache Attributes
+/** Offset 0x01E5 - Program Cache Attributes
Program Cache Attributes; <b>0: Program</b>; 1: Disable Program.
$EN_DIS
**/
UINT8 DisableMtrrProgram;
-/** Offset 0x01E3 - Maximum clr turbo ratio override
+/** Offset 0x01E6 - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
**/
UINT8 RingMaxOcRatio;
-/** Offset 0x01E4 - Hyper Threading Enable/Disable
+/** Offset 0x01E7 - Hyper Threading Enable/Disable
Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 HyperThreading;
-/** Offset 0x01E5 - CPU ratio value
+/** Offset 0x01E8 - CPU ratio value
CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.
**/
UINT8 CpuRatio;
-/** Offset 0x01E6 - Boot frequency
+/** Offset 0x01E9 - Boot frequency
Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
<b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
@@ -929,164 +939,156 @@ typedef struct {
**/
UINT8 BootFrequency;
-/** Offset 0x01E7 - Number of active cores
+/** Offset 0x01EA - Number of active cores
Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
2 </b>;<b>3: 3 </b>
0:All, 1:1, 2:2, 3:3
**/
UINT8 ActiveCoreCount;
-/** Offset 0x01E8 - Processor Early Power On Configuration FCLK setting
+/** Offset 0x01EB - Processor Early Power On Configuration FCLK setting
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
2: 400 MHz. - 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
**/
UINT8 FClkFrequency;
-/** Offset 0x01E9 - Set JTAG power in C10 and deeper power states
+/** Offset 0x01EC - Set JTAG power in C10 and deeper power states
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
and deeper power states for debug purpose. <b>0: False</b>; 1: True.
0: False, 1: True
**/
UINT8 JtagC10PowerGateDisable;
-/** Offset 0x01EA - Enable or Disable VMX
+/** Offset 0x01ED - Enable or Disable VMX
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 VmxEnable;
-/** Offset 0x01EB - AVX2 Ratio Offset
+/** Offset 0x01EE - AVX2 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx2RatioOffset;
-/** Offset 0x01EC - AVX3 Ratio Offset
+/** Offset 0x01EF - AVX3 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx3RatioOffset;
-/** Offset 0x01ED - BCLK Adaptive Voltage Enable
+/** Offset 0x01F0 - BCLK Adaptive Voltage Enable
When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
Disable;<b> 1: Enable
$EN_DIS
**/
UINT8 BclkAdaptiveVoltage;
-/** Offset 0x01EE - Core PLL voltage offset
+/** Offset 0x01F1 - Core PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
**/
UINT8 CorePllVoltageOffset;
-/** Offset 0x01EF
-**/
- UINT8 UnusedUpdSpace4;
-
-/** Offset 0x01F0 - core voltage override
+/** Offset 0x01F2 - core voltage override
The core voltage override which is applied to the entire range of cpu core frequencies.
Valid Range 0 to 2000
**/
UINT16 CoreVoltageOverride;
-/** Offset 0x01F2 - Core Turbo voltage Adaptive
+/** Offset 0x01F4 - Core Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
Valid Range 0 to 2000
**/
UINT16 CoreVoltageAdaptive;
-/** Offset 0x01F4 - Core Turbo voltage Offset
+/** Offset 0x01F6 - Core Turbo voltage Offset
The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
**/
UINT16 CoreVoltageOffset;
-/** Offset 0x01F6 - Ring Downbin
+/** Offset 0x01F8 - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
lower than the core ratio.0: Disable; <b>1: Enable.</b>
$EN_DIS
**/
UINT8 RingDownBin;
-/** Offset 0x01F7 - Ring voltage mode
+/** Offset 0x01F9 - Ring voltage mode
Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 RingVoltageMode;
-/** Offset 0x01F8 - Ring voltage override
+/** Offset 0x01FA - Ring voltage override
The ring voltage override which is applied to the entire range of cpu ring frequencies.
Valid Range 0 to 2000
**/
UINT16 RingVoltageOverride;
-/** Offset 0x01FA - Ring Turbo voltage Adaptive
+/** Offset 0x01FC - Ring Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
Valid Range 0 to 2000
**/
UINT16 RingVoltageAdaptive;
-/** Offset 0x01FC - Ring Turbo voltage Offset
+/** Offset 0x01FE - Ring Turbo voltage Offset
The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
**/
UINT16 RingVoltageOffset;
-/** Offset 0x01FE - TjMax Offset
+/** Offset 0x0200 - TjMax Offset
TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
**/
UINT8 TjMaxOffset;
-/** Offset 0x01FF - BiosGuard
+/** Offset 0x0201 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x0200
+/** Offset 0x0202
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x0201 - EnableSgx
+/** Offset 0x0203 - EnableSgx
Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
0: Disable, 1: Enable, 2: Software Control
**/
UINT8 EnableSgx;
-/** Offset 0x0202 - Txt
+/** Offset 0x0204 - Txt
Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
$EN_DIS
**/
UINT8 Txt;
-/** Offset 0x0203
+/** Offset 0x0205
**/
- UINT8 UnusedUpdSpace5;
+ UINT8 UnusedUpdSpace4[3];
-/** Offset 0x0204 - PrmrrSize
+/** Offset 0x0208 - PrmrrSize
0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
**/
UINT32 PrmrrSize;
-/** Offset 0x0208 - SinitMemorySize
+/** Offset 0x020C - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x020C - TxtHeapMemorySize
+/** Offset 0x0210 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x0210 - TxtDprMemorySize
+/** Offset 0x0214 - TxtDprMemorySize
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x0214
-**/
- UINT8 UnusedUpdSpace6[4];
-
/** Offset 0x0218 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
@@ -1436,7 +1438,7 @@ typedef struct {
/** Offset 0x044E
**/
- UINT8 UnusedUpdSpace7[2];
+ UINT8 UnusedUpdSpace5[2];
/** Offset 0x0450 - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@@ -1842,7 +1844,7 @@ typedef struct {
/** Offset 0x04A5
**/
- UINT8 UnusedUpdSpace8;
+ UINT8 UnusedUpdSpace6;
/** Offset 0x04A6 - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -1931,7 +1933,7 @@ typedef struct {
/** Offset 0x04BB
**/
- UINT8 UnusedUpdSpace9;
+ UINT8 UnusedUpdSpace7;
/** Offset 0x04BC - RAPL PL 2 Power
range[0;2^14-1]= [2047.875;0]in W, (222= Def)
@@ -2376,13 +2378,25 @@ typedef struct {
**/
UINT8 MrcTrainOnWarm;
-/** Offset 0x050E
+/** Offset 0x050E - Lpddr Dram Odt
+ Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)
+ 0:Disable, 1:Enable, 2:AUTO
+**/
+ UINT8 LpddrDramOdt;
+
+/** Offset 0x050F - DDR4 Skip Refresh Enable
+ Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)
+ 0:Disable, 1:Enable
**/
- UINT8 UnusedUpdSpace10[2];
+ UINT8 Ddr4SkipRefreshEn;
/** Offset 0x0510
**/
- UINT8 ReservedFspmUpd[8];
+ UINT8 UnusedUpdSpace8[2];
+
+/** Offset 0x0512
+**/
+ UINT8 ReservedFspmUpd[6];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
@@ -2607,7 +2621,7 @@ typedef struct {
/** Offset 0x0571
**/
- UINT8 UnusedUpdSpace11;
+ UINT8 UnusedUpdSpace9;
/** Offset 0x0572 - Jitter Dwell Time for PCIe Gen3 Software Equalization
Range: 0-65535, default is 1000. @warning Do not change from the default
@@ -2650,7 +2664,7 @@ typedef struct {
/** Offset 0x057D
**/
- UINT8 UnusedUpdSpace12;
+ UINT8 UnusedUpdSpace10;
/** Offset 0x057E - Delta T12 Power Cycle Delay required in ms
Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
@@ -2667,7 +2681,7 @@ typedef struct {
/** Offset 0x0589
**/
- UINT8 UnusedUpdSpace13;
+ UINT8 UnusedUpdSpace11;
/** Offset 0x058A - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@@ -2869,7 +2883,7 @@ typedef struct {
/** Offset 0x05C0
**/
- UINT8 ReservedFspmTestUpd[4];
+ UINT8 ReservedFspmTestUpd[8];
} FSP_M_TEST_CONFIG;
/** Fsp M UPD Configuration
@@ -2892,9 +2906,13 @@ typedef struct {
**/
FSP_M_TEST_CONFIG FspmTestConfig;
-/** Offset 0x05C4
+/** Offset 0x05C8
+**/
+ UINT8 UnusedUpdSpace12[6];
+
+/** Offset 0x05CE
**/
- UINT32 UpdTerminator;
+ UINT16 UpdTerminator;
} FSPM_UPD;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
index e6f891987e..49da429b47 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
@@ -139,306 +139,316 @@ typedef struct {
**/
UINT8 Heci3Enabled;
-/** Offset 0x003B - AMT Switch
+/** Offset 0x003B - HECI1 state
+ Determine if HECI1 is hidden prior to boot to OS. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 Heci1Disabled;
+
+/** Offset 0x003C - AMT Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
$EN_DIS
**/
UINT8 AmtEnabled;
-/** Offset 0x003C - WatchDog Timer Switch
+/** Offset 0x003D - WatchDog Timer Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 WatchDogEnabled;
-/** Offset 0x003D - Manageability Mode set by Mebx
+/** Offset 0x003E - Manageability Mode set by Mebx
Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
$EN_DIS
**/
UINT8 ManageabilityMode;
-/** Offset 0x003E - PET Progress
+/** Offset 0x003F - PET Progress
Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
PET Events. Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 FwProgress;
-/** Offset 0x003F - SOL Switch
+/** Offset 0x0040 - SOL Switch
Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 AmtSolEnabled;
-/** Offset 0x0040 - OS Timer
+/** Offset 0x0041
+**/
+ UINT8 UnusedUpdSpace1;
+
+/** Offset 0x0042 - OS Timer
16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerOs;
-/** Offset 0x0042 - BIOS Timer
+/** Offset 0x0044 - BIOS Timer
16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerBios;
-/** Offset 0x0044 - Remote Assistance Trigger Availablilty
+/** Offset 0x0046 - Remote Assistance Trigger Availablilty
Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx.
$EN_DIS
**/
UINT8 RemoteAssistance;
-/** Offset 0x0045 - KVM Switch
+/** Offset 0x0047 - KVM Switch
Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting
is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 AmtKvmEnabled;
-/** Offset 0x0046 - MEBX execution
+/** Offset 0x0048 - MEBX execution
Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
$EN_DIS
**/
UINT8 ForcMebxSyncUp;
-/** Offset 0x0047 - Enable/Disable SA CRID
+/** Offset 0x0049 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
-/** Offset 0x0048 - DMI ASPM
+/** Offset 0x004A - DMI ASPM
0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
0:Disable, 1:L0s, 2:L1, 3:L0sL1
**/
UINT8 DmiAspm;
-/** Offset 0x0049 - PCIe DeEmphasis control per root port
+/** Offset 0x004B - PCIe DeEmphasis control per root port
0: -6dB, 1(Default): -3.5dB
0:-6dB, 1:-3.5dB
**/
UINT8 PegDeEmphasis[4];
-/** Offset 0x004D - PCIe Slot Power Limit value per root port
+/** Offset 0x004F - PCIe Slot Power Limit value per root port
Slot power limit value per root port
**/
UINT8 PegSlotPowerLimitValue[4];
-/** Offset 0x0051 - PCIe Slot Power Limit scale per root port
+/** Offset 0x0053 - PCIe Slot Power Limit scale per root port
Slot power limit scale per root port
0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
**/
UINT8 PegSlotPowerLimitScale[4];
-/** Offset 0x0055
+/** Offset 0x0057
**/
- UINT8 UnusedUpdSpace1[1];
+ UINT8 UnusedUpdSpace2[1];
-/** Offset 0x0056 - PCIe Physical Slot Number per root port
+/** Offset 0x0058 - PCIe Physical Slot Number per root port
Physical Slot Number per root port
**/
UINT16 PegPhysicalSlotNumber[4];
-/** Offset 0x005E - Enable/Disable PavpEnable
+/** Offset 0x0060 - Enable/Disable PavpEnable
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
$EN_DIS
**/
UINT8 PavpEnable;
-/** Offset 0x005F - CdClock Frequency selection
+/** Offset 0x0061 - CdClock Frequency selection
0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz
0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
**/
UINT8 CdClock;
-/** Offset 0x0060 - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x0062 - Enable/Disable PeiGraphicsPeimInit
Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
-/** Offset 0x0061 - Enable or disable GNA device
+/** Offset 0x0063 - Enable or disable GNA device
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 GnaEnable;
-/** Offset 0x0062 - State of X2APIC_OPT_OUT bit in the DMAR table
+/** Offset 0x0064 - State of X2APIC_OPT_OUT bit in the DMAR table
0=Disable/Clear, 1=Enable/Set
$EN_DIS
**/
UINT8 X2ApicOptOutDeprecated;
-/** Offset 0x0063
+/** Offset 0x0065
**/
- UINT8 UnusedUpdSpace2[1];
+ UINT8 UnusedUpdSpace3[3];
-/** Offset 0x0064 - Base addresses for VT-d function MMIO access
+/** Offset 0x0068 - Base addresses for VT-d function MMIO access
Base addresses for VT-d MMIO access per VT-d engine
**/
UINT32 VtdBaseAddressDeprecated[3];
-/** Offset 0x0070 - Enable or disable eDP device
+/** Offset 0x0074 - Enable or disable eDP device
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortEdp;
-/** Offset 0x0071 - Enable or disable HPD of DDI port B
+/** Offset 0x0075 - Enable or disable HPD of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBHpd;
-/** Offset 0x0072 - Enable or disable HPD of DDI port C
+/** Offset 0x0076 - Enable or disable HPD of DDI port C
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortCHpd;
-/** Offset 0x0073 - Enable or disable HPD of DDI port D
+/** Offset 0x0077 - Enable or disable HPD of DDI port D
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortDHpd;
-/** Offset 0x0074 - Enable or disable HPD of DDI port F
+/** Offset 0x0078 - Enable or disable HPD of DDI port F
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortFHpd;
-/** Offset 0x0075 - Enable or disable DDC of DDI port B
+/** Offset 0x0079 - Enable or disable DDC of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBDdc;
-/** Offset 0x0076 - Enable or disable DDC of DDI port C
+/** Offset 0x007A - Enable or disable DDC of DDI port C
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortCDdc;
-/** Offset 0x0077 - Enable or disable DDC of DDI port D
+/** Offset 0x007B - Enable or disable DDC of DDI port D
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortDDdc;
-/** Offset 0x0078 - Enable or disable DDC of DDI port F
+/** Offset 0x007C - Enable or disable DDC of DDI port F
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortFDdc;
-/** Offset 0x0079 - Enable/Disable SkipS3CdClockInit
+/** Offset 0x007D - Enable/Disable SkipS3CdClockInit
Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
CD clock in S3 resume due to GOP absent
$EN_DIS
**/
UINT8 SkipS3CdClockInit;
-/** Offset 0x007A - Delta T12 Power Cycle Delay required in ms
+/** Offset 0x007E - Delta T12 Power Cycle Delay required in ms
DEPRECATED
0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
**/
UINT16 DeltaT12PowerCycleDelay;
-/** Offset 0x007C - Blt Buffer Address
+/** Offset 0x0080 - Blt Buffer Address
Address of Blt buffer
**/
UINT32 BltBufferAddress;
-/** Offset 0x0080 - Blt Buffer Size
+/** Offset 0x0084 - Blt Buffer Size
Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
**/
UINT32 BltBufferSize;
-/** Offset 0x0084 - Program GT Chicken bits
+/** Offset 0x0088 - Program GT Chicken bits
Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1]
**/
UINT8 ProgramGtChickenBits;
-/** Offset 0x0085 - SaPostMemProductionRsvd
+/** Offset 0x0089 - SaPostMemProductionRsvd
Reserved for SA Post-Mem Production
$EN_DIS
**/
UINT8 SaPostMemProductionRsvd[34];
-/** Offset 0x00A7 - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
+/** Offset 0x00AB - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
Alpine ridge
**/
UINT8 PcieRootPortGen2PllL1CgDisable[24];
-/** Offset 0x00BF - Advanced Encryption Standard (AES) feature
+/** Offset 0x00C3 - Advanced Encryption Standard (AES) feature
Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
$EN_DIS
**/
UINT8 AesEnable;
-/** Offset 0x00C0 - Power State 3 enable/disable
+/** Offset 0x00C4 - Power State 3 enable/disable
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
For all VR Indexes
**/
UINT8 Psi3Enable[5];
-/** Offset 0x00C5 - Power State 4 enable/disable
+/** Offset 0x00C9 - Power State 4 enable/disable
PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
all VR Indexes
**/
UINT8 Psi4Enable[5];
-/** Offset 0x00CA - Imon slope correction
+/** Offset 0x00CE - Imon slope correction
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
**/
UINT8 ImonSlope[5];
-/** Offset 0x00CF - Imon offset correction
+/** Offset 0x00D3 - Imon offset correction
DEPRECATED
**/
UINT8 ImonOffset[5];
-/** Offset 0x00D4 - Enable/Disable BIOS configuration of VR
+/** Offset 0x00D8 - Enable/Disable BIOS configuration of VR
Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
**/
UINT8 VrConfigEnable[5];
-/** Offset 0x00D9 - Thermal Design Current enable/disable
+/** Offset 0x00DD - Thermal Design Current enable/disable
PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
Enable.For all VR Indexes
**/
UINT8 TdcEnable[5];
-/** Offset 0x00DE - HECI3 state
+/** Offset 0x00E2 - HECI3 state
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
, 8 - 8ms , 10 - 10ms.For all VR Indexe
**/
UINT8 TdcTimeWindow[5];
-/** Offset 0x00E3 - Thermal Design Current Lock
+/** Offset 0x00E7 - Thermal Design Current Lock
PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
all VR Indexes
**/
UINT8 TdcLock[5];
-/** Offset 0x00E8 - Platform Psys slope correction
+/** Offset 0x00EC - Platform Psys slope correction
PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
1/100 increment values. Range is 0-200. 125 = 1.25
**/
UINT8 PsysSlope;
-/** Offset 0x00E9 - Platform Psys offset correction
+/** Offset 0x00ED - Platform Psys offset correction
PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
Range 0-255. Value of 100 = 100/4 = 25 offset
**/
UINT8 PsysOffset;
-/** Offset 0x00EA - Acoustic Noise Mitigation feature
+/** Offset 0x00EE - Acoustic Noise Mitigation feature
Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
Disabled</b>; 1: Enabled
@@ -446,96 +456,96 @@ typedef struct {
**/
UINT8 AcousticNoiseMitigation;
-/** Offset 0x00EB - Disable Fast Slew Rate for Deep Package C States for VR IA domain
+/** Offset 0x00EF - Disable Fast Slew Rate for Deep Package C States for VR IA domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableIa;
-/** Offset 0x00EC - Slew Rate configuration for Deep Package C States for VR IA domain
+/** Offset 0x00F0 - Slew Rate configuration for Deep Package C States for VR IA domain
Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForIa;
-/** Offset 0x00ED - Slew Rate configuration for Deep Package C States for VR GT domain
+/** Offset 0x00F1 - Slew Rate configuration for Deep Package C States for VR GT domain
Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForGt;
-/** Offset 0x00EE - Slew Rate configuration for Deep Package C States for VR SA domain
+/** Offset 0x00F2 - Slew Rate configuration for Deep Package C States for VR SA domain
Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForSa;
-/** Offset 0x00EF
+/** Offset 0x00F3
**/
- UINT8 UnusedUpdSpace3[1];
+ UINT8 UnusedUpdSpace4[1];
-/** Offset 0x00F0 - Thermal Design Current current limit
+/** Offset 0x00F4 - Thermal Design Current current limit
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
**/
UINT16 TdcPowerLimit[5];
-/** Offset 0x00FA - AcLoadline
+/** Offset 0x00FE - AcLoadline
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
**/
UINT16 AcLoadline[5];
-/** Offset 0x0104 - DcLoadline
+/** Offset 0x0108 - DcLoadline
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
**/
UINT16 DcLoadline[5];
-/** Offset 0x010E - Power State 1 Threshold current
+/** Offset 0x0112 - Power State 1 Threshold current
PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
**/
UINT16 Psi1Threshold[5];
-/** Offset 0x0118 - Power State 2 Threshold current
+/** Offset 0x011C - Power State 2 Threshold current
PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
**/
UINT16 Psi2Threshold[5];
-/** Offset 0x0122 - Power State 3 Threshold current
+/** Offset 0x0126 - Power State 3 Threshold current
PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
**/
UINT16 Psi3Threshold[5];
-/** Offset 0x012C - Icc Max limit
+/** Offset 0x0130 - Icc Max limit
PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
**/
UINT16 IccMax[5];
-/** Offset 0x0136 - VR Voltage Limit
+/** Offset 0x013A - VR Voltage Limit
PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
**/
UINT16 VrVoltageLimit[5];
-/** Offset 0x0140 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
+/** Offset 0x0144 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableGt;
-/** Offset 0x0141 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
+/** Offset 0x0145 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableSa;
-/** Offset 0x0142 - Enable VR specific mailbox command
+/** Offset 0x0146 - Enable VR specific mailbox command
VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
command sent for PS4 exit issue. 11b - Reserved.
@@ -543,209 +553,209 @@ typedef struct {
**/
UINT8 SendVrMbxCmd;
-/** Offset 0x0143 - Reserved
+/** Offset 0x0147 - Reserved
Reserved
**/
UINT8 Reserved2;
-/** Offset 0x0144 - Enable or Disable TXT
+/** Offset 0x0148 - Enable or Disable TXT
Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 TxtEnable;
-/** Offset 0x0145 - Deprecated DO NOT USE Skip Multi-Processor Initialization
+/** Offset 0x0149 - Deprecated DO NOT USE Skip Multi-Processor Initialization
@deprecated SkipMpInit has been moved to FspmUpd
$EN_DIS
**/
UINT8 SkipMpInitDeprecated;
-/** Offset 0x0146 - McIVR RFI Frequency Prefix
+/** Offset 0x014A - McIVR RFI Frequency Prefix
PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
Minus (-).
**/
UINT8 McivrRfiFrequencyPrefix;
-/** Offset 0x0147 - McIVR RFI Frequency Adjustment
+/** Offset 0x014B - McIVR RFI Frequency Adjustment
PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
**/
UINT8 McivrRfiFrequencyAdjust;
-/** Offset 0x0148 - FIVR RFI Frequency
+/** Offset 0x014C - FIVR RFI Frequency
PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
0-1535 (Up to 153.5MHz) for 19MHz clock.
**/
UINT16 FivrRfiFrequency;
-/** Offset 0x014A - McIVR RFI Spread Spectrum
+/** Offset 0x014E - McIVR RFI Spread Spectrum
PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
**/
UINT8 McivrSpreadSpectrum;
-/** Offset 0x014B - FIVR RFI Spread Spectrum
+/** Offset 0x014F - FIVR RFI Spread Spectrum
PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
Range: 0.0% to 10.0% (0-100).
**/
UINT8 FivrSpreadSpectrum;
-/** Offset 0x014C - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
+/** Offset 0x0150 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisableFivr;
-/** Offset 0x014D - Slew Rate configuration for Deep Package C States for VR FIVR domain
+/** Offset 0x0151 - Slew Rate configuration for Deep Package C States for VR FIVR domain
Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
**/
UINT8 SlowSlewRateForFivr;
-/** Offset 0x014E
+/** Offset 0x0152
**/
- UINT8 UnusedUpdSpace4[2];
+ UINT8 UnusedUpdSpace5[2];
-/** Offset 0x0150 - CpuBistData
+/** Offset 0x0154 - CpuBistData
Pointer CPU BIST Data
**/
UINT32 CpuBistData;
-/** Offset 0x0154 - Activates VR mailbox command for Intersil VR C-state issues.
+/** Offset 0x0158 - Activates VR mailbox command for Intersil VR C-state issues.
Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
**/
UINT8 IslVrCmd;
-/** Offset 0x0155
+/** Offset 0x0159
**/
- UINT8 UnusedUpdSpace5[1];
+ UINT8 UnusedUpdSpace6[1];
-/** Offset 0x0156 - Imon slope1 correction
+/** Offset 0x015A - Imon slope1 correction
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
**/
UINT16 ImonSlope1[5];
-/** Offset 0x0160 - CPU VR Power Delivery Design
+/** Offset 0x0164 - CPU VR Power Delivery Design
Used to communicate the power delivery design capability of the board. This value
is an enum of the available power delivery segments that are defined in the Platform
Design Guide.
**/
UINT32 VrPowerDeliveryDesign;
-/** Offset 0x0164 - Pre Wake Randomization time
+/** Offset 0x0168 - Pre Wake Randomization time
PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
Range 0-255 <b>0</b>.
**/
UINT8 PreWake;
-/** Offset 0x0165 - Ramp Up Randomization time
+/** Offset 0x0169 - Ramp Up Randomization time
PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
0-255 <b>0</b>.
**/
UINT8 RampUp;
-/** Offset 0x0166 - Ramp Down Randomization time
+/** Offset 0x016A - Ramp Down Randomization time
PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
0-255 <b>0</b>.
**/
UINT8 RampDown;
-/** Offset 0x0167
+/** Offset 0x016B
**/
- UINT8 UnusedUpdSpace6;
+ UINT8 UnusedUpdSpace7;
-/** Offset 0x0168 - CpuMpPpi
+/** Offset 0x016C - CpuMpPpi
Pointer for CpuMpPpi
**/
UINT32 CpuMpPpi;
-/** Offset 0x016C - CpuMpHob
+/** Offset 0x0170 - CpuMpHob
Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage.
**/
UINT32 CpuMpHob;
-/** Offset 0x0170 - Enable or Disable processor debug features
+/** Offset 0x0174 - Enable or Disable processor debug features
Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DebugInterfaceEnable;
-/** Offset 0x0171
+/** Offset 0x0175
**/
- UINT8 UnusedUpdSpace7[1];
+ UINT8 UnusedUpdSpace8[1];
-/** Offset 0x0172 - Imon offset 1 correction
+/** Offset 0x0176 - Imon offset 1 correction
PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
**/
UINT16 ImonOffset1[5];
-/** Offset 0x017C - ReservedCpuPostMemProduction
+/** Offset 0x0180 - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production
$EN_DIS
**/
UINT8 ReservedCpuPostMemProduction[8];
-/** Offset 0x0184 - Enable HD Audio DSP
+/** Offset 0x0188 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x0185 - SPI0 Chip Select Polarity
+/** Offset 0x0189 - SPI0 Chip Select Polarity
Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow,
1:PchSerialIoCsActiveHigh
**/
UINT8 SerialIoSpi0CsPolarity[2];
-/** Offset 0x0187 - SPI1 Chip Select Polarity
+/** Offset 0x018B - SPI1 Chip Select Polarity
Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow,
1:PchSerialIoCsActiveHigh
**/
UINT8 SerialIoSpi1CsPolarity[2];
-/** Offset 0x0189 - SPI2 Chip Select Polarity
+/** Offset 0x018D - SPI2 Chip Select Polarity
Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow,
1:PchSerialIoCsActiveHigh
**/
UINT8 SerialIoSpi2CsPolarity[2];
-/** Offset 0x018B - SPI0 Chip Select Enable
+/** Offset 0x018F - SPI0 Chip Select Enable
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
**/
UINT8 SerialIoSpi0CsEnable[2];
-/** Offset 0x018D - SPI1 Chip Select Enable
+/** Offset 0x0191 - SPI1 Chip Select Enable
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
**/
UINT8 SerialIoSpi1CsEnable[2];
-/** Offset 0x018F - SPI2 Chip Select Enable
+/** Offset 0x0193 - SPI2 Chip Select Enable
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
**/
UINT8 SerialIoSpi2CsEnable[2];
-/** Offset 0x0191 - SPIn Device Mode
+/** Offset 0x0195 - SPIn Device Mode
Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
**/
UINT8 SerialIoSpiMode[3];
-/** Offset 0x0194 - SPIn Default Chip Select Output
+/** Offset 0x0198 - SPIn Default Chip Select Output
Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available
options: 0:CS0, 1:CS1
**/
UINT8 SerialIoSpiDefaultCsOutput[3];
-/** Offset 0x0197 - PCH SerialIo I2C Pads Termination
+/** Offset 0x019B - PCH SerialIo I2C Pads Termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
@@ -753,1035 +763,1037 @@ typedef struct {
**/
UINT8 PchSerialIoI2cPadsTermination[6];
-/** Offset 0x019D - I2Cn Device Mode
+/** Offset 0x01A1 - I2Cn Device Mode
Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
**/
UINT8 SerialIoI2cMode[6];
-/** Offset 0x01A3 - UARTn Device Mode
+/** Offset 0x01A7 - UARTn Device Mode
Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartMode[3];
-/** Offset 0x01A6
+/** Offset 0x01AA
**/
- UINT8 UnusedUpdSpace8[2];
+ UINT8 UnusedUpdSpace9[2];
-/** Offset 0x01A8 - Default BaudRate for each Serial IO UART
+/** Offset 0x01AC - Default BaudRate for each Serial IO UART
Set default BaudRate Supported from 0 - default to 6000000
**/
UINT32 SerialIoUartBaudRate[3];
-/** Offset 0x01B4 - Default ParityType for each Serial IO UART
+/** Offset 0x01B8 - Default ParityType for each Serial IO UART
Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 SerialIoUartParity[3];
-/** Offset 0x01B7 - Default DataBits for each Serial IO UART
+/** Offset 0x01BB - Default DataBits for each Serial IO UART
Set default word length. 0: Default, 5,6,7,8
**/
UINT8 SerialIoUartDataBits[3];
-/** Offset 0x01BA - Default StopBits for each Serial IO UART
+/** Offset 0x01BE - Default StopBits for each Serial IO UART
Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
TwoStopBits
**/
UINT8 SerialIoUartStopBits[3];
-/** Offset 0x01BD - Power Gating mode for each Serial IO UART that works in COM mode
+/** Offset 0x01C1 - Power Gating mode for each Serial IO UART that works in COM mode
Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
**/
UINT8 SerialIoUartPowerGating[3];
-/** Offset 0x01C0 - Enable Dma for each Serial IO UART that supports it
+/** Offset 0x01C4 - Enable Dma for each Serial IO UART that supports it
Set DMA/PIO mode. 0: Disabled, 1: Enabled
**/
UINT8 SerialIoUartDmaEnable[3];
-/** Offset 0x01C3 - Enables UART hardware flow control, CTS and RTS lines
+/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines
Enables UART hardware flow control, CTS and RTS lines.
**/
UINT8 SerialIoUartAutoFlow[3];
-/** Offset 0x01C6 - Serial IO UART Pin Mux
+/** Offset 0x01CA - Serial IO UART Pin Mux
Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 -
F7 (PCH LP) J5 - J7 (PCH H)
**/
UINT8 SerialIoUartPinMux[3];
-/** Offset 0x01C9 - UART Number For Debug Purpose
+/** Offset 0x01CD - UART Number For Debug Purpose
UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
as CNVi BT Core interface, it cannot be used for debug purpose.
0:UART0, 1:UART1, 2:UART2
**/
UINT8 SerialIoDebugUartNumber;
-/** Offset 0x01CA - Serial IO UART DBG2 table
+/** Offset 0x01CE - Serial IO UART DBG2 table
Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
1: Enable.
**/
UINT8 SerialIoUartDbg2[3];
-/** Offset 0x01CD - Enable eMMC Controller
+/** Offset 0x01D1 - Enable eMMC Controller
Enable/disable eMMC Controller.
$EN_DIS
**/
UINT8 ScsEmmcEnabled;
-/** Offset 0x01CE - Enable eMMC HS400 Mode
+/** Offset 0x01D2 - Enable eMMC HS400 Mode
Enable eMMC HS400 Mode.
$EN_DIS
**/
UINT8 ScsEmmcHs400Enabled;
-/** Offset 0x01CF - Enable SdCard Controller
+/** Offset 0x01D3 - Enable SdCard Controller
Enable/disable SD Card Controller.
$EN_DIS
**/
UINT8 ScsSdCardEnabled;
-/** Offset 0x01D0 - Show SPI controller
+/** Offset 0x01D4 - Show SPI controller
Enable/disable to show SPI controller.
$EN_DIS
**/
UINT8 ShowSpiController;
-/** Offset 0x01D1 - Enable SATA SALP Support
+/** Offset 0x01D5 - Enable SATA SALP Support
Enable/disable SATA Aggressive Link Power Management.
$EN_DIS
**/
UINT8 SataSalpSupport;
-/** Offset 0x01D2 - Enable SATA ports
+/** Offset 0x01D6 - Enable SATA ports
Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
and so on.
**/
UINT8 SataPortsEnable[8];
-/** Offset 0x01DA - Enable SATA DEVSLP Feature
+/** Offset 0x01DE - Enable SATA DEVSLP Feature
Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
port, byte0 for port0, byte1 for port1, and so on.
**/
UINT8 SataPortsDevSlp[8];
-/** Offset 0x01E2 - Enable USB2 ports
+/** Offset 0x01E6 - Enable USB2 ports
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on.
**/
UINT8 PortUsb20Enable[16];
-/** Offset 0x01F2 - Enable USB3 ports
+/** Offset 0x01F6 - Enable USB3 ports
Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on.
**/
UINT8 PortUsb30Enable[10];
-/** Offset 0x01FC - Enable xDCI controller
+/** Offset 0x0200 - Enable xDCI controller
Enable/disable to xDCI controller.
$EN_DIS
**/
UINT8 XdciEnable;
-/** Offset 0x01FD
+/** Offset 0x0201
**/
- UINT8 UnusedUpdSpace9[3];
+ UINT8 UnusedUpdSpace10[3];
-/** Offset 0x0200 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+/** Offset 0x0204 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
**/
UINT32 DevIntConfigPtr;
-/** Offset 0x0204 - Number of DevIntConfig Entry
+/** Offset 0x0208 - Number of DevIntConfig Entry
Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
must not be NULL.
**/
UINT8 NumOfDevIntConfig;
-/** Offset 0x0205 - PIRQx to IRQx Map Config
+/** Offset 0x0209 - PIRQx to IRQx Map Config
PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
8259 PCI mode.
**/
UINT8 PxRcConfig[8];
-/** Offset 0x020D - Select GPIO IRQ Route
+/** Offset 0x0211 - Select GPIO IRQ Route
GPIO IRQ Select. The valid value is 14 or 15.
**/
UINT8 GpioIrqRoute;
-/** Offset 0x020E - Select SciIrqSelect
+/** Offset 0x0212 - Select SciIrqSelect
SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
**/
UINT8 SciIrqSelect;
-/** Offset 0x020F - Select TcoIrqSelect
+/** Offset 0x0213 - Select TcoIrqSelect
TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
**/
UINT8 TcoIrqSelect;
-/** Offset 0x0210 - Enable/Disable Tco IRQ
+/** Offset 0x0214 - Enable/Disable Tco IRQ
Enable/disable TCO IRQ
$EN_DIS
**/
UINT8 TcoIrqEnable;
-/** Offset 0x0211 - PCH HDA Verb Table Entry Number
+/** Offset 0x0215 - PCH HDA Verb Table Entry Number
Number of Entries in Verb Table.
**/
UINT8 PchHdaVerbTableEntryNum;
-/** Offset 0x0212
+/** Offset 0x0216
**/
- UINT8 UnusedUpdSpace10[2];
+ UINT8 UnusedUpdSpace11[2];
-/** Offset 0x0214 - PCH HDA Verb Table Pointer
+/** Offset 0x0218 - PCH HDA Verb Table Pointer
Pointer to Array of pointers to Verb Table.
**/
UINT32 PchHdaVerbTablePtr;
-/** Offset 0x0218 - PCH HDA Codec Sx Wake Capability
+/** Offset 0x021C - PCH HDA Codec Sx Wake Capability
Capability to detect wake initiated by a codec in Sx
**/
UINT8 PchHdaCodecSxWakeCapability;
-/** Offset 0x0219 - Enable SATA
+/** Offset 0x021D - Enable SATA
Enable/disable SATA controller.
$EN_DIS
**/
UINT8 SataEnable;
-/** Offset 0x021A - SATA Mode
+/** Offset 0x021E - SATA Mode
Select SATA controller working mode.
0:AHCI, 1:RAID
**/
UINT8 SataMode;
-/** Offset 0x021B - USB Per Port HS Preemphasis Bias
+/** Offset 0x021F - USB Per Port HS Preemphasis Bias
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
**/
UINT8 Usb2AfePetxiset[16];
-/** Offset 0x022B - USB Per Port HS Transmitter Bias
+/** Offset 0x022F - USB Per Port HS Transmitter Bias
USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
**/
UINT8 Usb2AfeTxiset[16];
-/** Offset 0x023B - USB Per Port HS Transmitter Emphasis
+/** Offset 0x023F - USB Per Port HS Transmitter Emphasis
USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
**/
UINT8 Usb2AfePredeemp[16];
-/** Offset 0x024B - USB Per Port Half Bit Pre-emphasis
+/** Offset 0x024F - USB Per Port Half Bit Pre-emphasis
USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
One byte for each port.
**/
UINT8 Usb2AfePehalfbit[16];
-/** Offset 0x025B - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+/** Offset 0x025F - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDeEmphEnable[10];
-/** Offset 0x0265 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+/** Offset 0x0269 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
<b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
**/
UINT8 Usb3HsioTxDeEmph[10];
-/** Offset 0x026F - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x0273 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-/** Offset 0x0279 - USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x027D - USB 3.0 TX Output Downscale Amplitude Adjustment
USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
= 00h</b>. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmp[10];
-/** Offset 0x0283 - Enable xHCI LTR override
+/** Offset 0x0287 - Enable xHCI LTR override
Enables override of recommended LTR values for xHCI
$EN_DIS
**/
UINT8 PchUsbLtrOverrideEnable;
-/** Offset 0x0284 - xHCI High Idle Time LTR override
+/** Offset 0x0288 - xHCI High Idle Time LTR override
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
**/
UINT32 PchUsbLtrHighIdleTimeOverride;
-/** Offset 0x0288 - xHCI Medium Idle Time LTR override
+/** Offset 0x028C - xHCI Medium Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
**/
UINT32 PchUsbLtrMediumIdleTimeOverride;
-/** Offset 0x028C - xHCI Low Idle Time LTR override
+/** Offset 0x0290 - xHCI Low Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
UINT32 PchUsbLtrLowIdleTimeOverride;
-/** Offset 0x0290 - Enable LAN
+/** Offset 0x0294 - Enable LAN
Enable/disable LAN controller.
$EN_DIS
**/
UINT8 PchLanEnable;
-/** Offset 0x0291 - Enable HD Audio Link
+/** Offset 0x0295 - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHda;
-/** Offset 0x0292 - Enable HD Audio DMIC0 Link
+/** Offset 0x0296 - Enable HD Audio DMIC0 Link
Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
$EN_DIS
**/
UINT8 PchHdaAudioLinkDmic0;
-/** Offset 0x0293 - Enable HD Audio DMIC1 Link
+/** Offset 0x0297 - Enable HD Audio DMIC1 Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
$EN_DIS
**/
UINT8 PchHdaAudioLinkDmic1;
-/** Offset 0x0294 - Enable HD Audio SSP0 Link
+/** Offset 0x0298 - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSsp0;
-/** Offset 0x0295 - Enable HD Audio SSP1 Link
+/** Offset 0x0299 - Enable HD Audio SSP1 Link
Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSsp1;
-/** Offset 0x0296 - Enable HD Audio SSP2 Link
+/** Offset 0x029A - Enable HD Audio SSP2 Link
Enable/disable HD Audio SSP2/I2S link.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSsp2;
-/** Offset 0x0297 - Enable HD Audio SoundWire#1 Link
+/** Offset 0x029B - Enable HD Audio SoundWire#1 Link
Enable/disable HD Audio SNDW1 link. Muxed with HDA.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSndw1;
-/** Offset 0x0298 - Enable HD Audio SoundWire#2 Link
+/** Offset 0x029C - Enable HD Audio SoundWire#2 Link
Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSndw2;
-/** Offset 0x0299 - Enable HD Audio SoundWire#3 Link
+/** Offset 0x029D - Enable HD Audio SoundWire#3 Link
Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSndw3;
-/** Offset 0x029A - Enable HD Audio SoundWire#4 Link
+/** Offset 0x029E - Enable HD Audio SoundWire#4 Link
Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
$EN_DIS
**/
UINT8 PchHdaAudioLinkSndw4;
-/** Offset 0x029B - Soundwire Clock Buffer GPIO RCOMP Setting
+/** Offset 0x029F - Soundwire Clock Buffer GPIO RCOMP Setting
0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
$EN_DIS
**/
UINT8 PchHdaSndwBufferRcomp;
-/** Offset 0x029C - PTM for PCIE RP Mask
+/** Offset 0x02A0 - PTM for PCIE RP Mask
Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
One bit for each port, bit0 for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpPtmMask;
-/** Offset 0x02A0 - DPC for PCIE RP Mask
+/** Offset 0x02A4 - DPC for PCIE RP Mask
Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
One bit for each port, bit0 for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpDpcMask;
-/** Offset 0x02A4 - DPC Extensions PCIE RP Mask
+/** Offset 0x02A8 - DPC Extensions PCIE RP Mask
Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
for each port, bit0 for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpDpcExtensionsMask;
-/** Offset 0x02A8 - USB PDO Programming
+/** Offset 0x02AC - USB PDO Programming
Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
during later phase. 1: enable, 0: disable
$EN_DIS
**/
UINT8 UsbPdoProgramming;
-/** Offset 0x02A9
+/** Offset 0x02AD
**/
- UINT8 UnusedUpdSpace11[3];
+ UINT8 UnusedUpdSpace12[3];
-/** Offset 0x02AC - Power button debounce configuration
+/** Offset 0x02B0 - Power button debounce configuration
Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
**/
UINT32 PmcPowerButtonDebounce;
-/** Offset 0x02B0 - PCH eSPI Master and Slave BME enabled
+/** Offset 0x02B4 - PCH eSPI Master and Slave BME enabled
PCH eSPI Master and Slave BME enabled
$EN_DIS
**/
UINT8 PchEspiBmeMasterSlaveEnabled;
-/** Offset 0x02B1 - PCH SATA use RST Legacy OROM
+/** Offset 0x02B5 - PCH SATA use RST Legacy OROM
Use PCH SATA RST Legacy OROM when CSM is Enabled
$EN_DIS
**/
UINT8 SataRstLegacyOrom;
-/** Offset 0x02B2
+/** Offset 0x02B6
**/
- UINT8 UnusedUpdSpace12[2];
+ UINT8 UnusedUpdSpace13[2];
-/** Offset 0x02B4 - Trace Hub Memory Base
+/** Offset 0x02B8 - Trace Hub Memory Base
If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
memory is configured properly.
**/
UINT32 TraceHubMemBase;
-/** Offset 0x02B8 - PMC Debug Message Enable
+/** Offset 0x02BC - PMC Debug Message Enable
When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
$EN_DIS
**/
UINT8 PmcDbgMsgEn;
-/** Offset 0x02B9
+/** Offset 0x02BD
**/
- UINT8 UnusedUpdSpace13[3];
+ UINT8 UnusedUpdSpace14[3];
-/** Offset 0x02BC - Pointer of ChipsetInit Binary
+/** Offset 0x02C0 - Pointer of ChipsetInit Binary
ChipsetInit Binary Pointer.
**/
UINT32 ChipsetInitBinPtr;
-/** Offset 0x02C0 - Length of ChipsetInit Binary
+/** Offset 0x02C4 - Length of ChipsetInit Binary
ChipsetInit Binary Length.
**/
UINT32 ChipsetInitBinLen;
-/** Offset 0x02C4 - Enable Ufs Controller
+/** Offset 0x02C8 - Enable Ufs Controller
Enable/disable Ufs 2.0 Controller.
$EN_DIS
**/
UINT8 ScsUfsEnabled;
-/** Offset 0x02C5 - CNVi Configuration
+/** Offset 0x02C9 - CNVi Configuration
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
0:Disable, 1:Auto
**/
UINT8 CnviMode;
-/** Offset 0x02C6 - CNVi BT Core
+/** Offset 0x02CA - CNVi BT Core
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtCore;
-/** Offset 0x02C7 - CNVi BT Audio Offload
+/** Offset 0x02CB - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
-/** Offset 0x02C8 - SdCard power enable polarity
+/** Offset 0x02CC - SdCard power enable polarity
Choose SD_PWREN# polarity
0: Active low, 1: Active high
**/
UINT8 SdCardPowerEnableActiveHigh;
-/** Offset 0x02C9 - PCH USB2 PHY Power Gating enable
+/** Offset 0x02CD - PCH USB2 PHY Power Gating enable
1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
Sus Well PG
$EN_DIS
**/
UINT8 PchUsb2PhySusPgEnable;
-/** Offset 0x02CA - PCH USB OverCurrent mapping enable
+/** Offset 0x02CE - PCH USB OverCurrent mapping enable
1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
mapping allow for NOA usage of OC pins
$EN_DIS
**/
UINT8 PchUsbOverCurrentEnable;
-/** Offset 0x02CB - Espi Lgmr Memory Range decode
+/** Offset 0x02CF - Espi Lgmr Memory Range decode
This option enables or disables espi lgmr
$EN_DIS
**/
UINT8 PchEspiLgmrEnable;
-/** Offset 0x02CC - PCHHOT# pin
+/** Offset 0x02D0 - PCHHOT# pin
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchHotEnable;
-/** Offset 0x02CD - SATA LED
+/** Offset 0x02D1 - SATA LED
SATA LED indicating SATA controller activity. 0: disable, 1: enable
$EN_DIS
**/
UINT8 SataLedEnable;
-/** Offset 0x02CE - VRAlert# Pin
+/** Offset 0x02D2 - VRAlert# Pin
When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmVrAlert;
-/** Offset 0x02CF - SLP_S0 VM Dynamic Control
+/** Offset 0x02D3 - SLP_S0 VM Dynamic Control
SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmSlpS0VmRuntimeControl;
-/** Offset 0x02D0 - SLP_S0 VM 0.70V Support
+/** Offset 0x02D4 - SLP_S0 VM 0.70V Support
SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmSlpS0Vm070VSupport;
-/** Offset 0x02D1 - SLP_S0 VM 0.75V Support
+/** Offset 0x02D5 - SLP_S0 VM 0.75V Support
SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmSlpS0Vm075VSupport;
-/** Offset 0x02D2 - PCH PCIe root port connection type
+/** Offset 0x02D6 - PCH PCIe root port connection type
0: built-in device, 1:slot
**/
UINT8 PcieRpSlotImplemented[24];
-/** Offset 0x02EA - Usage type for ClkSrc
+/** Offset 0x02EE - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
(free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[16];
-/** Offset 0x02FA - ClkReq-to-ClkSrc mapping
+/** Offset 0x02FE - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[16];
-/** Offset 0x030A - PCIE RP Access Control Services Extended Capability
+/** Offset 0x030E - PCIE RP Access Control Services Extended Capability
Enable/Disable PCIE RP Access Control Services Extended Capability
**/
UINT8 PcieRpAcsEnabled[24];
-/** Offset 0x0322 - PCIE RP Clock Power Management
+/** Offset 0x0326 - PCIE RP Clock Power Management
Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
can still be controlled by L1 PM substates mechanism
**/
UINT8 PcieRpEnableCpm[24];
-/** Offset 0x033A - PCIE RP Detect Timeout Ms
+/** Offset 0x033E - PCIE RP Detect Timeout Ms
The number of milliseconds within 0~65535 in reference code will wait for link to
exit Detect state for enabled ports before assuming there is no device and potentially
disabling the port.
**/
UINT16 PcieRpDetectTimeoutMs[24];
-/** Offset 0x036A - ModPHY SUS Power Domain Dynamic Gating
+/** Offset 0x036E - ModPHY SUS Power Domain Dynamic Gating
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
PCH-H. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcModPhySusPgEnable;
-/** Offset 0x036B - SlpS0WithGbeSupport
+/** Offset 0x036F - SlpS0WithGbeSupport
Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping
CPU and 1 for all other CPUs. 0: Disable, 1: Enable
$EN_DIS
**/
UINT8 SlpS0WithGbeSupport;
-/** Offset 0x036C - Enable Power Optimizer
+/** Offset 0x0370 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x036D - PCH Flash Protection Ranges Write Enble
+/** Offset 0x0371 - PCH Flash Protection Ranges Write Enble
Write or erase is blocked by hardware.
**/
UINT8 PchWriteProtectionEnable[5];
-/** Offset 0x0372 - PCH Flash Protection Ranges Read Enble
+/** Offset 0x0376 - PCH Flash Protection Ranges Read Enble
Read is blocked by hardware.
**/
UINT8 PchReadProtectionEnable[5];
-/** Offset 0x0377
+/** Offset 0x037B
**/
- UINT8 UnusedUpdSpace14[1];
+ UINT8 UnusedUpdSpace15[1];
-/** Offset 0x0378 - PCH Protect Range Limit
+/** Offset 0x037C - PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
-/** Offset 0x0382 - PCH Protect Range Base
+/** Offset 0x0386 - PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
-/** Offset 0x038C - Enable Pme
+/** Offset 0x0390 - Enable Pme
Enable Azalia wake-on-ring.
$EN_DIS
**/
UINT8 PchHdaPme;
-/** Offset 0x038D - VC Type
+/** Offset 0x0391 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1.
0: VC0, 1: VC1
**/
UINT8 PchHdaVcType;
-/** Offset 0x038E - HD Audio Link Frequency
+/** Offset 0x0392 - HD Audio Link Frequency
HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
0: 6MHz, 1: 12MHz, 2: 24MHz
**/
UINT8 PchHdaLinkFrequency;
-/** Offset 0x038F - iDisp-Link Frequency
+/** Offset 0x0393 - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x0390 - iDisp-Link T-mode
+/** Offset 0x0394 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
0: 2T, 1: 1T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x0391 - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x0395 - Universal Audio Architecture compliance for DSP enabled system
0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
driver or SST driver supported).
$EN_DIS
**/
UINT8 PchHdaDspUaaCompliance;
-/** Offset 0x0392 - iDisplay Audio Codec disconnection
+/** Offset 0x0396 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x0393 - USB LFPS Filter selection
+/** Offset 0x0397 - USB LFPS Filter selection
For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns,
3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.
**/
UINT8 PchUsbHsioFilterSel[10];
-/** Offset 0x039D - Enable PCH Io Apic Entry 24-119
+/** Offset 0x03A1 - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIoApicEntry24_119;
-/** Offset 0x039E - PCH Io Apic ID
+/** Offset 0x03A2 - PCH Io Apic ID
This member determines IOAPIC ID. Default is 0x02.
**/
UINT8 PchIoApicId;
-/** Offset 0x039F - Enable PCH ISH SPI GPIO pins assigned
+/** Offset 0x03A3 - Enable PCH ISH SPI GPIO pins assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshSpiGpioAssign;
-/** Offset 0x03A0 - Enable PCH ISH UART0 GPIO pins assigned
+/** Offset 0x03A4 - Enable PCH ISH UART0 GPIO pins assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshUart0GpioAssign;
-/** Offset 0x03A1 - Enable PCH ISH UART1 GPIO pins assigned
+/** Offset 0x03A5 - Enable PCH ISH UART1 GPIO pins assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshUart1GpioAssign;
-/** Offset 0x03A2 - Enable PCH ISH I2C0 GPIO pins assigned
+/** Offset 0x03A6 - Enable PCH ISH I2C0 GPIO pins assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshI2c0GpioAssign;
-/** Offset 0x03A3 - Enable PCH ISH I2C1 GPIO pins assigned
+/** Offset 0x03A7 - Enable PCH ISH I2C1 GPIO pins assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshI2c1GpioAssign;
-/** Offset 0x03A4 - Enable PCH ISH I2C2 GPIO pins assigned
+/** Offset 0x03A8 - Enable PCH ISH I2C2 GPIO pins assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshI2c2GpioAssign;
-/** Offset 0x03A5 - Enable PCH ISH GP_0 GPIO pin assigned
+/** Offset 0x03A9 - Enable PCH ISH GP_0 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp0GpioAssign;
-/** Offset 0x03A6 - Enable PCH ISH GP_1 GPIO pin assigned
+/** Offset 0x03AA - Enable PCH ISH GP_1 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp1GpioAssign;
-/** Offset 0x03A7 - Enable PCH ISH GP_2 GPIO pin assigned
+/** Offset 0x03AB - Enable PCH ISH GP_2 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp2GpioAssign;
-/** Offset 0x03A8 - Enable PCH ISH GP_3 GPIO pin assigned
+/** Offset 0x03AC - Enable PCH ISH GP_3 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp3GpioAssign;
-/** Offset 0x03A9 - Enable PCH ISH GP_4 GPIO pin assigned
+/** Offset 0x03AD - Enable PCH ISH GP_4 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp4GpioAssign;
-/** Offset 0x03AA - Enable PCH ISH GP_5 GPIO pin assigned
+/** Offset 0x03AE - Enable PCH ISH GP_5 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp5GpioAssign;
-/** Offset 0x03AB - Enable PCH ISH GP_6 GPIO pin assigned
+/** Offset 0x03AF - Enable PCH ISH GP_6 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp6GpioAssign;
-/** Offset 0x03AC - Enable PCH ISH GP_7 GPIO pin assigned
+/** Offset 0x03B0 - Enable PCH ISH GP_7 GPIO pin assigned
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIshGp7GpioAssign;
-/** Offset 0x03AD - PCH ISH PDT Unlock Msg
+/** Offset 0x03B1 - PCH ISH PDT Unlock Msg
0: False; 1: True.
$EN_DIS
**/
UINT8 PchIshPdtUnlock;
-/** Offset 0x03AE - Enable PCH Lan LTR capabilty of PCH internal LAN
+/** Offset 0x03B2 - Enable PCH Lan LTR capabilty of PCH internal LAN
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchLanLtrEnable;
-/** Offset 0x03AF - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x03B3 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x03B0 - PCH Compatibility Revision ID
+/** Offset 0x03B4 - PCH Compatibility Revision ID
This member describes whether or not the CRID feature of PCH should be enabled.
$EN_DIS
**/
UINT8 PchCrid;
-/** Offset 0x03B1 - RTC CMOS MEMORY LOCK
+/** Offset 0x03B5 - RTC CMOS MEMORY LOCK
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 PchLockDownRtcMemoryLock;
-/** Offset 0x03B2 - Enable PCIE RP HotPlug
+/** Offset 0x03B6 - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[24];
-/** Offset 0x03CA - Enable PCIE RP Pm Sci
+/** Offset 0x03CE - Enable PCIE RP Pm Sci
Indicate whether the root port power manager SCI is enabled.
**/
UINT8 PcieRpPmSci[24];
-/** Offset 0x03E2 - Enable PCIE RP Ext Sync
+/** Offset 0x03E6 - Enable PCIE RP Ext Sync
Indicate whether the extended synch is enabled.
**/
UINT8 PcieRpExtSync[24];
-/** Offset 0x03FA - Enable PCIE RP Transmitter Half Swing
+/** Offset 0x03FE - Enable PCIE RP Transmitter Half Swing
Indicate whether the Transmitter Half Swing is enabled.
**/
UINT8 PcieRpTransmitterHalfSwing[24];
-/** Offset 0x0412 - Enable PCIE RP Clk Req Detect
+/** Offset 0x0416 - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[24];
-/** Offset 0x042A - PCIE RP Advanced Error Report
+/** Offset 0x042E - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[24];
-/** Offset 0x0442 - PCIE RP Unsupported Request Report
+/** Offset 0x0446 - PCIE RP Unsupported Request Report
Indicate whether the Unsupported Request Report is enabled.
**/
UINT8 PcieRpUnsupportedRequestReport[24];
-/** Offset 0x045A - PCIE RP Fatal Error Report
+/** Offset 0x045E - PCIE RP Fatal Error Report
Indicate whether the Fatal Error Report is enabled.
**/
UINT8 PcieRpFatalErrorReport[24];
-/** Offset 0x0472 - PCIE RP No Fatal Error Report
+/** Offset 0x0476 - PCIE RP No Fatal Error Report
Indicate whether the No Fatal Error Report is enabled.
**/
UINT8 PcieRpNoFatalErrorReport[24];
-/** Offset 0x048A - PCIE RP Correctable Error Report
+/** Offset 0x048E - PCIE RP Correctable Error Report
Indicate whether the Correctable Error Report is enabled.
**/
UINT8 PcieRpCorrectableErrorReport[24];
-/** Offset 0x04A2 - PCIE RP System Error On Fatal Error
+/** Offset 0x04A6 - PCIE RP System Error On Fatal Error
Indicate whether the System Error on Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnFatalError[24];
-/** Offset 0x04BA - PCIE RP System Error On Non Fatal Error
+/** Offset 0x04BE - PCIE RP System Error On Non Fatal Error
Indicate whether the System Error on Non Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnNonFatalError[24];
-/** Offset 0x04D2 - PCIE RP System Error On Correctable Error
+/** Offset 0x04D6 - PCIE RP System Error On Correctable Error
Indicate whether the System Error on Correctable Error is enabled.
**/
UINT8 PcieRpSystemErrorOnCorrectableError[24];
-/** Offset 0x04EA - PCIE RP Max Payload
+/** Offset 0x04EE - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[24];
-/** Offset 0x0502 - PCH USB3 RX HSIO Tuning parameters
+/** Offset 0x0506 - PCH USB3 RX HSIO Tuning parameters
Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for
controlling the input offset
**/
UINT8 PchUsbHsioRxTuningParameters[10];
-/** Offset 0x050C - PCH USB3 HSIO Rx Tuning Enable
+/** Offset 0x0510 - PCH USB3 HSIO Rx Tuning Enable
Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
**/
UINT8 PchUsbHsioRxTuningEnable[10];
-/** Offset 0x0516 - PCIE RP Pcie Speed
+/** Offset 0x051A - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
PCH_PCIE_SPEED).
**/
UINT8 PcieRpPcieSpeed[24];
-/** Offset 0x052E - PCIE RP Gen3 Equalization Phase Method
+/** Offset 0x0532 - PCIE RP Gen3 Equalization Phase Method
PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
1: hardware equalization; 4: Fixed Coeficients.
**/
UINT8 PcieRpGen3EqPh3Method[24];
-/** Offset 0x0546 - PCIE RP Physical Slot Number
+/** Offset 0x054A - PCIE RP Physical Slot Number
Indicates the slot number for the root port. Default is the value as root port index.
**/
UINT8 PcieRpPhysicalSlotNumber[24];
-/** Offset 0x055E - PCIE RP Completion Timeout
+/** Offset 0x0562 - PCIE RP Completion Timeout
The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
**/
UINT8 PcieRpCompletionTimeout[24];
-/** Offset 0x0576 - PCIE RP Aspm
+/** Offset 0x057A - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[24];
-/** Offset 0x058E - PCIE RP L1 Substates
+/** Offset 0x0592 - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[24];
-/** Offset 0x05A6 - PCIE RP Ltr Enable
+/** Offset 0x05AA - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[24];
-/** Offset 0x05BE - PCIE RP Ltr Config Lock
+/** Offset 0x05C2 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 PcieRpLtrConfigLock[24];
-/** Offset 0x05D6 - PCIE Eq Ph3 Lane Param Cm
+/** Offset 0x05DA - PCIE Eq Ph3 Lane Param Cm
PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
**/
UINT8 PcieEqPh3LaneParamCm[24];
-/** Offset 0x05EE - PCIE Eq Ph3 Lane Param Cp
+/** Offset 0x05F2 - PCIE Eq Ph3 Lane Param Cp
PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
**/
UINT8 PcieEqPh3LaneParamCp[24];
-/** Offset 0x0606 - PCIE Sw Eq CoeffList Cm
- PCH_PCIE_EQ_PARAM. Coefficient C-1.
+/** Offset 0x060A - PCIE Sw Eq CoeffList Cm
+ PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients,
+ the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered.
**/
UINT8 PcieSwEqCoeffListCm[5];
-/** Offset 0x060B - PCIE Sw Eq CoeffList Cp
- PCH_PCIE_EQ_PARAM. Coefficient C+1.
+/** Offset 0x060F - PCIE Sw Eq CoeffList Cp
+ PCH_PCIE_EQ_PARAM. Coefficient C+1.The values depend on PcieNumOfCoefficients, the
+ default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered.
**/
UINT8 PcieSwEqCoeffListCp[5];
-/** Offset 0x0610 - PCIE Disable RootPort Clock Gating
+/** Offset 0x0614 - PCIE Disable RootPort Clock Gating
Describes whether the PCI Express Clock Gating for each root port is enabled by
platform modules. 0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PcieDisableRootPortClockGating;
-/** Offset 0x0611 - PCIE Enable Peer Memory Write
+/** Offset 0x0615 - PCIE Enable Peer Memory Write
This member describes whether Peer Memory Writes are enabled on the platform.
$EN_DIS
**/
UINT8 PcieEnablePeerMemoryWrite;
-/** Offset 0x0612 - PCIE Compliance Test Mode
+/** Offset 0x0616 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 PcieComplianceTestMode;
-/** Offset 0x0613 - PCIE Rp Function Swap
+/** Offset 0x0617 - PCIE Rp Function Swap
Allows BIOS to use root port function number swapping when root port of function
0 is disabled.
$EN_DIS
**/
UINT8 PcieRpFunctionSwap;
-/** Offset 0x0614 - Teton Glacier Cycle Router
+/** Offset 0x0618 - Teton Glacier Cycle Router
Specify to which cycle router Teton Glacier is connected, it is valid only when
Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system
**/
UINT8 TetonGlacierCR;
-/** Offset 0x0615 - PCH Pm PME_B0_S5_DIS
+/** Offset 0x0619 - PCH Pm PME_B0_S5_DIS
When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
$EN_DIS
**/
UINT8 PchPmPmeB0S5Dis;
-/** Offset 0x0616 - PCIE IMR
+/** Offset 0x061A - PCIE IMR
Enables Isolated Memory Region for PCIe.
$EN_DIS
**/
UINT8 PcieRpImrEnabled;
-/** Offset 0x0617 - PCIE IMR port number
+/** Offset 0x061B - PCIE IMR port number
Selects PCIE root port number for IMR feature.
**/
UINT8 PcieRpImrSelection;
-/** Offset 0x0618 - Teton Glacier Detection and Configuration Mode
+/** Offset 0x061C - Teton Glacier Detection and Configuration Mode
Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic
Configuration. Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 TetonGlacierMode;
-/** Offset 0x0619 - PCH Pm Wol Enable Override
+/** Offset 0x061D - PCH Pm Wol Enable Override
Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
$EN_DIS
**/
UINT8 PchPmWolEnableOverride;
-/** Offset 0x061A - PCH Pm Pcie Wake From DeepSx
+/** Offset 0x061E - PCH Pm Pcie Wake From DeepSx
Determine if enable PCIe to wake from deep Sx.
$EN_DIS
**/
UINT8 PchPmPcieWakeFromDeepSx;
-/** Offset 0x061B - PCH Pm WoW lan Enable
+/** Offset 0x061F - PCH Pm WoW lan Enable
Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanEnable;
-/** Offset 0x061C - PCH Pm WoW lan DeepSx Enable
+/** Offset 0x0620 - PCH Pm WoW lan DeepSx Enable
Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanDeepSxEnable;
-/** Offset 0x061D - PCH Pm Lan Wake From DeepSx
+/** Offset 0x0621 - PCH Pm Lan Wake From DeepSx
Determine if enable LAN to wake from deep Sx.
$EN_DIS
**/
UINT8 PchPmLanWakeFromDeepSx;
-/** Offset 0x061E - PCH Pm Deep Sx Pol
+/** Offset 0x0622 - PCH Pm Deep Sx Pol
Deep Sx Policy.
$EN_DIS
**/
UINT8 PchPmDeepSxPol;
-/** Offset 0x061F - PCH Pm Slp S3 Min Assert
+/** Offset 0x0623 - PCH Pm Slp S3 Min Assert
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
UINT8 PchPmSlpS3MinAssert;
-/** Offset 0x0620 - PCH Pm Slp S4 Min Assert
+/** Offset 0x0624 - PCH Pm Slp S4 Min Assert
SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
**/
UINT8 PchPmSlpS4MinAssert;
-/** Offset 0x0621 - PCH Pm Slp Sus Min Assert
+/** Offset 0x0625 - PCH Pm Slp Sus Min Assert
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
UINT8 PchPmSlpSusMinAssert;
-/** Offset 0x0622 - PCH Pm Slp A Min Assert
+/** Offset 0x0626 - PCH Pm Slp A Min Assert
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
UINT8 PchPmSlpAMinAssert;
-/** Offset 0x0623 - SLP_S0# Override
+/** Offset 0x0627 - SLP_S0# Override
Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
when debug is enabled. \n
@@ -1791,7 +1803,7 @@ typedef struct {
**/
UINT8 SlpS0Override;
-/** Offset 0x0624 - S0ix Override Settings
+/** Offset 0x0628 - S0ix Override Settings
Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
keep PMC default settings. Or select the desired debug probe type for S0ix Override
settings.\n
@@ -1802,498 +1814,498 @@ typedef struct {
**/
UINT8 SlpS0DisQForDebug;
-/** Offset 0x0625 - USB Overcurrent Override for DbC
+/** Offset 0x0629 - USB Overcurrent Override for DbC
This option overrides USB Over Current enablement state that USB OC will be disabled
after enabling this option. Enable when DbC is used to avoid signaling conflicts.
$EN_DIS
**/
UINT8 PchEnableDbcObs;
-/** Offset 0x0626 - PCH Legacy IO Low Latency Enable
+/** Offset 0x062A - PCH Legacy IO Low Latency Enable
Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
$EN_DIS
**/
UINT8 PchLegacyIoLowLatency;
-/** Offset 0x0627 - PCH Pm Lpc Clock Run
+/** Offset 0x062B - PCH Pm Lpc Clock Run
This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
Default value is Disabled
$EN_DIS
**/
UINT8 PchPmLpcClockRun;
-/** Offset 0x0628 - PCH Pm Slp Strch Sus Up
+/** Offset 0x062C - PCH Pm Slp Strch Sus Up
Enable SLP_X Stretching After SUS Well Power Up.
$EN_DIS
**/
UINT8 PchPmSlpStrchSusUp;
-/** Offset 0x0629 - PCH Pm Slp Lan Low Dc
+/** Offset 0x062D - PCH Pm Slp Lan Low Dc
Enable/Disable SLP_LAN# Low on DC Power.
$EN_DIS
**/
UINT8 PchPmSlpLanLowDc;
-/** Offset 0x062A - PCH Pm Pwr Btn Override Period
+/** Offset 0x062E - PCH Pm Pwr Btn Override Period
PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
**/
UINT8 PchPmPwrBtnOverridePeriod;
-/** Offset 0x062B - PCH Pm Disable Dsx Ac Present Pulldown
+/** Offset 0x062F - PCH Pm Disable Dsx Ac Present Pulldown
When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
$EN_DIS
**/
UINT8 PchPmDisableDsxAcPresentPulldown;
-/** Offset 0x062C - PCH Pm Disable Native Power Button
+/** Offset 0x0630 - PCH Pm Disable Native Power Button
Power button native mode disable.
$EN_DIS
**/
UINT8 PchPmDisableNativePowerButton;
-/** Offset 0x062D - PCH Pm Slp S0 Enable
+/** Offset 0x0631 - PCH Pm Slp S0 Enable
Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
$EN_DIS
**/
UINT8 PchPmSlpS0Enable;
-/** Offset 0x062E - PCH Pm ME_WAKE_STS
+/** Offset 0x0632 - PCH Pm ME_WAKE_STS
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmMeWakeSts;
-/** Offset 0x062F - PCH Pm WOL_OVR_WK_STS
+/** Offset 0x0633 - PCH Pm WOL_OVR_WK_STS
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmWolOvrWkSts;
-/** Offset 0x0630 - PCH Pm Reset Power Cycle Duration
+/** Offset 0x0634 - PCH Pm Reset Power Cycle Duration
Could be customized in the unit of second. Please refer to EDS for all support settings.
0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
UINT8 PchPmPwrCycDur;
-/** Offset 0x0631 - PCH Pm Pcie Pll Ssc
+/** Offset 0x0635 - PCH Pm Pcie Pll Ssc
Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
BIOS override.
**/
UINT8 PchPmPciePllSsc;
-/** Offset 0x0632 - PCH Sata Pwr Opt Enable
+/** Offset 0x0636 - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x0633 - PCH Sata eSATA Speed Limit
+/** Offset 0x0637 - PCH Sata eSATA Speed Limit
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
$EN_DIS
**/
UINT8 EsataSpeedLimit;
-/** Offset 0x0634 - PCH Sata Speed Limit
+/** Offset 0x0638 - PCH Sata Speed Limit
Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
**/
UINT8 SataSpeedLimit;
-/** Offset 0x0635 - Enable SATA Port HotPlug
+/** Offset 0x0639 - Enable SATA Port HotPlug
Enable SATA Port HotPlug.
**/
UINT8 SataPortsHotPlug[8];
-/** Offset 0x063D - Enable SATA Port Interlock Sw
+/** Offset 0x0641 - Enable SATA Port Interlock Sw
Enable SATA Port Interlock Sw.
**/
UINT8 SataPortsInterlockSw[8];
-/** Offset 0x0645 - Enable SATA Port External
+/** Offset 0x0649 - Enable SATA Port External
Enable SATA Port External.
**/
UINT8 SataPortsExternal[8];
-/** Offset 0x064D - Enable SATA Port SpinUp
+/** Offset 0x0651 - Enable SATA Port SpinUp
Enable the COMRESET initialization Sequence to the device.
**/
UINT8 SataPortsSpinUp[8];
-/** Offset 0x0655 - Enable SATA Port Solid State Drive
+/** Offset 0x0659 - Enable SATA Port Solid State Drive
0: HDD; 1: SSD.
**/
UINT8 SataPortsSolidStateDrive[8];
-/** Offset 0x065D - Enable SATA Port Enable Dito Config
+/** Offset 0x0661 - Enable SATA Port Enable Dito Config
Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
**/
UINT8 SataPortsEnableDitoConfig[8];
-/** Offset 0x0665 - Enable SATA Port DmVal
+/** Offset 0x0669 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x066D
+/** Offset 0x0671
**/
- UINT8 UnusedUpdSpace15[1];
+ UINT8 UnusedUpdSpace16[1];
-/** Offset 0x066E - Enable SATA Port DmVal
+/** Offset 0x0672 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x067E - Enable SATA Port ZpOdd
+/** Offset 0x0682 - Enable SATA Port ZpOdd
Support zero power ODD.
**/
UINT8 SataPortsZpOdd[8];
-/** Offset 0x0686 - PCH Sata Rst Raid Device Id
+/** Offset 0x068A - PCH Sata Rst Raid Device Id
Enable RAID Alternate ID.
0:Client, 1:Alternate, 2:Server
**/
UINT8 SataRstRaidDeviceId;
-/** Offset 0x0687 - PCH Sata Rst Raid0
+/** Offset 0x068B - PCH Sata Rst Raid0
RAID0.
$EN_DIS
**/
UINT8 SataRstRaid0;
-/** Offset 0x0688 - PCH Sata Rst Raid1
+/** Offset 0x068C - PCH Sata Rst Raid1
RAID1.
$EN_DIS
**/
UINT8 SataRstRaid1;
-/** Offset 0x0689 - PCH Sata Rst Raid10
+/** Offset 0x068D - PCH Sata Rst Raid10
RAID10.
$EN_DIS
**/
UINT8 SataRstRaid10;
-/** Offset 0x068A - PCH Sata Rst Raid5
+/** Offset 0x068E - PCH Sata Rst Raid5
RAID5.
$EN_DIS
**/
UINT8 SataRstRaid5;
-/** Offset 0x068B - PCH Sata Rst Irrt
+/** Offset 0x068F - PCH Sata Rst Irrt
Intel Rapid Recovery Technology.
$EN_DIS
**/
UINT8 SataRstIrrt;
-/** Offset 0x068C - PCH Sata Rst Orom Ui Banner
+/** Offset 0x0690 - PCH Sata Rst Orom Ui Banner
OROM UI and BANNER.
$EN_DIS
**/
UINT8 SataRstOromUiBanner;
-/** Offset 0x068D - PCH Sata Rst Orom Ui Delay
+/** Offset 0x0691 - PCH Sata Rst Orom Ui Delay
00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
**/
UINT8 SataRstOromUiDelay;
-/** Offset 0x068E - PCH Sata Rst Hdd Unlock
+/** Offset 0x0692 - PCH Sata Rst Hdd Unlock
Indicates that the HDD password unlock in the OS is enabled.
$EN_DIS
**/
UINT8 SataRstHddUnlock;
-/** Offset 0x068F - PCH Sata Rst Led Locate
+/** Offset 0x0693 - PCH Sata Rst Led Locate
Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
enabled on the OS.
$EN_DIS
**/
UINT8 SataRstLedLocate;
-/** Offset 0x0690 - PCH Sata Rst Irrt Only
+/** Offset 0x0694 - PCH Sata Rst Irrt Only
Allow only IRRT drives to span internal and external ports.
$EN_DIS
**/
UINT8 SataRstIrrtOnly;
-/** Offset 0x0691 - PCH Sata Rst Smart Storage
+/** Offset 0x0695 - PCH Sata Rst Smart Storage
RST Smart Storage caching Bit.
$EN_DIS
**/
UINT8 SataRstSmartStorage;
-/** Offset 0x0692 - PCH Sata Rst Pcie Storage Remap enable
+/** Offset 0x0696 - PCH Sata Rst Pcie Storage Remap enable
Enable Intel RST for PCIe Storage remapping.
**/
UINT8 SataRstPcieEnable[3];
-/** Offset 0x0695 - PCH Sata Rst Pcie Storage Port
+/** Offset 0x0699 - PCH Sata Rst Pcie Storage Port
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
**/
UINT8 SataRstPcieStoragePort[3];
-/** Offset 0x0698 - PCH Sata Rst Pcie Device Reset Delay
+/** Offset 0x069C - PCH Sata Rst Pcie Device Reset Delay
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
**/
UINT8 SataRstPcieDeviceResetDelay[3];
-/** Offset 0x069B - Enable eMMC HS400 Training
+/** Offset 0x069F - Enable eMMC HS400 Training
Deprecated.
$EN_DIS
**/
UINT8 PchScsEmmcHs400TuningRequired;
-/** Offset 0x069C - Set HS400 Tuning Data Valid
+/** Offset 0x06A0 - Set HS400 Tuning Data Valid
Set if HS400 Tuning Data Valid.
$EN_DIS
**/
UINT8 PchScsEmmcHs400DllDataValid;
-/** Offset 0x069D - Rx Strobe Delay Control
+/** Offset 0x06A1 - Rx Strobe Delay Control
Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
**/
UINT8 PchScsEmmcHs400RxStrobeDll1;
-/** Offset 0x069E - Tx Data Delay Control
+/** Offset 0x06A2 - Tx Data Delay Control
Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
**/
UINT8 PchScsEmmcHs400TxDataDll;
-/** Offset 0x069F - I/O Driver Strength
+/** Offset 0x06A3 - I/O Driver Strength
Deprecated.
0:33 Ohm, 1:40 Ohm, 2:50 Ohm
**/
UINT8 PchScsEmmcHs400DriverStrength;
-/** Offset 0x06A0 - Enable Serial IRQ
+/** Offset 0x06A4 - Enable Serial IRQ
Determines if enable Serial IRQ.
$EN_DIS
**/
UINT8 PchSirqEnable;
-/** Offset 0x06A1 - Serial IRQ Mode Select
+/** Offset 0x06A5 - Serial IRQ Mode Select
Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
$EN_DIS
**/
UINT8 PchSirqMode;
-/** Offset 0x06A2 - Start Frame Pulse Width
+/** Offset 0x06A6 - Start Frame Pulse Width
Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
**/
UINT8 PchStartFramePulse;
-/** Offset 0x06A3 - Reserved
+/** Offset 0x06A7 - Reserved
Reserved
$EN_DIS
**/
UINT8 ReservedForFuture1;
-/** Offset 0x06A4 - Thermal Device SMI Enable
+/** Offset 0x06A8 - Thermal Device SMI Enable
This locks down SMI Enable on Alert Thermal Sensor Trip.
$EN_DIS
**/
UINT8 PchTsmicLock;
-/** Offset 0x06A5
+/** Offset 0x06A9
**/
- UINT8 UnusedUpdSpace16;
+ UINT8 UnusedUpdSpace17;
-/** Offset 0x06A6 - Thermal Throttling Custimized T0Level Value
+/** Offset 0x06AA - Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 PchT0Level;
-/** Offset 0x06A8 - Thermal Throttling Custimized T1Level Value
+/** Offset 0x06AC - Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 PchT1Level;
-/** Offset 0x06AA - Thermal Throttling Custimized T2Level Value
+/** Offset 0x06AE - Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 PchT2Level;
-/** Offset 0x06AC - Enable The Thermal Throttle
+/** Offset 0x06B0 - Enable The Thermal Throttle
Enable the thermal throttle function.
$EN_DIS
**/
UINT8 PchTTEnable;
-/** Offset 0x06AD - PMSync State 13
+/** Offset 0x06B1 - PMSync State 13
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
at least T2 state.
$EN_DIS
**/
UINT8 PchTTState13Enable;
-/** Offset 0x06AE - Thermal Throttle Lock
+/** Offset 0x06B2 - Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 PchTTLock;
-/** Offset 0x06AF - Thermal Throttling Suggested Setting
+/** Offset 0x06B3 - Thermal Throttling Suggested Setting
Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 TTSuggestedSetting;
-/** Offset 0x06B0 - Enable PCH Cross Throttling
+/** Offset 0x06B4 - Enable PCH Cross Throttling
Enable/Disable PCH Cross Throttling
$EN_DIS
**/
UINT8 TTCrossThrottling;
-/** Offset 0x06B1 - DMI Thermal Sensor Autonomous Width Enable
+/** Offset 0x06B5 - DMI Thermal Sensor Autonomous Width Enable
DMI Thermal Sensor Autonomous Width Enable.
$EN_DIS
**/
UINT8 PchDmiTsawEn;
-/** Offset 0x06B2 - DMI Thermal Sensor Suggested Setting
+/** Offset 0x06B6 - DMI Thermal Sensor Suggested Setting
DMT thermal sensor suggested representative values.
$EN_DIS
**/
UINT8 DmiSuggestedSetting;
-/** Offset 0x06B3 - Thermal Sensor 0 Target Width
+/** Offset 0x06B7 - Thermal Sensor 0 Target Width
DMT thermal sensor suggested representative values.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS0TW;
-/** Offset 0x06B4 - Thermal Sensor 1 Target Width
+/** Offset 0x06B8 - Thermal Sensor 1 Target Width
Thermal Sensor 1 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS1TW;
-/** Offset 0x06B5 - Thermal Sensor 2 Target Width
+/** Offset 0x06B9 - Thermal Sensor 2 Target Width
Thermal Sensor 2 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS2TW;
-/** Offset 0x06B6 - Thermal Sensor 3 Target Width
+/** Offset 0x06BA - Thermal Sensor 3 Target Width
Thermal Sensor 3 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS3TW;
-/** Offset 0x06B7 - Port 0 T1 Multipler
+/** Offset 0x06BB - Port 0 T1 Multipler
Port 0 T1 Multipler.
**/
UINT8 SataP0T1M;
-/** Offset 0x06B8 - Port 0 T2 Multipler
+/** Offset 0x06BC - Port 0 T2 Multipler
Port 0 T2 Multipler.
**/
UINT8 SataP0T2M;
-/** Offset 0x06B9 - Port 0 T3 Multipler
+/** Offset 0x06BD - Port 0 T3 Multipler
Port 0 T3 Multipler.
**/
UINT8 SataP0T3M;
-/** Offset 0x06BA - Port 0 Tdispatch
+/** Offset 0x06BE - Port 0 Tdispatch
Port 0 Tdispatch.
**/
UINT8 SataP0TDisp;
-/** Offset 0x06BB - Port 1 T1 Multipler
+/** Offset 0x06BF - Port 1 T1 Multipler
Port 1 T1 Multipler.
**/
UINT8 SataP1T1M;
-/** Offset 0x06BC - Port 1 T2 Multipler
+/** Offset 0x06C0 - Port 1 T2 Multipler
Port 1 T2 Multipler.
**/
UINT8 SataP1T2M;
-/** Offset 0x06BD - Port 1 T3 Multipler
+/** Offset 0x06C1 - Port 1 T3 Multipler
Port 1 T3 Multipler.
**/
UINT8 SataP1T3M;
-/** Offset 0x06BE - Port 1 Tdispatch
+/** Offset 0x06C2 - Port 1 Tdispatch
Port 1 Tdispatch.
**/
UINT8 SataP1TDisp;
-/** Offset 0x06BF - Port 0 Tinactive
+/** Offset 0x06C3 - Port 0 Tinactive
Port 0 Tinactive.
**/
UINT8 SataP0Tinact;
-/** Offset 0x06C0 - Port 0 Alternate Fast Init Tdispatch
+/** Offset 0x06C4 - Port 0 Alternate Fast Init Tdispatch
Port 0 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP0TDispFinit;
-/** Offset 0x06C1 - Port 1 Tinactive
+/** Offset 0x06C5 - Port 1 Tinactive
Port 1 Tinactive.
**/
UINT8 SataP1Tinact;
-/** Offset 0x06C2 - Port 1 Alternate Fast Init Tdispatch
+/** Offset 0x06C6 - Port 1 Alternate Fast Init Tdispatch
Port 1 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP1TDispFinit;
-/** Offset 0x06C3 - Sata Thermal Throttling Suggested Setting
+/** Offset 0x06C7 - Sata Thermal Throttling Suggested Setting
Sata Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 SataThermalSuggestedSetting;
-/** Offset 0x06C4 - Enable Memory Thermal Throttling
+/** Offset 0x06C8 - Enable Memory Thermal Throttling
Enable Memory Thermal Throttling.
$EN_DIS
**/
UINT8 PchMemoryThrottlingEnable;
-/** Offset 0x06C5 - Memory Thermal Throttling
+/** Offset 0x06C9 - Memory Thermal Throttling
Enable Memory Thermal Throttling.
**/
UINT8 PchMemoryPmsyncEnable[2];
-/** Offset 0x06C7 - Enable Memory Thermal Throttling
+/** Offset 0x06CB - Enable Memory Thermal Throttling
Enable Memory Thermal Throttling.
**/
UINT8 PchMemoryC0TransmitEnable[2];
-/** Offset 0x06C9 - Enable Memory Thermal Throttling
+/** Offset 0x06CD - Enable Memory Thermal Throttling
Enable Memory Thermal Throttling.
**/
UINT8 PchMemoryPinSelection[2];
-/** Offset 0x06CB
+/** Offset 0x06CF
**/
- UINT8 UnusedUpdSpace17;
+ UINT8 UnusedUpdSpace18;
-/** Offset 0x06CC - Thermal Device Temperature
+/** Offset 0x06D0 - Thermal Device Temperature
Decides the temperature.
**/
UINT16 PchTemperatureHotLevel;
-/** Offset 0x06CE - Enable xHCI Compliance Mode
+/** Offset 0x06D2 - Enable xHCI Compliance Mode
Compliance Mode can be enabled for testing through this option but this is disabled
by default.
$EN_DIS
**/
UINT8 PchEnableComplianceMode;
-/** Offset 0x06CF - USB2 Port Over Current Pin
+/** Offset 0x06D3 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x06DF - USB3 Port Over Current Pin
+/** Offset 0x06E3 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x06E9 - Enable 8254 Static Clock Gating
+/** Offset 0x06ED - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2301,19 +2313,19 @@ typedef struct {
**/
UINT8 Enable8254ClockGating;
-/** Offset 0x06EA - PCH Sata Rst Optane Memory
+/** Offset 0x06EE - PCH Sata Rst Optane Memory
Optane Memory
$EN_DIS
**/
UINT8 SataRstOptaneMemory;
-/** Offset 0x06EB - PCH Sata Rst CPU Attached Storage
+/** Offset 0x06EF - PCH Sata Rst CPU Attached Storage
CPU Attached Storage
$EN_DIS
**/
UINT8 SataRstCpuAttachedStorage;
-/** Offset 0x06EC - Enable 8254 Static Clock Gating On S3
+/** Offset 0x06F0 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -2321,11 +2333,11 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x06ED
+/** Offset 0x06F1
**/
- UINT8 UnusedUpdSpace18[3];
+ UINT8 UnusedUpdSpace19[3];
-/** Offset 0x06F0 - Pch PCIE device override table pointer
+/** Offset 0x06F4 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This
is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
@@ -2333,7 +2345,7 @@ typedef struct {
**/
UINT32 PchPcieDeviceOverrideTablePtr;
-/** Offset 0x06F4 - Enable TCO timer.
+/** Offset 0x06F8 - Enable TCO timer.
When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
emulation must be enabled, and WDAT table must not be exposed to the OS.
@@ -2341,7 +2353,7 @@ typedef struct {
**/
UINT8 EnableTcoTimer;
-/** Offset 0x06F5 - Enable PS_ON.
+/** Offset 0x06F9 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -2349,155 +2361,177 @@ typedef struct {
**/
UINT8 PsOnEnable;
-/** Offset 0x06F6 - Pmc Cpu C10 Gate Pin Enable
+/** Offset 0x06FA - Pmc Cpu C10 Gate Pin Enable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
and VccSTG rails instead of SLP_S0# pin.
$EN_DIS
**/
UINT8 PmcCpuC10GatePinEnable;
-/** Offset 0x06F7 - Pch Dmi Aspm Ctrl
+/** Offset 0x06FB - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/
UINT8 PchDmiAspmCtrl;
-/** Offset 0x06F8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x06FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-/** Offset 0x0702 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x0706 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
= 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTran[10];
-/** Offset 0x070C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x0710 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-/** Offset 0x0716 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x071A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x0720 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x0724 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-/** Offset 0x072A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x072E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTran[10];
-/** Offset 0x0734 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x0738 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-/** Offset 0x073E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x0742 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTran[10];
-/** Offset 0x0748 - ReservedPchPostMem
+/** Offset 0x074C - Number of Coefficients to be used
+ The number of coefficients to be used for equalization, default value is 3
+**/
+ UINT8 PcieNumOfCoefficients;
+
+/** Offset 0x074D - GPIO RCOMP Community Clock Gating
+ 0 = Disable dynamic RCOMP clock local clock gating, 1 = Enable dynamic RCOMP clock
+ local clock gating, default value is 1
+ $EN_DIS
+**/
+ UINT8 GpioPmRcompCommunityLocalClockGating;
+
+/** Offset 0x074E - Enable SD Card Write Protect Pin
+ Enable/disable SD Card Write Protect Pin.
+ $EN_DIS
+**/
+ UINT8 ScsSdCardWpPinEnabled;
+
+/** Offset 0x074F - ReservedPchPostMem
Reserved for Pch Post-Mem
$EN_DIS
**/
UINT8 ReservedPchPostMem[16];
-/** Offset 0x0758 - BgpdtHash[4]
+/** Offset 0x075F
+**/
+ UINT8 UnusedUpdSpace20[1];
+
+/** Offset 0x0760 - BgpdtHash[4]
BgpdtHash values
**/
UINT64 BgpdtHash[4];
-/** Offset 0x0778 - BiosGuardAttr
+/** Offset 0x0780 - BiosGuardAttr
BiosGuardAttr default values
**/
UINT32 BiosGuardAttr;
-/** Offset 0x077C
+/** Offset 0x0784
**/
- UINT8 UnusedUpdSpace19[4];
+ UINT8 UnusedUpdSpace21[4];
-/** Offset 0x0780 - BiosGuardModulePtr
+/** Offset 0x0788 - BiosGuardModulePtr
BiosGuardModulePtr default values
**/
UINT64 BiosGuardModulePtr;
-/** Offset 0x0788 - SendEcCmd
+/** Offset 0x0790 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
-/** Offset 0x0790 - EcCmdProvisionEav
+/** Offset 0x0798 - EcCmdProvisionEav
Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
**/
UINT8 EcCmdProvisionEav;
-/** Offset 0x0791 - EcCmdLock
+/** Offset 0x0799 - EcCmdLock
EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
**/
UINT8 EcCmdLock;
-/** Offset 0x0792
+/** Offset 0x079A
**/
- UINT8 UnusedUpdSpace20[6];
+ UINT8 UnusedUpdSpace22[6];
-/** Offset 0x0798 - SgxEpoch0
+/** Offset 0x07A0 - SgxEpoch0
SgxEpoch0 default values
**/
UINT64 SgxEpoch0;
-/** Offset 0x07A0 - SgxEpoch1
+/** Offset 0x07A8 - SgxEpoch1
SgxEpoch1 default values
**/
UINT64 SgxEpoch1;
-/** Offset 0x07A8 - SgxSinitNvsData
+/** Offset 0x07B0 - SgxSinitNvsData
SgxSinitNvsData default values
**/
UINT8 SgxSinitNvsData;
-/** Offset 0x07A9 - Si Config CSM Flag.
+/** Offset 0x07B1 - Si Config CSM Flag.
Platform specific common policies that used by several silicon components. CSM status flag.
$EN_DIS
**/
UINT8 SiCsmFlag;
-/** Offset 0x07AA
+/** Offset 0x07B2
**/
- UINT8 UnusedUpdSpace21[2];
+ UINT8 UnusedUpdSpace23[2];
-/** Offset 0x07AC - SVID SDID table Poniter.
+/** Offset 0x07B4 - SVID SDID table Poniter.
The address of the table of SVID SDID to customize each SVID SDID entry.
**/
UINT32 SiSsidTablePtr;
-/** Offset 0x07B0 - Number of ssid table.
+/** Offset 0x07B8 - Number of ssid table.
SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
**/
UINT16 SiNumberOfSsidTableEntry;
-/** Offset 0x07B2 - SATA RST Interrupt Mode
+/** Offset 0x07BA - SATA RST Interrupt Mode
Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
0:Msix, 1:Msi, 2:Legacy
**/
UINT8 SataRstInterrupt;
-/** Offset 0x07B3 - ME Unconfig on RTC clear
+/** Offset 0x07BB - ME Unconfig on RTC clear
0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2: Cmos is clear, status unkonwn. 3: Reserved
0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -2505,11 +2539,11 @@ typedef struct {
**/
UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x07B4
+/** Offset 0x07BC
**/
- UINT8 UnusedUpdSpace22[3];
+ UINT8 UnusedUpdSpace24[3];
-/** Offset 0x07B7
+/** Offset 0x07BF
**/
UINT8 ReservedFspsUpd[1];
} FSP_S_CONFIG;
@@ -2518,74 +2552,74 @@ typedef struct {
**/
typedef struct {
-/** Offset 0x07B8
+/** Offset 0x07C0
**/
UINT32 Signature;
-/** Offset 0x07BC - Enable/Disable Device 7
+/** Offset 0x07C4 - Enable/Disable Device 7
Enable: Device 7 enabled, Disable (Default): Device 7 disabled
$EN_DIS
**/
UINT8 ChapDeviceEnable;
-/** Offset 0x07BD - Skip PAM register lock
+/** Offset 0x07C5 - Skip PAM register lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x07BE - EDRAM Test Mode
+/** Offset 0x07C6 - EDRAM Test Mode
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
**/
UINT8 EdramTestMode;
-/** Offset 0x07BF - DMI Extended Sync Control
+/** Offset 0x07C7 - DMI Extended Sync Control
Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
Sync Control
$EN_DIS
**/
UINT8 DmiExtSync;
-/** Offset 0x07C0 - DMI IOT Control
+/** Offset 0x07C8 - DMI IOT Control
Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
$EN_DIS
**/
UINT8 DmiIot;
-/** Offset 0x07C1 - PEG Max Payload size per root port
+/** Offset 0x07C9 - PEG Max Payload size per root port
0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
**/
UINT8 PegMaxPayload[4];
-/** Offset 0x07C5 - Enable/Disable IGFX RenderStandby
+/** Offset 0x07CD - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x07C6 - Enable/Disable IGFX PmSupport
+/** Offset 0x07CE - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
-/** Offset 0x07C7 - Enable/Disable CdynmaxClamp
+/** Offset 0x07CF - Enable/Disable CdynmaxClamp
Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
$EN_DIS
**/
UINT8 CdynmaxClampEnable;
-/** Offset 0x07C8 - Disable VT-d
+/** Offset 0x07D0 - Disable VT-d
0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
$EN_DIS
**/
UINT8 VtdDisableDeprecated;
-/** Offset 0x07C9 - GT Frequency Limit
+/** Offset 0x07D1 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -2599,19 +2633,19 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x07CA - Disable Turbo GT
+/** Offset 0x07D2 - Disable Turbo GT
0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
$EN_DIS
**/
UINT8 DisableTurboGt;
-/** Offset 0x07CB - SaPostMemTestRsvd
+/** Offset 0x07D3 - SaPostMemTestRsvd
Reserved for SA Post-Mem Test
$EN_DIS
**/
UINT8 SaPostMemTestRsvd[11];
-/** Offset 0x07D6 - 1-Core Ratio Limit
+/** Offset 0x07DE - 1-Core Ratio Limit
1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core
Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
@@ -2619,79 +2653,79 @@ typedef struct {
**/
UINT8 OneCoreRatioLimit;
-/** Offset 0x07D7 - 2-Core Ratio Limit
+/** Offset 0x07DF - 2-Core Ratio Limit
2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 TwoCoreRatioLimit;
-/** Offset 0x07D8 - 3-Core Ratio Limit
+/** Offset 0x07E0 - 3-Core Ratio Limit
3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 ThreeCoreRatioLimit;
-/** Offset 0x07D9 - 4-Core Ratio Limit
+/** Offset 0x07E1 - 4-Core Ratio Limit
4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 FourCoreRatioLimit;
-/** Offset 0x07DA - Enable or Disable HWP
+/** Offset 0x07E2 - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2-3:Reserved
$EN_DIS
**/
UINT8 Hwp;
-/** Offset 0x07DB - Hardware Duty Cycle Control
+/** Offset 0x07E3 - Hardware Duty Cycle Control
Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
$EN_DIS
**/
UINT8 HdcControl;
-/** Offset 0x07DC - Package Long duration turbo mode time
+/** Offset 0x07E4 - Package Long duration turbo mode time
Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds.
Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40
, 48 , 56 , 64 , 80 , 96 , 112 , 128
**/
UINT8 PowerLimit1Time;
-/** Offset 0x07DD - Short Duration Turbo Mode
+/** Offset 0x07E5 - Short Duration Turbo Mode
Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PowerLimit2;
-/** Offset 0x07DE - Turbo settings Lock
+/** Offset 0x07E6 - Turbo settings Lock
Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
$EN_DIS
**/
UINT8 TurboPowerLimitLock;
-/** Offset 0x07DF - Package PL3 time window
+/** Offset 0x07E7 - Package PL3 time window
Package PL3 time window range for this policy from 0 to 64ms
**/
UINT8 PowerLimit3Time;
-/** Offset 0x07E0 - Package PL3 Duty Cycle
+/** Offset 0x07E8 - Package PL3 Duty Cycle
Package PL3 Duty Cycle; Valid Range is 0 to 100
**/
UINT8 PowerLimit3DutyCycle;
-/** Offset 0x07E1 - Package PL3 Lock
+/** Offset 0x07E9 - Package PL3 Lock
Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
$EN_DIS
**/
UINT8 PowerLimit3Lock;
-/** Offset 0x07E2 - Package PL4 Lock
+/** Offset 0x07EA - Package PL4 Lock
Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
$EN_DIS
**/
UINT8 PowerLimit4Lock;
-/** Offset 0x07E3 - TCC Activation Offset
+/** Offset 0x07EB - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
@@ -2699,7 +2733,7 @@ typedef struct {
**/
UINT8 TccActivationOffset;
-/** Offset 0x07E4 - Tcc Offset Clamp Enable/Disable
+/** Offset 0x07EC - Tcc Offset Clamp Enable/Disable
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
For all other SKUs the recommended default are <b>0: Disabled</b>.
@@ -2707,345 +2741,345 @@ typedef struct {
**/
UINT8 TccOffsetClamp;
-/** Offset 0x07E5 - Tcc Offset Lock
+/** Offset 0x07ED - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
-/** Offset 0x07E6 - Custom Ratio State Entries
+/** Offset 0x07EE - Custom Ratio State Entries
The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
ratio table.Sets the number of custom P-states. At least 2 states must be present
**/
UINT8 NumberOfEntries;
-/** Offset 0x07E7 - Custom Short term Power Limit time window
+/** Offset 0x07EF - Custom Short term Power Limit time window
Short term Power Limit time window value for custom CTDP level 1. Valid Range 0
to 128, 0 = AUTO
**/
UINT8 Custom1PowerLimit1Time;
-/** Offset 0x07E8 - Custom Turbo Activation Ratio
+/** Offset 0x07F0 - Custom Turbo Activation Ratio
Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
**/
UINT8 Custom1TurboActivationRatio;
-/** Offset 0x07E9 - Custom Config Tdp Control
+/** Offset 0x07F1 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom1ConfigTdpControl;
-/** Offset 0x07EA - Custom Short term Power Limit time window
+/** Offset 0x07F2 - Custom Short term Power Limit time window
Short term Power Limit time window value for custom CTDP level 2. Valid Range 0
to 128, 0 = AUTO
**/
UINT8 Custom2PowerLimit1Time;
-/** Offset 0x07EB - Custom Turbo Activation Ratio
+/** Offset 0x07F3 - Custom Turbo Activation Ratio
Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
**/
UINT8 Custom2TurboActivationRatio;
-/** Offset 0x07EC - Custom Config Tdp Control
+/** Offset 0x07F4 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom2ConfigTdpControl;
-/** Offset 0x07ED - Custom Short term Power Limit time window
+/** Offset 0x07F5 - Custom Short term Power Limit time window
Short term Power Limit time window value for custom CTDP level 3. Valid Range 0
to 128, 0 = AUTO
**/
UINT8 Custom3PowerLimit1Time;
-/** Offset 0x07EE - Custom Turbo Activation Ratio
+/** Offset 0x07F6 - Custom Turbo Activation Ratio
Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
**/
UINT8 Custom3TurboActivationRatio;
-/** Offset 0x07EF - Custom Config Tdp Control
+/** Offset 0x07F7 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom3ConfigTdpControl;
-/** Offset 0x07F0 - ConfigTdp mode settings Lock
+/** Offset 0x07F8 - ConfigTdp mode settings Lock
Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 ConfigTdpLock;
-/** Offset 0x07F1 - Load Configurable TDP SSDT
+/** Offset 0x07F9 - Load Configurable TDP SSDT
Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ConfigTdpBios;
-/** Offset 0x07F2 - PL1 Enable value
+/** Offset 0x07FA - PL1 Enable value
PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 PsysPowerLimit1;
-/** Offset 0x07F3 - PL1 timewindow
+/** Offset 0x07FB - PL1 timewindow
PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds)
1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
**/
UINT8 PsysPowerLimit1Time;
-/** Offset 0x07F4 - PL2 Enable Value
+/** Offset 0x07FC - PL2 Enable Value
PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
1: Enable.
$EN_DIS
**/
UINT8 PsysPowerLimit2;
-/** Offset 0x07F5 - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x07FD - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MlcStreamerPrefetcher;
-/** Offset 0x07F6 - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x07FE - Enable or Disable MLC Spatial Prefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 MlcSpatialPrefetcher;
-/** Offset 0x07F7 - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x07FF - Enable or Disable Monitor /MWAIT instructions
Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MonitorMwaitEnable;
-/** Offset 0x07F8 - Enable or Disable initialization of machine check registers
+/** Offset 0x0800 - Enable or Disable initialization of machine check registers
Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MachineCheckEnable;
-/** Offset 0x07F9 - Deprecated DO NOT USE Enable or Disable processor debug features
+/** Offset 0x0801 - Deprecated DO NOT USE Enable or Disable processor debug features
@deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DebugInterfaceEnable;
-/** Offset 0x07FA - Lock or Unlock debug interface features
+/** Offset 0x0802 - Lock or Unlock debug interface features
Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DebugInterfaceLockEnable;
-/** Offset 0x07FB - AP Idle Manner of waiting for SIPI
+/** Offset 0x0803 - AP Idle Manner of waiting for SIPI
AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
1: HALT loop, 2: MWAIT loop, 3: RUN loop
**/
UINT8 ApIdleManner;
-/** Offset 0x07FC - Control on Processor Trace output scheme
+/** Offset 0x0804 - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
0: Single Range Output, 1: ToPA Output
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x07FD - Enable or Disable Processor Trace feature
+/** Offset 0x0805 - Enable or Disable Processor Trace feature
Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcessorTraceEnable;
-/** Offset 0x07FE
+/** Offset 0x0806
**/
- UINT8 UnusedUpdSpace23[2];
+ UINT8 UnusedUpdSpace25[2];
-/** Offset 0x0800 - Base of memory region allocated for Processor Trace
+/** Offset 0x0808 - Base of memory region allocated for Processor Trace
Base address of memory region allocated for Processor Trace. Processor Trace requires
2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
**/
UINT64 ProcessorTraceMemBase;
-/** Offset 0x0808 - Memory region allocation for Processor Trace
+/** Offset 0x0810 - Memory region allocation for Processor Trace
Length in bytes of memory region allocated for Processor Trace. Processor Trace
requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
**/
UINT32 ProcessorTraceMemLength;
-/** Offset 0x080C - Enable or Disable Voltage Optimization feature
+/** Offset 0x0814 - Enable or Disable Voltage Optimization feature
Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 VoltageOptimization;
-/** Offset 0x080D - Enable or Disable Intel SpeedStep Technology
+/** Offset 0x0815 - Enable or Disable Intel SpeedStep Technology
Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Eist;
-/** Offset 0x080E - Enable or Disable Energy Efficient P-state
+/** Offset 0x0816 - Enable or Disable Energy Efficient P-state
Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
<b>1: Enable</b>
$EN_DIS
**/
UINT8 EnergyEfficientPState;
-/** Offset 0x080F - Enable or Disable Energy Efficient Turbo
+/** Offset 0x0817 - Enable or Disable Energy Efficient Turbo
Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
<b>1: Enable</b>
$EN_DIS
**/
UINT8 EnergyEfficientTurbo;
-/** Offset 0x0810 - Enable or Disable T states
+/** Offset 0x0818 - Enable or Disable T states
Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TStates;
-/** Offset 0x0811 - Enable or Disable Bi-Directional PROCHOT#
+/** Offset 0x0819 - Enable or Disable Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 BiProcHot;
-/** Offset 0x0812 - Enable or Disable PROCHOT# signal being driven externally
+/** Offset 0x081A - Enable or Disable PROCHOT# signal being driven externally
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DisableProcHotOut;
-/** Offset 0x0813 - Enable or Disable PROCHOT# Response
+/** Offset 0x081B - Enable or Disable PROCHOT# Response
Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcHotResponse;
-/** Offset 0x0814 - Enable or Disable VR Thermal Alert
+/** Offset 0x081C - Enable or Disable VR Thermal Alert
Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DisableVrThermalAlert;
-/** Offset 0x0815 - Enable or Disable Thermal Reporting
+/** Offset 0x081D - Enable or Disable Thermal Reporting
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 AutoThermalReporting;
-/** Offset 0x0816 - Enable or Disable Thermal Monitor
+/** Offset 0x081E - Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThermalMonitor;
-/** Offset 0x0817 - Enable or Disable CPU power states (C-states)
+/** Offset 0x081F - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x0818 - Configure C-State Configuration Lock
+/** Offset 0x0820 - Configure C-State Configuration Lock
Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 PmgCstCfgCtrlLock;
-/** Offset 0x0819 - Enable or Disable Enhanced C-states
+/** Offset 0x0821 - Enable or Disable Enhanced C-states
Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1e;
-/** Offset 0x081A - Enable or Disable Package Cstate Demotion
+/** Offset 0x0822 - Enable or Disable Package Cstate Demotion
Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 PkgCStateDemotion;
-/** Offset 0x081B - Enable or Disable Package Cstate UnDemotion
+/** Offset 0x0823 - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 PkgCStateUnDemotion;
-/** Offset 0x081C - Enable or Disable CState-Pre wake
+/** Offset 0x0824 - Enable or Disable CState-Pre wake
Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
-/** Offset 0x081D - Enable or Disable TimedMwait Support.
+/** Offset 0x0825 - Enable or Disable TimedMwait Support.
Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
-/** Offset 0x081E - Enable or Disable IO to MWAIT redirection
+/** Offset 0x0826 - Enable or Disable IO to MWAIT redirection
Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CstCfgCtrIoMwaitRedirection;
-/** Offset 0x081F - Set the Max Pkg Cstate
+/** Offset 0x0827 - Set the Max Pkg Cstate
Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
**/
UINT8 PkgCStateLimit;
-/** Offset 0x0820 - TimeUnit for C-State Latency Control0
+/** Offset 0x0828 - TimeUnit for C-State Latency Control0
TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl0TimeUnit;
-/** Offset 0x0821 - TimeUnit for C-State Latency Control1
+/** Offset 0x0829 - TimeUnit for C-State Latency Control1
TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl1TimeUnit;
-/** Offset 0x0822 - TimeUnit for C-State Latency Control2
+/** Offset 0x082A - TimeUnit for C-State Latency Control2
TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl2TimeUnit;
-/** Offset 0x0823 - TimeUnit for C-State Latency Control3
+/** Offset 0x082B - TimeUnit for C-State Latency Control3
TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl3TimeUnit;
-/** Offset 0x0824 - TimeUnit for C-State Latency Control4
+/** Offset 0x082C - TimeUnit for C-State Latency Control4
Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl4TimeUnit;
-/** Offset 0x0825 - TimeUnit for C-State Latency Control5
+/** Offset 0x082D - TimeUnit for C-State Latency Control5
TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl5TimeUnit;
-/** Offset 0x0826 - Interrupt Redirection Mode Select
+/** Offset 0x082E - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
**/
UINT8 PpmIrmSetting;
-/** Offset 0x0827 - Lock prochot configuration
+/** Offset 0x082F - Lock prochot configuration
Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 ProcHotLock;
-/** Offset 0x0828 - Configuration for boot TDP selection
+/** Offset 0x0830 - Configuration for boot TDP selection
Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
Up;0xFF : Deactivate
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x0829 - Race To Halt
+/** Offset 0x0831 - Race To Halt
Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
through MSR 1FC bit 20)Disable; <b>1: Enable</b>
@@ -3053,19 +3087,19 @@ typedef struct {
**/
UINT8 RaceToHalt;
-/** Offset 0x082A - Max P-State Ratio
+/** Offset 0x0832 - Max P-State Ratio
Max P-State Ratio, Valid Range 0 to 0x7F
**/
UINT8 MaxRatio;
-/** Offset 0x082B - P-state ratios for custom P-state table
+/** Offset 0x0833 - P-state ratios for custom P-state table
P-state ratios for custom P-state table. NumberOfEntries has valid range between
0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
are configurable. Valid Range of each entry is 0 to 0x7F
**/
UINT8 StateRatio[40];
-/** Offset 0x0853 - P-state ratios for max 16 version of custom P-state table
+/** Offset 0x085B - P-state ratios for max 16 version of custom P-state table
P-state ratios for max 16 version of custom P-state table. This table is used for
OS versions limited to a max of 16 P-States. If the first entry of this table is
0, or if Number of Entries is 16 or less, then this table will be ignored, and
@@ -3074,391 +3108,391 @@ typedef struct {
**/
UINT8 StateRatioMax16[16];
-/** Offset 0x0863
+/** Offset 0x086B
**/
- UINT8 UnusedUpdSpace24;
+ UINT8 UnusedUpdSpace26;
-/** Offset 0x0864 - Platform Power Pmax
+/** Offset 0x086C - Platform Power Pmax
PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
Range 0-1024 Watts. Value of 800 = 100W
**/
UINT16 PsysPmax;
-/** Offset 0x0866 - Interrupt Response Time Limit of C-State LatencyContol0
+/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol0
Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
**/
UINT16 CstateLatencyControl0Irtl;
-/** Offset 0x0868 - Interrupt Response Time Limit of C-State LatencyContol1
+/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol1
Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
**/
UINT16 CstateLatencyControl1Irtl;
-/** Offset 0x086A - Interrupt Response Time Limit of C-State LatencyContol2
+/** Offset 0x0872 - Interrupt Response Time Limit of C-State LatencyContol2
Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
**/
UINT16 CstateLatencyControl2Irtl;
-/** Offset 0x086C - Interrupt Response Time Limit of C-State LatencyContol3
+/** Offset 0x0874 - Interrupt Response Time Limit of C-State LatencyContol3
Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
**/
UINT16 CstateLatencyControl3Irtl;
-/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol4
+/** Offset 0x0876 - Interrupt Response Time Limit of C-State LatencyContol4
Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
**/
UINT16 CstateLatencyControl4Irtl;
-/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol5
+/** Offset 0x0878 - Interrupt Response Time Limit of C-State LatencyContol5
Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
**/
UINT16 CstateLatencyControl5Irtl;
-/** Offset 0x0872
+/** Offset 0x087A
**/
- UINT8 UnusedUpdSpace25[2];
+ UINT8 UnusedUpdSpace27[2];
-/** Offset 0x0874 - Package Long duration turbo mode power limit
+/** Offset 0x087C - Package Long duration turbo mode power limit
Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Valid Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit1;
-/** Offset 0x0878 - Package Short duration turbo mode power limit
+/** Offset 0x0880 - Package Short duration turbo mode power limit
Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit2Power;
-/** Offset 0x087C - Package PL3 power limit
+/** Offset 0x0884 - Package PL3 power limit
Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit3;
-/** Offset 0x0880 - Package PL4 power limit
+/** Offset 0x0888 - Package PL4 power limit
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 1023875 in Step size of 125
**/
UINT32 PowerLimit4;
-/** Offset 0x0884 - Tcc Offset Time Window for RATL
+/** Offset 0x088C - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 1023875 in Step size of 125
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 1
Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x088C - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 1
Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 2
Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x089C - Long term Power Limit value for custom cTDP level 2
Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x08A0 - Short term Power Limit value for custom cTDP level 3
Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x089C - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x08A4 - Long term Power Limit value for custom cTDP level 3
Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x08A0 - Platform PL1 power
+/** Offset 0x08A8 - Platform PL1 power
Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
0 to 4095875 in Step size of 125
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x08A4 - Platform PL2 power
+/** Offset 0x08AC - Platform PL2 power
Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
0 to 4095875 in Step size of 125
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x08A8 - Set Three Strike Counter Disable
+/** Offset 0x08B0 - Set Three Strike Counter Disable
False (default): Three Strike counter will be incremented and True: Prevents Three
Strike counter from incrementing; <b>0: False</b>; 1: True.
0: False, 1: True
**/
UINT8 ThreeStrikeCounterDisable;
-/** Offset 0x08A9 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+/** Offset 0x08B1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
-/** Offset 0x08AA - 5-Core Ratio Limit
+/** Offset 0x08B2 - 5-Core Ratio Limit
5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
0x0:0xFF
**/
UINT8 FiveCoreRatioLimit;
-/** Offset 0x08AB - 6-Core Ratio Limit
+/** Offset 0x08B3 - 6-Core Ratio Limit
6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
0x0:0xFF
**/
UINT8 SixCoreRatioLimit;
-/** Offset 0x08AC - 7-Core Ratio Limit
+/** Offset 0x08B4 - 7-Core Ratio Limit
7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
0x0:0xFF
**/
UINT8 SevenCoreRatioLimit;
-/** Offset 0x08AD - 8-Core Ratio Limit
+/** Offset 0x08B5 - 8-Core Ratio Limit
8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core
Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
0x0:0xFF
**/
UINT8 EightCoreRatioLimit;
-/** Offset 0x08AE - Intel Turbo Boost Max Technology 3.0
+/** Offset 0x08B6 - Intel Turbo Boost Max Technology 3.0
Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
$EN_DIS
**/
UINT8 EnableItbm;
-/** Offset 0x08AF - Intel Turbo Boost Max Technology 3.0 Driver
+/** Offset 0x08B7 - Intel Turbo Boost Max Technology 3.0 Driver
Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
$EN_DIS
**/
UINT8 EnableItbmDriver;
-/** Offset 0x08B0 - Enable or Disable C1 Cstate Demotion
+/** Offset 0x08B8 - Enable or Disable C1 Cstate Demotion
Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateAutoDemotion;
-/** Offset 0x08B1 - Enable or Disable C1 Cstate UnDemotion
+/** Offset 0x08B9 - Enable or Disable C1 Cstate UnDemotion
Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateUnDemotion;
-/** Offset 0x08B2 - CpuWakeUpTimer
+/** Offset 0x08BA - CpuWakeUpTimer
Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
to 180 seconds. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CpuWakeUpTimer;
-/** Offset 0x08B3 - Minimum Ring ratio limit override
+/** Offset 0x08BB - Minimum Ring ratio limit override
Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MinRingRatioLimit;
-/** Offset 0x08B4 - Minimum Ring ratio limit override
+/** Offset 0x08BC - Minimum Ring ratio limit override
Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x08B5 - Enable or Disable C3 Cstate Demotion
+/** Offset 0x08BD - Enable or Disable C3 Cstate Demotion
Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C3StateAutoDemotion;
-/** Offset 0x08B6 - Enable or Disable C3 Cstate UnDemotion
+/** Offset 0x08BE - Enable or Disable C3 Cstate UnDemotion
Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C3StateUnDemotion;
-/** Offset 0x08B7 - ReservedCpuPostMemTest
+/** Offset 0x08BF - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
UINT8 ReservedCpuPostMemTest[19];
-/** Offset 0x08CA - SgxSinitDataFromTpm
+/** Offset 0x08D2 - SgxSinitDataFromTpm
SgxSinitDataFromTpm default values
**/
UINT8 SgxSinitDataFromTpm;
-/** Offset 0x08CB - End of Post message
+/** Offset 0x08D3 - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
-/** Offset 0x08CC - D0I3 Setting for HECI Disable
+/** Offset 0x08D4 - D0I3 Setting for HECI Disable
Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
HECI devices
$EN_DIS
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x08CD
+/** Offset 0x08D5
**/
- UINT8 UnusedUpdSpace26;
+ UINT8 UnusedUpdSpace28;
-/** Offset 0x08CE - HD Audio Reset Wait Timer
+/** Offset 0x08D6 - HD Audio Reset Wait Timer
The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
**/
UINT16 PchHdaResetWaitTimer;
-/** Offset 0x08D0 - Enable LOCKDOWN SMI
+/** Offset 0x08D8 - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x08D1 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x08D9 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x08D2 - Unlock all GPIO pads
+/** Offset 0x08DA - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x08D3 - PCH Unlock SideBand access
+/** Offset 0x08DB - PCH Unlock SideBand access
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
$EN_DIS
**/
UINT8 PchSbAccessUnlock;
-/** Offset 0x08D4 - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x08DC - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[24];
-/** Offset 0x0904 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x090C - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[24];
-/** Offset 0x0934 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x093C - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 PcieRpSnoopLatencyOverrideMode[24];
-/** Offset 0x094C - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x0954 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
-/** Offset 0x0964 - PCIE RP Snoop Latency Override Value
+/** Offset 0x096C - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 PcieRpSnoopLatencyOverrideValue[24];
-/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x099C - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
-/** Offset 0x09AC - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
-/** Offset 0x09C4 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x09CC - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
-/** Offset 0x09F4 - PCIE RP Slot Power Limit Scale
+/** Offset 0x09FC - PCIE RP Slot Power Limit Scale
Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
UINT8 PcieRpSlotPowerLimitScale[24];
-/** Offset 0x0A0C - PCIE RP Slot Power Limit Value
+/** Offset 0x0A14 - PCIE RP Slot Power Limit Value
Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
UINT16 PcieRpSlotPowerLimitValue[24];
-/** Offset 0x0A3C - PCIE RP Upstream Port Transmiter Preset
+/** Offset 0x0A44 - PCIE RP Upstream Port Transmiter Preset
Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
**/
UINT8 PcieRpUptp[24];
-/** Offset 0x0A54 - PCIE RP Downstream Port Transmiter Preset
+/** Offset 0x0A5C - PCIE RP Downstream Port Transmiter Preset
Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
**/
UINT8 PcieRpDptp[24];
-/** Offset 0x0A6C - PCIE RP Enable Port8xh Decode
+/** Offset 0x0A74 - PCIE RP Enable Port8xh Decode
This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
1: Enable.
$EN_DIS
**/
UINT8 PcieEnablePort8xhDecode;
-/** Offset 0x0A6D - PCIE Port8xh Decode Port Index
+/** Offset 0x0A75 - PCIE Port8xh Decode Port Index
The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
**/
UINT8 PchPciePort8xhDecodePortIndex;
-/** Offset 0x0A6E - PCH Energy Reporting
+/** Offset 0x0A76 - PCH Energy Reporting
Disable/Enable PCH to CPU energy report feature.
$EN_DIS
**/
UINT8 PchPmDisableEnergyReport;
-/** Offset 0x0A6F - PCH Sata Test Mode
+/** Offset 0x0A77 - PCH Sata Test Mode
Allow entrance to the PCH SATA test modes.
$EN_DIS
**/
UINT8 SataTestMode;
-/** Offset 0x0A70 - PCH USB OverCurrent mapping lock enable
+/** Offset 0x0A78 - PCH USB OverCurrent mapping lock enable
If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
$EN_DIS
**/
UINT8 PchXhciOcLock;
-/** Offset 0x0A71 - ReservedPchPostMemTest
+/** Offset 0x0A79 - ReservedPchPostMemTest
Reserved for Pch Post-Mem Test
$EN_DIS
**/
UINT8 ReservedPchPostMemTest[16];
-/** Offset 0x0A81 - Mctp Broadcast Cycle
+/** Offset 0x0A89 - Mctp Broadcast Cycle
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x0A82
+/** Offset 0x0A8A
**/
- UINT8 UnusedUpdSpace27[2];
+ UINT8 UnusedUpdSpace29[2];
-/** Offset 0x0A84
+/** Offset 0x0A8C
**/
UINT8 ReservedFspsTestUpd[12];
} FSP_S_TEST_CONFIG;
@@ -3475,15 +3509,15 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x07B8
+/** Offset 0x07C0
**/
FSP_S_TEST_CONFIG FspsTestConfig;
-/** Offset 0x0A90
+/** Offset 0x0A98
**/
- UINT8 UnusedUpdSpace28[6];
+ UINT8 UnusedUpdSpace30[6];
-/** Offset 0x0A96
+/** Offset 0x0A9E
**/
UINT16 UpdTerminator;
} FSPS_UPD;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 12:29:04 +0000