Remove whitespace.

Fix issues reported by new lint test.

Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

53 files changed, 247 insertions, 247 deletions

diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index c53ee57409..87e09d6822 100755
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -61,9 +61,9 @@ config XIP_ROM_SIZE
 	hex
 	default 0x80000
 	depends on CPU_AMD_AGESA_FAMILY12
-	
+
 config HAVE_INIT_TIMER
 	bool
 	default y
-	depends on CPU_AMD_AGESA_FAMILY12 
-		
+	depends on CPU_AMD_AGESA_FAMILY12
+
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
index 5aa41276e1..4c7b2fde55 100755
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -2,7 +2,7 @@
 #
 # Copyright (c) 2011, Advanced Micro Devices, Inc.
 # All rights reserved.
-# 
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are met:
 #     * Redistributions of source code must retain the above copyright
@@ -10,10 +10,10 @@
 #     * Redistributions in binary form must reproduce the above copyright
 #       notice, this list of conditions and the following disclaimer in the
 #       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
-#       its contributors may be used to endorse or promote products derived 
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+#       its contributors may be used to endorse or promote products derived
 #       from this software without specific prior written permission.
-# 
+#
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -24,9 +24,9 @@
 # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-# 
+#
 #*****************************************************************************
- 
+
 ramstage-y += chip_name.c
 driver-y += model_12_init.c
 
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 955aec9514..4625da1ca0 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -146,7 +146,7 @@ CAR_FAM10_out:
    #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
 	orl	$(1 << 2), %eax
    #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
-	orl	$(2 << 2), %eax	
+	orl	$(2 << 2), %eax
    #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
 	orl	$(3 << 2), %eax
    #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index aad23690fd..90e6d2b88f 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -182,7 +182,7 @@ clear_fixed_var_mtrr_out:
 	movl	%eax, %esp
 
 #ifdef CARTEST
-testok:	
+testok:
 	post_code(0x40)
 	xorl	%edx, %edx
 	xorl	%eax, %eax
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 740ea47bc7..f74e1b8737 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -6,8 +6,8 @@
 	.code32
 
 
-	/* This is the GDT for the ROM stage part of coreboot. It 
-	 * is different from the RAM stage GDT which is defined in 
+	/* This is the GDT for the ROM stage part of coreboot. It
+	 * is different from the RAM stage GDT which is defined in
 	 * c_start.S
 	 */
 
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index fe8ed705d6..261b90f2b2 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -75,7 +75,7 @@ unsigned char uart8250_rx_byte(unsigned base_port)
 {
 	unsigned long int i = SINGLE_CHAR_TIMEOUT;
 	while (i-- && !uart8250_can_rx_byte(base_port));
-	
+
 	if (i)
 		return inb(base_port + UART_RBR);
 	else
diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout
index 8315401c7b..3b98cbb6a1 100644
--- a/src/mainboard/amd/inagua/cmos.layout
+++ b/src/mainboard/amd/inagua/cmos.layout
@@ -1,18 +1,18 @@
 #*****************************************************************************
-# 
+#
 #  This file is part of the coreboot project.
-# 
+#
 #  Copyright (C) 2011 Advanced Micro Devices, Inc.
-# 
+#
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
 #  the Free Software Foundation; version 2 of the License.
-# 
+#
 #  This program is distributed in the hope that it will be useful,
 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 #  GNU General Public License for more details.
-# 
+#
 #  You should have received a copy of the GNU General Public License
 #  along with this program; if not, write to the Free Software
 #  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index 3fb0e875db..3cfd741755 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       return CalloutStatus;
     }
   }
- 
+
   return CalloutStatus;
 }
 
@@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     } else {
       /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the 
+         Update NextNodeOffset and BufferSize to include the
          size of BIOS_BUFFER_NODE
       */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
@@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-   
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
@@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h
index 750b59dd3d..f9201ce67e 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.h
+++ b/src/mainboard/amd/south_station/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c
index 8749e3d19e..07aee7d484 100644
--- a/src/mainboard/amd/south_station/PlatformGnbPcie.c
+++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }       
+        }
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
@@ -116,8 +116,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
@@ -125,10 +125,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE); 
+    ASSERT(FALSE);
     return;
   }
-  
+
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
@@ -136,7 +136,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- 
+
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
@@ -146,7 +146,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
-     
+
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
@@ -160,7 +160,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100644
--- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 63f12f0f4a..f87522c944 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 /**
  * @file
  *
@@ -55,13 +55,13 @@
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 
-/* 
- * Agesa optional capabilities selection.  
+/*
+ * Agesa optional capabilities selection.
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
@@ -102,7 +102,7 @@
 #define BLDOPT_REMOVE_HT_ASSIST         TRUE
 #define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
@@ -219,10 +219,10 @@
 #define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 
-/* 
- * Agesa configuration values selection.  
+/*
+ * Agesa configuration values selection.
  * Uncomment and specify the value for the configuration options
- * needed by the system. 
+ * needed by the system.
  */
 #include "AGESA.h"
 #include "CommonReturns.h"
diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout
index 8315401c7b..3b98cbb6a1 100644
--- a/src/mainboard/amd/south_station/cmos.layout
+++ b/src/mainboard/amd/south_station/cmos.layout
@@ -1,18 +1,18 @@
 #*****************************************************************************
-# 
+#
 #  This file is part of the coreboot project.
-# 
+#
 #  Copyright (C) 2011 Advanced Micro Devices, Inc.
-# 
+#
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
 #  the Free Software Foundation; version 2 of the License.
-# 
+#
 #  This program is distributed in the hope that it will be useful,
 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 #  GNU General Public License for more details.
-# 
+#
 #  You should have received a copy of the GNU General Public License
 #  along with this program; if not, write to the Free Software
 #  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/mainboard/amd/south_station/dimmSpd.c b/src/mainboard/amd/south_station/dimmSpd.c
index 9da0e0e3a8..2bd27d6f42 100644
--- a/src/mainboard/amd/south_station/dimmSpd.c
+++ b/src/mainboard/amd/south_station/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
-   
+
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
-   
+
    return 0;
    }
 
@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
index 4bc5b48218..2d28023574 100644
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ b/src/mainboard/amd/south_station/get_bus_conf.c
@@ -69,22 +69,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
-	
+
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 5c8ae5ac43..5242f69bf1 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   u32 dword;
   u8 byte;
-    
+
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
@@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v)
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/amd/torpedo/cmos.layout b/src/mainboard/amd/torpedo/cmos.layout
index 8315401c7b..3b98cbb6a1 100755
--- a/src/mainboard/amd/torpedo/cmos.layout
+++ b/src/mainboard/amd/torpedo/cmos.layout
@@ -1,18 +1,18 @@
 #*****************************************************************************
-# 
+#
 #  This file is part of the coreboot project.
-# 
+#
 #  Copyright (C) 2011 Advanced Micro Devices, Inc.
-# 
+#
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
 #  the Free Software Foundation; version 2 of the License.
-# 
+#
 #  This program is distributed in the hope that it will be useful,
 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 #  GNU General Public License for more details.
-# 
+#
 #  You should have received a copy of the GNU General Public License
 #  along with this program; if not, write to the Free Software
 #  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl
index 2355e46827..bc812e4158 100755
--- a/src/mainboard/amd/torpedo/dsdt.asl
+++ b/src/mainboard/amd/torpedo/dsdt.asl
@@ -1066,7 +1066,7 @@ DefinitionBlock (
 						}
 					}
 				}
-			
+
 				Device (PS2K) {
 					Name (_HID, EisaId ("PNP0303"))
 					Name (_CRS, ResourceTemplate () {
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index 3fb0e875db..3cfd741755 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       return CalloutStatus;
     }
   }
- 
+
   return CalloutStatus;
 }
 
@@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     } else {
       /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the 
+         Update NextNodeOffset and BufferSize to include the
          size of BIOS_BUFFER_NODE
       */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
@@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-   
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
@@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h
index 750b59dd3d..f9201ce67e 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.h
+++ b/src/mainboard/amd/union_station/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c
index 59d31efb77..b0389b82d9 100644
--- a/src/mainboard/amd/union_station/PlatformGnbPcie.c
+++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }       
+        }
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
@@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
@@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE); 
+    ASSERT(FALSE);
     return;
   }
-  
+
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
@@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- 
+
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
@@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
-     
+
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
@@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100644
--- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 48e18a6ba0..20d667d6e7 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 /**
  * @file
  *
@@ -55,13 +55,13 @@
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 
-/* 
- * Agesa optional capabilities selection.  
+/*
+ * Agesa optional capabilities selection.
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
@@ -102,7 +102,7 @@
 #define BLDOPT_REMOVE_HT_ASSIST         TRUE
 #define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
@@ -219,10 +219,10 @@
 #define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 
-/* 
- * Agesa configuration values selection.  
+/*
+ * Agesa configuration values selection.
  * Uncomment and specify the value for the configuration options
- * needed by the system. 
+ * needed by the system.
  */
 #include "AGESA.h"
 #include "CommonReturns.h"
diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout
index 8315401c7b..3b98cbb6a1 100644
--- a/src/mainboard/amd/union_station/cmos.layout
+++ b/src/mainboard/amd/union_station/cmos.layout
@@ -1,18 +1,18 @@
 #*****************************************************************************
-# 
+#
 #  This file is part of the coreboot project.
-# 
+#
 #  Copyright (C) 2011 Advanced Micro Devices, Inc.
-# 
+#
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
 #  the Free Software Foundation; version 2 of the License.
-# 
+#
 #  This program is distributed in the hope that it will be useful,
 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 #  GNU General Public License for more details.
-# 
+#
 #  You should have received a copy of the GNU General Public License
 #  along with this program; if not, write to the Free Software
 #  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/mainboard/amd/union_station/dimmSpd.c b/src/mainboard/amd/union_station/dimmSpd.c
index 9da0e0e3a8..2bd27d6f42 100644
--- a/src/mainboard/amd/union_station/dimmSpd.c
+++ b/src/mainboard/amd/union_station/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
-   
+
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
-   
+
    return 0;
    }
 
@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
index 4bc5b48218..2d28023574 100644
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ b/src/mainboard/amd/union_station/get_bus_conf.c
@@ -69,22 +69,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
-	
+
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 5c8ae5ac43..5242f69bf1 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   u32 dword;
   u8 byte;
-    
+
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
@@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v)
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/asrock/939a785gmh/acpi/routing.asl b/src/mainboard/asrock/939a785gmh/acpi/routing.asl
index fa3760e045..fd02eac46b 100644
--- a/src/mainboard/asrock/939a785gmh/acpi/routing.asl
+++ b/src/mainboard/asrock/939a785gmh/acpi/routing.asl
@@ -32,12 +32,12 @@ Scope(\_SB) {
 		/* Bus 0, Dev 0 - RS780 Host Controller */
 		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
 		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		
+
 		Package(){0x0002FFFF, 0, INTC, 0 },
 		Package(){0x0002FFFF, 1, INTD, 0 },
 		Package(){0x0002FFFF, 2, INTA, 0 },
 		Package(){0x0002FFFF, 3, INTB, 0 },
-		
+
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices */
@@ -83,7 +83,7 @@ Scope(\_SB) {
 		Package(){0x0009FFFF, 1, 0, 18 },
 		Package(){0x0009FFFF, 2, 0, 19 },
 		Package(){0x0009FFFF, 3, 0, 10 },
-		
+
 		/* Bus 0, Dev A - PCIe internal ethernet */
 		Package(){0x000AFFFF, 0, 0, 18 },
 		Package(){0x000AFFFF, 1, 0, 19 },
@@ -146,7 +146,7 @@ Scope(\_SB) {
 		Package(){0x0000FFFF, 2, 0, 16 },
 		Package(){0x0000FFFF, 3, 0, 17 },
 	})
-	
+
 	Name(PS9, Package(){
 		/* PCIe slot - Hooked to PCIe x1 */
 		Package(){0x0000FFFF, 0, INTD, 0 },
diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig
index 1e4fff95cf..e6acd427a7 100644
--- a/src/mainboard/asrock/Kconfig
+++ b/src/mainboard/asrock/Kconfig
@@ -28,7 +28,7 @@ config BOARD_ASROCK_E350M1
 
 endchoice
 
-source "src/mainboard/asrock/939a785gmh/Kconfig"

+source "src/mainboard/asrock/939a785gmh/Kconfig"
 source "src/mainboard/asrock/e350m1/Kconfig"
 
 config MAINBOARD_VENDOR
diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout
index 8315401c7b..3b98cbb6a1 100644
--- a/src/mainboard/asrock/e350m1/cmos.layout
+++ b/src/mainboard/asrock/e350m1/cmos.layout
@@ -1,18 +1,18 @@
 #*****************************************************************************
-# 
+#
 #  This file is part of the coreboot project.
-# 
+#
 #  Copyright (C) 2011 Advanced Micro Devices, Inc.
-# 
+#
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
 #  the Free Software Foundation; version 2 of the License.
-# 
+#
 #  This program is distributed in the hope that it will be useful,
 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 #  GNU General Public License for more details.
-# 
+#
 #  You should have received a copy of the GNU General Public License
 #  along with this program; if not, write to the Free Software
 #  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl
index 6538b83eeb..70faab2836 100644
--- a/src/mainboard/getac/p470/acpi/ec.asl
+++ b/src/mainboard/getac/p470/acpi/ec.asl
@@ -151,7 +151,7 @@ Device(EC0)
 			TRAP(0xc1)
 		}
 	}
-	
+
 	Method (_Q09, 0)
 	{
 		Notify(BAT0, 0x80)
@@ -162,7 +162,7 @@ Device(EC0)
 	{
 		Notify(\_TZ.THRM, 0x80)
 	}
-	
+
 	Method (_Q20, 0)
 	{
 		Notify(\_SB.ECO, 0x81)
@@ -668,8 +668,8 @@ Scope(\_SB)
 			}
 			Return (0)
 		}
-		
-	
+
+
 
 	}
 }
diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
index c78d7d6248..b84acd921f 100644
--- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
+++ b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-/* This is board specific information: IRQ routing for the 
+/* This is board specific information: IRQ routing for the
  * i945
  */
 
diff --git a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl
index 28b06a1e3e..d9fba6b8c6 100644
--- a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl
@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-/* This is board specific information: IRQ routing for the 
+/* This is board specific information: IRQ routing for the
  * 0:1e.0 PCI bridge of the ICH7
  */
 
diff --git a/src/mainboard/getac/p470/acpi/mainboard.asl b/src/mainboard/getac/p470/acpi/mainboard.asl
index 88ff8b4ea7..396d8d8b0d 100644
--- a/src/mainboard/getac/p470/acpi/mainboard.asl
+++ b/src/mainboard/getac/p470/acpi/mainboard.asl
@@ -40,7 +40,7 @@ Device (SLPB)
 Device (PWRB)
 {
 	Name(_HID, EisaId("PNP0C0C"))
-	
+
 	// Wake
 	Name(_PRW, Package(){0x1d, 0x04})
 }
diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl
index eeaded838f..01de2e4842 100644
--- a/src/mainboard/getac/p470/acpi/platform.asl
+++ b/src/mainboard/getac/p470/acpi/platform.asl
@@ -53,9 +53,9 @@ Field(SMI1, AnyAcc, NoLock, Preserve)
 	INFO, 1024
 }
 
-/* The _PIC method is called by the OS to choose between interrupt 
+/* The _PIC method is called by the OS to choose between interrupt
  * routing via the i8259 interrupt controller or the APIC.
- * 
+ *
  * _PIC is called with a parameter of 0 for i8259 configuration and
  * with a parameter of 1 for Local Apic/IOAPIC configuration.
  */
@@ -119,7 +119,7 @@ Method(_WAK,1)
 
 	// Notify PCI Express slots in case a card
 	// was inserted while a sleep state was active.
-	
+
 	If (LEqual(RP1D, 0)) {
 		Notify(\_SB.PCI0.RP01, 0)
 	}
@@ -132,13 +132,13 @@ Method(_WAK,1)
 		Notify(\_SB.PCI0.RP04, 0)
 	}
 
-	// Are we coming from S3? 
+	// Are we coming from S3?
 	If (LEqual(Arg0, 3)) {
 		TRAP(0xeb)
 		TRAP(0x46)
 	}
 
-	// Are we coming from S4? 
+	// Are we coming from S4?
 	If (LEqual(Arg0, 4)) {
 		Notify(SLPB, 0x02)
 		If (DTSE) {
diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl
index e84c204d98..6614016f5f 100644
--- a/src/mainboard/getac/p470/acpi/superio.asl
+++ b/src/mainboard/getac/p470/acpi/superio.asl
@@ -136,7 +136,7 @@ Device (SIO1)
 			CreateByteField(RSRC, 0x05, IORH) // Why?
 			CreateByteField(RSRC,
 				\_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQL)
-			
+
 			Store (READ(0, 0x24, 0xff), Local0)
 			And (Local0, 0xc0, Local1)
 			ShiftRight(Local1, 0x06, Local1)
@@ -291,7 +291,7 @@ Device (SIO1)
 			CreateByteField(RSRC, 0x05, IORH)
 			CreateByteField(RSRC,
 				\_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQL)
-			
+
 			Store (READ(0, 0x25, 0xff), Local0)
 			And (Local0, 0xc0, Local1)
 			ShiftRight(Local1, 0x06, Local1)
@@ -445,7 +445,7 @@ Device (SIO1)
 			CreateByteField(RSRC, 0x05, IORH) // Why?
 			CreateByteField(RSRC,
 				\_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQL)
-			
+
 			Store (READ(0, 0x1b, 0xff), Local0)
 			And (Local0, 0xc0, Local1)
 			ShiftRight(Local1, 0x06, Local1)
@@ -597,7 +597,7 @@ Device (SIO1)
 			CreateByteField(RSRC, 0x05, IORH) // Why?
 			CreateByteField(RSRC,
 				\_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQL)
-			
+
 			Store (READ(0, 0x1c, 0xff), Local0)
 			And (Local0, 0xc0, Local1)
 			ShiftRight(Local1, 0x06, Local1)
diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl
index 93bdbcfe66..e5ea75e191 100644
--- a/src/mainboard/getac/p470/acpi/thermal.asl
+++ b/src/mainboard/getac/p470/acpi/thermal.asl
@@ -26,7 +26,7 @@ Scope (\_TZ)
 	ThermalZone (THRM)
 	{
 		// TODO These could/should be read from the
-		// GNVS area, so they can be controlled by 
+		// GNVS area, so they can be controlled by
 		// coreboot
 		Name(TC1V, 0x00)
 		Name(TC2V, 0x0a)
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout
index 130f1cefc6..c8790789b8 100644
--- a/src/mainboard/getac/p470/cmos.layout
+++ b/src/mainboard/getac/p470/cmos.layout
@@ -1,6 +1,6 @@
 #
 # This file is part of the coreboot project.
-# 
+#
 # Copyright (C) 2007-2008 coresystems GmbH
 #
 # This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index 9b376c79cf..bdd959edde 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -1,6 +1,6 @@
 ##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007-2009 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or
@@ -27,7 +27,7 @@ chip northbridge/intel/i945
                 end
         end
 
-        device pci_domain 0 on 
+        device pci_domain 0 on
                 device pci 00.0 on end # host bridge
 		# autodetect:
 		#device pci 01.0 off end # i945 PCIe root port
@@ -74,10 +74,10 @@ chip northbridge/intel/i945
                 	device pci 1d.7 on end # USB2 EHCI
                 	device pci 1e.0 on
 				chip southbridge/ti/pcixx12
-				  
+
 				end
 			end # PCI bridge
-			#device pci 1e.2 off end # AC'97 Audio 
+			#device pci 1e.2 off end # AC'97 Audio
 			#device pci 1e.3 off end # AC'97 Modem
                         device pci 1f.0 on # LPC bridge
                                 chip superio/smsc/fdc37n972
diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl
index f6c6cf785d..9728ea260c 100644
--- a/src/mainboard/getac/p470/dsdt.asl
+++ b/src/mainboard/getac/p470/dsdt.asl
@@ -42,7 +42,7 @@ DefinitionBlock(
 
 	// mainboard specific devices
 	#include "acpi/mainboard.asl"
-	
+
 	// Thermal Zone
 	#include "acpi/thermal.asl"
 
diff --git a/src/mainboard/msi/ms7135/dsdt.asl b/src/mainboard/msi/ms7135/dsdt.asl
index 090a3b2860..3e3fbfb835 100644
--- a/src/mainboard/msi/ms7135/dsdt.asl
+++ b/src/mainboard/msi/ms7135/dsdt.asl
@@ -260,7 +260,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "CB-DSDT ", 1)
 						Store (ETBA, HPT)
 						Return (CRS)
 					}
-						
+
 				}
 #endif
 			}
diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig
index 983e94ce8b..1bc74067a8 100644
--- a/src/mainboard/siemens/sitemp_g1p1/Kconfig
+++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig
@@ -23,12 +23,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select QRANK_DIMM_SUPPORT
 	select SET_FIDVID
 	select GFXUMA
-	select EXT_CONF_SUPPORT	
-	
+	select EXT_CONF_SUPPORT
+
 config MAINBOARD_DIR
 	string
 	default siemens/sitemp_g1p1
-	
+
 config LINT01_CONVERSION
 	bool
 	default y
@@ -48,7 +48,7 @@ config MAX_CPUS
 config MAX_PHYSICAL_CPUS
 	int
 	default 1
-	
+
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1
@@ -68,13 +68,13 @@ config IRQ_SLOT_COUNT
 config IOMMU
 	bool
 	default n
-	
+
 config HW_SCRUBBER
 	bool
 	default n
-	
+
 config ECC_MEMORY
 	bool
 	default n
-	
+
 endif # BOARD_SIEMENS_SITEMP_G1P1
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
index 546f31b4ad..3f3fed2fd0 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 /* Supported sleep states: */
 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
index 1115388905..82df7fe376 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl
@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-	
+
 /* Routing is in System Bus scope */
 Scope(\_SB)
 {
@@ -55,7 +55,7 @@ Scope(\_SB)
 		Package(){0x0013FFFF, 3, 0, 19 },
 
 		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
-		Package(){0x0014FFFF, 0, 0, 16 }, 
+		Package(){0x0014FFFF, 0, 0, 16 },
 		Package(){0x0014FFFF, 1, 0, 17 },
 		Package(){0x0014FFFF, 2, 0, 18 },
 		Package(){0x0014FFFF, 3, 0, 19 },
@@ -162,9 +162,9 @@ Scope(\_SB)
 		Package(){0x004FFFF, 0, \_SB.PCI0.LPC0.INTE, 0 },
 		Package(){0x004FFFF, 1, \_SB.PCI0.LPC0.INTF, 0 },
 		Package(){0x004FFFF, 2, \_SB.PCI0.LPC0.INTG, 0 },
-		Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 },	
+		Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 },
 	})
-	
+
 	Name(AP2P, Package(){
 		/* PCI slots: slot 0 behind Dev14, Fun4. */
 		Package(){0x0005FFFF, 0, 0, 21 }, // Phoenix does it
@@ -174,5 +174,5 @@ Scope(\_SB)
 		Package(){0x0004FFFF, 2, 0, 22 },
 		Package(){0x0004FFFF, 3, 0, 23 },
 	})
-			
+
 }
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
index 1d36f27a9c..035e7d4ad1 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  *
  */
- 
+
 /* THERMAL */
 Scope(\_TZ) {
 	Name (KELV, 2732)
@@ -51,7 +51,7 @@ Scope(\_TZ) {
 				/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
 			}
 		}
-		
+
 		// Processors used for active cooling
 		Method (_PSL, 0, Serialized)
 		{
@@ -60,7 +60,7 @@ Scope(\_TZ) {
 			}
 			Return (Package() {\_PR.CPU0})
 		}
-		
+
 		Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
 			/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
 			Return (Add (THOT, KELV))
@@ -96,4 +96,4 @@ Scope(\_TZ) {
 			}
 		} /* end of _TMP */
 	} /* end of TZ00 */
-}
\ No newline at end of file
+}
diff --git a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
index adbe757bad..6f068e4823 100644
--- a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
+++ b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb
@@ -15,7 +15,7 @@ chip northbridge/amd/amdk8/root_complex
 		end
 	end
 	device pci_domain 0 on
-		subsystemid 0x110a 0x4076 inherit	
+		subsystemid 0x110a 0x4076 inherit
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
@@ -24,7 +24,7 @@ chip northbridge/amd/amdk8/root_complex
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						device pci 5.0 on # Internal Graphics 0x791F
 						end
-						device pci 5.2 on # 
+						device pci 5.2 on #
 						end
 					end
 					device pci 2.0 on  #  PCIE P2P bridge 0x7913  (external GFX-port0)
diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
index f4752af6e5..8ad0f82c90 100644
--- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
@@ -37,8 +37,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 	Name(UOM7, 2)
 	Name(UOM8, 6)
 	Name(UOM9, 6)
-	
-	Name(DSEN, 1)		// Display Output Switching Enable 
+
+	Name(DSEN, 1)		// Display Output Switching Enable
 	// Power notification
 
 	/* PIC IRQ mapping registers, C00h-C01h */
@@ -252,13 +252,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 		PCBA,   32,
 		MPEN,	8
 	}
-	
+
 	Name (IOLM,0xe0000000)
-	
-#include "acpi/platform.asl"	
+
+#include "acpi/platform.asl"
 
 	Scope(\_SB) {
-	
+
 		/* PCIe Configuration Space for 16 busses */
 		OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */
 			Field(PCFG, ByteAcc, NoLock, Preserve) {
@@ -286,7 +286,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 			,14,
 			P92E, 1,		/* Port92 decode enable */
 		}
-		
+
 		OperationRegion(BAR5, SystemMemory, STB5, 0x1000)
 			Field(BAR5, AnyAcc, NoLock, Preserve)
 			{
@@ -359,7 +359,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 			P3PR, 1,
 		}
 	}
-#include "acpi/event.asl"	
+#include "acpi/event.asl"
 #include "acpi/routing.asl"
 #include "acpi/usb.asl"
 
@@ -367,7 +367,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 	Scope(\_SB)
 	{
 		/* Start \_SB scope */
-	
+
 #include "acpi/globutil.asl"
 
 		Device(PWRB) {	/* Start Power button device */
@@ -386,16 +386,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
-			
+
 			Method(_BBN, 0) { /* Bus number = 0 */
 				Return(0)
-			}			
+			}
 
 			Method(_STA, 0) {
 				/* DBGO("\\_SB\\PCI0\\_STA\n") */
 				Return(0x0B)     /* Status is visible */
 			}
-	
+
             Device (MEMR)
             {
                 Name (_HID, EisaId ("PNP0C02"))
@@ -432,18 +432,18 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				If(PCIF){ Return(APR0) }   /* APIC mode */
 				Return (PR0)                  /* PIC Mode */
 			} /* end _PRT */
-		
+
             OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
             Field (BAR1, ByteAcc, NoLock, Preserve)
             {
                 Z009,   32
             }
-			
+
 			/* Describe the Northbridge devices */
 			Device(AMRT) {
 				Name(_ADR, 0x00000000)
 			} /* end AMRT */
-			
+
 			/* The internal GFX bridge */
 			Device(AGPB) {
 				Name(_ADR, 0x00010000)
@@ -494,7 +494,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				Name(_PRW, Package() {0x18, 4})
 				Method(_PRT,0) {
 					If(PCIF){ Return(APS5) }   /* APIC mode */
-					Return (PS5)                  /* PIC Mode */  
+					Return (PS5)                  /* PIC Mode */
 				} /* end _PRT */
 			} /* end PBR5 */
 
@@ -520,7 +520,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 			/* PCI slot 1 */
 			Device(PIBR) {
 				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {4, 5}) //  Phoenix doeas it so 
+				Name(_PRW, Package() {4, 5}) //  Phoenix doeas it so
 				Method(_PRT, 0) {
 					If(PCIF){ Return(AP2P) }  /* APIC Mode */
 					Return (PCIB)             /* PIC Mode */
@@ -530,7 +530,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 			/* Describe the Southbridge devices */
 			Device(SATA) {
 				Name(_ADR, 0x00120000)
-#include "acpi/sata.asl" 
+#include "acpi/sata.asl"
 			} /* end SATA */
 
 			Device(UOH1) {
@@ -608,18 +608,18 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				}
 			} /* end AZHD */
 
-			Device(LPC0) 
+			Device(LPC0)
 			{
                 Name (_ADR, 0x00140003)
                 Mutex (PSMX, 0x00)
-				
+
 				/* PIC IRQ mapping registers, C00h-C01h */
 				OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
 				Field(PRQM, ByteAcc, NoLock, Preserve) {
 					PRQI, 0x00000008,
 					PRQD, 0x00000008,  /* Offset: 1h */
 				}
-	
+
 				IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 					PINA, 0x00000008,	/* Index 0  */
 					PINB, 0x00000008,	/* Index 1 */
@@ -632,7 +632,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 					PING, 0x00000008,	/* Index B */
 					PINH, 0x00000008,	/* Index C */
 				}
-				
+
 				Method(CIRQ, 0x00, NotSerialized)
 				{
 					Store(0, PINA)
@@ -653,11 +653,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				Name(IRQP, ResourceTemplate(){
 					IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7}
 				})
-				
+
 				Name(PITF, ResourceTemplate(){
 					IRQ(Level,ActiveLow,Exclusive){9}
-				})	
-				
+				})
+
 				Device(INTA) {
 					Name(_HID, EISAID("PNP0C0F"))
 					Name(_UID, 1)
@@ -679,7 +679,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 					} /* Method(_SB.INTA._PRS) */
 
 					Method(_CRS ,0) {
-						Store (IRQB, Local0) // 
+						Store (IRQB, Local0) //
 						CreateWordField(Local0, 0x1, IRQ0)
 						ShiftLeft(1, PINA, IRQ0)
 						Return(Local0)
@@ -725,7 +725,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 						/* Use lowest available IRQ */
 						FindSetRightBit(IRQ0, Local0)
 						Decrement(Local0)
-						Store(Local0, PINB)                    
+						Store(Local0, PINB)
 					} /* End Method(_SB.INTB._SRS) */
 				} /* End Device(INTB)  */
 
@@ -761,7 +761,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 						/* Use lowest available IRQ */
 						FindSetRightBit(IRQ0, Local0)
 						Decrement(Local0)
-						Store(Local0, PINC)    
+						Store(Local0, PINC)
 					} /* End Method(_SB.INTC._SRS) */
 				} /* End Device(INTC)  */
 
@@ -804,7 +804,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				Device(INTE) {
 					Name(_HID, EISAID("PNP0C0F"))
 					Name(_UID, 5)
-					
+
 					Method(_STA, 0) {
 						if (PINE) {
 							Return(0x0B) /* sata is invisible */
@@ -817,7 +817,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 						Store(0, PINE)
 					} /* End Method(_SB.INTE._DIS) */
 
-					Method(_PRS ,0) { 
+					Method(_PRS ,0) {
 						Return(IRQB) // Return(IRQP)
 					}
 
@@ -944,7 +944,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 						Store(Local0, PINH)
 					} /* End Method(_SB.INTH._SRS)  */
 				} /* End Device(INTH)   */
-		
+
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
@@ -1000,7 +1000,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
 					Name(_CRS, ResourceTemplate() {
 						IO(Decode16, 0x00F0, 0x00F0, 1, 0x10)
-						IRQ (Edge, ActiveHigh, Exclusive, ) {13} 
+						IRQ (Edge, ActiveHigh, Exclusive, ) {13}
 					})
 				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
 
@@ -1018,7 +1018,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 						Return(CRS)
 					}
                 }
-				
+
                 Device (KBC0)
                 {
                     Name (_HID, EisaId ("PNP0303"))
@@ -1039,7 +1039,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
                         IRQ (Edge, ActiveHigh, Exclusive, ) {1}
                     })
 				}
-				
+
                 Device (MSE0)
                 {
                     Name (_HID, EisaId ("PNP0F13"))
@@ -1054,7 +1054,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				Name(_ADR, 0x00140005)
 				Name (_PRW, Package (0x02)
                 {
-                    0x0C, 
+                    0x0C,
                     0x04
                 })
 			} /* end Ac97audio */
@@ -1063,7 +1063,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				Name(_ADR, 0x00140006)
 				Name (_PRW, Package (0x02)
                 {
-                    0x0C, 
+                    0x0C,
                     0x04
                 })
 			} /* end Ac97modem */
@@ -1183,7 +1183,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 				CreateDWordField(CRES, ^EMM2._MIN, EM2B)
 				CreateDWordField(CRES, ^EMM2._MAX, EM2E)
 				CreateDWordField(CRES, ^EMM2._LEN, EM2L)
-				
+
 				Store(TOM1, EM2B)
 				Subtract(IOLM, 1, EM2E)
 				Subtract(IOLM, TOM1, EM2L)
@@ -1223,9 +1223,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 			SCMD,   8,  /* SMBUS shaow cmd */
 			SEVT,   8,  /* SMBUS slave event */
 			SDAT,   8,  /* SMBUS slave data */
-			SMK1,   8, 
-            SLMC,   8, 
-            RADD,   8, 
+			SMK1,   8,
+            SLMC,   8,
+            RADD,   8,
             SADD,   8
 	}
 
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
index d43b81e1ab..cb30e43969 100644
--- a/src/mainboard/wyse/s50/devicetree.cb
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -20,7 +20,7 @@
 ##
 
 chip northbridge/amd/gx2
-	device pci_domain 0 on 
+	device pci_domain 0 on
 		device pci 1.0 on end	# Geode GX2 Host Bridge
 		device pci 1.1 on end	# Geode GX2 Graphics Processor
 		chip southbridge/amd/cs5536
diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc
index 3bda8d5cc4..8f0fe0d773 100755
--- a/src/northbridge/amd/agesa/family12/Makefile.inc
+++ b/src/northbridge/amd/agesa/family12/Makefile.inc
@@ -16,7 +16,7 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
- 
+
 driver-y += northbridge.c
 
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
\ No newline at end of file
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 899d517055..d3a125c57a 100644
--- a/src/northbridge/amd/agesa/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
@@ -16,5 +16,5 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
- 
+
 driver-y += northbridge.c
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 74e0ff454b..a14339e52a 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -119,5 +119,5 @@ config SVI_HIGH_FREQ
         help
           Select this for boards with a Voltage Regulator able to operate
           at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
- 
+
 source src/northbridge/amd/amdfam10/root_complex/Kconfig
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index e55efcb667..37fcf7e307 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -335,7 +335,7 @@ static void GLPCIInit(void)
 	/* we are ignoring the 5530 case for now, and perhaps forever. */
 
 	/* 553X NB Init */
-	
+
 	/* Arbiter setup */
 	msrnum = GLPCI_ARB;
 	msr = rdmsr(msrnum);
@@ -404,7 +404,7 @@ static void ClockGatingInit(void)
 static void GeodeLinkPriority(void)
 {
 	msr_t msr = { 0, 0 };
-	
+
 	struct msrinit *prio = GeodeLinkPriorityTable;
 	int i;
 
@@ -426,7 +426,7 @@ static void GeodeLinkPriority(void)
 static uint64_t getShadow(void)
 {
 	msr_t msr = { 0, 0 };
-	
+
 	msr = rdmsr(GLIU0_P2D_SC_0);
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index a6bd2026d9..3550954583 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -36,7 +36,7 @@ config EHCI_DEBUG_OFFSET
 
 config USBDEBUG_DEFAULT_PORT
 	int
-	default 1 
+	default 1
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
         string