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authorPaul Menzel <pmenzel@molgen.mpg.de>2018-02-14 15:13:38 +0100
committerMartin Roth <martinroth@google.com>2018-02-15 21:39:38 +0000
commit3985112898b953e6b152271c917f67c9fd5e8758 (patch)
treeefccf6fafbffe155df536e65e1dd9ff5eefc7396 /src
parente0d306447a13652905f6224163d6c96d5a21e9bf (diff)
cpu/x86/16bit/entry16.inc: Fix typo in comment
Add the missing *r* of the possessive pronoun *your*. Change-Id: I2b520f398a904eb8e4412835d90bde1ee0b504b7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/23758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/x86/16bit/entry16.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index cf366e0af6..a87ce754fa 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -54,7 +54,7 @@ _start16bit:
* If we are hyperthreaded or we have multiple cores it is bad,
* for SMP startup. On Opterons it causes a 5 second delay.
* Invalidating the cache was pure paranoia in any event.
- * If you CPU needs it you can write a CPU dependent version of
+ * If your CPU needs it you can write a CPU dependent version of
* entry16.inc.
*/