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authorElyes HAOUAS <ehaouas@noos.fr>2020-03-31 21:10:20 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-04-09 23:49:12 +0000
commit3408a0ef0c9cc3b2f546b5d6c864ee00d61956f5 (patch)
tree88c2bc65a2444bdec1e886a8257888eedf9fa03f /src
parent408fdeba7fc8fdbe99eba6851aec3bedef90de32 (diff)
mb/intel/d945gclf: Improve code formatting of devicetree
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/d945gclf/devicetree.cb94
1 files changed, 45 insertions, 49 deletions
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 3d7e8c632a..9d81e31232 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -14,22 +14,22 @@
chip northbridge/intel/i945
- device cpu_cluster 0 on
- chip cpu/intel/socket_441
- device lapic 0 on end
- end
- end
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_441
+ device lapic 0 on end
+ end
+ end
register "pci_mmio_size" = "768"
- device domain 0 on
- subsystemid 0x8086 0x464c inherit
- device pci 00.0 on end # host bridge
+ device domain 0 on
+ subsystemid 0x8086 0x464c inherit
+ device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
- device pci 02.1 on end # display controller
+ device pci 02.0 on end # vga controller
+ device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx
+ chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x07"
register "pirqc_routing" = "0x05"
@@ -46,60 +46,56 @@ chip northbridge/intel/i945
register "gpi13_routing" = "1"
register "gpe0_en" = "0x20000601"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- register "gen1_dec" = "0x0007c0681" # SuperIO Power Management
+ register "gen1_dec" = "0x0007c0681" # SuperIO Power Management
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe port 1
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe port 1
device pci 1c.1 off end # PCIe port 2
- device pci 1c.2 on end # PCIe port 3
- device pci 1c.3 on end # PCIe port 4
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
+ device pci 1c.2 on end # PCIe port 3
+ device pci 1c.3 on end # PCIe port 4
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
device pci 1d.3 off end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47m15x
- device pnp 2e.0 off # Floppy
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/lpc47m15x
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.3 off end # Parport
+ device pnp 2e.4 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
end
- device pnp 2e.3 off # Parport
- end
- device pnp 2e.4 on
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 on
- io 0x60 = 0x2f8
- irq 0x70 = 3
+ device pnp 2e.5 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
- end
- device pnp 2e.7 on # Keyboard+Mouse
+ end
+ device pnp 2e.7 on # Keyboard+Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
- irq 0xf0 = 0x82 # HW accel A20.
+ irq 0xf0 = 0x82 # HW accel A20.
end
- device pnp 2e.8 on # GAME
+ device pnp 2e.8 on # GAME
# all default
end
- device pnp 2e.a on # PME
- end
- device pnp 2e.b on # MPU
- end
- end
- end
+ device pnp 2e.a on end # PME
+ device pnp 2e.b on end # MPU
+ end
+ end
device pci 1f.1 off end # IDE
- device pci 1f.2 on end # SATA
- device pci 1f.3 on end # SMBus
- end
- end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ end
+ end
end