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authorPeter Stuge <peter@stuge.se>2011-06-04 15:47:30 +0000
committerPeter Stuge <peter@stuge.se>2011-06-04 15:47:30 +0000
commit2334c8d2b7771dd77299ef0e5983dc994c798a60 (patch)
treeb8e46c524ea0d8a5a73d19cb612b4ff9fc835a8f /src
parent314f4a2077b78fbbab3bfe60308e82b875ddcc07 (diff)
Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 9dceae6700..d1e4a8b0c8 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -99,12 +99,12 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
end #LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # USB 2
- device pci 15.0 on end # PCIe PortA
- device pci 15.1 on end # PCIe PortB
- device pci 15.2 on end # PCIe PortC
- device pci 15.3 on end # PCIe PortD
- register "gpp_configuration" = "4" #1:1:1:1
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ device pci 15.0 off end # PCIe PortA
+ device pci 15.1 off end # PCIe PortB
+ device pci 15.2 off end # PCIe PortC
+ device pci 15.3 off end # PCIe PortD
+ register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx_wrapper/sb800
# end # device pci 18.0
# These seem unnecessary