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authorNaveen Krishna Chatradhi <naveenkrishna.ch@intel.com>2015-07-10 16:00:51 +0530
committerAaron Durbin <adurbin@chromium.org>2015-08-27 14:16:30 +0000
commit133dcd386f2ae620b635446bb3d7b34d3b95eca8 (patch)
tree2502384f66d89d45c26b24e2458c881f6c6831ff /src
parent31f0521a996791f842af94f0c561c18fd2aec2ba (diff)
Kunimitsu: enable deep S5
This patche enables the deep S5 and disables Deep S3. Kunimitsu does not resume from deep S3. This change will unblock the S3 resume path on kunimitsu board. BRANCH=None BUG=chrome-os-partner:42331 TEST=Built and booted on kunimitsu; check s3 works. Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291250 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I07b95a324a27ab658e80674686b47b86412ea097 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 09e41b97da..b5f0dbb335 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -82,6 +82,13 @@ chip soc/intel/skylake
# Integrated Sensor
register "IshEnable" = "0"
+ # Enable deep Sx states
+ register "deep_s3_enable" = "0"
+ register "deep_s5_enable" = "1"
+
+ # CPU Thermal participant device
+ register "Device4Enable" = "1"
+
# XDCI controller
register "XdciEnable" = "0"
@@ -131,6 +138,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
device pci 1f.4 off end # SMBus Controller
device pci 1f.5 on end # SPI