diff options
| author | Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> | 2021-08-31 11:05:14 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-09-03 07:10:36 +0000 |
| commit | e895b2aa9dc42084ad26456b3ba472bec964a92b (patch) | |
| tree | 7089970679c2faf7b35a3e4bea99eb97b805d1e3 /src/vendorcode | |
| parent | d37aeb1bcbd8950806bec3c0b83337c8beecdfa1 (diff) | |
vc/mediatek/mt8195: Remove unused code
Remove unused drivers and some fast calibration implementations
to align with the latest MTK memory reference code.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c | 1792 | ||||
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c | 238 |
2 files changed, 1 insertions, 2029 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index 16f16ff0e4..7233f33929 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -143,7 +143,6 @@ static U32 CATrain_CsDelay[CHANNEL_NUM][RANK_MAX]; static S32 wrlevel_dqs_final_delay[RANK_MAX][DQS_BYTE_NUMBER]; // 3 is channel number //static U16 u2rx_window_sum; -JMETER_DELAYCELL_T JMeter_DelayCell_Table[DRAM_DFS_SRAM_MAX]={0}; U8 gFinalRXVrefDQForSpeedUp[CHANNEL_NUM][RANK_MAX][2/*ODT_onoff*/][2/*2bytes*/] = {0}; U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX] = {{0,0,0,0},{0,0,0,0},{0,0,0,0}};//ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN @@ -2821,360 +2820,6 @@ void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay) P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS)); } } -#if 0 -static void CATrainingPosCal(DRAMC_CTX_T *p, U8* pu1DieNum, S8* ps1CAMacroDelay, S16 *ps1CACenterDiff, U8 u1CABitNum) -{ - U8 u1RankIdx, u1DieIdx, u1CAIdx; - S8 s1Intersect_min, s1Intersect_max; - S8 s1Intersect_min_byBit[CATRAINING_NUM], s1Intersect_max_byBit[CATRAINING_NUM], s1CACenter_min;//, s1CACenter[CATRAINING_NUM]; - S8 s1TempFirstPass, s1TempLastPass; - U8 u1PerBitDelayCellEnable =0; - S8 s1CACenter[CATRAINING_NUM]; - -#if CA_PER_BIT_DELAY_CELL - u1PerBitDelayCellEnable = 1; -#endif - - mcSHOW_DBG_MSG(("\n[CATrainingPosCal] consider %d rank data\n", p->rank +1)); - - s1Intersect_min = -127; // 127 - s1Intersect_max = 127; //-127 - s1CACenter_min = 0x7f; - - for(u1CAIdx=0; u1CAIdx < u1CABitNum; u1CAIdx++) - { - s1Intersect_min_byBit[u1CAIdx] = -127; // 127 - s1Intersect_max_byBit[u1CAIdx] = 127; //-127 - - for (u1RankIdx = RANK_0; u1RankIdx <= p->rank; u1RankIdx++) - { - for (u1DieIdx = 0; u1DieIdx < pu1DieNum[u1RankIdx]; u1DieIdx++) - { - s1TempFirstPass = iFirstCAPass[u1RankIdx][u1DieIdx][u1CAIdx]; - s1TempLastPass = iLastCAPass[u1RankIdx][u1DieIdx][u1CAIdx]; - //mcSHOW_DBG_MSG(("RK%d, Die%d ,CA%d,iFirstCAPass = %d, iLastCAPass=%d \n",u1RankIdx, u1DieIdx, u1CAIdx, s1TempFirstPass, s1TempLastPass)); - - // Intersection by Macro - if(s1TempFirstPass > s1Intersect_min) - s1Intersect_min = s1TempFirstPass; - - if(s1TempLastPass < s1Intersect_max) - s1Intersect_max = s1TempLastPass; - - // intersection by CA bit - if(s1TempFirstPass > s1Intersect_min_byBit[u1CAIdx]) - s1Intersect_min_byBit[u1CAIdx] = s1TempFirstPass; - - if(s1TempLastPass < s1Intersect_max_byBit[u1CAIdx]) - s1Intersect_max_byBit[u1CAIdx] = s1TempLastPass; - } - } - - s1CACenter[u1CAIdx] = s1Intersect_min_byBit[u1CAIdx] + (s1Intersect_max_byBit[u1CAIdx] - s1Intersect_min_byBit[u1CAIdx])/2; - - if(s1CACenter[u1CAIdx] < s1CACenter_min) - s1CACenter_min = s1CACenter[u1CAIdx]; - } - - // If CA perbit, choose min CA PI of all bits. - // If CA perbyte, choose middle position of intersenction range of all bits. - - // CA perbit enable - if(u1PerBitDelayCellEnable && (p->u2DelayCellTimex100 !=0)) - { - if(s1CACenter_min <0) //don't move clk - { - //mcSHOW_DBG_MSG(("warning : Minimum CA PI delay is %d(<0) and changed to 0\n", s1CACenter_min)); - s1CACenter_min =0; - } - - *ps1CAMacroDelay = s1CACenter_min; - - mcSHOW_DBG_MSG(("u2DelayCellTimex100 = %d/100 ps\n", p->u2DelayCellTimex100)); - - for(u1CAIdx=0; u1CAIdx < u1CABitNum; u1CAIdx++) - { - if(s1CACenter[u1CAIdx] <0) //don't move clk - { - s1CACenter[u1CAIdx] =0; - ps1CACenterDiff[u1CAIdx]=0; - } - else - { - ps1CACenterDiff[u1CAIdx] = s1CACenter[u1CAIdx] - s1CACenter_min; - } - - mcSHOW_DBG_MSG(("CA%d delay=%d (%d~%d),", u1CAIdx, s1CACenter[u1CAIdx], s1Intersect_min_byBit[u1CAIdx], s1Intersect_max_byBit[u1CAIdx])); - mcSHOW_DBG_MSG(("Diff = %d PI ", ps1CACenterDiff[u1CAIdx])); - ps1CACenterDiff[u1CAIdx] = (ps1CACenterDiff[u1CAIdx]*100000000/(DDRPhyGetRealFreq(p)<<6))/p->u2DelayCellTimex100; - mcSHOW_DBG_MSG(("(%d cell)", ps1CACenterDiff[u1CAIdx])); - - //mcDUMP_REG_MSG(("CA%d delay=%d (%d~%d),", u1CAIdx, s1CACenter[u1CAIdx], s1Intersect_min_byBit[u1CAIdx], s1Intersect_max_byBit[u1CAIdx])); - //mcDUMP_REG_MSG(("Diff = %d PI ", ps1CACenterDiff[u1CAIdx])); - //mcDUMP_REG_MSG(("(%d cell)\n", ps1CACenterDiff[u1CAIdx])); - - if(ps1CACenterDiff[u1CAIdx]>0x7f) - { - mcSHOW_DBG_MSG(("[WARNING] CA%d delay cell %d >15, adjust to 15 cell", u1CAIdx, ps1CACenterDiff[u1CAIdx])); - //mcDUMP_REG_MSG(("[WARNING] CA%d delay cell %d >15, adjust to 15 cell\n", u1CAIdx, ps1CACenterDiff[u1CAIdx])); - ps1CACenterDiff[u1CAIdx] =0x7f; - } - - mcSHOW_DBG_MSG(("\n")); - -#ifdef FOR_HQA_REPORT_USED - if (gHQALog_flag == 1) - { - HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_2, "CA_PosCal_Cell", " ", u1CAIdx, ps1CACenterDiff[u1CAIdx], NULL); - } -#endif - } - - mcSHOW_DBG_MSG(("\nCA PerBit enable=%d, CA PI delay=%d\n", u1PerBitDelayCellEnable, *ps1CAMacroDelay)); - } - else //CA perbyte - { - *ps1CAMacroDelay = s1Intersect_min + (s1Intersect_max - s1Intersect_min)/2; - - if(*ps1CAMacroDelay <0)//don't move clk - { - //mcSHOW_DBG_MSG(("warning : CA PI delay is %d(<0) and changed to 0\n", *ps1CAMacroDelay)); - *ps1CAMacroDelay =0; - } - mcSHOW_DBG_MSG(("CA PerBit enable=%d, CA PI delay=%d (%d~%d)\n", u1PerBitDelayCellEnable, *ps1CAMacroDelay, s1Intersect_min, s1Intersect_max)); - } -} -#endif -#if 0 -static u32 new_cbt_pat_result(DRAMC_CTX_T *p) -{ - u32 res = 0, res0 = 0, res_final = 0; - u32 fld; - - if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) { -#if __LP5_COMBO__ - if (is_lp5_family(p)) - fld = CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0; - else -#endif - fld = CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1; - - res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), fld); - } else { - res0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), - CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0); - res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), - CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1); - } - - res_final = res | res0; - - return res_final; -} -#endif -#if 0 -static u32 new_cbt_pat_compare(DRAMC_CTX_T *p) -{ - u32 res_final = 0; - u32 time_cnt, rdy; - - time_cnt = TIME_OUT_CNT; - -#if CBT_O1_PINMUX_WORKAROUND - res_final = new_cbt_pat_compare_workaround(p, &ncm); -#else - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN); - - - do { - rdy = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), - CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT); - time_cnt--; - mcDELAY_US(1); - } while ((rdy == 0) && (time_cnt > 0)); - - if (time_cnt == 0) { - mcSHOW_DBG_MSG(("[new_cbt_pat_compare] Resp fail (time out)\n")); - //return DRAM_FAIL; - } - - res_final = new_cbt_pat_result(p); - - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN); -#endif - - return res_final; // return pattern compre result -} -#endif -#if 0 -static u32 new_cs_pat_compare(DRAMC_CTX_T *p) -{ - u32 res_final = 0; - u32 time_cnt, rdy; - - time_cnt = TIME_OUT_CNT; - - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN); - - do { - rdy = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), - CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT); - time_cnt--; - mcDELAY_US(1); - } while ((rdy == 0) && (time_cnt > 0)); - - if (time_cnt == 0) { - mcSHOW_ERR_MSG(("[new_cs_pat_compare] Resp fail (time out)\n")); - //return DRAM_FAIL; - } - - res_final = new_cbt_pat_result(p); - - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN); - - return res_final; // return pattern compre result -} -#endif -#if CBT_OLDMODE_SUPPORT -#if 0 -static U32 CBTDelayCACLKCompare(DRAMC_CTX_T *p) -{ - U32 u4Result = 0, u4Result0 = 0, u4Ready, res_final = 0; - U32 u4Fld, u4TimeCnt; - - u4TimeCnt = TIME_OUT_CNT; - -#if CBT_O1_PINMUX_WORKAROUND - res_final = CBTDelayCACLKCompareWorkaround(p); -#else /* Without WA */ - //Let R_DMTESTCATRAIN=1 to enable HW CAPAT Generator - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_CAPATEN); - - //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT) - do - { - u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_CPT); - u4TimeCnt --; - mcDELAY_US(1); - }while ((u4Ready == 0) && (u4TimeCnt > 0)); - - if (u4TimeCnt == 0)//time out - { - mcSHOW_ERR_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n")); - - mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test - - //return DRAM_FAIL; - } - - //Get CA training compare result (dramc_conf_nao 0x3fc , CATRAIN_CMP_ERR) - if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) - { -#if __LP5_COMBO__ - if (is_lp5_family(p)) - u4Fld = CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0; - else -#endif - u4Fld = CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1; - - u4Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), u4Fld); - } - else - { - u4Result0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0); -// mcSHOW_DBG_MSG(("[Francis] TCMDO1LAT_CATRAIN_CMP_ERR0=0x%x\n", u4Result0)); - u4Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1); -// mcSHOW_DBG_MSG(("[Francis] TCMDO1LAT_CATRAIN_CMP_ERR=0x%x\n", u4Result)); - } - - res_final = (u4Result | u4Result0); - - //Let R_DMTESTCATRAIN=0 to disable HW CAPAT Generator - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_CAPATEN); -#endif - - return res_final; // return pattern compre result -} -#endif -#endif -#if 0 -static U32 CBTDelayCSCompare(DRAMC_CTX_T *p, U32 uiDelay) -{ - U32 u4Result, u4Golden, u4Ready; - U32 u4TimeCnt; - U32 u4dq_o1; -#if (fcFOR_CHIP_ID==fcA60868) - U8 *uiLPDDR_O1_Mapping = NULL; - U32 u4byte_index; -#endif - - u4TimeCnt = TIME_OUT_CNT; - -#if (fcFOR_CHIP_ID==fcA60868) -#if (__LP5_COMBO__) - if (is_lp5_family(p)) { - uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel]; - } else -#endif - { - uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel]; - } -#endif - - //Step 5: toggle CS/CA for CS training by R_DMTCMDEN (wait dramc_nao tcmd_response=1, disable R_DMTCMDEN), 0x1e4[5] - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_TCMDEN); - do - { - u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TCMD_RESPONSE); - u4TimeCnt --; - mcDELAY_US(1); - }while ((u4Ready == 0) && (u4TimeCnt > 0)); - - - if (u4TimeCnt == 0)//time out - { - mcSHOW_ERR_MSG(("[CBTDelayCSCompare] Resp fail (time out)\n")); - //return DRAM_FAIL; - } - - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_TCMDEN); - - //Step 6: check CS training result on DQ[13:8] by O1, DDRPHYCFG 0xF80 - //Expected CA value is h2a (CA pulse width is 6UI, CS pulse is 1UI) - u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO); - u4Golden = 0x2a; - u4Result = 0; - -#if (fcFOR_CHIP_ID==fcA60868) -#if __LP5_COMBO__ - if (is_lp5_family(p)) { - for (u4byte_index = 0; u4byte_index <= 6; u4byte_index++) - { - u4Result |= (((u4dq_o1 & (1 << uiLPDDR_O1_Mapping[u4byte_index])) >> (uiLPDDR_O1_Mapping[u4byte_index])) << (u4byte_index)); - } - } - else -#endif - { - for (u4byte_index = 8; u4byte_index <= 13; u4byte_index++) { - u4Result |= (((u4dq_o1 & (1 << uiLPDDR_O1_Mapping[u4byte_index])) >> (uiLPDDR_O1_Mapping[u4byte_index])) << (u4byte_index - 8)); - } - } -#else -#if __LP5_COMBO__ - if (is_lp5_family(p)) { - u4Result = (u4dq_o1& 0x7F); // ignore DQ7 - } - else -#endif - { - u4Result = (u4dq_o1& 0xFF00)>>8; - } -#endif - - return u4Result ^ u4Golden; // return pattern compre result -} -#endif #if CBT_AUTO_K_SUPPORT /* @@ -3349,40 +2994,7 @@ static void cbt_autok_maxwindow(DRAMC_CTX_T *p, } #endif #endif -#if 0 -static void DramcCmdBusTrainingPostProcess(DRAMC_CTX_T *p) -{ - S32 iCSFinalClkDelay=0, iCSFinalCmdDelay, iCSFinalCSDelay; - U8 backup_rank, irank; - - // CBT Rank0/1 must set Clk/CA/CS the same from Wei-Jen - - mcSHOW_DBG_MSG(("[DramcCmdBusTrainingPostProcess] p->frequency=%d\n", p->frequency)); - - backup_rank = u1GetRank(p); - - iCSFinalCmdDelay = (CATrain_CmdDelay[p->channel][RANK_0] + CATrain_CmdDelay[p->channel][RANK_1]) / 2; - CATrain_CmdDelay[p->channel][RANK_0] = iCSFinalCmdDelay; - CATrain_CmdDelay[p->channel][RANK_1] = iCSFinalCmdDelay; - iCSFinalCSDelay = (CATrain_CsDelay[p->channel][RANK_0] + CATrain_CsDelay[p->channel][RANK_1]) / 2; - CATrain_CsDelay[p->channel][RANK_0] = iCSFinalCSDelay; - CATrain_CsDelay[p->channel][RANK_1] = iCSFinalCSDelay; - - for (irank = RANK_0; irank < RANK_MAX; irank++) - { - vSetRank(p, irank); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), P_Fld(iCSFinalClkDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) | - P_Fld(iCSFinalCmdDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) | - P_Fld(iCSFinalCSDelay, SHU_R0_CA_CMD0_RG_ARPI_CS)); - } - - mcSHOW_DBG_MSG(("Clk Dly = %d\nCmd Dly = %d\nCS Dly = %d\n", iCSFinalClkDelay, iCSFinalCmdDelay, iCSFinalCSDelay)); - - vSetRank(p, backup_rank); - -} -#endif static void CBTAdjustCS(DRAMC_CTX_T *p, int autok) { S32 iCSFinalDelay = 0;//iFirstCSPass = 0, iLastCSPass = 0, iCSCenter @@ -12254,330 +11866,12 @@ static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlySte //------------------------------------------------------------------------- #ifdef ENABLE_MIOCK_JMETER -static U16 DramcMiockJmeter(DRAMC_CTX_T *p) -{ - U8 backup_rank, u1RankIdx; - U16 ucstart_period = 0, ucmiddle_period = 0, ucend_period = 0; - // Read PCW - U16 u2real_freq, u2real_period; - // DQSIEN - U8 u1RxGatingPI = 0, u1RxGatingPI_start = 0, u1RxGatingPI_end = 63; - // Jmeter Scan - JMETER_T JmtrInfo; - //U8 u1JmtrPrintCnt = 0; - U8 u1GatingPI_Step = 1; - U16 num_dlycell_perT; - U16 delay_cell_ps; - - U32 u4RegBackupAddress[] = - { - (DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)), - (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), - (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), - (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), - (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)), - (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)), - (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)), - (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)), - (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)), - (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)), - (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)), - (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), // need porting to Jmeter - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), // need porting to Jmeter - (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)), - //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), // for gating on/off - //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), // for gating on/off - //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), // for gating on/off - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)), - (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)), - (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)), - (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)), - - }; - - if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) - u1GatingPI_Step = 1 << 3; - else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) - u1GatingPI_Step = 1 << 4; - else - u1GatingPI_Step = 1; - - backup_rank = u1GetRank(p); - memset(&JmtrInfo, 0, sizeof(JmtrInfo)); - - //backup register value - DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - - //mcDUMP_REG_MSG(("\n[dumpRG] DramcMiockJmeter\n")); - - //default set fail - vSetCalibrationResult(p, DRAM_CALIBRATION_JITTER_METER, DRAM_FAIL); - -#if VENDER_JV_LOG - vPrintCalibrationBasicInfo_ForJV(p); -#else - vPrintCalibrationBasicInfo(p); -#endif - mcSHOW_DBG_MSG(("[DramcMiockJmeter]\n")); - - DramcJmeterInit(p, TRUE); - - for (u1RxGatingPI = u1RxGatingPI_start; u1RxGatingPI < u1RxGatingPI_end; u1RxGatingPI += u1GatingPI_Step) - { - mcSHOW_DBG_MSG2(("\nu1RxGatingPI = %d\n", u1RxGatingPI)); - - for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) - { - vSetRank(p, u1RankIdx); - // SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0[6] no use (ignore) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1RxGatingPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); // for rank*_B0 - //Darren---vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), u1RxGatingPI, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); // for rank*_B0 - } - vSetRank(p, backup_rank); - - DramcJmeterCalib(p, &JmtrInfo, 4, TRUE); - - if ((JmtrInfo.u1TransCnt == CYCLE_1T) || (JmtrInfo.u1TransCnt == CYCLE_05T)) // (1T or 0.5T) - break; - } - - //restore to orignal value - OECKCKE_Control(p, ENABLE); - DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - -#if 0 //@Darren, for debug print - for (u1JmtrPrintCnt = 0; u1JmtrPrintCnt < JmtrInfo.u1TransCnt; u1JmtrPrintCnt++) - { - mcSHOW_DBG_MSG(("\n\t JmtrInfo.JmtrInfo[%d].u1JmDelay = %d\n", u1JmtrPrintCnt, JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1JmDelay)); - mcSHOW_DBG_MSG(("\n\t JmtrInfo.JmtrInfo[%d].u1TransLevel = %d\n", u1JmtrPrintCnt, JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1TransLevel)); - } - mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter - ucsearch_state = %d\n", ucsearch_state)); -#endif - - if (JmtrInfo.u1TransCnt != CYCLE_1T) - { - if (JmtrInfo.u1TransCnt != CYCLE_05T) - { - mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter - ch=%d\n", p->channel)); - mcSHOW_DBG_MSG(("\tLess than 0.5T data. Cannot calculate delay cell time\n\n")); - - delay_cell_ps = 0; //for LP3 and LP4 lookup table used - - return delay_cell_ps; - } - else - { // for 0.5T - //Calculate 1 delay cell = ? ps - // 1T = ? delay cell - ucstart_period = JmtrInfo.JmtrInfo[0].u1JmDelay; - ucmiddle_period = JmtrInfo.JmtrInfo[JmtrInfo.u1TransCnt-1].u1JmDelay; - num_dlycell_perT = (ucmiddle_period - ucstart_period) * 2; - // 1T = ? ps - } - } - else - { // for 1T - //Calculate 1 delay cell = ? ps - // 1T = ? delay cell - ucstart_period = JmtrInfo.JmtrInfo[0].u1JmDelay; - ucend_period = JmtrInfo.JmtrInfo[JmtrInfo.u1TransCnt-1].u1JmDelay; - num_dlycell_perT = (ucend_period - ucstart_period); - // 1T = ? ps - } - vSetCalibrationResult(p, DRAM_CALIBRATION_JITTER_METER, DRAM_OK); - - u2real_freq = DDRPhyGetRealFreq(p); - u2real_period = (U16) (1000000 / u2real_freq); - - //calculate delay cell time - delay_cell_ps = u2real_period * 100 / num_dlycell_perT; - - if (JmtrInfo.u1TransCnt == CYCLE_1T) - { // 1T - mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n" - "1T = (%d-%d) = %d dly cells\n" - "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n\n", - p->channel, - ucend_period, ucstart_period, num_dlycell_perT, - u2real_freq, u2real_period, delay_cell_ps)); - /*mcDUMP_REG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n" - "1T = (%d-%d) = %d dly cells\n" - "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n", - p->channel, - ucend_period, ucstart_period, num_dlycell_perT, - u2real_freq, u2real_period, delay_cell_ps));*/ - } - else - { // 0.5T - mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n" - "1T = (%d-%d)*2 = %d dly cells\n" - "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n\n", - p->channel, - ucmiddle_period, ucstart_period, num_dlycell_perT, - u2real_freq, u2real_period, delay_cell_ps)); - /*mcDUMP_REG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n" - "1T = (%d-%d)*2 = %d dly cells\n" - "Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n", - p->channel, - ucmiddle_period, ucstart_period, num_dlycell_perT, - u2real_freq, u2real_period, delay_cell_ps));*/ - } - - return delay_cell_ps; - -// log example -/* dly: sample_cnt DQS0_cnt DQS1_cnt - 0 : 10962054, 0, 0 - 1 : 10958229, 0, 0 - 2 : 10961109, 0, 0 - 3 : 10946916, 0, 0 - 4 : 10955421, 0, 0 - 5 : 10967274, 0, 0 - 6 : 10893582, 0, 0 - 7 : 10974762, 0, 0 - 8 : 10990278, 0, 0 - 9 : 10972026, 0, 0 - 10 : 7421004, 0, 0 - 11 : 10943883, 0, 0 - 12 : 10984275, 0, 0 - 13 : 10955268, 0, 0 - 14 : 10960326, 0, 0 - 15 : 10952451, 0, 0 - 16 : 10956906, 0, 0 - 17 : 10960803, 0, 0 - 18 : 10944108, 0, 0 - 19 : 10959939, 0, 0 - 20 : 10959246, 0, 0 - 21 : 11002212, 0, 0 - 22 : 10919700, 0, 0 - 23 : 10977489, 0, 0 - 24 : 11009853, 0, 0 - 25 : 10991133, 0, 0 - 26 : 10990431, 0, 0 - 27 : 10970703, 11161, 0 - 28 : 10970775, 257118, 0 - 29 : 10934442, 9450467, 0 - 30 : 10970622, 10968475, 0 - 31 : 10968831, 10968831, 0 - 32 : 10956123, 10956123, 0 - 33 : 10950273, 10950273, 0 - 34 : 10975770, 10975770, 0 - 35 : 10983024, 10983024, 0 - 36 : 10981701, 10981701, 0 - 37 : 10936782, 10936782, 0 - 38 : 10889523, 10889523, 0 - 39 : 10985913, 10985913, 55562 - 40 : 10970235, 10970235, 272294 - 41 : 10996056, 10996056, 9322868 - 42 : 10972350, 10972350, 10969738 - 43 : 10963917, 10963917, 10963917 - 44 : 10967895, 10967895, 10967895 - 45 : 10961739, 10961739, 10961739 - 46 : 10937097, 10937097, 10937097 - 47 : 10937952, 10937952, 10937952 - 48 : 10926018, 10926018, 10926018 - 49 : 10943793, 10943793, 10943793 - 50 : 10954638, 10954638, 10954638 - 51 : 10968048, 10968048, 10968048 - 52 : 10944036, 10944036, 10944036 - 53 : 11012112, 11012112, 11012112 - 54 : 10969137, 10969137, 10969137 - 55 : 10968516, 10968516, 10968516 - 56 : 10952532, 10952532, 10952532 - 57 : 10985832, 10985832, 10985832 - 58 : 11002527, 11002527, 11002527 - 59 : 10950660, 10873571, 10950660 - 60 : 10949022, 10781797, 10949022 - 61 : 10974366, 10700617, 10974366 - 62 : 10972422, 1331974, 10972422 - 63 : 10926567, 0, 10926567 - 64 : 10961658, 0, 10961658 - 65 : 10978893, 0, 10978893 - 66 : 10962828, 0, 10962828 - 67 : 10957599, 0, 10957599 - 68 : 10969227, 0, 10969227 - 69 : 10960722, 0, 10960722 - 70 : 10970937, 0, 10963180 - 71 : 10962054, 0, 10711639 - 72 : 10954719, 0, 10612707 - 73 : 10958778, 0, 479589 - 74 : 10973898, 0, 0 - 75 : 11004156, 0, 0 - 76 : 10944261, 0, 0 - 77 : 10955340, 0, 0 - 78 : 10998153, 0, 0 - 79 : 10998774, 0, 0 - 80 : 10953234, 0, 0 - 81 : 10960020, 0, 0 - 82 : 10923831, 0, 0 - 83 : 10951362, 0, 0 - 84 : 10965249, 0, 0 - 85 : 10949103, 0, 0 - 86 : 10948707, 0, 0 - 87 : 10941147, 0, 0 - 88 : 10966572, 0, 0 - 89 : 10971333, 0, 0 - 90 : 10943721, 0, 0 - 91 : 10949337, 0, 0 - 92 : 10965942, 0, 0 - 93 : 10970397, 0, 0 - 94 : 10956429, 0, 0 - 95 : 10939896, 0, 0 - 96 : 10967112, 0, 0 - 97 : 10951911, 0, 0 - 98 : 10953702, 0, 0 - 99 : 10971090, 0, 0 - 100 : 10939590, 0, 0 - 101 : 10993392, 0, 0 - 102 : 10975932, 0, 0 - 103 : 10949499, 40748, 0 - 104 : 10962522, 258638, 0 - 105 : 10951524, 275292, 0 - 106 : 10982475, 417642, 0 - 107 : 10966887, 10564347, 0 - =============================================================================== - MIOCK jitter meter - channel=0 - =============================================================================== - 1T = (107-29) = 78 delay cells - Clock frequency = 936 MHz, Clock period = 1068 ps, 1 delay cell = 13 ps -*/ -} - -static U16 get_DelayCell_by_Vcore(U32 check_vcore_value) -{ - U8 i= 0; - - for (i = SRAM_SHU0; i < DRAM_DFS_SRAM_MAX; i++) - { - if (JMeter_DelayCell_Table[i].Vcore == check_vcore_value) - { - return JMeter_DelayCell_Table[i].delay_cell_ps; //found !! - } - } - - return 0; //not found -} - /* "picoseconds per delay cell" depends on Vcore only (frequency doesn't matter) * 1. Retrieve current freq's vcore voltage using pmic API * 2. Perform delay cell time calculation (Bypass if shuffle vcore value is the same as before) */ U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p) { - U32 curr_vcore_value; - U16 delay_cell_ps; - int vcore_i=0; #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if(p->femmc_Ready==1) @@ -12587,68 +11881,7 @@ U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p) } #endif -#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) - curr_vcore_value = dramc_get_vcore_voltage(); -#endif - - /* find delay cell by curr_vcore_value */ - delay_cell_ps = get_DelayCell_by_Vcore(curr_vcore_value); - - if (delay_cell_ps == 0) - { - /* not found!! */ - - /* can K JMeter */ - if (p->frequency > 600) - { - delay_cell_ps = DramcMiockJmeter(p); - -#ifdef FOR_HQA_TEST_USED - /* if K fail, then look up table */ - if (delay_cell_ps == 0) delay_cell_ps = GetVcoreDelayCellTimeFromTable(p); //lookup table -#endif - } -#ifdef FOR_HQA_TEST_USED - else - { - /* save K JMeter's time, use llok up table directly */ - delay_cell_ps = GetVcoreDelayCellTimeFromTable(p); //lookup table - } -#endif - if (delay_cell_ps == 0) - { - //not found finally - mcSHOW_ERR_MSG(("[%s] Get Delay Cell by Vcore fail!!\n", __func__)); -#if __ETT__ - while(1); -#endif - } - - /* save values */ - for(vcore_i=0; vcore_i<DRAM_DFS_SRAM_MAX; vcore_i++) - { - if (JMeter_DelayCell_Table[vcore_i].Vcore == 0) //save current vcore's delay cell - { - JMeter_DelayCell_Table[vcore_i].delay_cell_ps = delay_cell_ps; - JMeter_DelayCell_Table[vcore_i].Vcore = curr_vcore_value; - break; -} - } - } -#if __ETT__ - mcSHOW_DBG_MSG(("[%s] Freq=%d, VCORE=%d, cell=%d\n", __func__, p->frequency, curr_vcore_value, delay_cell_ps)); -#endif - - mcSHOW_DBG_MSG3(("DelayCellTimex100 (VCORE=%d, cell=%d)\n", JMeter_DelayCell_Table[vcore_i].Vcore, delay_cell_ps)); - -#ifdef FOR_HQA_REPORT_USED - if (gHQALog_flag == 1) - { - HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("delaycell_CBT %d\n", delay_cell_ps)); - } -#endif - - return delay_cell_ps; + return 0; } void Get_RX_DelayCell(DRAMC_CTX_T *p) @@ -13755,180 +12988,6 @@ void DQDQMDutyScan_CopyDQRG2DQMRG(DRAMC_CTX_T *p) #endif #endif - -// offset is not related to DQ/DQM/DQS -// we have a circuit to measure duty, But this circuit is not very accurate -// so we need to K offset of this circuit first -// After we got this offset, then we can use it to measure duty -// this offset can measure DQ/DQS/DQM, and every byte has this circuit, too. -// B0/B1/CA all have one circuit. -// CA's circuit can measure CLK duty -// B0/B1's can measure DQ/DQM/DQS duty -#if 0 //[FOR_CHROMEOS] -static S8 DutyScan_Offset_Convert(U8 val) -{ - U8 calibration_sequence[15]= { - 0xf, 0xe, 0xd, 0xc, - 0xb, 0xa, 0x9, 0x0, - 0x1, 0x2, 0x3, 0x4, - 0x5, 0x6, 0x7 - }; - - return ((S8)(calibration_sequence[val]>8 ? 0-(calibration_sequence[val]&0x7) : calibration_sequence[val])); - -} -#endif -#if 0 -static void DutyScan_SetDutyOffset(DRAMC_CTX_T *p, U8 u1B0, U8 u1B1, U8 u1CA) -{ - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), u1B0, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), u1B1, B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), u1CA, CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA); -} - -static void DutyScan_Offset_Calibration(DRAMC_CTX_T *p, U8 *u1OfB0, U8 *u1OfB1, U8 *u1OfCA) -{ - U8 calibration_sequence[15]={0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7}; - U8 i, read_val_b0, read_val_b1, read_val_ca; - U8 cal_i_b0=0xff, cal_i_b1=0xff, cal_i_ca=0xff; - -#if VENDER_JV_LOG - vPrintCalibrationBasicInfo_ForJV(p); -#else - vPrintCalibrationBasicInfo(p); -#endif - - mcSHOW_DBG_MSG(("[Duty_Offset_Calibration]\n")); - - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), - P_Fld(0, MISC_CTRL4_R_OPT2_MPDIV_CG) | - P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQS)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3), - P_Fld(0, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT) | - P_Fld(0, MISC_CTRL3_ARPI_CG_DQS_OPT)); - - - - //B0/B1/CA RG setting - for(i=0; i<3; i++) - { - if (i<2) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) + i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(1, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B0) | - P_Fld(2, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) + i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0) | - P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)); - } - else - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), - P_Fld(1, CA_CMD6_RG_TX_ARCMD_DATA_SWAP_EN) | - P_Fld(2, CA_CMD6_RG_TX_ARCMD_DATA_SWAP)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), - P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA)); - } - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5) + i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0)); - - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3) + i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(0x38, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0) | - P_Fld(0x0, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0) | - P_Fld(0x1, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B0)); - - mcDELAY_US(1); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) + i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0)); - } - - mcSHOW_DBG_MSG2((" Offset\tB0\tB1\tCA\n")); - mcSHOW_DBG_MSG2(("====================================================\n")); - - for(i=0; i<15; i++) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), calibration_sequence[i], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), calibration_sequence[i], B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), calibration_sequence[i], CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA); - - mcDELAY_US(1); - - read_val_b0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0); - read_val_b1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1); - read_val_ca = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0); - - //mcSHOW_DBG_MSG2((" %d \t%d\t%d\t%d\n", DutyScan_Offset_Convert(i), read_val_b0, read_val_b1, read_val_ca)); [FOR_CHROMEOS] - - if (read_val_b0 == 0 && cal_i_b0==0xff) - { - cal_i_b0 = i; - } - - if (read_val_b1 == 0 && cal_i_b1==0xff) - { - cal_i_b1 = i; - } - - if (read_val_ca == 0 && cal_i_ca==0xff) - { - cal_i_ca = i; - } - } - - if (cal_i_b0==0 || cal_i_b1==0 || cal_i_ca==0) - { - mcSHOW_ERR_MSG(("offset calibration i=-7 and AD_RX_*RDQ_O1_B*<2>/AD_RX_*RCA2_O1 ==0 !!\n")); - } - else if ((read_val_b0==1 && cal_i_b0==0xff) || (read_val_b1==1 && cal_i_b1==0xff) || (read_val_ca==1 && cal_i_ca==0xff)) - { - mcSHOW_ERR_MSG(("offset calibration i=7 and AD_RX_*RDQ_O1_B*<2>/AD_RX_*RCA2_O1 ==1 !!\n")); - if (read_val_b0==1 && cal_i_b0==0xff) - cal_i_b0 = (i-1); //max - if (read_val_b1==1 && cal_i_b1==0xff) - cal_i_b1 = (i-1); //max - if (read_val_ca==1 && cal_i_ca==0xff) - cal_i_ca = (i-1); //max - } - - mcSHOW_DBG_MSG2(("====================================================\n")); - //[FOR_CHROMEOS] - //mcSHOW_DBG_MSG((" Final\tB0:%d\tB1:%d\tCA:%d\n",DutyScan_Offset_Convert(cal_i_b0),DutyScan_Offset_Convert(cal_i_b1),DutyScan_Offset_Convert(cal_i_ca))); - //mcDUMP_REG_MSG((" Final\tB0:%d\tB1:%d\tCA:%d\n",DutyScan_Offset_Convert(cal_i_b0),DutyScan_Offset_Convert(cal_i_b1),DutyScan_Offset_Convert(cal_i_ca))); - - - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), - P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), - P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), - P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA)); - - if (cal_i_b0!=0xff) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), calibration_sequence[cal_i_b0], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0); - *u1OfB0 = calibration_sequence[cal_i_b0]; - } - if (cal_i_b1!=0xff) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), calibration_sequence[cal_i_b1], B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1); - *u1OfB1 = calibration_sequence[cal_i_b1]; - } - if (cal_i_ca!=0xff) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), calibration_sequence[cal_i_ca], CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA); - *u1OfCA = calibration_sequence[cal_i_ca]; - } - - for(i=0; i<3; i++) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) + i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(1, B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0)); - } - - return; -} -#endif - S8 gcFinal_K_CLK_delay_cell[DQS_BYTE_NUMBER]; S8 gcFinal_K_DQS_delay_cell[DQS_BYTE_NUMBER]; S8 gcFinal_K_WCK_delay_cell[DQS_BYTE_NUMBER]; @@ -13946,788 +13005,11 @@ typedef struct _TEST_DUTY_AVG_LOG_PARAMETER_T U32 ucFinal_duty_max_clk_dly; U32 ucFinal_duty_min_clk_dly; } TEST_DUTY_AVG_LOG_PARAMETER_T; -#if 0 -static DRAM_STATUS_T DutyScan_Calibration_Flow(DRAMC_CTX_T *p, U8 k_type, U8 ft_test_type) -{ - DRAM_STATUS_T KResult = DRAM_FAIL; - BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - REG_TRANSFER_T CA_SWAP_Reg, B1_SWAP_Reg, CA_VrefSel_Reg, B1_VrefSel_Reg, CA_CmpOut_Reg, B1_CmpOut_Reg; - - S8 scinner_duty_ofst, scFinal_clk_delay_cell[DQS_BYTE_NUMBER]={0,0}, scinner_duty_ofst_step; - S8 scinner_duty_ofst_start = 0, scinner_duty_ofst_end = 0; - S32 s4PICnt, s4PIBegin, s4PIEnd, s4PICnt_mod64; - S8 i, swap_idx, ucdqs_i, ucdqs_i_count=2; - U32 u4DutyDiff, u4DutyDiff_Limit=900; - - U8 vref_sel_value[2], cal_out_value; - S32 duty_value[2]; - S32 final_duty; - - U32 ucperiod_duty_max=0, ucperiod_duty_min=0xffffffff, ucperiod_duty_max_clk_dly=0, ucperiod_duty_min_clk_dly=0; - U32 ucperiod_duty_averige=0, ucStart_period_duty_averige[DQS_BYTE_NUMBER]={0,0}, ucFinal_period_duty_averige[DQS_BYTE_NUMBER]={0,0}, ucmost_approach_50_percent=0xffffffff; - //U32 ucperiod_duty_averige_past=0, ; - - /* temp local record duty calibration result of every step to find first pass and last pass */ - TEST_DUTY_AVG_LOG_PARAMETER_T record_duty_log={0}; - U32 record_ucmost_approach_50_percent, temp_value; - S8 temp_first_pass=0, temp_last_pass=0; - - U32 ucFinal_period_duty_max[DQS_BYTE_NUMBER] = {0,0}, ucFinal_period_duty_min[DQS_BYTE_NUMBER] = {0,0}; - U32 ucFinal_duty_max_clk_dly[DQS_BYTE_NUMBER]={0},ucFinal_duty_min_clk_dly[DQS_BYTE_NUMBER]={0}; - U8 early_break_count=0; -//fra U8 str_clk_duty[]="CLK", str_dqs_duty[]="DQS", str_dq_duty[]="DQ", str_dqm_duty[]="DQM", str_wck_duty[]="WCK"; - //U8 *str_clk_duty, *str_dqs_duty, *str_dq_duty, *str_dqm_duty, *str_wck_duty; - -//fra U8 *str_who_am_I=str_clk_duty; - const char *str_who_am_I = "CLK"; -#if FT_DSIM_USED - S32 s4FT_Test_Final_duty[2][3]={0}; -#endif - - U8 clksel =0; - U8 tDelay; - //U32 tmp; - - if (!isLP4_DSC) - { - CA_SWAP_Reg.u4Addr = DDRPHY_REG_CA_CMD6; - CA_SWAP_Reg.u4Fld = CA_CMD6_RG_TX_ARCMD_DATA_SWAP; - B1_SWAP_Reg.u4Addr = DDRPHY_REG_B1_DQ6; - B1_SWAP_Reg.u4Fld = B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1; - CA_VrefSel_Reg.u4Addr = DDRPHY_REG_CA_PHY3; - CA_VrefSel_Reg.u4Fld = CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA; - B1_VrefSel_Reg.u4Addr = DDRPHY_REG_B1_PHY3; - B1_VrefSel_Reg.u4Fld = B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1; - CA_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS; - CA_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0; - B1_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS; - B1_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1; - } - else - { - CA_SWAP_Reg.u4Addr = DDRPHY_REG_B1_DQ6; - CA_SWAP_Reg.u4Fld = B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1; - B1_SWAP_Reg.u4Addr = DDRPHY_REG_CA_CMD6; - B1_SWAP_Reg.u4Fld = CA_CMD6_RG_TX_ARCMD_DATA_SWAP; - CA_VrefSel_Reg.u4Addr = DDRPHY_REG_B1_PHY3; - CA_VrefSel_Reg.u4Fld = B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1; - B1_VrefSel_Reg.u4Addr = DDRPHY_REG_CA_PHY3; - B1_VrefSel_Reg.u4Fld = CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA; - CA_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS; - CA_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1; - B1_CmpOut_Reg.u4Addr = DDRPHY_REG_MISC_DUTYCAL_STATUS; - B1_CmpOut_Reg.u4Fld = MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0; - } - - - mcSHOW_DBG_MSG3(("\n[DutyScan_Calibration_Flow] k_type=%d\n", k_type)); - /*TINFO="\n[DutyScan_Calibration_Flow] k_type=%d\n", k_type */ - - //CLK Source Select (DQ/DQM/DQS/CLK) - if (k_type == DutyScan_Calibration_K_CLK) // K CLK - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3), - P_Fld(0, MISC_CTRL3_ARPI_CG_CLK_OPT)); - - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), - P_Fld(1, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE)); - ucdqs_i_count = 1; - } - else - { -#if APPLY_DQDQM_DUTY_CALIBRATION - //CLK Source Select (DQ/DQM/DQS/CLK) - if (k_type == DutyScan_Calibration_K_DQ) // K DQ - { -#if SUPPORT_SAVE_TIME_FOR_CALIBRATION - if(p->femmc_Ready==1) - { - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); - return DRAM_OK; - } -#endif - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), - P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQ)); - - clksel = 1; - str_who_am_I = "DQ"; - } - else if (k_type == DutyScan_Calibration_K_DQM) // K DQM - { -#if SUPPORT_SAVE_TIME_FOR_CALIBRATION - if(p->femmc_Ready==1) - { - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); - return DRAM_OK; - } -#endif - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), - P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQM)); - - clksel = 3; - str_who_am_I = "DQM"; - } -#endif - else if (k_type == DutyScan_Calibration_K_DQS) // K DQS - { - str_who_am_I = "DQS"; - } - else if (k_type == DutyScan_Calibration_K_WCK) // K WCK - { - clksel = 2; - str_who_am_I = "WCK"; - } - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), - P_Fld(1, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) | - P_Fld(1, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE)); - - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), - P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0)); - if (!isLP4_DSC) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), - P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1)); - } - else - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), - P_Fld(0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA)); - } - } - - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), - clksel, B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B0); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), - clksel, B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B1); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), - clksel, CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_SEL_CA); - - scinner_duty_ofst_start = DUTY_OFFSET_START; - scinner_duty_ofst_end = DUTY_OFFSET_END; - -#if FOR_DV_SIMULATION_USED - scinner_duty_ofst_step = DUTY_OFFSET_STEP * 2; -#else - scinner_duty_ofst_step = DUTY_OFFSET_STEP; -#endif - -#if FT_DSIM_USED - if (ft_test_type == 0) - { - scinner_duty_ofst_start=0; - scinner_duty_ofst_end=0; - } - else - { - scinner_duty_ofst_start = DUTY_OFFSET_START; - scinner_duty_ofst_end = DUTY_OFFSET_END; - scinner_duty_ofst_step = DUTY_OFFSET_END //8; - } -#endif - -#if (fcFOR_CHIP_ID == fcA60868) - if (k_type == DutyScan_Calibration_K_CLK) - { - u4DutyDiff_Limit = 530; - } - else - { - u4DutyDiff_Limit = 580; - } -#endif - -#if 0//(fcFOR_CHIP_ID == fcLafite) - if (k_type == DutyScan_Calibration_K_CLK && p->channel == CHANNEL_A) - { - s4PIBegin = 0; - s4PIEnd = 0; - } - else -#endif - { - s4PIBegin = CLOCK_PI_START; - s4PIEnd = CLOCK_PI_END; - } - - for(ucdqs_i=0; ucdqs_i<ucdqs_i_count; ucdqs_i++) - { - if (k_type == DutyScan_Calibration_K_CLK) - { - mcSHOW_DBG_MSG(("[%s Duty scan]\n", str_who_am_I)); - /*TINFO="\n[CLK Duty scan]\n", ucdqs_i */ - } - else - { - mcSHOW_DBG_MSG(("[%s B%d Duty scan]\n", str_who_am_I, ucdqs_i)); - /*TINFO="\n[%s B%d Duty scan]\n", str_who_am_I, ucdqs_i */ - } - - ucmost_approach_50_percent=0xffff; - record_ucmost_approach_50_percent=0xffff; - early_break_count=0; - - mcSHOW_DBG_MSG2((" DutyOffset\tMaxDuty\tMinDuty\tAvgDuty\tAvg-50%%\tMax-Min\n")); - - //Set Duty Offset - for(scinner_duty_ofst=scinner_duty_ofst_start; scinner_duty_ofst<=scinner_duty_ofst_end; scinner_duty_ofst+=scinner_duty_ofst_step) - { - ucperiod_duty_max = 0; - ucperiod_duty_min = 100000; - - DramcDutyDelayRGSettingConvert(p, scinner_duty_ofst, &tDelay); - - if (k_type == DutyScan_Calibration_K_DQS) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0)); - } -#if __LP5_COMBO__ - if (k_type == DutyScan_Calibration_K_WCK) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0)); - } -#endif - if (k_type == DutyScan_Calibration_K_CLK) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_TXDUTY), - P_Fld(tDelay, SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY)); - } - - -#if APPLY_DQDQM_DUTY_CALIBRATION - if (k_type == DutyScan_Calibration_K_DQ) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0)); - } - - if (k_type == DutyScan_Calibration_K_DQM) - { - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, - P_Fld(tDelay, SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0)); - } -#endif - - for(s4PICnt=s4PIBegin; s4PICnt<=s4PIEnd; s4PICnt+=CLOCK_PI_STEP) - { - s4PICnt_mod64 = (s4PICnt+64)&0x3f;//s4PICnt_mod64 = (s4PICnt+64)%64; -#if DutyPrintAllLog - //if(scinner_duty_ofst!=DUTY_OFFSET_START) - mcSHOW_DBG_MSG(("PI= %d\n", s4PICnt_mod64)); -#endif - - if (k_type == DutyScan_Calibration_K_DQS || k_type == DutyScan_Calibration_K_WCK) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, s4PICnt_mod64, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); - } - else - if (k_type == DutyScan_Calibration_K_CLK) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), s4PICnt_mod64, SHU_R0_CA_CMD0_RG_ARPI_CLK); - } - else - if (k_type == DutyScan_Calibration_K_DQ) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, s4PICnt_mod64, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); - } - else - if (k_type == DutyScan_Calibration_K_DQM) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0) + ucdqs_i*DDRPHY_AO_B0_B1_OFFSET, s4PICnt_mod64, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); - } - - for(swap_idx=0; swap_idx<2; swap_idx++) - { - if (k_type == DutyScan_Calibration_K_CLK) - { - if (swap_idx==0) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_SWAP_Reg.u4Addr), 2, CA_SWAP_Reg.u4Fld); - } - else - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_SWAP_Reg.u4Addr), 3, CA_SWAP_Reg.u4Fld); - } - - vref_sel_value[swap_idx]= 0; - vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], CA_VrefSel_Reg.u4Fld); - } - else - { - if (swap_idx==0) - { - if (ucdqs_i==0) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 2, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0); - } - else - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_SWAP_Reg.u4Addr), 2, B1_SWAP_Reg.u4Fld); - } - } - else - { - if (ucdqs_i==0) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 3, B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0); - } - else - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_SWAP_Reg.u4Addr), 3, B1_SWAP_Reg.u4Fld); - } - } - - vref_sel_value[swap_idx]= 0; - if (ucdqs_i==0) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), vref_sel_value[swap_idx], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0); - } - else - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], B1_VrefSel_Reg.u4Fld); - } - } - - for(i=6; i>=0; i--) - { - if (k_type == DutyScan_Calibration_K_CLK) - { - vref_sel_value[swap_idx] |= (1<<i); - vIO32WriteFldAlign(DRAMC_REG_ADDR(CA_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], CA_VrefSel_Reg.u4Fld); - mcDELAY_US(1); - - cal_out_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(CA_CmpOut_Reg.u4Addr), CA_CmpOut_Reg.u4Fld); - - if (cal_out_value == 0) - { - vref_sel_value[swap_idx] &= ~(1<<i); - } - } - else - { - vref_sel_value[swap_idx] |= (1<<i); - if (ucdqs_i==0) - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), vref_sel_value[swap_idx], B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0); - } - else - { - vIO32WriteFldAlign(DRAMC_REG_ADDR(B1_VrefSel_Reg.u4Addr), vref_sel_value[swap_idx], B1_VrefSel_Reg.u4Fld); - } - mcDELAY_US(1); - - if (ucdqs_i==0) - { - cal_out_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYCAL_STATUS), MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0); - } - else - { - cal_out_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(B1_CmpOut_Reg.u4Addr), B1_CmpOut_Reg.u4Fld); - } - -#if DutyPrintAllLog - mcSHOW_DBG_MSG(("Fra i=%d vref_sel_value[swap_idx]=%x, cal_out=%d\n",i, vref_sel_value[swap_idx], cal_out_value)); -#endif - - if (cal_out_value == 0) - { - vref_sel_value[swap_idx] &= ~(1<<i); - } - } - } - } - - - for(swap_idx=0; swap_idx<2; swap_idx++) - { - //La_fite duty calculation - #if 0 //zj - if (vref_sel_value[swap_idx]<=31) - { - duty_value[swap_idx] = ((vref_sel_value[swap_idx]-21)*726)/10+5017; - } - else - { - duty_value[swap_idx] = ((vref_sel_value[swap_idx]-32)*475)/10+5786; - } - #endif - //A60868 duty calculcation - //duty = vref_sel * 0.624 + 15.366 - duty_value[swap_idx] = ((vref_sel_value[swap_idx]*624)+15366) / 10; - } -#if DutyPrintAllLog - mcSHOW_DBG_MSG(("\t[%d][%d] B%d : Vref_Sel=0x%x, Swap Vref_Sel=0x%x\n", scinner_duty_ofst, s4PICnt, ucdqs_i, vref_sel_value[0], vref_sel_value[1])); - mcSHOW_DBG_MSG(("\t[%d][%d] B%d : duty_value=%d, Swap duty_value=%d\n", scinner_duty_ofst, s4PICnt, ucdqs_i, duty_value[0], duty_value[1])); -#endif - - final_duty = 5000+((duty_value[0]-duty_value[1])/2); - - if (final_duty > (S32) ucperiod_duty_max) - { - ucperiod_duty_max = final_duty; - ucperiod_duty_max_clk_dly = s4PICnt; - } - if (final_duty < (S32) ucperiod_duty_min) - { - ucperiod_duty_min = final_duty; - ucperiod_duty_min_clk_dly = s4PICnt; - } - -#if DutyPrintAllLog - mcSHOW_DBG_MSG(("\t[%d][%d] B%d : Final_Duty=%d\n", scinner_duty_ofst, s4PICnt, ucdqs_i, final_duty)); -#endif - } - - - - ucperiod_duty_averige = (ucperiod_duty_max + ucperiod_duty_min)>>1; - -#if FT_DSIM_USED - if (ft_test_type==1) - { - if (scinner_duty_ofst==DUTY_OFFSET_START) - { - s4FT_Test_Final_duty[ucdqs_i][0] = ucperiod_duty_averige; - } - else - if (scinner_duty_ofst==0) - { - s4FT_Test_Final_duty[ucdqs_i][1] = ucperiod_duty_averige; - } - else - if (scinner_duty_ofst==DUTY_OFFSET_END) - { - s4FT_Test_Final_duty[ucdqs_i][2] = ucperiod_duty_averige; - } - } -#endif - - mcSHOW_DBG_MSG2((" [%d] ",scinner_duty_ofst)); - mcSHOW_DBG_MSG2(("\t%d%%",ucperiod_duty_max)); - /*TINFO="\tMAX Duty = %d%%(X100), CLK PI=%d\n",ucperiod_duty_max, ucperiod_duty_max_clk_dly */ - mcSHOW_DBG_MSG2(("\t%d%%",ucperiod_duty_min)); - /*TINFO="\tMIN Duty = %d%%(X100), CLK PI=%d\n",ucperiod_duty_min, ucperiod_duty_min_clk_dly */ - mcSHOW_DBG_MSG2(("\t%d%%", ucperiod_duty_averige)); - /*TINFO="\tAVG Duty = %d%%(X100)\n", ucperiod_duty_averige */ - mcSHOW_DBG_MSG2(("\t%d%%", (ucperiod_duty_averige-ClockDutyMiddleBound)*(ucperiod_duty_averige>=ClockDutyMiddleBound?1:-1))); - /*TINFO="\tAVG Duty = %d%%(X100)\n", ucperiod_duty_averige */ - mcSHOW_DBG_MSG2(("\t%d%%", (ucperiod_duty_max-ucperiod_duty_min))); - /*TINFO="\tAVG Duty = %d%%(X100)\n", ucperiod_duty_averige */ - - if ((ucperiod_duty_max-ucperiod_duty_min)<=20) - { - mcSHOW_ERR_MSG(("\n[DutyScan Cal] Warnning: Need confirm duty calibration (MaxDuty-MinDuty<=50) !!!\n")); - } - - if (scinner_duty_ofst == scinner_duty_ofst_start) - { - ucStart_period_duty_averige[ucdqs_i] = ucperiod_duty_averige; - } - - if (ucperiod_duty_averige >= ClockDutyMiddleBound) - { - /* record duty calibration result of every step */ - temp_value = ucperiod_duty_averige-ClockDutyMiddleBound+(ucperiod_duty_max-ucperiod_duty_min)*3/4; - } - else - { - /* record duty calibration result of every step */ - temp_value = ClockDutyMiddleBound-ucperiod_duty_averige+(ucperiod_duty_max-ucperiod_duty_min)*3/4; - } - - if (temp_value < record_ucmost_approach_50_percent) - { - record_ucmost_approach_50_percent = temp_value; - temp_first_pass = temp_last_pass = scinner_duty_ofst; - - record_duty_log.ucmost_approach_50_percent = temp_value; - record_duty_log.ucFinal_period_duty_averige = ucperiod_duty_averige; - record_duty_log.ucFinal_period_duty_max = ucperiod_duty_max; - record_duty_log.ucFinal_period_duty_min = ucperiod_duty_min; - record_duty_log.ucFinal_duty_max_clk_dly = ucperiod_duty_max_clk_dly; - record_duty_log.ucFinal_duty_min_clk_dly = ucperiod_duty_min_clk_dly; - } - else if (temp_value == record_ucmost_approach_50_percent) - { - temp_last_pass = scinner_duty_ofst; - } - - if (ucperiod_duty_averige >= ClockDutyMiddleBound) - { - if ((scinner_duty_ofst<=0 && (temp_value <= ucmost_approach_50_percent)) || - (scinner_duty_ofst>0 && (temp_value < ucmost_approach_50_percent))) - { - ucmost_approach_50_percent = temp_value; - - mcSHOW_DBG_MSG2(("\t ==> ucmost_approach_50_percent = %d%%(X100) !!!",ucmost_approach_50_percent)); - /*TINFO="!!! ucmost_approach_50_percent = %d%%(X100) !!!\n",ucmost_approach_50_percent */ - - early_break_count = 0; - } - else - { - early_break_count ++; - if (early_break_count>=2) - { - mcSHOW_DBG_MSG2(("\t ==> Early Break !!!\n")); - break; //early break; - } - } - } - else - { - if ((scinner_duty_ofst<=0 && (temp_value <= ucmost_approach_50_percent)) || - (scinner_duty_ofst>0 && (temp_value < ucmost_approach_50_percent))) - { - ucmost_approach_50_percent = temp_value; - - mcSHOW_DBG_MSG2(("\t ==> ucmost_approach_50_percent = %d%%(X100) !!!",ucmost_approach_50_percent)); - /*TINFO="!!! ucmost_approach_50_percent = %d%%(X100) !!!\n",ucmost_approach_50_percent */ - - early_break_count = 0; - } - else - { - early_break_count ++; - if (early_break_count>=2) - { - mcSHOW_DBG_MSG2(("\t ==> Early Break !!!\n")); - break; //early break; - } - } - } - - mcSHOW_DBG_MSG2(("\n")); - /*TINFO="\n" */ - } - - /* set this best pass to final result */ - scFinal_clk_delay_cell[ucdqs_i] = (temp_first_pass + temp_last_pass) / 2; /* best step is (first pass+last pass)/2 */ - ucFinal_period_duty_averige[ucdqs_i] = record_duty_log.ucFinal_period_duty_averige; - ucFinal_period_duty_max[ucdqs_i] = record_duty_log.ucFinal_period_duty_max; - ucFinal_period_duty_min[ucdqs_i] = record_duty_log.ucFinal_period_duty_min; - ucFinal_duty_max_clk_dly[ucdqs_i] = record_duty_log.ucFinal_duty_max_clk_dly; - ucFinal_duty_min_clk_dly[ucdqs_i] = record_duty_log.ucFinal_duty_min_clk_dly; - - mcSHOW_DBG_MSG4(("[%d] record_duty_log_ucmost_approach_50_percent=%d\n",scinner_duty_ofst, record_duty_log.ucmost_approach_50_percent)); - mcSHOW_DBG_MSG(("Find : first_pass = %d, last_pass = %d \n", temp_first_pass, temp_last_pass)); - mcSHOW_DBG_MSG(("Final : Best Pass = %d\n", scFinal_clk_delay_cell[ucdqs_i])); - } - - mcSHOW_DBG_MSG2(("====================================================\n")); - - for(ucdqs_i=0; ucdqs_i<ucdqs_i_count; ucdqs_i++) - { - //for SLT, use ERR_MSG to force print log - if (k_type == DutyScan_Calibration_K_CLK) - { - mcSHOW_DBG_MSG(("Final %s duty delay cell = %d\n", str_who_am_I, scFinal_clk_delay_cell[ucdqs_i])); - //mcDUMP_REG_MSG(("Final %s duty delay cell = %d\n", str_who_am_I, scFinal_clk_delay_cell[ucdqs_i])); - - /*TINFO="Final %s duty delay cell = %d\n", str_who_am_I, scFinal_clk_delay_cell[ucdqs_i] */ - } - else - { - mcSHOW_DBG_MSG(("Final %s %d duty delay cell = %d\n", str_who_am_I, ucdqs_i, scFinal_clk_delay_cell[ucdqs_i])); - //mcDUMP_REG_MSG(("Final %s %d duty delay cell = %d\n", str_who_am_I, ucdqs_i, scFinal_clk_delay_cell[ucdqs_i])); - - /*TINFO="Final %s %d duty delay cell = %d\n", str_who_am_I, ucdqs_i, scFinal_clk_delay_cell[ucdqs_i] */ - } - mcSHOW_DBG_MSG(("[%d] MAX Duty = %d%%(X100), PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_max[ucdqs_i], ucFinal_duty_max_clk_dly[ucdqs_i])); - /*TINFO="[%d] MAX Duty = %d%%(X100), DQS PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_max[ucdqs_i], ucFinal_duty_max_clk_dly[ucdqs_i] */ - mcSHOW_DBG_MSG(("[%d] MIN Duty = %d%%(X100), PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_min[ucdqs_i], ucFinal_duty_min_clk_dly[ucdqs_i])); - /*TINFO="[%d] MIN Duty = %d%%(X100), DQS PI = %d\n",scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_min[ucdqs_i], ucFinal_duty_min_clk_dly[ucdqs_i] */ - mcSHOW_DBG_MSG(("[%d] AVG Duty = %d%%(X100)\n", scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_averige[ucdqs_i])); - /*TINFO="[%d] AVG Duty = %d%%(X100)\n", scFinal_clk_delay_cell[ucdqs_i], ucFinal_period_duty_averige[ucdqs_i] */ - - // expend Delay code from +/-4 to +/-8 - if ((scFinal_clk_delay_cell[ucdqs_i]>8)||(scFinal_clk_delay_cell[ucdqs_i]<-8)) - { - mcSHOW_ERR_MSG(("[DutyScan Cal] Warnning: Need confirm Duty calibration (Duty Offset Unexpected) !!!\n")); - #if __ETT__ - if (p->channel==CHANNEL_B) - { - while(1); - } - #endif - } - // expect final duty avg will be larger the the first one - if ((ucFinal_period_duty_averige[ucdqs_i]-ucStart_period_duty_averige[ucdqs_i])<100) - { - mcSHOW_ERR_MSG(("\n[DutyScan Cal] Warnning: Need confirm duty calibration (duty offset not moving) !!!\n")); - #if __ETT__ - while(1); - #endif - } - - //Duty Pass/Fail Criteria - u4DutyDiff = ucFinal_period_duty_max[ucdqs_i]-ucFinal_period_duty_min[ucdqs_i]; - if ((((k_type == DutyScan_Calibration_K_CLK) || (k_type == DutyScan_Calibration_K_DQS)) && (u4DutyDiff < u4DutyDiff_Limit)) || - #if APPLY_DQDQM_DUTY_CALIBRATION - (((k_type == DutyScan_Calibration_K_DQ) || (k_type == DutyScan_Calibration_K_DQM)) && (u4DutyDiff < u4DutyDiff_Limit))) - #else - (((k_type == DutyScan_Calibration_K_DQ) || (k_type == DutyScan_Calibration_K_DQM)) && ((u4DutyDiff < u4DutyDiff_Limit) && (ucFinal_period_duty_averige[ucdqs_i] >= 4550 && ucFinal_period_duty_averige[ucdqs_i] <= 5450)))) - #endif - { - if (k_type == DutyScan_Calibration_K_CLK) - { - mcSHOW_DBG_MSG(("CH%d %s Duty spec in!! Max-Min= %d%%\n\n",p->channel, str_who_am_I, u4DutyDiff)); - /*TINFO="\nCH%d %s Duty spec in!! Max-Min= %d%%\n",p->channel, str_who_am_I, u4DutyDiff */ - } - else - { - mcSHOW_DBG_MSG(("CH%d %s %d Duty spec in!! Max-Min= %d%%\n\n",p->channel, str_who_am_I, ucdqs_i, u4DutyDiff)); - /*TINFO="\nCH%d %s %d Duty spec in!! Max-Min= %d%%\n",p->channel, str_who_am_I, ucdqs_i, u4DutyDiff */ - } - KResult = DRAM_OK; - } - else - { - if (k_type == DutyScan_Calibration_K_CLK) - { - mcSHOW_ERR_MSG(("CH%d %s Duty spec out!! Max-Min= %d%% >%d%%\n\n", p->channel, str_who_am_I, u4DutyDiff, u4DutyDiff_Limit)); - /*TINFO="\nCH%d %s Duty spec out!! Max-Min= %d%% >8%%\n", p->channel, str_who_am_I, u4DutyDiff */ - #if __ETT__ - if (p->channel==CHANNEL_B) - { - while(1); - } - #endif - } - else - { - mcSHOW_ERR_MSG(("CH%d %s %d Duty spec out!! Max-Min= %d%% >%d%%\n\n", p->channel, str_who_am_I, ucdqs_i, u4DutyDiff, u4DutyDiff_Limit)); - /*TINFO="\nCH%d %s %d Duty spec out!! Max-Min= %d%% >8%%\n", p->channel, str_who_am_I, ucdqs_i, u4DutyDiff */ - #if __ETT__ - //while(1); - #endif - } - } - } - -#if FT_DSIM_USED - if (ft_test_type==0) - { - FT_Duty_Compare_PassFail(p->channel, k_type, ucFinal_period_duty_max[0] , ucFinal_period_duty_min[0],ucFinal_period_duty_max[1] , ucFinal_period_duty_min[1]); - } - else - { - FT_Duty_Ofst_Diff_PassFail(p->channel, k_type, s4FT_Test_Final_duty[0][0], s4FT_Test_Final_duty[0][1], s4FT_Test_Final_duty[0][2], s4FT_Test_Final_duty[1][0], s4FT_Test_Final_duty[1][1], s4FT_Test_Final_duty[1][2]); - } - *GPIO_GPIO_DOUT0 |= 0x04000000; //PAD_PWM_0, // Lafi_te / round done -#else - for(ucdqs_i=0; ucdqs_i<ucdqs_i_count; ucdqs_i++) - { - u4DutyDiff = ucFinal_period_duty_max[ucdqs_i] - ucFinal_period_duty_min[ucdqs_i]; - -#if DQS_DUTY_SLT_CONDITION_TEST - if (k_type == DutyScan_Calibration_K_CLK || (k_type == DutyScan_Calibration_K_DQS)) - { - u4DQSDutyDiff_Rec[p->channel][ucdqs_i][u1GlobalTestCnt]=u4DutyDiff; - - u4DQSDutyDutyDly[p->channel][ucdqs_i] = scFinal_clk_delay_cell[ucdqs_i]; - - if(u4DutyDiff > u4DQSDutyDiff_Max[p->channel][ucdqs_i]) - u4DQSDutyDiff_Max[p->channel][ucdqs_i] = u4DutyDiff; - - if(u4DutyDiff < u4DQSDutyDiff_Min[p->channel][ucdqs_i]) - u4DQSDutyDiff_Min[p->channel][ucdqs_i] = u4DutyDiff; - - u4DQSDutyDiff_Avrg[p->channel][ucdqs_i] += u4DutyDiff; - } -#endif - } - -#endif - - if (k_type == DutyScan_Calibration_K_DQS) - { - // backup final values - gcFinal_K_DQS_delay_cell[0] = scFinal_clk_delay_cell[0]; - gcFinal_K_DQS_delay_cell[1] = scFinal_clk_delay_cell[1]; - - DQSDutyScan_SetDqsDelayCell(p, scFinal_clk_delay_cell); - -#ifdef FOR_HQA_TEST_USED - gFinalDQSDuty[p->channel][0] = scFinal_clk_delay_cell[0]; - gFinalDQSDuty[p->channel][1] = scFinal_clk_delay_cell[1]; - gFinalDQSDutyMinMax[p->channel][0][0] = ucFinal_period_duty_min[0]; - gFinalDQSDutyMinMax[p->channel][0][1] = ucFinal_period_duty_max[0]; - gFinalDQSDutyMinMax[p->channel][1][0] = ucFinal_period_duty_min[1]; - gFinalDQSDutyMinMax[p->channel][1][1] = ucFinal_period_duty_max[1]; -#endif - } -#if __LP5_COMBO__ - if (k_type == DutyScan_Calibration_K_WCK) - { - // backup final values - gcFinal_K_WCK_delay_cell[0] = scFinal_clk_delay_cell[0]; - gcFinal_K_WCK_delay_cell[1] = scFinal_clk_delay_cell[1]; - - WCKDutyScan_SetWCKDelayCell(p, scFinal_clk_delay_cell); - -#if 0 //zj #ifdef FOR_HQA_TEST_USED - gFinalDQSDuty[p->channel][0] = scFinal_clk_delay_cell[0]; - gFinalDQSDuty[p->channel][1] = scFinal_clk_delay_cell[1]; - gFinalDQSDutyMinMax[p->channel][0][0] = ucFinal_period_duty_min[0]; - gFinalDQSDutyMinMax[p->channel][0][1] = ucFinal_period_duty_max[0]; - gFinalDQSDutyMinMax[p->channel][1][0] = ucFinal_period_duty_min[1]; - gFinalDQSDutyMinMax[p->channel][1][1] = ucFinal_period_duty_max[1]; -#endif - } -#endif - if (k_type == DutyScan_Calibration_K_CLK) - { - DramcClockDutySetClkDelayCell(p, scFinal_clk_delay_cell); - - // backup final values - gcFinal_K_CLK_delay_cell[0] = scFinal_clk_delay_cell[0]; - gcFinal_K_CLK_delay_cell[1] = scFinal_clk_delay_cell[1]; - -#ifdef FOR_HQA_TEST_USED - gFinalClkDuty[p->channel] = scFinal_clk_delay_cell[0]; - gFinalClkDutyMinMax[p->channel][0] = ucFinal_period_duty_min[0]; - gFinalClkDutyMinMax[p->channel][1] = ucFinal_period_duty_max[0]; -#endif - } - -#if APPLY_DQDQM_DUTY_CALIBRATION - if (k_type == DutyScan_Calibration_K_DQ) - { - // backup final values - gcFinal_K_DQ_delay_cell[0] = scFinal_clk_delay_cell[0]; - gcFinal_K_DQ_delay_cell[1] = scFinal_clk_delay_cell[1]; - - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, scFinal_clk_delay_cell, DutyScan_Calibration_K_DQ); - } - - if (k_type == DutyScan_Calibration_K_DQM) - { - // backup final values - gcFinal_K_DQM_delay_cell[0] = scFinal_clk_delay_cell[0]; - gcFinal_K_DQM_delay_cell[1] = scFinal_clk_delay_cell[1]; - - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, scFinal_clk_delay_cell, DutyScan_Calibration_K_DQM); - } -#endif - - DramPhyReset(p); - - mcSHOW_DBG_MSG3(("[DutyScan_Calibration_Flow] ====Done====\n")); - /*TINFO="[DutyScan_Calibration_Flow] ====Done====\n" */ - - return KResult; -} -#endif void DramcNewDutyCalibration(DRAMC_CTX_T *p) { U8 u1backup_rank; - //U8 u1OfsB0=0, u1OfsB1=0, u1OfsCA=0; BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - - //OE releated RG U32 backup_DDRPHY_REG_B0_DQ2=0, backup_DDRPHY_REG_B1_DQ2=0, backup_DDRPHY_REG_CA_CMD2=0; U32 backup_DDRPHY_REG_SHU_B0_DQ13=0, backup_DDRPHY_REG_SHU_B1_DQ13=0, backup_DDRPHY_REG_SHU_CA_CMD13=0; @@ -14737,46 +13019,6 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) U32 u4Variance; #endif - //DRAM_STATUS_T u2FailStatusByCh={0}; - - //backup register value -#if FT_DSIM_USED==0 -#if 0 - U32 u4RegBackupAddress[] = - { - DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), - DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), - DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3), - - DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), - DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), - - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2), - - DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), - DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), - - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), - - DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), - DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD5), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), - - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_LPBK_CTRL), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_LPBK_CTRL), - DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_LPBK_CTRL), - }; -#endif -#endif u1backup_rank = u1GetRank(p); vSetRank(p, RANK_0); @@ -14829,38 +13071,6 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) return; } #endif - //clear global variables to 0 delay - - - - - - //Clk free run {Move to Init_DRAM() and only call once} - //zj EnableDramcPhyDCM(p, 0); - - //Fix rank to rank0 - - //backup register value - - /* Set OE/ODT loopback MUX to DATA at LPBK path from WL @ 20200529 - 00 tie low - 01 DATA - 10 OE - 11 ODT - */ - - - - - //copy DQ RG to DQM - - - //restore to orignal value - - - - - } OECKCKE_Control(p, ENABLE); diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c index f3fc126cc8..d0a7f2073e 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c @@ -819,69 +819,6 @@ void DramcSWTxTracking(DRAMC_CTX_T *p) } #endif - -#if ENABLE_RX_TRACKING -void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p) -{ - U8 ii, backup_rank; - U32 u4WbrBackup = GetDramcBroadcast(); - - backup_rank = u1GetRank(p); - DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - - //Enable RX_FIFO macro DIV4 clock CG - vIO32WriteFldAlign((DDRPHY_REG_MISC_CG_CTRL1), 0xffffffff, MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL); - - for (ii = RANK_0; ii < p->support_rank_num; ii++) - { - vSetRank(p, ii); - - //DVS mode to RG mode - vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0); - vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1); - - //Turn off F_DLY individual calibration option (CTO_AGENT_RDAT cannot separate DR/DF error) - //tracking rising and update rising/falling together - vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x1, RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0); - vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x1, RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1); - - //DQ/DQM/DQS DLY MAX/MIN value under Tracking mode - /* DQS, DQ, DQM (DQ, DQM are tied together now) -> controlled using DQM MAX_MIN */ - - /* Byte 0 */ - vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS3), P_Fld(0x0, RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0) | P_Fld(0xff, RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0)); - vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS4), P_Fld(0x0, RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0) | P_Fld(0x1ff, RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0)); - - /* Byte 1 */ - vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS3), P_Fld(0x0, RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1) | P_Fld(0xff, RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1)); - vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS4), P_Fld(0x0, RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1) | P_Fld(0x1ff, RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1)); - - //Threshold for LEAD/LAG filter - vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS1), P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD) | P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG)); - vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS1), P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD) | P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG)); - - //DQ/DQS Rx DLY adjustment for tracking mode - vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0) | P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0)); - vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1) | P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1)); - - vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0) | P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0)); - vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1) | P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1)); - - } - vSetRank(p, backup_rank); - - //Tracking lead/lag counter >> Rx DLY adjustment fixed to 1 - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x0, B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x0, B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1); - - //DQIEN pre-state option to block update for RX ASVA 1-2 - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1); - - DramcBroadcastOnOff(u4WbrBackup); -} -#endif - #if SIMULATION_RX_DVS || ENABLE_RX_TRACKING void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) { @@ -974,76 +911,6 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) } #endif -#if ENABLE_RX_TRACKING -void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p) -{ - BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - DRAM_CHANNEL_T channel_bak = p->channel; - U8 ii, backup_rank; - U32 u4WbrBackup = GetDramcBroadcast(); - DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - - vSetPHY2ChannelMapping(p, CHANNEL_A); - backup_rank = u1GetRank(p); - - //Rx DLY tracking setting (Static) - vIO32WriteFldMulti((DDRPHY_REG_B0_RXDVS0), - P_Fld(1, B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0) | - P_Fld(0, B0_RXDVS0_R_RX_RANKINCTL_B0) | - P_Fld(1, B0_RXDVS0_R_RX_RANKINSEL_B0)); - - vIO32WriteFldMulti((DDRPHY_REG_B1_RXDVS0), - P_Fld(1, B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1) | - P_Fld(0, B1_RXDVS0_R_RX_RANKINCTL_B1) | - P_Fld(1, B1_RXDVS0_R_RX_RANKINSEL_B1)); - - vIO32WriteFldMulti((DDRPHY_REG_B0_DQ9), P_Fld(0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0) | P_Fld(0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0)); - vIO32WriteFldMulti((DDRPHY_REG_B1_DQ9), P_Fld(!isLP4_DSC, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1)); - vIO32WriteFldMulti((DDRPHY_REG_CA_CMD9), P_Fld(isLP4_DSC, CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_VALID_LAT_CA)); - - //Rx DLY tracking function CG enable - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1); - - //Rx DLY tracking lead/lag counter enable - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1); - -#ifdef DPM_CONTROL_AFTERK - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 3, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN); -#endif - - //fra 0: origin mode (use LEAD/LAG rising tracking) 1: new mode (use LEAD/LAG rising/fall tracking, more faster) - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS1), 1, B0_RXDVS1_F_LEADLAG_TRACK_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS1), 1, B1_RXDVS1_F_LEADLAG_TRACK_B1); - - for (ii = RANK_0; ii < p->support_rank_num; ii++) - { - vSetRank(p, ii); - - //Rx DLY tracking update enable (HW mode) - vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), - P_Fld(2, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0) | - P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0) | - P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)); - - vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), - P_Fld(2, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1) | - P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1) | - P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)); - } - vSetRank(p, backup_rank); - - //Rx DLY tracking: "TRACK_CLR" let rx_dly reload the correct dly setting - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 1, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 1, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1); - vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0); - vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1); - - DramcBroadcastOnOff(u4WbrBackup); -} -#endif - ///TODO: wait for porting +++ #if __A60868_TO_BE_PORTING__ #if RX_DLY_TRACK_ONLY_FOR_DEBUG @@ -1201,111 +1068,6 @@ void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn) #endif // __A60868_TO_BE_PORTING__ -#ifdef DUMMY_READ_FOR_TRACKING -void DramcDummyReadAddressSetting(DRAMC_CTX_T *p) -{ - U8 backup_channel = p->channel, backup_rank = p->rank; - U8 channelIdx, rankIdx; - dram_addr_t dram_addr; - -// for (channelIdx = CHANNEL_A; channelIdx < CHANNEL_NUM; channelIdx++) - for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++) - { - vSetPHY2ChannelMapping(p, channelIdx); - for (rankIdx = RANK_0; rankIdx < RANK_MAX; rankIdx++) - { - vSetRank(p, rankIdx); - - dram_addr.ch = channelIdx; - dram_addr.rk = rankIdx; - - get_dummy_read_addr(&dram_addr); - mcSHOW_DBG_MSG3(("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n", - channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col)); - - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR2), P_Fld(dram_addr.row, RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR) - | P_Fld(dram_addr.bk, RK_DUMMY_RD_ADR2_DMY_RD_BK)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), P_Fld(dram_addr.col, RK_DUMMY_RD_ADR_DMY_RD_COL_ADR) - | P_Fld(0, RK_DUMMY_RD_ADR_DMY_RD_LEN)); - } - } - - vSetPHY2ChannelMapping(p, backup_channel); - vSetRank(p, backup_rank); - -} - -void DramcDummyReadForTrackingEnable(DRAMC_CTX_T *p) -{ - U8 backup_rank = p->rank; - U8 rankIdx; - - /* Dummy read pattern (Better efficiency during rx dly tracking) DE: YH Tsai, Wei-jen */ - for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++) - { - vSetRank(p, rankIdx); - - vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA0, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0 - vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA1, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1 - vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA2, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2 - vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA3, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3 - } - vSetRank(p, backup_rank); - - vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent - -#if 0//__ETT__ - /* indicate ROW_ADR = 2 for Dummy Write pattern address, in order to avoid pattern will be overwrited by MEM_TEST(test range 0xffff) - * Pattern locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */ - dram_addr_t dram_addr; - - dram_addr.ch = 0; - dram_addr.rk = 0; - get_dummy_read_addr(&dram_addr); - - vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR) - | P_Fld(dram_addr.col, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR) - | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN)); - vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_BK), dram_addr.bk, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK); - - dram_addr.rk = 1; - get_dummy_read_addr(&dram_addr); - - vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR) - | P_Fld(dram_addr.col, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR) - | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN)); - vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_BK), dram_addr.bk, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK); - - /* trigger dummy write pattern 0xAAAA5555 */ - vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG); - vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG); -#else - DramcDummyReadAddressSetting(p); -#endif - - /* DUMMY_RD_RX_TRACK = 1: - * During "RX input delay tracking enable" and "DUMMY_RD_EN=1" Dummy read will force a read command to a certain rank, - * ignoring whether or not EMI has executed a read command to that certain rank in the past 4us. - */ - - if (p->frequency >= 1600) - { -#ifdef DPM_CONTROL_AFTERK - vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, - P_Fld(3, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL) | P_Fld(3, LPIF_LOW_POWER_CFG_1_DMYRD_EN)); -#endif - vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DMY_RD_RX_TRACK) | P_Fld(1, DUMMY_RD_DUMMY_RD_EN)); - mcSHOW_DBG_MSG2(("High Freq DUMMY_READ_FOR_TRACKING: ON\n")); - } - else - { - mcSHOW_DBG_MSG2(("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n")); - } - - return; -} -#endif - #ifdef IMPEDANCE_HW_SAVING void DramcImpedanceHWSaving(DRAMC_CTX_T *p) { |