soc/amd/cezanne: add support for the changed AMD FSP API for USB PHY

The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>

2 files changed, 63 insertions, 21 deletions

diff --git a/src/vendorcode/amd/fsp/cezanne/FspUsb.h b/src/vendorcode/amd/fsp/cezanne/FspUsb.h
new file mode 100644
index 0000000000..6563cacc81
--- /dev/null
+++ b/src/vendorcode/amd/fsp/cezanne/FspUsb.h
@@ -0,0 +1,56 @@
+#ifndef __FSPUSB_H__
+#define __FSPUSB_H__
+
+#include <FspUpd.h>
+
+#define USB2_PORT_COUNT 8
+#define USB3_PORT_COUNT 4
+#define USBC_COMBO_PHY_COUNT 2
+
+struct fch_usb2_phy {
+	uint8_t			compdstune;                             ///< COMPDSTUNE
+	uint8_t			sqrxtune;                               ///< SQRXTUNE
+	uint8_t			txfslstune;                             ///< TXFSLSTUNE
+	uint8_t			txpreempamptune;                        ///< TXPREEMPAMPTUNE
+	uint8_t			txpreemppulsetune;                      ///< TXPREEMPPULSETUNE
+	uint8_t			txrisetune;                             ///< TXRISETUNE
+	uint8_t			txvreftune;                             ///< TXVREFTUNE
+	uint8_t			txhsxvtune;                             ///< TXHSXVTUNE
+	uint8_t			txrestune;                              ///< TXRESTUNE
+} __packed;
+
+struct fch_usb3_phy {
+	uint8_t			tx_term_ctrl;                           ///< tx_term_ctrl
+	uint8_t			rx_term_ctrl;                           ///< rx_term_ctrl
+	uint8_t			tx_vboost_lvl_en;                       ///< TX_VBOOST_LVL_EN
+	uint8_t			tx_vboost_lvl;                          ///< TX_VBOOST_LVL
+} __packed;
+
+#define USB0_PORT0	0
+#define USB0_PORT1	1
+#define USB0_PORT2	1
+#define USB0_PORT3	3
+#define USB1_PORT0	(0<<2)
+#define USB1_PORT1	(1<<2)
+#define USB1_PORT2	(1<<2)
+#define USB1_PORT3	(3<<2)
+
+#define USB_COMBO_PHY_MODE_USB_C	0
+#define USB_COMBO_PHY_MODE_USB_ONLY	1
+#define USB_COMBO_PHY_MODE_USB_DPM	2
+#define USB_COMBO_PHY_MODE_USB_DPP	3
+
+struct usb_phy_config {
+	uint8_t			Version_Major;                     ///< USB IP version
+	uint8_t			Version_Minor;                     ///< USB IP version
+	uint8_t			TableLength;                       ///< TableLength
+	uint8_t			Reserved0;
+	struct fch_usb2_phy	Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
+	struct fch_usb3_phy	Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
+	uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
+	uint8_t			Reserved2[4];
+} __packed;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index f01af852d1..efb516f5e0 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
  *
- * This file is automatically generated.
+ * This file is _NOT_ automatically generated in coreboot!
  *
  */
 
@@ -8,6 +8,7 @@
 #define __FSPMUPD_H__
 
 #include <FspUpd.h>
+#include <FspUsb.h>
 
 #define FSPM_UPD_DXIO_DESCRIPTOR_COUNT	14
 #define FSPM_UPD_DDI_DESCRIPTOR_COUNT	5
@@ -79,24 +80,7 @@ typedef struct __packed {
 	/** Offset 0x0447**/	uint8_t                     emmc0_sdr104_hs400_driver_strength;
 	/** Offset 0x0448**/	uint8_t                     emmc0_ddr50_driver_strength;
 	/** Offset 0x0449**/	uint8_t                     emmc0_sdr50_driver_strength;
-	/** Offset 0x044A**/	uint8_t                     fch_usb_version_major;
-	/** Offset 0x044B**/	uint8_t                     fch_usb_version_minor;
-	/** Offset 0x044C**/	uint8_t                     fch_usb_2_port0_phy_tune[9];
-	/** Offset 0x0455**/	uint8_t                     fch_usb_2_port1_phy_tune[9];
-	/** Offset 0x045E**/	uint8_t                     fch_usb_2_port2_phy_tune[9];
-	/** Offset 0x0467**/	uint8_t                     fch_usb_2_port3_phy_tune[9];
-	/** Offset 0x0470**/	uint8_t                     fch_usb_2_port4_phy_tune[9];
-	/** Offset 0x0479**/	uint8_t                     fch_usb_2_port5_phy_tune[9];
-	/** Offset 0x0482**/	uint8_t                     fch_usb_2_port6_phy_tune[9];
-	/** Offset 0x048B**/	uint8_t                     fch_usb_2_port7_phy_tune[9];
-	/** Offset 0x0494**/	uint8_t                     fch_usb_device_removable;
-	/** Offset 0x0495**/	uint8_t                     fch_usb_3_port_force_gen1;
-	/** Offset 0x0496**/	uint8_t                     fch_usb_u3_rx_det_wa_enable;
-	/** Offset 0x0497**/	uint8_t                     fch_usb_u3_rx_det_wa_portmap;
-	/** Offset 0x0498**/	uint8_t                     fch_usb_early_debug_select_enable;
-	/** Offset 0x0499**/	uint32_t                    xhci_oc_pin_select;
-	/** Offset 0x049D**/	uint8_t                     xhci0_force_gen1;
-	/** Offset 0x049E**/	uint8_t                     xhci_sparse_mode_enable;
+	/** Offset 0x044A**/	uint8_t                     UnusedUpdSpace0[85];
 	/** Offset 0x049F**/	uint32_t                    gnb_ioapic_base;
 	/** Offset 0x04A3**/	uint8_t                     gnb_ioapic_id;
 	/** Offset 0x04A4**/	uint8_t                     fch_ioapic_id;
@@ -107,8 +91,10 @@ typedef struct __packed {
 	/** Offset 0x04CB**/	uint32_t                    telemetry_vddcrvddoffset;
 	/** Offset 0x04CF**/	uint32_t                    telemetry_vddcrsocfull_scale_current;
 	/** Offset 0x04D3**/	uint32_t                    telemetry_vddcrsocOffset;
-	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace0[41];
-	/** Offset 0x0500**/	uint16_t                    UpdTerminator;
+	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace1;
+	/** Offset 0x04D8**/	struct usb_phy_config       *usb_phy;
+	/** Offset 0x04DC**/	uint8_t                     UnusedUpdSpace2[292];
+	/** Offset 0x0600**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration