diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2016-10-15 09:20:43 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-07 20:36:13 +0100 |
| commit | a04006513008ef72a863bc0eb04e6d4f729ca8ab (patch) | |
| tree | 7b1ac3072d8c478954b5f7550ff09c6469e7727f /src/vendorcode | |
| parent | 9ef6e52353dbbcfac727e0207dbbcc07dfb75d47 (diff) | |
vendorcode/amd: Copy 00670F00 files from PI package
Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions. Change the license text and fix
up misc. whitespace.
This will facilitate the review of binaryPI changes in the
vendorcode directory.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)
Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode')
31 files changed, 1177 insertions, 185 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h index 5f0e3f9e82..311e876276 100644 --- a/src/vendorcode/amd/pi/00670F00/AGESA.h +++ b/src/vendorcode/amd/pi/00670F00/AGESA.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 314282 $ @e \$Date: 2015-03-08 04:44:40 -0500 (Sun, 08 Mar 2015) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -610,8 +610,8 @@ typedef struct { * @li @b Bit31 - last descriptor in topology */ IN UINT32 SocketId; ///< Socket Id - IN const PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - IN const PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN VOID *Reserved; ///< Reserved for future use } PCIe_COMPLEX_DESCRIPTOR; @@ -759,6 +759,7 @@ typedef enum { #define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02 ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training #define EXT_DISPLAY_PATH_CAPS_HDMI20_PI3EQX1204 0x04 ///< BIT[2] HDMI 2.0 connector #define EXT_DISPLAY_PATH_CAPS_HDMI20_TISN65DP159RSBT 0x08 ///< BIT[3] HDMI 2.0 connector +#define EXT_DISPLAY_PATH_CAPS_HDMI20_PARADE_PS175 0x0C ///< BIT[3:2] DP -> HDMI recoverter chip /// DP receiver definitions with fixed voltage swing typedef enum { @@ -828,7 +829,7 @@ mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mF {mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \ {mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}} #define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ -{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0} +{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}, 0, 0} #define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \ {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0} #define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \ @@ -984,6 +985,22 @@ typedef struct { IN UINT8 ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} IN UINT8 ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM} IN UINT64 ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 DP0ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} + IN UINT8 DP0ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_NUM} + IN UINT64 DP0ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 DP1ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} + IN UINT8 DP1ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_NUM} + IN UINT64 DP1ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 DP2ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} + IN UINT8 DP2ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_NUM} + IN UINT64 DP2ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 DP0ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6G_REG_NUM} + IN UINT64 DP0ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6Ghz_REG_INFO} + IN UINT8 DP1ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6G_REG_NUM} + IN UINT64 DP1ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6Ghz_REG_INFO} + IN UINT8 DP2ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6G_REG_NUM} + IN UINT64 DP2ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6Ghz_REG_INFO} + } GNB_ENV_CONFIGURATION; /// Configuration settings for GNB. @@ -1002,7 +1019,7 @@ typedef struct { /// GNB configuration info typedef struct { - IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code @@ -1243,7 +1260,8 @@ typedef enum { /// UMA Version typedef enum { UMA_LEGACY = 0, ///< UMA Legacy Version - UMA_NON_LEGACY = 1 ///< UMA Non Legacy Version + UMA_NON_LEGACY = 1, ///< UMA Non Legacy Version + UMA_HSFB = 2 ///< UMA HSFB Version } UMA_VERSION; /// UMA Mode @@ -1268,6 +1286,14 @@ typedef enum { PMU_TRAIN_AUTO = 3 ///< Auto - PMU Training depend on configuration } PMU_TRAIN_MODE; +/// BankSwapOnly Mode +typedef enum { + BANK_SWAP_ONLY_DISABLED = 0, ///< Disable Bank Swap Only + BANK_SWAP_ONLY_ENABLED = 1, ///< Enable Bank Swap Only + BANK_SWAP_ONLY_AUTO = 2 ///< Auto - BankSwapOnly depending on family specific configuration +} BANK_SWAP_ONLY_MODE; + + /// The possible DRAM prefetch mode settings. typedef enum { DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. @@ -1379,7 +1405,7 @@ typedef struct _SPD_DEF_STRUCT { IN UINT8 PageAddress; ///< Indicates the 256 Byte EE Page the data belongs to ///< 0 = Lower Page ///< 1 = Upper Page (DDR4 Only) - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[512]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT; //----------------------------------------------------------------------------- @@ -1646,6 +1672,8 @@ typedef struct _CH_TIMING_STRUCT { OUT UINT16 MaxRdLat3; ///< Max Read Latency 3 OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed + OUT UINT8 RdOdtOnDuration; ///< RdOdtOnDuration + OUT UINT8 WrOdtOnDuration; ///< WrOdtOnDuration } CH_TIMING_STRUCT; /// @@ -2304,7 +2332,7 @@ typedef union { #define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training #define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" #define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data -#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK +#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK" #define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify #define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported #define MEM_ERROR_VDDPVDDR_UNSUPPORTED 0x04032500ul ///< VDDP/VDDR value indicated by the platform BIOS is not supported @@ -3035,12 +3063,29 @@ typedef struct { IN UINT8 CfgExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} IN UINT8 CfgExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM} IN UINT64 CfgExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 CfgDP0ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} + IN UINT8 CfgDP0ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_NUM} + IN UINT64 CfgDP0ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 CfgDP1ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} + IN UINT8 CfgDP1ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_NUM} + IN UINT64 CfgDP1ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 CfgDP2ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} + IN UINT8 CfgDP2ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_NUM} + IN UINT64 CfgDP2ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_INFO} + IN UINT8 CfgDP0ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6G_REG_NUM} + IN UINT64 CfgDP0ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6Ghz_REG_INFO} + IN UINT8 CfgDP1ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6G_REG_NUM} + IN UINT64 CfgDP1ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6Ghz_REG_INFO} + IN UINT8 CfgDP2ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6G_REG_NUM} + IN UINT64 CfgDP2ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6Ghz_REG_INFO} IN UINT32 CfgThermCtlLimit; ///< @BldCfgItem{BLDCFG_THERMCTL_LIMIT} - IN UINT32 CfgCodecVerbTable; ///< @BldCfgItem{BLDCFG_CODEC_VERB_TABLE} + IN UINT64 CfgCodecVerbTable; ///< @BldCfgItem{BLDCFG_CODEC_VERB_TABLE} IN UINT32 CfgGnbAzSsid; ///< @BldCfgItem{BLDCFG_GNB_AZ_SSID} IN UINT16 CfgCustomVddioVoltage; ///< Custom VDDIO voltage ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE} IN BOOLEAN CfgAcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING} + IN BOOLEAN CfgSmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING} + IN BOOLEAN CfgSmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR} IN BOOLEAN Reserved; ///< reserved... } BUILD_OPT_CFG; @@ -3123,6 +3168,8 @@ typedef struct _PLATFORM_CONFIGURATION { IN UINT32 GnbAzI2sBusSelect; ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_SELECT} IN UINT32 GnbAzI2sBusPinConfig; ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_PIN_CONFIG} IN BOOLEAN AcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING} + IN BOOLEAN SmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING} + IN BOOLEAN SmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR} } PLATFORM_CONFIGURATION; @@ -3316,7 +3363,7 @@ typedef struct { OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. OUT CHAR8 SerialNumber[9]; ///< Serial Number. - OUT CHAR8 PartNumber[19]; ///< Part Number. + OUT CHAR8 PartNumber[21]; ///< Part Number. OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. OUT UINT32 ExtSize; ///< Extended Size. OUT UINT16 ConfigSpeed; ///< Configured memory clock speed @@ -3341,7 +3388,7 @@ typedef struct { OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. OUT UINT8 SerialNumber[4]; ///< Serial Number. - OUT UINT8 PartNumber[18]; ///< Part Number. + OUT UINT8 PartNumber[21]; ///< Part Number. OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. OUT UINT32 ExtSize; ///< Extended Size. OUT UINT16 ConfigSpeed; ///< Configured memory clock speed diff --git a/src/vendorcode/amd/pi/00670F00/AMD.h b/src/vendorcode/amd/pi/00670F00/AMD.h index aa68204e8d..a111ceebae 100644 --- a/src/vendorcode/amd/pi/00670F00/AMD.h +++ b/src/vendorcode/amd/pi/00670F00/AMD.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -44,12 +44,8 @@ #ifndef _AMD_H_ #define _AMD_H_ -#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8) -#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h)) - #define AGESA_REVISION "Arch2008" -#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00} +#define AGESA_ID "AGESA" // // @@ -57,8 +53,7 @@ // // #define LAST_ENTRY 0xFFFFFFFFul -#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') -#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D') +#define IMAGE_SIGNATURE 'DMA$' #define IOCF8 0xCF8 #define IOCFC 0xCFC @@ -129,38 +124,27 @@ typedef enum ACCESS_WIDTH { /// AGESA struct name typedef enum { // AGESA BASIC FUNCTIONS - AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle - AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle - AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle - AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle - AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle - AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle - AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle - AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle - AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle - AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle - AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle - AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle - AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle - AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle - AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle - AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle - AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle - AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle - AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle - // Add - AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, - AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, - FCH_INIT_RESET = 0x00040000, - FCH_INIT_ENV = 0x00041000, - FCH_INIT_MID = 0x00042000, - FCH_INIT_LATE = 0x00043000, - FCH_INIT_S3_EARLY_RESTORE = 0x00044000, - FCH_INIT_S3_LATE_RESTORE = 0x00045000, - AMD_SET_VALUE = 0x00081000, - AMD_GET_VALUE = 0x00082000 + AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle + AMD_CREATE_STRUCT, ///< AmdCreateStruct handle + AMD_INIT_EARLY, ///< AmdInitEarly entry point handle + AMD_INIT_ENV, ///< AmdInitEnv entry point handle + AMD_INIT_LATE, ///< AmdInitLate entry point handle + AMD_INIT_MID, ///< AmdInitMid entry point handle + AMD_INIT_POST, ///< AmdInitPost entry point handle + AMD_INIT_RESET, ///< AmdInitReset entry point handle + AMD_INIT_RESUME, ///< AmdInitResume entry point handle + AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle + AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle + AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle + AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle + AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle + AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle + AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle + AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ @@ -175,9 +159,9 @@ typedef enum { /// The standard header for all AGESA services. /// For internal AGESA naming conventions, see @ref amdconfigparamname . typedef struct { - IN VOID * ImageBasePtr; ///< The AGESA Image base address. + IN UINT32 ImageBasePtr; ///< The AGESA Image base address. IN UINT32 Func; ///< The service desired - IN VOID * AltImageBasePtr; ///< Alternate Image location + IN UINT32 AltImageBasePtr; ///< Alternate Image location IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA IN UINT8 HeapStatus; ///< For heap status from boot time slide. IN UINT64 HeapBasePtr; ///< Location of the heap diff --git a/src/vendorcode/amd/pi/00670F00/Dispatcher.h b/src/vendorcode/amd/pi/00670F00/Dispatcher.h index 777f05cd9e..7ec23607ec 100644 --- a/src/vendorcode/amd/pi/00670F00/Dispatcher.h +++ b/src/vendorcode/amd/pi/00670F00/Dispatcher.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Legacy - * @e \$Revision: 281175 $ @e \$Date: 2013-12-18 15:53:00 +0800 (Wed, 18 Dec 2013) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/Filecode.h b/src/vendorcode/amd/pi/00670F00/Include/Filecode.h index 0e01812626..74e60f7d0b 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Filecode.h @@ -12,11 +12,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -129,7 +129,8 @@ #define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101) #define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102) -#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZ_FILECODE (0xA202) +#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZD_FILECODE (0xA201) +#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZM_FILECODE (0xA202) #define PROC_GNB_MODULES_GNBINITCZ_GFXENVINITCZ_FILECODE (0xA203) #define PROC_GNB_MODULES_GNBINITCZ_GFXGMCINITCZ_FILECODE (0xA204) #define PROC_GNB_MODULES_GNBINITCZ_GFXINTEGRATEDINFOTABLECZ_FILECODE (0xA205) @@ -159,6 +160,35 @@ #define PROC_GNB_MODULES_GNBINITCZ_GNBPSPCZ_FILECODE (0xA21E) #define PROC_GNB_MODULES_GNBINITCZ_GNBSMUINITCZ_FILECODE (0xA21F) +#define PROC_GNB_MODULES_GNBINITST_ALIBST_FILECODE (0xA300) +#define PROC_GNB_MODULES_GNBINITST_GFXENVINITST_FILECODE (0xA301) +#define PROC_GNB_MODULES_GNBINITST_GFXGMCINITST_FILECODE (0xA302) +#define PROC_GNB_MODULES_GNBINITST_GFXINTEGRATEDINFOTABLEST_FILECODE (0xA303) +#define PROC_GNB_MODULES_GNBINITST_GFXLIBST_FILECODE (0xA304) +#define PROC_GNB_MODULES_GNBINITST_GFXMIDINITST_FILECODE (0xA305) +#define PROC_GNB_MODULES_GNBINITST_GFXPOSTINITST_FILECODE (0xA306) +#define PROC_GNB_MODULES_GNBINITST_GNBEARLYINITST_FILECODE (0xA307) +#define PROC_GNB_MODULES_GNBINITST_GNBENVINITST_FILECODE (0xA308) +#define PROC_GNB_MODULES_GNBINITST_GNBFUSETABLEST_FILECODE (0xA309) +#define PROC_GNB_MODULES_GNBINITST_GNBIOMMUIVRSST_FILECODE (0xA30A) +#define PROC_GNB_MODULES_GNBINITST_GNBMIDINITST_FILECODE (0xA30B) +#define PROC_GNB_MODULES_GNBINITST_GNBPOSTINITST_FILECODE (0xA30C) +#define PROC_GNB_MODULES_GNBINITST_GNBREGISTERACCST_FILECODE (0xA30D) +#define PROC_GNB_MODULES_GNBINITST_GNBURATOKENMAPST_FILECODE (0xA30E) +#define PROC_GNB_MODULES_GNBINITST_PCIECOMPLEXDATAST_FILECODE (0xA30F) +#define PROC_GNB_MODULES_GNBINITST_PCIECONFIGST_FILECODE (0xA310) +#define PROC_GNB_MODULES_GNBINITST_PCIEEARLYINITST_FILECODE (0xA311) +#define PROC_GNB_MODULES_GNBINITST_PCIEENVINITST_FILECODE (0xA312) +#define PROC_GNB_MODULES_GNBINITST_PCIELIBST_FILECODE (0xA313) +#define PROC_GNB_MODULES_GNBINITST_PCIEMIDINITST_FILECODE (0xA314) +#define PROC_GNB_MODULES_GNBINITST_PCIEPOSTINITST_FILECODE (0xA315) +#define PROC_GNB_MODULES_GNBINITST_PCIEPOWERGATEST_FILECODE (0xA316) +#define PROC_GNB_MODULES_GNBINITST_GNBURAST_FILECODE (0xA317) +#define PROC_GNB_MODULES_GNBINITST_PCIEARIINITST_FILECODE (0xA318) +#define PROC_GNB_MODULES_GNBINITST_GNBBOOTTIMECALST_FILECODE (0xA319) +#define PROC_GNB_MODULES_GNBINITST_GNBPSPST_FILECODE (0xA31A) +#define PROC_GNB_MODULES_GNBINITST_GNBSMUINITST_FILECODE (0xA31B) + #define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) #define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) #define PROC_GNB_GNBINITATRTB_FILECODE (0xAE03) @@ -447,6 +477,31 @@ #define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCONNECTEDSTANDBY_FILECODE (0xCB89) #define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZBTC_FILECODE (0xCB8A) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCOREAFTERRESET_FILECODE (0xCB90) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STDMI_FILECODE (0xCB91) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STNBAFTERRESET_FILECODE (0xCB92) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPSTATE_FILECODE (0xCB93) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STLOGICALIDTABLES_FILECODE (0xCB94) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STMICROCODEPATCHTABLES_FILECODE (0xCB95) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STALLCORETABLES_FILECODE (0xCB96) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCOMPUTEUNITTABLES_FILECODE (0xCB97) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STEQUIVALENCETABLE_FILECODE (0xCB98) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPRIMARYCORETABLES_FILECODE (0xCB99) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPOWERMGMTSYSTEMTABLES_FILECODE (0xCB9A) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STUTILITIES_FILECODE (0xCB9C) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STC6STATE_FILECODE (0xCB9D) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCPB_FILECODE (0xCB9E) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STIOCSTATE_FILECODE (0xCB9F) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCACHEFLUSHONHALT_FILECODE (0xCBA0) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STHTC_FILECODE (0xCBA1) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STINITEARLYTABLE_FILECODE (0xCBA2) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STEARLYSAMPLES_FILECODE (0xCBA3) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STPSI_FILECODE (0xCBA5) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STWORKAROUNDTABLE_FILECODE (0xCBA7) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCC6EXITCONTROL_FILECODE (0xCBA8) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STCONNECTEDSTANDBY_FILECODE (0xCBA9) +#define PROC_CPU_FAMILY_0X15_ST_CPUF15STBTC_FILECODE (0xCBAA) + #define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) #define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) #define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) @@ -491,6 +546,7 @@ #define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) #define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) #define PROC_IDS_FAMILY_0X15_CZ_IDSF15CZALLSERVICE_FILECODE (0xE821) +#define PROC_IDS_FAMILY_0X15_ST_IDSF15STALLSERVICE_FILECODE (0xE822) ///0xE820 ~ 0xE840 is reserved for ids extend module @@ -523,13 +579,16 @@ #define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C) #define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F) #define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0) +#define PROC_MEM_FEAT_LVDDR4_MFLVDDR4_FILECODE (0xF0A1) #define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) #define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) #define PROC_MEM_MAIN_MM_FILECODE (0xF103) #define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) -#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) -#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) +#define PROC_MEM_FEAT_DMI_MFDMID4_FILECODE (0xF105) +#define PROC_MEM_FEAT_DMI_MFDMID34_FILECODE (0xF106) +#define PROC_MEM_MAIN_MMECC_FILECODE (0xF107) +#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF108) #define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) #define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) #define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) @@ -543,7 +602,13 @@ #define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) #define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) +#define PROC_MEM_MAIN_MMLVDDR4_FILECODE (0xF11A) #define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127) +#define PROC_MEM_MAIN_ST_MMFLOWD3ST_FILECODE (0xF129) +#define PROC_MEM_MAIN_CZ_MMFLOWD4CZ_FILECODE (0xF12A) +#define PROC_MEM_MAIN_CZ_MMFLOWD34CZ_FILECODE (0xF12B) +#define PROC_MEM_MAIN_ST_MMFLOWD4ST_FILECODE (0xF12C) +#define PROC_MEM_MAIN_ST_MMFLOWD34ST_FILECODE (0xF12D) #define PROC_MEM_NB_MN_FILECODE (0XF27C) #define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) @@ -554,19 +619,48 @@ #define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) #define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) #define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8) -#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9) -#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF2DA) -#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF2DB) -#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF2DC) -#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF2DD) -#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF2DE) -#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF) -#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0) -#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1) -#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3) - +#define PROC_MEM_NB_MNPMU_FILECODE (0xF286) +#define PROC_MEM_NB_MNMRSD3_FILECODE (0xF287) +#define PROC_MEM_NB_MNMRSD4_FILECODE (0xF288) +#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF289) +#define PROC_MEM_NB_CZ_MND3CZ_FILECODE (0xF28A) +#define PROC_MEM_NB_CZ_MND4CZ_FILECODE (0xF28B) +#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF28C) +#define PROC_MEM_NB_CZ_MNDCTD3CZ_FILECODE (0xF28D) +#define PROC_MEM_NB_CZ_MNDCTD4CZ_FILECODE (0xF28E) +#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF28F) +#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF290) +#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF291) +#define PROC_MEM_NB_CZ_MNPHYD3CZ_FILECODE (0xF292) +#define PROC_MEM_NB_CZ_MNPHYD4CZ_FILECODE (0xF293) +#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF294) +#define PROC_MEM_NB_CZ_MNPMUD3CZ_FILECODE (0xF295) +#define PROC_MEM_NB_CZ_MNPMUD4CZ_FILECODE (0xF296) +#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF297) +#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF298) +#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF299) +#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF29A) +#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF29B) + +#define PROC_MEM_NB_ST_MNST_FILECODE (0xF2E4) +#define PROC_MEM_NB_ST_MNDCTST_FILECODE (0xF2E5) +#define PROC_MEM_NB_ST_MNIDENDIMMST_FILECODE (0xF2E6) +#define PROC_MEM_NB_ST_MNMCTST_FILECODE (0xF2E7) +#define PROC_MEM_NB_ST_MNPHYST_FILECODE (0xF2E8) +#define PROC_MEM_NB_ST_MNPMUST_FILECODE (0xF2E9) +#define PROC_MEM_NB_ST_MNPMUSRAMMSGBLOCKST_FILECODE (0xF2EA) +#define PROC_MEM_NB_ST_MNPROTOST_FILECODE (0xF2EB) +#define PROC_MEM_NB_ST_MNREGST_FILECODE (0xF2EC) +#define PROC_MEM_NB_ST_MNS3ST_FILECODE (0xF2ED) +#define PROC_MEM_NB_ST_MNPSPST_FILECODE (0XF2EE) +#define PROC_MEM_NB_ST_MNDCTD3ST_FILECODE (0xF2EF) +#define PROC_MEM_NB_ST_MNDCTD4ST_FILECODE (0xF2F0) +#define PROC_MEM_NB_ST_MND3ST_FILECODE (0xF2F1) +#define PROC_MEM_NB_ST_MND4ST_FILECODE (0xF2F2) +#define PROC_MEM_NB_ST_MNPHYD3ST_FILECODE (0xF2F3) +#define PROC_MEM_NB_ST_MNPHYD4ST_FILECODE (0xF2F4) +#define PROC_MEM_NB_ST_MNPMUD3ST_FILECODE (0xF2F5) +#define PROC_MEM_NB_ST_MNPMUD4ST_FILECODE (0xF2F6) #define PROC_MEM_PS_MP_FILECODE (0XF401) #define PROC_MEM_PS_MPRTT_FILECODE (0XF422) @@ -582,13 +676,37 @@ #define PROC_MEM_PS_MPS2D_FILECODE (0XF436) #define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) #define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) +#define PROC_MEM_PS_MPDATACFGD3_FILECODE (0XF43D) +#define PROC_MEM_PS_MPDATACFGD4_FILECODE (0XF43E) #define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445) #define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446) #define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447) -#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A) -#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4D3_FILECODE (0XF44A) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4D3_FILECODE (0XF44B) +#define PROC_MEM_PS_CZ_MPCZ4_FILECODE (0XF44C) +#define PROC_MEM_PS_CZ_MPSCZ4_FILECODE (0XF44D) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4D4_FILECODE (0XF44F) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4D4_FILECODE (0XF450) + +#define PROC_MEM_PS_ST_MPST3_FILECODE (0XF451) +#define PROC_MEM_PS_ST_MPSST3_FILECODE (0XF452) +#define PROC_MEM_PS_ST_MPUST3_FILECODE (0XF453) +#define PROC_MEM_PS_ST_FP4_MPSSTFP4D3_FILECODE (0XF454) +#define PROC_MEM_PS_ST_FP4_MPUSTFP4D3_FILECODE (0XF455) +#define PROC_MEM_PS_ST_FP4_MPSSTFP4D4_FILECODE (0XF456) +#define PROC_MEM_PS_ST_FP4_MPUSTFP4D4_FILECODE (0XF457) + +#define PROC_MEM_PS_CZ_AM4_MPUCZAM4D3_FILECODE (0XF458) +#define PROC_MEM_PS_CZ_AM4_MPUCZAM4D4_FILECODE (0XF459) + +#define PROC_MEM_PS_ST_FT4_MPSSTFT4D3_FILECODE (0XF45A) +#define PROC_MEM_PS_ST_FT4_MPSSTFT4D4_FILECODE (0XF45B) + +#define PROC_MEM_PS_ST_FT4_MPUSTFT4D3_FILECODE (0XF45C) +#define PROC_MEM_PS_ST_FT4_MPUSTFT4D4_FILECODE (0XF45D) +#define PROC_MEM_PS_CZ_MPUCZ4_FILECODE (0XF45E) +#define PROC_MEM_PS_ST_MPSST4_FILECODE (0XF45F) #define PROC_MEM_TECH_MT_FILECODE (0XF501) #define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) @@ -611,6 +729,8 @@ #define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) #define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_DDR4_MT4_FILECODE (0XF58D) +#define PROC_MEM_TECH_DDR4_MTSPD4_FILECODE (0XF58E) #define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590) #define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591) diff --git a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h index aea946a784..683ed64618 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h +++ b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h @@ -10,12 +10,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Common - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/Ids.h b/src/vendorcode/amd/pi/00670F00/Include/Ids.h index cb101869e3..69c06ec9c3 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Ids.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Ids.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: IDS - * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -223,7 +223,13 @@ typedef enum { //vv- for debug reference only IDS_AFTER_DQS_TRAINING, ///< a7 override any settings after DQS training IDS_OVERRIDE_DIMM_MASK, ///< a8 override DimmMask for S3 data blob creation IDS_BYPASS_S3_REGISTERS, ///< a9 bypass restoring certain registers - IDS_OPTION_END ///< AA End of IDS option + IDS_MEM_RTTNOM, ///< aa Hook for Override RttNom + IDS_MEM_RTTWR, ///< ab Hook for Override RttWr + IDS_MEM_RTTPARK, ///< ac Hook for Override RttPark + IDS_MEM_ADDR_CMD_TMG, ///< ad Address command timing + IDS_MEM_MR6_VREF_DQ, ///< ae MR6 VRefDQ + IDS_MEM_PMU_RETRAIN_TIMES, ///< af override memory PMU retrain times + IDS_OPTION_END ///< B0 End of IDS option } AGESA_IDS_OPTION; #include "OptionsIds.h" @@ -507,7 +513,9 @@ typedef enum { //vv- for debug reference only #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS #define IDS_TRACE_DEFAULT (0) #define IDS_INITIAL_F15_CZ_PM_STEP + #define IDS_INITIAL_F15_ST_PM_STEP #define IDS_F15_CZ_PM_CUSTOM_STEP + #define IDS_F15_ST_PM_CUSTOM_STEP #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) #define IDS_EXTENDED_HEAP_SIZE 0 @@ -655,7 +663,7 @@ typedef enum { //vv- for debug reference only #define MEM_FLOW DEBUG_PRINT_SHIFT (2) #define MEM_STATUS DEBUG_PRINT_SHIFT (3) #define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4) -#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) +#define MEM_PMU DEBUG_PRINT_SHIFT (5) #define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) #define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) #define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) @@ -761,10 +769,16 @@ typedef enum { //vv- for debug reference only #define MEMORY_TRACE_ALL\ (\ MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \ - MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \ + MEM_UNDEF_BF | MEM_PMU | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \ MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\ ) +#define MEMORY_TRACE_DEFAULT\ + (\ + MEM_FLOW | MEM_STATUS | MEM_PMU\ + ) + + #define TOPO_TRACE_ALL\ (\ TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \ @@ -792,7 +806,7 @@ typedef enum { //vv- for debug reference only #define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull) #ifndef IDS_DEBUG_PRINT_MASK - #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT | MEM_GETREG) + #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEMORY_TRACE_DEFAULT | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT) #endif /// if no specific define INIT & EXIT will be NULL @@ -1121,6 +1135,7 @@ typedef enum { TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage + TpProcMemLvDdr4, ///< 8E .. Before LV DDR4 // Gnb Earlier init TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init diff --git a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h index 0ec8a492f0..4663f8c35c 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h +++ b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: IDS - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/Options.h b/src/vendorcode/amd/pi/00670F00/Include/Options.h index 70c39f89e3..4bd67439aa 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Options.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Options.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Core - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h index 38f7f051f4..6a8a01789e 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h +++ b/src/vendorcode/amd/pi/00670F00/Include/PlatformMemoryConfiguration.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: OPTION - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -202,6 +202,19 @@ /// #define LAYERS_4 0x0 #define LAYERS_6 0x1 +/// DQS Routing Type +/// +#define DQS_ROUTING_TREE 0x1 ///< Tree topology is applied to DQS routing +#define DQS_ROUTING_DAISY_CHAIN 0x2 ///< Daisy chain topology is applied to DQS routing + +/// +/// DataMaskMbTypes +/// Motherboard type for processor Data Mask pins. +/// +#define DATAMASK_NO_CONNECT 0x00 ///< No connect +#define DATAMASK_DM_ROUTING 0x01 ///< Pins are routed per DM rules +#define DATAMASK_DQS_ROUTING 0x02 ///< Pins are routed per DQS rules + /*---------------------------------------------------------------------------------------- * * Platform Specific Overriding Table Definitions @@ -230,6 +243,10 @@ #define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent #define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel #define PSO_MOTHER_BOARD_LAYERS 20 ///< Mother board layer design +#define PSO_ON_DIMM_THERMAL_CONTROL 21 ///< On DIMM thermal override +#define PSO_DATA_MASK_MB_TYPE 22 ///< Motherboard type for processor Data Mask pins. +#define PSO_DQS_ROUTING_TYPE 23 ///< Dqs Routing Type +#define PSO_BYPASSED_DIMM_SLOTS 24 ///< Number of bypassed Dimm slots /*---------------------------------- * CONDITIONAL PSO SPECIFIC ENTRIES @@ -303,6 +320,9 @@ #define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \ PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel +#define NUMBER_OF_BYPASSED_DIMM_SLOTS(SocketID, ChannelID, NumberOfBypassedDimmSlots) \ + PSO_BYPASSED_DIMM_SLOTS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfBypassedDimmSlots + #define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel @@ -342,6 +362,15 @@ #define MOTHER_BOARD_LAYERS(Layers) \ PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers +#define ON_DIMM_THERMAL_CONTROL(SocketID, ChannelID, EnableDisable) \ + PSO_ON_DIMM_THERMAL_CONTROL, 4, SocketID, ChannelID, ALL_DIMMS, EnableDisable + +#define DATA_MASK_MB_TYPE(SocketID, ChannelID, DataMaskMbType) \ + PSO_DATA_MASK_MB_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, DataMaskMbType + +#define DQS_ROUTING_TYPE(Type) \ + PSO_DQS_ROUTING_TYPE, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Type + #define MAX_NUMBER_PSO_TABLES 13 /*---------------------------------------------------------------------------------------- * CONDITIONAL OVERRIDE TABLE MACROS diff --git a/src/vendorcode/amd/pi/00670F00/Include/Topology.h b/src/vendorcode/amd/pi/00670F00/Include/Topology.h index 099142eb82..11f49454d1 100644 --- a/src/vendorcode/amd/pi/00670F00/Include/Topology.h +++ b/src/vendorcode/amd/pi/00670F00/Include/Topology.h @@ -10,11 +10,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Core - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h index 62ef892eda..4883434002 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h index 3ee71cd624..87077ce805 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h index 7efbc523e4..418fb2f6d2 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h index 7cef71d4c3..04bd01334d 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h index 889be764a1..3ef723cd4f 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -429,8 +429,9 @@ typedef struct { #define CPUID_EXT_FAMILY_MASK 0x0FF00000ul #define CZ_SOCKET_FP4 0 +#define CZ_SOCKET_AM4 2 #define ST_SOCKET_FP4 0 -#define ST_SOCKET_FT4 3 +#define ST_SOCKET_FT4 4 #define SOCKET_IGNORE 0xF #define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h index 915144f8f9..c5f9529204 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h b/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h index f75f881601..57bfabbd03 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h index 6f87842a30..fe1803d88a 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h index a694d11543..84cd94c64c 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h index 35a76d20fd..46fa1a9bdb 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 311507 $ @e \$Date: 2015-01-22 06:57:51 +0800 (Thu, 22 Jan 2015) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -98,7 +98,9 @@ typedef struct { UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Ram; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram UINT8 SataDevSlpPort0S5Pin; ///< SataDevSlpPort0S5Pin - Reserved UINT8 SataDevSlpPort1S5Pin; ///< SataDevSlpPort1S5Pin - Reserved - UINT16 Dummy16; ///< Dummy16 - Reserved + UINT16 FchFlag16; ///< Dummy16 - Reserved + UINT32 FchFlag32; ///< Dummy32 - Reserved + /// @li <b>0</b> - Carrizo UINT32 SdMmioBase; ///< Sd Mmio Base - Reserved UINT32 EhciMmioBase; ///< Ehci Mmio Base - Reserved UINT32 XhciMmioBase; ///< Xhci Mmio Base - Reserved @@ -525,6 +527,7 @@ typedef struct { // UINT8 SataDevSlpPort1S5Pin; /// SataDevSlpPort1S5Pin - Reserved UINT8 SataDbgTX_DRV_STR ; /// TX_DRV_STR - Reserved UINT8 SataDbgTX_DE_EMPH_STR ; /// TX_DE_EMPH_STR - Reserved + BOOLEAN SataLongTrace[2]; /// Long Trace - Reserved UINT32 TempMmio; /// TempMmio - Reserved } FCH_SATA; @@ -545,6 +548,8 @@ typedef struct { #define Fun_87 0x87 #define Fun_88 0x88 #define Fun_89 0x89 +#define Fun_8B 0x8B +#define Fun_8C 0x8C #define Fun_90 0x90 #define MSG_IMC_TO_SYS 0x81 #define MSG_REG0 0x82 @@ -789,9 +794,37 @@ typedef struct _FCH_EC { UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24 UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7 // -// FLAG for Fun83/85/89 support +//EC LDN9 function 8C Startup PWM channel 0 // - UINT16 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; + UINT8 MsgFun8CZone0MsgReg0; ///<Reture 0xFA stands for success + UINT8 MsgFun8CZone0MsgReg1; ///<Bit 2-0 Thermal zone number + UINT8 MsgFun8CZone0MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid. + UINT8 MsgFun8CZone0MsgReg3; ///<Startup PWM (effective range 1~100) +// +//EC LDN9 function 8C Startup PWM channel 1 +// + UINT8 MsgFun8CZone1MsgReg0; ///<Reture 0xFA stands for success + UINT8 MsgFun8CZone1MsgReg1; ///<Bit 2-0 Thermal zone number + UINT8 MsgFun8CZone1MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid. + UINT8 MsgFun8CZone1MsgReg3; ///<Startup PWM (effective range 1~100) +// +//EC LDN9 function 8C Startup PWM channel 2 +// + UINT8 MsgFun8CZone2MsgReg0; ///<Reture 0xFA stands for success + UINT8 MsgFun8CZone2MsgReg1; ///<Bit 2-0 Thermal zone number + UINT8 MsgFun8CZone2MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid. + UINT8 MsgFun8CZone2MsgReg3; ///<Startup PWM (effective range 1~100) +// +//EC LDN9 function 8C Startup PWM channel 3 +// + UINT8 MsgFun8CZone3MsgReg0; ///<Reture 0xFA stands for success + UINT8 MsgFun8CZone3MsgReg1; ///<Bit 2-0 Thermal zone number + UINT8 MsgFun8CZone3MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid. + UINT8 MsgFun8CZone3MsgReg3; ///<Startup PWM (effective range 1~100) +// +// FLAG for Fun83/85/89/8C support +// + UINT32 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; } FCH_EC; /// @@ -1284,8 +1317,126 @@ typedef struct { BOOLEAN UsbBatteryChargeEnable; ///< USB Battery Charge Enable BOOLEAN ReduceUSB3PortToLastTwo; ///< Reduce USB3.0 ports to last 2 UINT8 USB30PortInit; ///< USB 3.0 Port Init + UINT8 USB30RxLfpsDetTh; ///< USB 3.0 Rx Lfps Detect Threshhold } FCH_USB; +//++++++++++++++++++++++++++++++++++ Promontory param structure +///PTXhciStructure +typedef struct { + UINT8 PTXhciGen1; ///< PTXhciGen1 + UINT8 PTXhciGen2; ///< PTXhciGen2 + UINT8 PTAOAC; ///< PTAOAC + UINT8 PTHW_LPM ; ///< PTHW_LPM + UINT8 PTDbC; ///< PTDbC + UINT8 PTXHC_PME; ///< PTXHC_PME + UINT8 PTSystemSpreadSpectrum; ///< PTSystemSpreadSpectrum + UINT8 Equalization4; ///< Enable/Disable Equalization 4 + UINT8 Redriver; ///< Enable/Disable Redriver Setting +} PT_USB; +///PTSataStructure +typedef struct { + UINT8 PTSataPortEnable; ///< PTSataEnable + UINT8 PTSataMode; ///< PTSataMode + UINT8 PTSataAggresiveDevSlpP0; ///< PTSataAggresiveDevSlpP0 + UINT8 PTSataAggresiveDevSlpP1; ///< PTSataAggresiveDevSlpP1 + UINT8 PTSataAggrLinkPmCap; ///< PTSataAggrLinkPmCap + UINT8 PTSataPscCap; ///< PTSataPscCap + UINT8 PTSataSscCap; ///< PTSataSscCap + UINT8 PTSataMsiCapability; ///< PTSataPscCap + UINT8 PTSataPortMdPort0; ///< PTSataPortMdPort0 + UINT8 PTSataPortMdPort1; ///< PTSataPortMdPort1 + UINT8 PTSataHotPlug; ///< PTSataHotPlug +} PT_SATA; +///PTPcieStructure +typedef struct { + UINT8 PromontoryPCIeEnable; ///< PCIeEnable + UINT8 PromontoryPCIeASPM; ///< PCIeASPM +} PT_PCIE; +///PTAddressStructure +typedef struct { + UINT8 GppNumber; ///< GppNumber + UINT32 XhciID; ///< XhciDIDVID + UINT32 SataID; ///< SataDIDVID + UINT32 GpioID; ///< GpioDIDVID + UINT64 FwVersion; ///< FwVersion +} PT_ADDR; +///PTUSBPortStructure +typedef struct { + UINT8 PTUsb31P0; ///< PTUsb31Port0 Enable/Disable + UINT8 PTUsb31P1; ///< PTUsb31Port0 Enable/Disable + UINT8 PTUsb30P0; ///< PTUsb30Port0 Enable/Disable + UINT8 PTUsb30P1; ///< PTUsb30Port1 Enable/Disable + UINT8 PTUsb30P2; ///< PTUsb30Port2 Enable/Disable + UINT8 PTUsb30P3; ///< PTUsb30Port3 Enable/Disable + UINT8 PTUsb30P4; ///< PTUsb30Port4 Enable/Disable + UINT8 PTUsb30P5; ///< PTUsb30Port5 Enable/Disable + UINT8 PTUsb20P0; ///< PTUsb20Port0 Enable/Disable + UINT8 PTUsb20P1; ///< PTUsb20Port1 Enable/Disable + UINT8 PTUsb20P2; ///< PTUsb20Port2 Enable/Disable + UINT8 PTUsb20P3; ///< PTUsb20Port3 Enable/Disable + UINT8 PTUsb20P4; ///< PTUsb20Port4 Enable/Disable + UINT8 PTUsb20P5; ///< PTUsb20Port5 Enable/Disable +} PT_USBPort; +///PTUSB31TxStructure +typedef struct { +UINT8 USB31Gen1Swing; ///< PTUSB31PCS_B1 genI swing +UINT8 USB31Gen2Swing; ///< PTUSB31PCS_B1 genI swing +UINT8 USB31Gen1PreEmEn; ///< PTUSB31PCS_B1 genI pre-emphasis enable +UINT8 USB31Gen2PreEmEn; ///< PTUSB31PCS_B1 genII pre-emphasis enable +UINT8 USB31Gen1PreEmLe; ///< PTUSB31PCS_B1 genI pre-emphasis level +UINT8 USB31Gen2PreEmLe; ///< PTUSB31PCS_B1 genII pre-emphasis level +UINT8 USB31Gen1PreShEn; ///< PTUSB31PCS_B1 genI pre-shoot enable +UINT8 USB31Gen2PreShEn; ///< PTUSB31PCS_B1 genII pre-shoot enable +UINT8 USB31Gen1PreShLe; ///< PTUSB31PCS_B1 genI pre-shoot level +UINT8 USB31Gen2PreShLe; ///< PTUSB31PCS_B1 genII pre-shoot level +} PT_USB31Tx; + +///PTUSB30TxStructure +typedef struct { +UINT8 USB30Gen1Swing; ///< PTUSB30PCS_B3 genI swing +UINT8 USB30Gen1PreEmEn; ///< PTUSB30PCS_B3 genI pre-emphasis enable +UINT8 USB30Gen1PreEmLe; ///< PTUSB30PCS_B3 genI pre-emphasis level +} PT_USB30Tx; + + +///PTUSBTxStructure +typedef struct { +PT_USB31Tx USB31Tx[2]; ///< USB31Tx setting +PT_USB30Tx USB30Tx[3]; ///< USB30Tx setting +UINT8 USB20B2Tx00; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[0] +UINT8 USB20B2Tx05; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[5] +UINT8 USB20B3Tx1113; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[13][11] +UINT8 USB20B3Tx1012; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[12][10] +UINT8 USB20B4Tx0206; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[2][6] +UINT8 USB20B4Tx0307; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[3][7] +UINT8 USB20B5Tx0408; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[4][8] +UINT8 USB20B5Tx0109; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[1][9] +} PT_USBTx; + +///PTSataTxStructure +typedef struct { +UINT8 SATAGen1Swing; ///< genI swing +UINT8 SATAGen2Swing; ///< genII swing +UINT8 SATAGen3Swing; ///< genIII swing +UINT8 SATAGen1PreEmEn; ///< genI pre-emphasis enable +UINT8 SATAGen2PreEmEn; ///< genII pre-emphasis enable +UINT8 SATAGen3PreEmEn; ///< genIII pre-emphasis enable +UINT8 SATAGen1PreEmLevel; ///< genI pre-emphasis level +UINT8 SATAGen2PreEmLevel; ///< genII pre-emphasis level +UINT8 SATAGen3PreEmLevel; ///< genIII pre-emphasis level +} PT_SATATx; +///PTDataStructure +typedef struct _FCH_PT { + PT_USB PromontoryUSB; ///<PTXhciStructure + PT_SATA PromontorySATA; ///<PTSataStructure + PT_PCIE PromontoryPCIE; ///<PTPcieStructure + PT_ADDR PromontoryAddr; ///<PTAddressStructure + PT_USBPort PromontoryUSBPort; ///<PTUSBPortStructure + PT_USBTx PTUSBTX; ///<PTUSBTX + PT_SATATx PTSATATX[8]; ///<PTSATATX +} FCH_PT; + +//-------------------------------------------- Promontory param structure /// Private: FCH_DATA_BLOCK_RESET typedef struct _FCH_RESET_DATA_BLOCK { @@ -1323,15 +1474,16 @@ typedef struct _FCH_RESET_DATA_BLOCK { BOOLEAN QeEnabled; /// Quad Mode Enabled BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous UINT8 LpcClockDriveStrength; ///< Lpc Clock Drive Strength - const VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table + FCH_PT Promontory; ///< Promontory structure + VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table // VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table } FCH_RESET_DATA_BLOCK; /// Private: FCH_DATA_BLOCK typedef struct _FCH_DATA_BLOCK { - AMD_CONFIG_PARAMS *StdHeader; ///< Header structure FCH_RUNTIME FchRunTime; ///< FCH Run Time Parameters + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure FCH_ACPI HwAcpi; ///< ACPI structure FCH_AB Ab; ///< AB structure @@ -1352,6 +1504,7 @@ typedef struct _FCH_DATA_BLOCK { FCH_IMC Imc; ///< IMC structure FCH_MISC Misc; ///< MISC structure FCH_IOMUX IoMux; ///< MISC structure + FCH_PT Promontory; ///< Promontory structure VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table } FCH_DATA_BLOCK; diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h index 41f103bd25..e1d0def2ef 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -72,6 +72,12 @@ VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader); UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader); UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN FchCheckBR_ST (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN FchCheckBR (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN FchCheckST (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader); +UINT64 FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader); /// /// Fch Ab Routines diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c index dfdab59f08..5836e5c176 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -375,7 +375,7 @@ RwAlink ( WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader); Index = FCH_AX_DATAP_REG3C | AccessType; } - WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader); + WriteAlink (Index, ReadAlink (Index, StdHeader) & AndMask | OrMask, StdHeader); } @@ -669,4 +669,4 @@ ClearAllSmiStatus ( for ( Index = 0; Index < 20; Index++ ) { ACPIMMIO8 (0xfed80280 + Index) |= 0; } -} +}
\ No newline at end of file diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c index 171ea0f3d0..9cd0e29557 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -40,7 +40,13 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ***************************************************************************/ + #include "FchPlatform.h" +#include "cpuFamilyTranslation.h" +//#include "Porting.h" +//#include "AMD.h" +//#include "amdlib.h" +#include "heapManager.h" #define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE /*----------------------------------------------------------------------------------------*/ @@ -179,8 +185,8 @@ ProgramFchGpioTbl ( { if (pGpioTbl != NULL) { while (pGpioTbl->GpioPin != 0xFF) { - ACPIMMIO8 (ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction); - ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + ((UINT32)pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte); + ACPIMMIO8 (ACPI_MMIO_BASE + IOMUX_BASE + pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction); + ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte); pGpioTbl++; } } @@ -308,3 +314,359 @@ SbSleepTrapControl ( ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); } } + +/** + * FchUsb3D3ColdCallback - Fch Usb3 D3Cold Callback + * + * + * @param[in] FchDataPtr + * + */ +VOID +FchUsb3D3ColdCallback ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + UINT8 Value8; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + //FCH_DEADLOOP (); + ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) |= FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown; + do { + } while ((ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) & FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown) == 0); + + ACPIMMIO32 (FCH_XHC_PMx00_Configure0) |= FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN; + + ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= ~ (AOAC_PWR_ON_DEV); + do { + } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 0); + + ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= 3; + + ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn; + + if ((ACPIMMIO8 (FCH_AOACx64_EHCI_D3_CONTROL) & 0x03) == 3) { + ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); + ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn; + } + + ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_XhcPwrGood + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); + Value8 = ACPIMMIO8 (0xFED803EE); + Value8 &= 0xFC; + Value8 |= 0x01; + ACPIMMIO8 (0xFED803EE) = Value8; +} + +/** + * FchUsb3D0Callback - Fch Usb3 D0 Callback + * + * + * @param[in] FchDataPtr + * + */ +VOID +FchUsb3D0Callback ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + UINT32 Dword32; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + ACPIMMIO8 (0xFED803EE) &= 0xFC; + + ACPIMMIO8 (FCH_AOACxA0_PwrGood_Control) |= (FCH_AOACxA0_PwrGood_Control_XhcPwrGood); + ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn); + ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn); + Dword32 = ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control); + Dword32 &= ~(FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); + ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) = ((FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB | Dword32) & (~ BIT29)); + + ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= 0xFC; + ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= (AOAC_PWR_ON_DEV); + do { + } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 7); + + do { + } while ((ACPIMMIO32 (FCH_XHC_PMx00_Configure0) & BIT7) != BIT7); + + ACPIMMIO32 (FCH_XHC_PMx00_Configure0) &= ~ (BIT16); + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Checks Bristol or Stoney + * + * NOTE: + * + * @param[in] StdHeader + * + */ +BOOLEAN +FchCheckBR_ST ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID LogicalId; + + // Only initialize on CZ processors, otherwise exit. + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) { + return TRUE; + } + if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) { + return TRUE; + } + + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Checks Bristol + * + * NOTE: + * + * @param[in] StdHeader + * + */ +BOOLEAN +FchCheckBR ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID LogicalId; + + // Only initialize on CZ processors, otherwise exit. + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) { + return TRUE; + } + + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Checks Stoney + * + * NOTE: + * + * @param[in] StdHeader + * + */ +BOOLEAN +FchCheckST ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID LogicalId; + + // Only initialize on CZ processors, otherwise exit. + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) { + return TRUE; + } + + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Checks Carrizo + * + * NOTE: + * + * @param[in] StdHeader + * + */ +BOOLEAN +FchCheckCZ ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID LogicalId; + + // Only initialize on CZ processors, otherwise exit. + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F15_CZ_ALL) != 0) { + return TRUE; + } + + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Checks Package AM4 + * + * NOTE: + * + * @param[in] StdHeader + * + */ +BOOLEAN +FchCheckPackageAM4 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuId; + UINT8 RegValue; + + LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); + RegValue = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + ///@todo - update the PkgType once it is reflected in BKDG + if (RegValue == 2) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Get Scratch Fuse + * + * NOTE: + * + * @param[in] StdHeader + * + */ +UINT64 +FchGetScratchFuse ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR D0F0xB8_SMU_Index_Address; + PCI_ADDR D0F0xBC_SMU_Index_Data; + UINT64 TempData64; + UINT32 TempData32; + + D0F0xB8_SMU_Index_Address.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xB8)); + D0F0xBC_SMU_Index_Data.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xBC)); + TempData64 = 0; + TempData32 = 0xC0016028; + LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); + LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); + TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) >> 9; + TempData32 = 0xC001602C; + LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); + LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); + TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (32 - 9); + TempData32 = 0xC0016030; + LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); + LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); + TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (64 - 9); + + return TempData64; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +FchAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + AllocHeapParams.RequestedBufferSize = (UINT32) Length; + AllocHeapParams.BufferHandle = Handle; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return AllocHeapParams.BufferPtr; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap and clear it + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +FchAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + VOID *Buffer; + Buffer = FchAllocateHeapBuffer (Handle, Length, StdHeader); + if (Buffer != NULL) { + LibAmdMemFill (Buffer, 0x00, Length, StdHeader); + } + return Buffer; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locates a previously allocated buffer on the heap. + * + * + * @param[in] Handle Buffer handle + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer handle not found + * + */ + +VOID * +MemLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + LOCATE_HEAP_PTR LocHeapParams; + LocHeapParams.BufferHandle = Handle; + Status = HeapLocateBuffer (&LocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return LocHeapParams.BufferPtr; +} + diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c index 656f7689bb..8313d81ded 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c index ed8bb81869..7c55c4e7ef 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h index 92201b8a49..4413e2ec04 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 314274 $ @e \$Date: 2015-03-08 03:53:49 -0500 (Sun, 08 Mar 2015) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -347,7 +347,7 @@ #define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1 #define FCH_IDE_DID 0x780C #define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2 -#define FCH_AZALIA_DID 0x157a +#define FCH_AZALIA_DID 0x780D #define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3 #define FCH_LPC_DID 0x780E #define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4 @@ -415,6 +415,7 @@ #define FCH_OHCI3_BUS 0 #define FCH_OHCI3_DEV 22 #define FCH_OHCI3_FUNC 0 +#define EHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-3 #define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4 #define FCH_EHCI1_BUS 0 #define FCH_EHCI1_DEV 18 @@ -435,9 +436,9 @@ #define FCH_IDE_BUS 0 #define FCH_IDE_DEV 20 #define FCH_IDE_FUNC 1 -#define AZALIA_BUS_DEV_FUN ((0x9 << 3) + 2) +#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) #define FCH_AZALIA_BUS 0 -#define FCH_AZALIA_DEV 9 +#define FCH_AZALIA_DEV 20 #define FCH_AZALIA_FUNC 2 #define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) #define FCH_LPC_BUS 0 @@ -856,7 +857,7 @@ // USB ports -#define NUM_USB1_PORTS 5 +#define NUM_USB1_PORTS 4 #define NUM_USB2_PORTS 5 #define NUM_USB3_PORTS 4 #define NUM_USB4_PORTS 2 @@ -2041,8 +2042,10 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x1C00 // #define FCH_XHC_PMx00_Configure0 0xFED81C00ul // +#define FCH_XHC_PMx00_Configure0_U3pPllReset BIT8 #define FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN BIT15 #define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 + #define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul // #define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul // #define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul // @@ -2052,6 +2055,7 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_XHC_PMx30_Xhci10_Enable 0xFED81C30ul // #define FCH_XHC_PMx60_xHC_Battery_Charger_Enable 0xFED81C60ul // +#define FCH_XHC_PMx88_SSPHY_Common_Clock_Control_Status 0xFED81C88ul // @@ -2506,6 +2510,7 @@ FCH_AOAC_REG4X-7x State field #define FCH_XHCI_IND_REG100 0x100 // #define FCH_XHCI_IND_REG120 0x120 // #define FCH_XHCI_IND_REG128 0x128 // +#define FCH_XHCI_IND_REG140 0x140 // #define FCH_XHCI_IND_REG200 0x200 // #define FCH_XHCI_IND_REG240 0x240 // #define FCH_XHCI_IND_REG280 0x280 // diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h index ca2a8d89a5..e7fff2320b 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h index a20ec19f55..bca7b5bd59 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c index 20a359ad0e..5c2410d7d4 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: PSP - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -48,10 +48,11 @@ */ #include "AGESA.h" #include "Filecode.h" +#include "Fch.h" #include "PspBaseLib.h" #define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE -#define PSP_BAR1_TMP_BASE 0xFEA00000ul +#define PSP_BAR_TMP_BASE 0xFEA00000ul #define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF) #define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F) @@ -74,6 +75,13 @@ #define PSP_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< Secure Part #define PSP_FRA_MODE (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< FRA Part +#define PSP_MUTEX_REG0_OFFSET (24 * 4) ///< PSP Mutex0 register offset +#define PSP_MUTEX_REG1_OFFSET (25 * 4) ///< PSP Mutex1 register offset + +#ifndef OFFSET_OF +#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field)) +#endif + /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- @@ -139,6 +147,37 @@ PspLibPciWritePspConfig ( PspLibPciWriteConfig ((UINT32) (PSP_PCI_BDA + Offset), Value); } +/// Structure for Program ID +typedef enum { + CZ_PROGRAM = 0x00, ///< Program ID for CZ + BR_PROGRAM = 0x01, ///< Program ID for BR + ST_PROGRAM = 0x02, ///< Program ID for ST + UNSUPPORTED_PROGRAM = 0xFF, ///< Program ID for unsupported +} PROGRAM_ID; + +PROGRAM_ID +PspGetProgarmId ( + VOID + ) +{ + CPUID_DATA Cpuid; + + LibAmdCpuidRead (0x00000001, &Cpuid, NULL); + //Stoney CPUID 0x00670F00 or 0x00670F01 + if ((Cpuid.EAX_Reg >> 16) == 0x67) { + return ST_PROGRAM; + } else if ((Cpuid.EAX_Reg >> 16) == 0x66) { + if ((Cpuid.EAX_Reg & 0xF0) == 0x50) { + //Bristol CPUID 0x00660F51 + return BR_PROGRAM; + } else if ((Cpuid.EAX_Reg & 0xF0) == 0x00) { + //Carrizo CPUID 0x00660F00 or 0x00660F01 + return CZ_PROGRAM; + } + } + return UNSUPPORTED_PROGRAM; +} + BOOLEAN GetPspDirBase ( IN OUT UINT32 *Address @@ -146,6 +185,7 @@ GetPspDirBase ( { UINTN i; FIRMWARE_ENTRY_TABLE *FirmwareTableBase; + PROGRAM_ID ProgramId; CONST UINT32 RomSigAddrTable[] = { 0xFFFA0000, // --> 512KB base @@ -156,32 +196,66 @@ GetPspDirBase ( 0xFF020000 // --> 16MB base }; + ProgramId = PspGetProgarmId (); + for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) { FirmwareTableBase = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i]; // Search flash for unique signature 0x55AA55AA if (FirmwareTableBase->Signature == FIRMWARE_TABLE_SIGNATURE) { - *Address = FirmwareTableBase->PspDirBase; + switch (ProgramId) { + case BR_PROGRAM: + case CZ_PROGRAM: + *Address = FirmwareTableBase->PspDirBase; + break; + case ST_PROGRAM: + *Address = FirmwareTableBase->NewPspDirBase; + break; + default: + *Address = FirmwareTableBase->PspDirBase; + break; + } return TRUE; } } - return (FALSE); } +/** + * Get specific PSP Entry information, this routine will auto detect the processor for loading + * correct PSP Directory + * + * + * + * @param[in] EntryType PSP DIR Entry Type + * @param[in,out] EntryAddress Address of the specific PSP Entry + * @param[in,out] EntrySize Size of the specific PSP Entry + */ + BOOLEAN PSPEntryInfo ( IN PSP_DIRECTORY_ENTRY_TYPE EntryType, IN OUT UINT64 *EntryAddress, - IN UINT32 *EntrySize + IN OUT UINT32 *EntrySize ) { PSP_DIRECTORY *PspDir; UINTN i; + PROGRAM_ID ProgramId; + PspDir = NULL; if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) { return FALSE; } + ProgramId = PspGetProgarmId (); + //Append BR Program ID + if ((ProgramId == BR_PROGRAM) && + ((EntryType == SMU_OFFCHIP_FW) || + (EntryType == SMU_OFF_CHIP_FW_2) || + (EntryType == AMD_SCS_BINARY))) { + EntryType |= (PSP_ENTRY_BR_PROGRAM_ID << 8); + } + for (i = 0; i < PspDir->Header.TotalEntries; i++) { if (PspDir->PspEntry[i].Type == EntryType) { *EntryAddress = PspDir->PspEntry[i].Location; @@ -193,6 +267,66 @@ PSPEntryInfo ( return (FALSE); } +BOOLEAN +PspSoftWareFuseInfo ( + IN OUT UINTN *FuseSpiAddress, + IN OUT UINT64 *FuseValue + ) +{ + PSP_DIRECTORY *PspDir; + UINTN i; + + PspDir = NULL; + if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) { + return FALSE; + } + + for (i = 0; i < PspDir->Header.TotalEntries; i++) { + if (PspDir->PspEntry[i].Type == AMD_SOFT_FUSE_CHAIN_01) { + *FuseSpiAddress = (UINT32) (UINTN) &PspDir->PspEntry[i].Location; + *FuseValue = PspDir->PspEntry[i].Location; + return (TRUE); + } + } + return (FALSE); +} + +UINT32 Fletcher32 ( + IN OUT UINT16 *data, + IN UINTN words + ) +{ + UINT32 sum1; + UINT32 sum2; + UINTN tlen; + + sum1 = 0xffff; + sum2 = 0xffff; + + while (words) { + tlen = words >= 359 ? 359 : words; + words -= tlen; + do { + sum2 += sum1 += *data++; + } while (--tlen); + sum1 = (sum1 & 0xffff) + (sum1 >> 16); + sum2 = (sum2 & 0xffff) + (sum2 >> 16); + } + // Second reduction step to reduce sums to 16 bits + sum1 = (sum1 & 0xffff) + (sum1 >> 16); + sum2 = (sum2 & 0xffff) + (sum2 >> 16); + return sum2 << 16 | sum1; +} + +VOID +UpdataPspDirCheckSum ( + IN OUT PSP_DIRECTORY *PspDir + ) +{ + PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \ + (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2); +} + /** Check if PSP device is present @@ -273,7 +407,7 @@ GetPspMboxStatus ( { UINT32 PspMmio; - if (GetPspBar1Addr (&PspMmio) == FALSE) { + if (GetPspBar3Addr (&PspMmio) == FALSE) { return (FALSE); } @@ -283,7 +417,7 @@ GetPspMboxStatus ( } BOOLEAN -PspBarInitEarly (void) +PspBarInitEarly () { UINT32 PspMmioSize; UINT32 Value32; @@ -293,18 +427,18 @@ PspBarInitEarly (void) } //Check if PSP BAR has been assigned, if not do the PSP BAR initialation - if (PspLibPciReadPspConfig (PSP_PCI_BAR1_REG) == 0) { + if (PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) == 0) { /// Get PSP BAR1 Size - PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, 0xFFFFFFFF); - PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG); + PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, 0xFFFFFFFF); + PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG); PspMmioSize = ~PspMmioSize + 1; - /// Assign BAR1 Temporary Address - PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, PSP_BAR1_TMP_BASE); + /// Assign BAR3 Temporary Address + PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, PSP_BAR_TMP_BASE); PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06); /// Enable GNB redirection to this space @todo use equate & also find proper fix - PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR1_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF); - PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR1_TMP_BASE >> 8) | 3); + PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF); + PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR_TMP_BASE >> 8) | 3); /// Enable MsixBarEn, Bar1En, Bar3En PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34); /// Capability chain update @@ -354,11 +488,21 @@ GetPspBar3Addr ( IN OUT UINT32 *PspMmio ) { + UINT32 PciReg48; + UINT64 MsrPspAddr; + if (CheckPspDevicePresent () == FALSE) { return (FALSE); } - *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG); + PciReg48 = PspLibPciReadPspConfig (PSP_PCI_EXTRAPCIHDR_REG); + if (PciReg48 & BIT12) { + // D8F0x48[12] Bar3Hide + LibAmdMsrRead (PSP_MSR_PRIVATE_BLOCK_BAR, &MsrPspAddr, NULL); + *PspMmio = (UINT32)MsrPspAddr; + } else { + *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) & 0xFFF00000; + } if ((*PspMmio) == 0xffffffff) { return (FALSE); @@ -366,6 +510,51 @@ GetPspBar3Addr ( return (TRUE); } +/** + * Acquire the Mutex for access PSP,X86 co-accessed register + * Call this routine before access SMIx98 & SMIxA8 + * + */ +VOID +AcquirePspSmiRegMutex ( + VOID + ) +{ + UINT32 PspBarAddr; + UINT32 MutexReg0; + UINT32 MutexReg1; + + PspBarAddr = 0; + if (GetPspBar3Addr (&PspBarAddr)) { + MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET; + MutexReg1 = PspBarAddr + PSP_MUTEX_REG1_OFFSET; + *(volatile UINT32*)(UINTN)(MutexReg0) |= BIT0; + *(volatile UINT32*)(UINTN)(MutexReg1) |= BIT0; + //Wait till PSP FW release the mutex + while ((*(volatile UINT32*)(UINTN)(MutexReg0)& BIT1) && (*(volatile UINT32*)(UINTN)(MutexReg1) & BIT0)) { + ; + } + } +} +/** + * Release the Mutex for access PSP,X86 co-accessed register + * Call this routine after access SMIx98 & SMIxA8 + * + */ +VOID +ReleasePspSmiRegMutex ( + VOID + ) +{ + UINT32 PspBarAddr; + UINT32 MutexReg0; + + PspBarAddr = 0; + if (GetPspBar3Addr (&PspBarAddr)) { + MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET; + *(volatile UINT32*)(UINTN)(MutexReg0) &= ~BIT0; + } +} /*---------------------------------------------------------------------------------------*/ /** @@ -461,4 +650,30 @@ PspLibPciIndirectWrite ( LibAmdPciWrite (Width, Address, Value, NULL); } +BOOLEAN +IsS3Resume ( + ) +{ + UINT16 AcpiPm1CntBlk; + UINT16 SleepType; + UINT8 PmioAddr; + + AcpiPm1CntBlk = 0; + //Get AcpiPm1CntBlk address + //PMIO register can only allow 8bits access + PmioAddr = PMIO_REG62; + LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL); + LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, &AcpiPm1CntBlk, NULL); + + PmioAddr++; + LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL); + LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, ((UINT8 *) &AcpiPm1CntBlk) + 1, NULL); + + //Get Sleep type + LibAmdIoRead (AccessWidth16, AcpiPm1CntBlk, &SleepType, NULL); + SleepType = SleepType & 0x1C00; + SleepType = ((SleepType >> 10) & 7); + + return ((SleepType == 3) ? TRUE : FALSE); +} diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h index 611539644f..e7f5a47d8d 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -9,12 +9,12 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: PSP - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ * */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -53,7 +53,7 @@ #define PSP_PCI_DEV 0x08 ///< PSP Device address #define PSP_PCI_FN 0x00 ///< PSP Fn address #define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8)) -#define GET_PSP_PCI_ADDR (Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset) +#define GET_PSP_PCI_ADDR(Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset) #define PSP_PCI_DEVID_REG 0x00 ///< DevId #define PSP_PCI_CMD_REG 0x04 ///< CmdReg @@ -63,7 +63,7 @@ #define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr #define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability -#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR) +#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2ul ///< PSP Private Block Base Address (PSP_ADDR) #define D8F0x44_PmNxtPtrW_MASK 0xff @@ -102,6 +102,28 @@ typedef struct { +#define PSP_SMM_COMMUNICATION_TYPE_S3SCRIPT 0x1 ///< PspCommunicationType for S3 script + +/// PSP communication structure for S3SCRIPT +typedef struct { + UINT64 PspBar3PciAddr; /// PCI address for PSP BAR3 + UINT32 PspBar3Val; /// PCI register value for PSP BAR3 + UINT64 Pspx48PciAddr; /// PCI address for PSP Register 48 + UINT32 Pspx48Val; /// PCI register value for PSP Register 48 +} PSP_SMM_COMMUNICATION_S3SCRIPT; + +/// Union for PSP_SMM_COMMUNICATE_DATA +typedef union _PSP_SMM_COMMUNICATE_DATA { + PSP_SMM_COMMUNICATION_S3SCRIPT S3Script; ///< S3Script +} PSP_SMM_COMMUNICATE_DATA; + +/// PSP communication header +typedef struct { + UINT32 PspCommunicationType; ///< Type of smm communication buffer + PSP_SMM_COMMUNICATE_DATA Data; ///< Communication buffer +} PSP_SMM_COMMUNICATION_BUFFER; + + UINT32 PspLibPciReadConfig ( IN UINT32 Register @@ -131,9 +153,20 @@ GetPspDirBase ( BOOLEAN PSPEntryInfo ( - IN PSP_DIRECTORY_ENTRY_TYPE EntryType, - IN OUT UINT64 *EntryAddress, - IN UINT32 *EntrySize + IN PSP_DIRECTORY_ENTRY_TYPE EntryType, + IN OUT UINT64 *EntryAddress, + IN OUT UINT32 *EntrySize + ); + +BOOLEAN +PspSoftWareFuseInfo ( + IN OUT UINTN *FuseSpiAddress, + IN OUT UINT64 *FuseValue + ); + +VOID +UpdataPspDirCheckSum ( + IN OUT PSP_DIRECTORY *PspDir ); BOOLEAN @@ -161,6 +194,15 @@ GetPspBar3Addr ( IN OUT UINT32 *PspMmio ); +VOID +AcquirePspSmiRegMutex ( + VOID + ); + +VOID +ReleasePspSmiRegMutex ( + VOID + ); BOOLEAN GetPspMboxStatus ( @@ -169,7 +211,7 @@ GetPspMboxStatus ( BOOLEAN -PspBarInitEarly (VOID); +PspBarInitEarly (); VOID PspLibPciIndirectRead ( @@ -187,12 +229,8 @@ PspLibPciIndirectWrite ( IN VOID *Value ); -UINT8 -PspLibAccessWidth ( - IN ACCESS_WIDTH AccessWidth - ); - BOOLEAN -IsS3Resume (VOID); +IsS3Resume (); + #endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h index 193cc6506c..e3fdd8d115 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h @@ -8,11 +8,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: PSP - * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * @e \$Revision$ @e \$Date$ */ /***************************************************************************** * - * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -51,6 +51,7 @@ typedef struct _FIRMWARE_ENTRY_TABLE { UINT32 GecRomBase; ///< Base Address for Gmc Firmware UINT32 XHCRomBase; ///< Base Address for XHCI Firmware UINT32 PspDirBase; ///< Base Address for PSP directory + UINT32 NewPspDirBase; ///< Base Address of PSP directory from program start from ST } FIRMWARE_ENTRY_TABLE; /// Define structure for PSP directory @@ -64,16 +65,32 @@ typedef struct { /// define various enum type for PSP entry type enum _PSP_DIRECTORY_ENTRY_TYPE { - AMD_PUBLIC_KEY = 0, ///< PSP entry pointer to AMD public key - PSP_FW_BOOT_LOADER = 1, ///< PSP entry points to PSP boot loader in SPI space - PSP_FW_TRUSTED_OS = 2, ///< PSP entry points to PSP Firmware region in SPI space - PSP_FW_RECOVERY_BOOT_LOADER = 3, ///< PSP entry point to PSP recovery region. - PSP_NV_DATA = 4, ///< PSP entry points to PSP data region in SPI space - BIOS_PUBLIC_KEY = 5, ///< PSP entry points to BIOS public key stored in SPI space - BIOS_RTM_FIRMWARE = 6, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space - BIOS_RTM_SIGNATURE = 7, ///< PSP entry points to signed BIOS RTM hash stored in SPI space - SMU_OFFCHIP_FW = 8 ///< PSP entry points to SMU image + AMD_PUBLIC_KEY = 0x00, ///< PSP entry pointer to AMD public key + PSP_FW_BOOT_LOADER = 0x01, ///< PSP entry points to PSP boot loader in SPI space + PSP_FW_TRUSTED_OS = 0x02, ///< PSP entry points to PSP Firmware region in SPI space + PSP_FW_RECOVERY_BOOT_LOADER = 0x03, ///< PSP entry point to PSP recovery region. + PSP_NV_DATA = 0x04, ///< PSP entry points to PSP data region in SPI space + BIOS_PUBLIC_KEY = 0x05, ///< PSP entry points to BIOS public key stored in SPI space + BIOS_RTM_FIRMWARE = 0x06, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space + BIOS_RTM_SIGNATURE = 0x07, ///< PSP entry points to signed BIOS RTM hash stored in SPI space + SMU_OFFCHIP_FW = 0x08, ///< PSP entry points to SMU image + AMD_SEC_DBG_PUBLIC_KEY = 0x09, ///< PSP entry pointer to Secure Unlock Public key + OEM_PSP_FW_PUBLIC_KEY = 0x0A, ///< PSP entry pointer to an optional public part of the OEM PSP Firmware Signing Key Token + AMD_SOFT_FUSE_CHAIN_01 = 0x0B, ///< PSP entry pointer to 64bit PSP Soft Fuse Chain + PSP_BOOT_TIME_TRUSTLETS = 0x0C, ///< PSP entry points to boot-loaded trustlet binaries + PSP_BOOT_TIME_TRUSTLETS_KEY = 0x0D, ///< PSP entry points to key of the boot-loaded trustlet binaries + PSP_AGESA_RESUME_FW = 0x10, ///< PSP Entry points to PSP Agesa-Resume-Firmware + SMU_OFF_CHIP_FW_2 = 0x12, ///< PSP entry points to secondary SMU image + PSP_S3_NV_DATA = 0x1A, ///< PSP entry pointer to S3 Data Blob + AMD_SCS_BINARY = 0x5F, ///< Software Configuration Settings Data Block }; + +#define PSP_ENTRY_PROGRAM_ID_0 0 ///< Program identifier 0, used when two programs share the same root key +#define PSP_ENTRY_PROGRAM_ID_1 1 ///< Program identifier 1, used when two programs share the same root key + +#define PSP_ENTRY_CZ_PROGRAM_ID PSP_ENTRY_PROGRAM_ID_0 ///< CZ Program identifier +#define PSP_ENTRY_BR_PROGRAM_ID PSP_ENTRY_PROGRAM_ID_1 ///< BR Program identifier + typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE; /// Structure for PSP Entry |