diff options
| author | Zheng Bao <fishbaozi@gmail.com> | 2021-12-06 23:09:37 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 23:57:06 +0000 |
| commit | 8b54c0e04bc3488a6479180b3cb9547b4e0fc763 (patch) | |
| tree | ad204fae0fa75a162b8f44a5778b895564fc673c /src/vendorcode | |
| parent | 2a404b599b3385b3246a2ee20844d2bc7a428035 (diff) | |
soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f21ca42169..7cee318126 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -95,7 +95,14 @@ typedef struct __packed { /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; /** Offset 0x04D8**/ struct usb_phy_config *usb_phy; - /** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292]; + /** Offset 0x04DC**/ uint8_t edp_phy_override; + /** Offset 0x04DD**/ uint8_t edp_physel; + /** Offset 0x04DE**/ uint8_t dp_vs_pemph_level; + /** Offset 0x04DF**/ uint8_t tx_eq_main; + /** Offset 0x04E0**/ uint8_t tx_eq_pre; + /** Offset 0x04E1**/ uint8_t tx_eq_post; + /** Offset 0x04E2**/ uint8_t tx_vboost_lvl; + /** Offset 0x04E3**/ uint8_t UnusedUpdSpace2[285]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; |