amd/*/gcccar.inc: Replace local declarations

Although useful to declare local symbols inside macros clang does not
support them. Using the \@ symbol which increments each time the macro
is used we can do the same. With BUILD_TIMELESS=1 the binaries don't
change and do build with GCC so nothing is lost here.

Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

5 files changed, 187 insertions, 268 deletions

diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 95dd74d6cb..ad9ff6ad34 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -245,7 +245,6 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
 *     SI[31:27]= reserved, =0
 ****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID
-    LOCAL  node_core_exit
 
     mov     $-1, %si
     GET_NODE_ID_CORE_ID_F10
@@ -256,16 +255,16 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
      * Check for unrecognized Family
      */
     cmp     $-1, %si                      # Has family (node/core) already been discovered?
-    jnz     node_core_exit              # Br if yes
+    jnz     node_core_exit\@              # Br if yes
 
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
 
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_exit              # Br if yes
+    jc      node_core_exit\@              # Br if yes
     hlt                                 # Kill APs
-node_core_exit:
+node_core_exit\@:
 
 .endm
 
@@ -297,12 +296,11 @@ node_core_exit:
 #   * No INVD or WBINVD, no exceptions, page faults or interrupts
 ****************************************************************************/
 .macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
-    LOCAL   fam10_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x01, %al                      # Is this family 10h?
-    jnz     fam10_enable_stack_hook_exit # Br if no
+    jnz     fam10_enable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -333,7 +331,7 @@ node_core_exit:
 fam10_skipClearingBit4:
     mov %esi, %eax                         # load core#
     or %al, %al                       # If (BSP)
-    jne  fam10_enable_stack_hook_exit
+    jne  fam10_enable_stack_hook_exit\@
     mov     $PERF_COUNTER3, %ecx       #   Select performance counter three
                                         #   to count number of CAR evictions
     xor     %eax, %eax                #   Initialize the lower part of the counter to zero
@@ -350,7 +348,7 @@ fam10_skipClearingBit4:
     bts     $EVENT_ENABLE, %eax        #   Enable it
     _WRMSR                          #   Save it
 
-fam10_enable_stack_hook_exit:
+fam10_enable_stack_hook_exit\@:
 .endm
 
 /****************************************************************************
@@ -378,7 +376,6 @@ fam10_enable_stack_hook_exit:
 *****************************************************************************/
 
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F10
-    LOCAL   fam10_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
@@ -448,22 +445,20 @@ fam10_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F10
 
-    LOCAL   node_core_f10_exit
-    LOCAL   node_core_f10_AP
 
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f10_exit          # Br if yes
+    jnz     node_core_f10_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x01, %al                     # Is this family 10h?
-    jnz     node_core_f10_exit          # Br if no
+    jnz     node_core_f10_exit\@          # Br if no
 
     xor     %esi, %esi                    # Assume BSC, clear flags
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax             # Is this the BSC?
-    jnc      node_core_f10_AP            # Br if no
+    jnc      node_core_f10_AP\@            # Br if no
 
         # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -476,7 +471,7 @@ fam10_disable_stack_hook_exit:
     out     %eax, %dx
     jmp     1f          #
 
-node_core_f10_AP:
+node_core_f10_AP\@:
     #
     # This is an AP. Routing tables have been enabled by the HT Init process.
     # Also, the MailBox register was set by the BSP during early init
@@ -532,7 +527,7 @@ node_core_f10_AP:
     mov     %eax, %esi                    # ESI = return value
 1:
  bts     $FLAG_IS_PRIMARY, %esi        # all Family 10h cores are primary
-node_core_f10_exit:
+node_core_f10_exit\@:
 .endm
 
 
@@ -564,12 +559,11 @@ node_core_f10_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F12
-    LOCAL   fam12_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x03, %al                     # Is this family 12h?
-    jnz     fam12_enable_stack_hook_exit # Br if no
+    jnz     fam12_enable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -601,7 +595,7 @@ fam12_skipClearingBit4:
     bts     $CL_FLUSH_SERIALIZE, %eax     # Serialize all CL Flush actions
     _WRMSR
 
-fam12_enable_stack_hook_exit:
+fam12_enable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -627,12 +621,11 @@ fam12_enable_stack_hook_exit:
 *   * MSRC001_1029[ClflushSerialize]=0
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F12
-    LOCAL   fam12_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x03, %al                     # Is this family 12h?
-    jnz     fam12_disable_stack_hook_exit # Br if no
+    jnz     fam12_disable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -673,7 +666,7 @@ fam12_enable_stack_hook_exit:
     # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------
 
-fam12_disable_stack_hook_exit:
+fam12_disable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -690,20 +683,19 @@ fam12_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F12
 
-    LOCAL   node_core_f12_exit
 
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f12_exit          # Br if yes
+    jnz     node_core_f12_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x03, %al                     # Is this family 12h?
-    jnz     node_core_f12_exit          # Br if no
+    jnz     node_core_f12_exit\@          # Br if no
 
     shr     $24, %ebx                     # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
     bts     $FLAG_IS_PRIMARY, %ebx        # all family 12h cores are primary
     mov     %ebx, %esi                    # ESI = Node#=0, core number
-node_core_f12_exit:
+node_core_f12_exit\@:
 .endm
 
 /*****************************************************************************
@@ -730,12 +722,11 @@ node_core_f12_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F14
-    LOCAL   fam14_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x05, %al                     # Is this family 14h?
-    jnz     fam14_enable_stack_hook_exit # Br if no
+    jnz     fam14_enable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -760,7 +751,7 @@ node_core_f12_exit:
     _WRMSR
 fam14_skipClearingBit4:                 # Keeping this label
 
-fam14_enable_stack_hook_exit:
+fam14_enable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -783,12 +774,11 @@ fam14_enable_stack_hook_exit:
 *   * MSRC001_1022[DIS_HW_PF]=0.
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F14
-    LOCAL   fam14_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x05, %al                     # Is this family 14h?
-    jnz     fam14_disable_stack_hook_exit # Br if no
+    jnz     fam14_disable_stack_hook_exit\@ # Br if no
 
     mov     $LS_CFG, %ecx                 # MSR:C001_1020
     _RDMSR
@@ -821,7 +811,7 @@ fam14_enable_stack_hook_exit:
     # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------
 
-fam14_disable_stack_hook_exit:
+fam14_disable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -838,24 +828,23 @@ fam14_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F14
 
-    LOCAL   node_core_f14_exit
 
     cmp     $-1, %si                    # Has node/core already been discovered?
-    jnz     node_core_f14_exit          # Br if yes
+    jnz     node_core_f14_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x05, %al                     # Is this family 14h?
-    jnz     node_core_f14_exit          # Br if no
+    jnz     node_core_f14_exit\@          # Br if no
 
     xor     %esi, %esi                    # Node must be 0
     bts     $FLAG_IS_PRIMARY, %esi        # all family 14h cores are primary
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_f14_exit          # Br if yes
+    jc      node_core_f14_exit\@          # Br if yes
     inc     %si                          # Set core to 1
-node_core_f14_exit:
+node_core_f14_exit\@:
 .endm
 
 
@@ -885,12 +874,11 @@ node_core_f14_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F15
-    LOCAL   fam15_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x06, %al                     # Is this family 15h?
-    jnz     fam15_enable_stack_hook_exit # Br if no
+    jnz     fam15_enable_stack_hook_exit\@ # Br if no
 
     bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
     jc      fam15_skipClearingBit4
@@ -921,7 +909,7 @@ fam15_skipClearingBit4:
     btr     $(COMBINE_CR0_CD - 32), %edx         # Clear CombineCr0Cd bit
     _WRMSR
 
-fam15_enable_stack_hook_exit:
+fam15_enable_stack_hook_exit\@:
 .endm
 
 
@@ -946,13 +934,12 @@ fam15_enable_stack_hook_exit:
 *   * MSRC001_1022[DIS_HW_PF]=0
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F15
-    LOCAL   fam15_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                    # Save revision info to EBX
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x06, %al                     # Is this family 15h?
-    jnz     fam15_disable_stack_hook_exit # Br if no
+    jnz     fam15_disable_stack_hook_exit\@ # Br if no
 
     mov     $LS_CFG, %ecx                 # MSR:C001_1020
     #.if (ebx != 00600F00h)              ; Is this rev A0?
@@ -1005,7 +992,7 @@ fam15_enable_stack_hook_exit:
     bts     $(COMBINE_CR0_CD - 32), %edx         # Set CombineCr0Cd bit
     _WRMSR
 
-fam15_disable_stack_hook_exit:
+fam15_disable_stack_hook_exit\@:
 .endm
 
 
@@ -1023,23 +1010,20 @@ fam15_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F15
 
-    LOCAL   node_core_f15_exit
-    LOCAL   node_core_f15_AP
-    LOCAL   node_core_f15_shared
 
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f15_exit          # Br if yes
+    jnz     node_core_f15_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $06, %al                     # Is this family 15h?
-    jnz     node_core_f15_exit          # Br if no
+    jnz     node_core_f15_exit\@          # Br if no
 
     xor     %esi, %esi                    # Assume BSC, clear local flags
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jnc      node_core_f15_AP            # Br if no
+    jnc      node_core_f15_AP\@            # Br if no
 
     # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -1050,9 +1034,9 @@ fam15_disable_stack_hook_exit:
     in      %dx, %eax
     btr     $0, %eax                      # Set LinkInitializationControl[RouteTblDis] = 0
     out     %eax, %dx
-    jmp     node_core_f15_shared        #
+    jmp     node_core_f15_shared\@        #
 
-node_core_f15_AP:
+node_core_f15_AP\@:
     #
     # This is an AP. Routing tables have been enabled by the HT Init process.
     # Also, the MailBox register was set by the BSP during early init
@@ -1110,7 +1094,7 @@ node_core_f15_AP:
       #
       #   determine if this core shares MTRRs
       #
-node_core_f15_shared:
+node_core_f15_shared\@:
     mov     $0x8000C580, %eax              # Compute Unit Status
     mov     %si, %bx
     shl     $3, %bh                       # Move node# to PCI Dev# field
@@ -1173,7 +1157,7 @@ node_core_f15_shared:
     #.endif
     2:
 
-node_core_f15_exit:
+node_core_f15_exit\@:
 
 .endm
 
@@ -1245,10 +1229,6 @@ node_core_f15_exit:
 .macro  AMD_ENABLE_STACK
 
 # These are local labels. Declared so linker doesn't cause 'redefined label' errors
-    LOCAL   SetupStack
-    LOCAL   Real16bMode
-    LOCAL   Protected32Mode
-    LOCAL   ClearTheStack
 
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
@@ -1262,14 +1242,14 @@ node_core_f15_exit:
     # It is =0 after reset; CAR setup sets it to enable the MTRRs
     mov     %cr0, %eax
     test    $CR0_MASK, %eax              # Is cache disabled? (CD & NW bits)
-    jnz     SetupStack                  # Jump if yes
+    jnz     SetupStack\@                  # Jump if yes
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR
     test    $MSR_MASK, %eax                     # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
-    jz      SetupStack                  # Jump if no
+    jz      SetupStack\@                  # Jump if no
     or      $FLAG_STACK_REENTRY, %esi             # Bit25, indicate stack has already been initialized
 
-SetupStack:
+SetupStack\@:
     # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
     mov     %esi, %ebx                    # Get my Node/Core info
     xor     %bl, %bl
@@ -1500,12 +1480,12 @@ SetupStack:
     mov     %cr0, %ecx                    # Check for 32-bit protect mode
     bt      $CR0_PE, %ecx                 #
     #.if (!carry?)                       # PE=0 means real mode
-    jc      Protected32Mode
+    jc      Protected32Mode\@
     mov     %cs, %cx                      # PE=1
     cmp     $0x0D000, %cx                  # Check for CS
-    jb      Protected32Mode             # If CS < D000, it is a selector instead of a segment
+    jb      Protected32Mode\@             # If CS < D000, it is a selector instead of a segment
             # alter SS:ESP for 16b Real Mode:
-Real16bMode:
+Real16bMode\@:
     mov     %edi, %eax
     shr     $4, %eax                      # Create a Real Mode segment for ss, ds, es
     mov     %ax, %ss
@@ -1520,7 +1500,7 @@ Real16bMode:
     #   Default is to use Protected 32b Mode
     #.endif
     ;
-Protected32Mode:
+Protected32Mode\@:
     #
     # Clear The Stack
     #   Now that we have set the location and the MTRRs, initialize the cache by
@@ -1533,7 +1513,7 @@ Protected32Mode:
     #       edi -  address of start of stack block
     #
 
-ClearTheStack:                          # Stack base is in SS, stack pointer is in ESP
+ClearTheStack\@:                          # Stack base is in SS, stack pointer is in ESP
     shr     $2, %ebx                      # ebx = stack block size in dwords
     mov     %bx, %cx                      #
     # Check our flags - Don't clear an existing stack
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index fb49c17c59..6a3ebaf7f8 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -286,7 +286,6 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
 *     SI[31:27]= reserved, =0
 ****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID
-    LOCAL  node_core_exit
 
     mov     $-1, %si
     GET_NODE_ID_CORE_ID_F10
@@ -297,16 +296,16 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
      * Check for unrecognized Family
      */
     cmp     $-1, %si                      # Has family (node/core) already been discovered?
-    jnz     node_core_exit              # Br if yes
+    jnz     node_core_exit\@              # Br if yes
 
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
 
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_exit              # Br if yes
+    jc      node_core_exit\@              # Br if yes
     hlt                                 # Kill APs
-node_core_exit:
+node_core_exit\@:
 
 .endm
 
@@ -338,12 +337,11 @@ node_core_exit:
 #   * No INVD or WBINVD, no exceptions, page faults or interrupts
 ****************************************************************************/
 .macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
-    LOCAL   fam10_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x01, %al                      # Is this family 10h?
-    jnz     fam10_enable_stack_hook_exit # Br if no
+    jnz     fam10_enable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -374,7 +372,7 @@ node_core_exit:
 fam10_skipClearingBit4:
     mov %esi, %eax                         # load core#
     or %al, %al                       # If (BSP)
-    jne  fam10_enable_stack_hook_exit
+    jne  fam10_enable_stack_hook_exit\@
     mov     $PERF_COUNTER3, %ecx       #   Select performance counter three
                                         #   to count number of CAR evictions
     xor     %eax, %eax                #   Initialize the lower part of the counter to zero
@@ -391,7 +389,7 @@ fam10_skipClearingBit4:
     bts     $EVENT_ENABLE, %eax        #   Enable it
     _WRMSR                          #   Save it
 
-fam10_enable_stack_hook_exit:
+fam10_enable_stack_hook_exit\@:
 .endm
 
 /****************************************************************************
@@ -419,12 +417,11 @@ fam10_enable_stack_hook_exit:
 *****************************************************************************/
 
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F10
-    LOCAL   fam10_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x01, %al                     # Is this family 10h?
-    jnz     fam10_disable_stack_hook_exit # Br if no
+    jnz     fam10_disable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -465,14 +462,14 @@ fam10_enable_stack_hook_exit:
     mov     $PERF_CONTROL3, %ecx          # Select the event control three
     _RDMSR                              # Retrieve the current value
     btc     $EVENT_ENABLE, %eax           # Is event enable, complement it as well
-    jnc     fam10_disable_stack_hook_exit # No
+    jnc     fam10_disable_stack_hook_exit\@ # No
     cmp     $CONFIG_EVENT_L, %ax          # Is the lower part of event set to capture the CAR Corruption
-    jne     fam10_disable_stack_hook_exit # No
+    jne     fam10_disable_stack_hook_exit\@ # No
     cmp     $CONFIG_EVENT_H, %dl        # Is the upper part of event set to capture the CAR Corruption
-    jne     fam10_disable_stack_hook_exit # No
+    jne     fam10_disable_stack_hook_exit\@ # No
     _WRMSR                              # Disable the event
 
-fam10_disable_stack_hook_exit:
+fam10_disable_stack_hook_exit\@:
 .endm
 
 /****************************************************************************
@@ -489,22 +486,20 @@ fam10_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F10
 
-    LOCAL   node_core_f10_exit
-    LOCAL   node_core_f10_AP
 
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f10_exit          # Br if yes
+    jnz     node_core_f10_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x01, %al                     # Is this family 10h?
-    jnz     node_core_f10_exit          # Br if no
+    jnz     node_core_f10_exit\@          # Br if no
 
     xor     %esi, %esi                    # Assume BSC, clear flags
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax             # Is this the BSC?
-    jnc      node_core_f10_AP            # Br if no
+    jnc      node_core_f10_AP\@            # Br if no
 
         # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -517,7 +512,7 @@ fam10_disable_stack_hook_exit:
     out     %eax, %dx
     jmp     1f          #
 
-node_core_f10_AP:
+node_core_f10_AP\@:
     #
     # This is an AP. Routing tables have been enabled by the HT Init process.
     # Also, the MailBox register was set by the BSP during early init
@@ -573,7 +568,7 @@ node_core_f10_AP:
     mov     %eax, %esi                    # ESI = return value
 1:
  bts     $FLAG_IS_PRIMARY, %esi        # all Family 10h cores are primary
-node_core_f10_exit:
+node_core_f10_exit\@:
 .endm
 
 /*****************************************************************************
@@ -604,12 +599,11 @@ node_core_f10_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F12
-    LOCAL   fam12_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x03, %al                     # Is this family 12h?
-    jnz     fam12_enable_stack_hook_exit # Br if no
+    jnz     fam12_enable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -641,7 +635,7 @@ fam12_skipClearingBit4:
     bts     $CL_FLUSH_SERIALIZE, %eax     # Serialize all CL Flush actions
     _WRMSR
 
-fam12_enable_stack_hook_exit:
+fam12_enable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -667,12 +661,11 @@ fam12_enable_stack_hook_exit:
 *   * MSRC001_1029[ClflushSerialize]=0
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F12
-    LOCAL   fam12_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x03, %al                     # Is this family 12h?
-    jnz     fam12_disable_stack_hook_exit # Br if no
+    jnz     fam12_disable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -713,7 +706,7 @@ fam12_enable_stack_hook_exit:
     # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------
 
-fam12_disable_stack_hook_exit:
+fam12_disable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -730,20 +723,19 @@ fam12_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F12
 
-    LOCAL   node_core_f12_exit
 
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f12_exit          # Br if yes
+    jnz     node_core_f12_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x03, %al                     # Is this family 12h?
-    jnz     node_core_f12_exit          # Br if no
+    jnz     node_core_f12_exit\@          # Br if no
 
     shr     $24, %ebx                     # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
     bts     $FLAG_IS_PRIMARY, %ebx        # all family 12h cores are primary
     mov     %ebx, %esi                    # ESI = Node#=0, core number
-node_core_f12_exit:
+node_core_f12_exit\@:
 .endm
 
 /*****************************************************************************
@@ -770,12 +762,11 @@ node_core_f12_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F14
-    LOCAL   fam14_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x05, %al                     # Is this family 14h?
-    jnz     fam14_enable_stack_hook_exit # Br if no
+    jnz     fam14_enable_stack_hook_exit\@ # Br if no
 
     mov     $DC_CFG, %ecx                 # MSR:C001_1022
     _RDMSR
@@ -800,7 +791,7 @@ node_core_f12_exit:
     _WRMSR
 fam14_skipClearingBit4:                 # Keeping this label
 
-fam14_enable_stack_hook_exit:
+fam14_enable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -823,12 +814,11 @@ fam14_enable_stack_hook_exit:
 *   * MSRC001_1022[DIS_HW_PF]=0.
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F14
-    LOCAL   fam14_disable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x05, %al                     # Is this family 14h?
-    jnz     fam14_disable_stack_hook_exit # Br if no
+    jnz     fam14_disable_stack_hook_exit\@ # Br if no
 
     mov     $LS_CFG, %ecx                 # MSR:C001_1020
     _RDMSR
@@ -861,7 +851,7 @@ fam14_enable_stack_hook_exit:
     # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------
 
-fam14_disable_stack_hook_exit:
+fam14_disable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -878,24 +868,23 @@ fam14_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F14
 
-    LOCAL   node_core_f14_exit
 
     cmp     $-1, %si                    # Has node/core already been discovered?
-    jnz     node_core_f14_exit          # Br if yes
+    jnz     node_core_f14_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x05, %al                     # Is this family 14h?
-    jnz     node_core_f14_exit          # Br if no
+    jnz     node_core_f14_exit\@          # Br if no
 
     xor     %esi, %esi                    # Node must be 0
     bts     $FLAG_IS_PRIMARY, %esi        # all family 14h cores are primary
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_f14_exit          # Br if yes
+    jc      node_core_f14_exit\@          # Br if yes
     inc     %si                          # Set core to 1
-node_core_f14_exit:
+node_core_f14_exit\@:
 .endm
 
 /*****************************************************************************
@@ -923,13 +912,12 @@ node_core_f14_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F15
-    LOCAL   fam15_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                # Save revision info to EBX
     shr     $20, %eax                 # AL = cpu extended family
     cmp     $0x06, %al                     # Is this family 15h?
-    jnz     fam15_enable_stack_hook_exit # Br if no
+    jnz     fam15_enable_stack_hook_exit\@ # Br if no
 
     bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
     jc      fam15_skipClearingBit4
@@ -1023,7 +1011,7 @@ fam15_skipClearingBit4:
     btr     $(COMBINE_CR0_CD - 32), %edx         # Clear CombineCr0Cd bit
     _WRMSR
 
-fam15_enable_stack_hook_exit:
+fam15_enable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -1047,14 +1035,12 @@ fam15_enable_stack_hook_exit:
 *   * MSRC001_1022[DIS_HW_PF]=0
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F15
-    LOCAL   fam15_disable_stack_hook_exit
-    LOCAL   fam15_disable_stack_remote_read_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                    # Save revision info to EBX
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x06, %al                     # Is this family 15h?
-    jnz     fam15_disable_stack_hook_exit # Br if no
+    jnz     fam15_disable_stack_hook_exit\@ # Br if no
 
     mov     %ebx, %edi                    # Save revision info to EDI
     AMD_CPUID  $AMD_CPUID_APIC
@@ -1170,7 +1156,7 @@ fam15_enable_stack_hook_exit:
                     cmp     $REMOTE_DELIVERY_PEND, %eax
                     jnz      8f
                     dec     %ch               # Check the timeout
-                    jz      fam15_disable_stack_hook_exit # Branch if there is an unreponsive core
+                    jz      fam15_disable_stack_hook_exit\@ # Branch if there is an unreponsive core
                     stc
                 jmp     9f
 8:              #.else
@@ -1300,7 +1286,7 @@ fam15_disable_stack_remote_read_exit:
 
 1:  #.endif
 
-fam15_disable_stack_hook_exit:
+fam15_disable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -1317,10 +1303,6 @@ fam15_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F15
 
-    LOCAL   node_core_f15_exit
-    LOCAL   node_core_f15_AP
-    LOCAL   node_core_f15_shared
-    LOCAL node_core_f15_AP_not_TN
 
 #define F15_L2Size	512
 #define F15_ShareCores  2
@@ -1329,12 +1311,12 @@ fam15_disable_stack_hook_exit:
 #define F15_SzAddrBus   48
 #define F15_pad         0
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f15_exit          # Br if yes
+    jnz     node_core_f15_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $12, %eax                     # AL = cpu extended family
     cmp     $06, %ah                     # Is this family 15h?
-    jnz     node_core_f15_exit          # Br if no
+    jnz     node_core_f15_exit\@          # Br if no
     shr     $4,  %al                     # AL = cpu extended model
     shr     $16, %ebx                    # BH = LocalApicId
     mov     %al, %bl                     # BL = cpu extended model
@@ -1346,7 +1328,7 @@ fam15_disable_stack_hook_exit:
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jnc      node_core_f15_AP            # Br if no
+    jnc      node_core_f15_AP\@            # Br if no
 
     # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -1357,17 +1339,17 @@ fam15_disable_stack_hook_exit:
     in      %dx, %eax
     btr     $0, %eax                      # Set LinkInitializationControl[RouteTblDis] = 0
     out     %eax, %dx
-    jmp     node_core_f15_shared        #
+    jmp     node_core_f15_shared\@        #
 
-node_core_f15_AP:
+node_core_f15_AP\@:
     mov     %bl, %al                        # AL = cpu extended model
     shr     $8,  %bx                        # BL = CPUID Fn0000_0001_EBX[LocalApicId]
     cmp    $1,  %al                        # Is This TN?
     jz     4f
     cmp    $3,  %al
-    jnz    node_core_f15_AP_not_TN
+    jnz    node_core_f15_AP_not_TN\@
 4:  mov     %bx, %si
-    jmp     node_core_f15_shared
+    jmp     node_core_f15_shared\@
     #
     # This is an AP. Routing tables have been enabled by the HT Init process.
     # Also, the MailBox register was set by the BSP during early init
@@ -1378,7 +1360,7 @@ node_core_f15_AP:
     #         UINT32 ModuleType:2;    // Single Module = 0, Multi-module = 1.
     #         UINT32 :20;             // Reserved
     #
-node_core_f15_AP_not_TN:
+node_core_f15_AP_not_TN\@:
     mov     $0x0C0000408, %ecx             # Read the family 15h mailbox
     _RDMSR                              #      MC4_MISC1[63:32]
     mov     %dx, %si                      # SI = raw mailbox contents (will extract node# from this)
@@ -1426,7 +1408,7 @@ node_core_f15_AP_not_TN:
       #
       #   determine if this core shares MTRRs
       #
-node_core_f15_shared:
+node_core_f15_shared\@:
     mov     $0x8000C580, %eax              # Compute Unit Status
     mov     %si, %bx
     shl     $3, %bh                       # Move node# to PCI Dev# field
@@ -1489,7 +1471,7 @@ node_core_f15_shared:
     #.endif
     2:
 
-node_core_f15_exit:
+node_core_f15_exit\@:
 
 .endm
 
@@ -1561,10 +1543,6 @@ node_core_f15_exit:
 .macro  AMD_ENABLE_STACK
 
 # These are local labels. Declared so linker doesn't cause 'redefined label' errors
-    LOCAL   SetupStack
-    LOCAL   Real16bMode
-    LOCAL   Protected32Mode
-    LOCAL   ClearTheStack
 
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
@@ -1578,14 +1556,14 @@ node_core_f15_exit:
     # It is =0 after reset; CAR setup sets it to enable the MTRRs
     mov     %cr0, %eax
     test    $CR0_MASK, %eax              # Is cache disabled? (CD & NW bits)
-    jnz     SetupStack                  # Jump if yes
+    jnz     SetupStack\@                  # Jump if yes
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR
     test    $MSR_MASK, %eax                     # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
-    jz      SetupStack                  # Jump if no
+    jz      SetupStack\@                  # Jump if no
     or      $FLAG_STACK_REENTRY, %esi             # Bit25, indicate stack has already been initialized
 
-SetupStack:
+SetupStack\@:
     # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
     mov     %esi, %ebx                    # Get my Node/Core info
     xor     %bl, %bl
@@ -1816,12 +1794,12 @@ SetupStack:
     mov     %cr0, %ecx                    # Check for 32-bit protect mode
     bt      $CR0_PE, %ecx                 #
     #.if (!carry?)                       # PE=0 means real mode
-    jc      Protected32Mode
+    jc      Protected32Mode\@
     mov     %cs, %cx                      # PE=1
     cmp     $0x0D000, %cx                  # Check for CS
-    jb      Protected32Mode             # If CS < D000, it is a selector instead of a segment
+    jb      Protected32Mode\@             # If CS < D000, it is a selector instead of a segment
             # alter SS:ESP for 16b Real Mode:
-Real16bMode:
+Real16bMode\@:
     mov     %edi, %eax
     shr     $4, %eax                      # Create a Real Mode segment for ss, ds, es
     mov     %ax, %ss
@@ -1836,7 +1814,7 @@ Real16bMode:
     #   Default is to use Protected 32b Mode
     #.endif
     ;
-Protected32Mode:
+Protected32Mode\@:
     #
     # Clear The Stack
     #   Now that we have set the location and the MTRRs, initialize the cache by
@@ -1849,7 +1827,7 @@ Protected32Mode:
     #       edi -  address of start of stack block
     #
 
-ClearTheStack:                          # Stack base is in SS, stack pointer is in ESP
+ClearTheStack\@:                          # Stack base is in SS, stack pointer is in ESP
     shr     $2, %ebx                      # ebx = stack block size in dwords
     mov     %bx, %cx                      #
     # Check our flags - Don't clear an existing stack
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 9c7bf47f43..cffebffbe1 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -281,7 +281,6 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
 *     SI[31:27]= reserved, =0
 ****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID
-    LOCAL  node_core_exit
 
     mov     $-1, %si
     GET_NODE_ID_CORE_ID_F16
@@ -290,16 +289,16 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
      * Check for unrecognized Family
      */
     cmp     $-1, %si                      # Has family (node/core) already been discovered?
-    jnz     node_core_exit              # Br if yes
+    jnz     node_core_exit\@              # Br if yes
 
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
 
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_exit              # Br if yes
+    jc      node_core_exit\@              # Br if yes
     hlt                                 # Kill APs
-node_core_exit:
+node_core_exit\@:
 
 .endm
 
@@ -335,13 +334,12 @@ Family 16h requirements (BKDG #48751 section 2.3.3):
 	*/
 
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F16
-    LOCAL   fam16_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                # Save revision info to EBX
     shr     $20, %eax                 # AL = cpu extended family
     cmp     $0x07, %al                     # Is this family 16h?
-    jnz     fam16_enable_stack_hook_exit # Br if no
+    jnz     fam16_enable_stack_hook_exit\@ # Br if no
 
     bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
     jc      fam16_skipClearingBit4
@@ -373,7 +371,7 @@ fam16_skipClearingBit4:
     bts     $CACHE_IC_ATTR_DIS, %eax
     _WRMSR
 
-fam16_enable_stack_hook_exit:
+fam16_enable_stack_hook_exit\@:
 .endm
 
 /*
@@ -400,15 +398,12 @@ fam16_enable_stack_hook_exit:
 ;---------------------------------------------------
 */
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F16
-    LOCAL   fam16_disable_stack_hook_exit
-    LOCAL   fam16_disable_stack_remote_read_exit
-#    LOCAL   fam16_invd_done_remote_read_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                    # Save revision info to EBX
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x07, %al                     # Is this family 16h?
-    jnz     fam16_disable_stack_hook_exit # Br if no
+    jnz     fam16_disable_stack_hook_exit\@ # Br if no
 
     mov     %ebx, %edi                    # Save revision info to EDI
     AMD_CPUID  $AMD_CPUID_APIC
@@ -510,7 +505,7 @@ fam16_enable_stack_hook_exit:
             #.while (carry?)
 7:          jnc     6f
                 dec     %ch                   #Check the timeout
-                jz      fam16_disable_stack_remote_read_exit
+                jz      fam16_disable_stack_remote_read_exit\@
                 mov     %es:(%ebx), %eax      # ax = 0000000000020338
                 bt      $DELIVERY_STS_BIT, %eax
             jmp     7b
@@ -524,7 +519,7 @@ fam16_enable_stack_hook_exit:
                     cmp     $REMOTE_DELIVERY_PEND, %eax
                     jnz      8f
                     dec     %ch               # Check the timeout
-                    jz      fam16_disable_stack_hook_exit # Branch if there is an unreponsive core
+                    jz      fam16_disable_stack_hook_exit\@ # Branch if there is an unreponsive core
                     stc
                 jmp     9f
 8:              #.else
@@ -549,13 +544,13 @@ fam16_enable_stack_hook_exit:
             jmp     7f
 6:          #.else
                 dec     %ch
-                jz      fam16_disable_stack_remote_read_exit
+                jz      fam16_disable_stack_remote_read_exit\@
                 stc
 7:          #.endif
         jmp     5b
 4:      #.endw
 
-fam16_disable_stack_remote_read_exit:
+fam16_disable_stack_remote_read_exit\@:
         rol   $8, %ecx                 # Restore ECX
 
 1:  #.endif
@@ -658,7 +653,7 @@ fam16_disable_stack_remote_read_exit:
             #.while (carry?)
 7:          jnc     6f
                 dec     %ch                   #Check the timeout
-                jz      fam16_invd_done_remote_read_exit
+                jz      fam16_invd_done_remote_read_exit\@
                 mov     %es:(%ebx), %eax      # ax = 0000000000020338
                 bt      $DELIVERY_STS_BIT, %eax
             jmp     7b
@@ -672,7 +667,7 @@ fam16_disable_stack_remote_read_exit:
                     cmp     $REMOTE_DELIVERY_PEND, %eax
                     jnz      8f
                     dec     %ch               # Check the timeout
-                    jz      fam16_invd_done_remote_read_exit # Branch if there is an unreponsive core
+                    jz      fam16_invd_done_remote_read_exit\@ # Branch if there is an unreponsive core
                     stc
                 jmp     9f
 8:              #.else
@@ -697,14 +692,14 @@ fam16_disable_stack_remote_read_exit:
             jmp     7f
 6:          #.else
                 dec     %ch
-                jz      fam16_invd_done_remote_read_exit
+                jz      fam16_invd_done_remote_read_exit\@
                 stc
 7:          #.endif
         jmp     5b
 4:      #.endw
 
      jmp  2f
-fam16_invd_done_remote_read_exit:
+fam16_invd_done_remote_read_exit\@:
 1: #.else
      mov    $APIC_BASE_ADDRESS, %ecx
      _RDMSR
@@ -715,17 +710,13 @@ fam16_invd_done_remote_read_exit:
      mov    %edi,  %es:(%ebx)
 2: #.endif
 
-fam16_disable_stack_hook_exit:
+fam16_disable_stack_hook_exit\@:
 .endm
 
 /*
 */
 .macro  GET_NODE_ID_CORE_ID_F16
 
-    LOCAL   node_core_f16_exit
-    LOCAL   node_core_f16_AP
-    LOCAL   node_core_f16_shared
-    LOCAL node_core_f16_AP_not_TN
 
 #define F16_L2Size	1024
 #define F16_ShareCores  4
@@ -734,12 +725,12 @@ fam16_disable_stack_hook_exit:
 #define F16_SzAddrBus   40
 #define F16_pad         0
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f16_exit          # Br if yes
+    jnz     node_core_f16_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $12, %eax                     # AL = cpu extended family
     cmp     $07, %ah                     # Is this family 16h?
-    jnz     node_core_f16_exit          # Br if no
+    jnz     node_core_f16_exit\@          # Br if no
     shr     $4,  %al                     # AL = cpu extended model
     shr     $16, %ebx                    # BH = LocalApicId
     mov     %al, %bl                     # BL = cpu extended model
@@ -751,7 +742,7 @@ fam16_disable_stack_hook_exit:
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jnc      node_core_f16_AP            # Br if no
+    jnc      node_core_f16_AP\@            # Br if no
 
     # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -764,7 +755,7 @@ fam16_disable_stack_hook_exit:
     out     %eax, %dx
     jmp     6f         #node_core_f16_shared        #
 
-node_core_f16_AP:
+node_core_f16_AP\@:
     mov     %bl, %al                        # AL = cpu extended model
     shr     $8,  %bx                        # BL = CPUID Fn0000_0001_EBX[LocalApicId]
     #.if (al == 0)
@@ -853,7 +844,7 @@ node_core_f16_AP:
     #.endif
     2:
 
-node_core_f16_exit:
+node_core_f16_exit\@:
 
 .endm
 
@@ -925,10 +916,6 @@ node_core_f16_exit:
 .macro  AMD_ENABLE_STACK
 
 # These are local labels. Declared so linker doesn't cause 'redefined label' errors
-    LOCAL   SetupStack
-    LOCAL   Real16bMode
-    LOCAL   Protected32Mode
-    LOCAL   ClearTheStack
 
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
@@ -942,14 +929,14 @@ node_core_f16_exit:
     # It is =0 after reset; CAR setup sets it to enable the MTRRs
     mov     %cr0, %eax
     test    $CR0_MASK, %eax              # Is cache disabled? (CD & NW bits)
-    jnz     SetupStack                  # Jump if yes
+    jnz     SetupStack\@                  # Jump if yes
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR
     test    $MSR_MASK, %eax                     # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
-    jz      SetupStack                  # Jump if no
+    jz      SetupStack\@                  # Jump if no
     or      $FLAG_STACK_REENTRY, %esi             # Bit25, indicate stack has already been initialized
 
-SetupStack:
+SetupStack\@:
     # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
     mov     %esi, %ebx                    # Get my Node/Core info
     xor     %bl, %bl
@@ -1180,12 +1167,12 @@ SetupStack:
     mov     %cr0, %ecx                    # Check for 32-bit protect mode
     bt      $CR0_PE, %ecx                 #
     #.if (!carry?)                       # PE=0 means real mode
-    jc      Protected32Mode
+    jc      Protected32Mode\@
     mov     %cs, %cx                      # PE=1
     cmp     $0x0D000, %cx                  # Check for CS
-    jb      Protected32Mode             # If CS < D000, it is a selector instead of a segment
+    jb      Protected32Mode\@             # If CS < D000, it is a selector instead of a segment
             # alter SS:ESP for 16b Real Mode:
-Real16bMode:
+Real16bMode\@:
     mov     %edi, %eax
     shr     $4, %eax                      # Create a Real Mode segment for ss, ds, es
     mov     %ax, %ss
@@ -1200,7 +1187,7 @@ Real16bMode:
     #   Default is to use Protected 32b Mode
     #.endif
     ;
-Protected32Mode:
+Protected32Mode\@:
     #
     # Clear The Stack
     #   Now that we have set the location and the MTRRs, initialize the cache by
@@ -1213,7 +1200,7 @@ Protected32Mode:
     #       edi -  address of start of stack block
     #
 
-ClearTheStack:                          # Stack base is in SS, stack pointer is in ESP
+ClearTheStack\@:                          # Stack base is in SS, stack pointer is in ESP
     shr     $2, %ebx                      # ebx = stack block size in dwords
     mov     %bx, %cx                      #
     # Check our flags - Don't clear an existing stack
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 152e2799c6..ae0ad37d17 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -290,7 +290,6 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
 *     SI[31:27]= reserved, =0
 ****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID
-    LOCAL  node_core_exit
 
     mov     $-1, %si
     //GET_NODE_ID_CORE_ID_F10
@@ -301,16 +300,16 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
      * Check for unrecognized Family
      */
     cmp     $-1, %si                      # Has family (node/core) already been discovered?
-    jnz     node_core_exit              # Br if yes
+    jnz     node_core_exit\@              # Br if yes
 
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
 
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_exit              # Br if yes
+    jc      node_core_exit\@              # Br if yes
     hlt                                 # Kill APs
-node_core_exit:
+node_core_exit\@:
 
 .endm
 
@@ -340,13 +339,12 @@ node_core_exit:
 *   * No INVD or WBINVD, no exceptions, page faults or interrupts
 *****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F15
-    LOCAL   fam15_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                # Save revision info to EBX
     shr     $20, %eax                 # AL = cpu extended family
     cmp     $0x06, %al                     # Is this family 15h?
-    jnz     fam15_enable_stack_hook_exit # Br if no
+    jnz     fam15_enable_stack_hook_exit\@ # Br if no
 
     bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
     jc      fam15_skipClearingBit4
@@ -391,7 +389,7 @@ dofamily15w:  # Do Standard Family 15 work
     btr     $(COMBINE_CR0_CD - 32), %edx         # Clear CombineCr0Cd bit
     _WRMSR
 
-fam15_enable_stack_hook_exit:
+fam15_enable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -415,14 +413,12 @@ fam15_enable_stack_hook_exit:
 *   * MSRC001_1022[DIS_HW_PF]=0
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F15
-    LOCAL   fam15_disable_stack_hook_exit
-    LOCAL   fam15_disable_stack_remote_read_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                    # Save revision info to EBX
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x06, %al                     # Is this family 15h?
-    jnz     fam15_disable_stack_hook_exit # Br if no
+    jnz     fam15_disable_stack_hook_exit\@ # Br if no
 
     mov     %ebx, %edi                    # Save revision info to EDI
     AMD_CPUID  $AMD_CPUID_APIC
@@ -525,7 +521,7 @@ fam15_enable_stack_hook_exit:
             #.while (carry?)
 7:          jnc     6f
                 dec     %ch                   #Check the timeout
-                jz      fam15_disable_stack_remote_read_exit
+                jz      fam15_disable_stack_remote_read_exit\@
                 mov     %es:(%ebx), %eax      # ax = 0000000000020338
                 bt      $DELIVERY_STS_BIT, %eax
             jmp     7b
@@ -539,7 +535,7 @@ fam15_enable_stack_hook_exit:
                     cmp     $REMOTE_DELIVERY_PEND, %eax
                     jnz      8f
                     dec     %ch               # Check the timeout
-                    jz      fam15_disable_stack_hook_exit # Branch if there is an unreponsive core
+                    jz      fam15_disable_stack_hook_exit\@ # Branch if there is an unreponsive core
                     stc
                 jmp     9f
 8:              #.else
@@ -564,13 +560,13 @@ fam15_enable_stack_hook_exit:
             jmp     7f
 6:          #.else
                 dec     %ch
-                jz      fam15_disable_stack_remote_read_exit
+                jz      fam15_disable_stack_remote_read_exit\@
                 stc
 7:          #.endif
         jmp     5b
 4:      #.endw
 
-fam15_disable_stack_remote_read_exit:
+fam15_disable_stack_remote_read_exit\@:
         rol   $8, %ecx                 # Restore ECX
 
 1:  #.endif
@@ -686,7 +682,7 @@ fam15_disable_stack_remote_read_exit:
 
 1:  #.endif
 
-fam15_disable_stack_hook_exit:
+fam15_disable_stack_hook_exit\@:
 .endm
 
 /*****************************************************************************
@@ -703,9 +699,6 @@ fam15_disable_stack_hook_exit:
 *****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID_F15
 
-    LOCAL   node_core_f15_exit
-    LOCAL   node_core_f15_AP
-    LOCAL   node_core_f15_shared
 
 #define F15_L2Size	512
 #define F15_ShareCores  2
@@ -714,12 +707,12 @@ fam15_disable_stack_hook_exit:
 #define F15_SzAddrBus   48
 #define F15_pad         0
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f15_exit          # Br if yes
+    jnz     node_core_f15_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $12, %eax                     # AL = cpu extended family
     cmp     $06, %ah                     # Is this family 15h?
-    jnz     node_core_f15_exit          # Br if no
+    jnz     node_core_f15_exit\@          # Br if no
     shr     $4,  %al                     # AL = cpu extended model
     shr     $16, %ebx                    # BH = LocalApicId
     mov     %al, %bl                     # BL = cpu extended model
@@ -731,7 +724,7 @@ fam15_disable_stack_hook_exit:
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jnc      node_core_f15_AP            # Br if no
+    jnc      node_core_f15_AP\@            # Br if no
 
     # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -742,18 +735,18 @@ fam15_disable_stack_hook_exit:
     in      %dx, %eax
     btr     $0, %eax                      # Set LinkInitializationControl[RouteTblDis] = 0
     out     %eax, %dx
-    jmp     node_core_f15_shared        #
+    jmp     node_core_f15_shared\@        #
 
-node_core_f15_AP:
+node_core_f15_AP\@:
 //1:	jmp 1b   # not crash
     mov     %bl, %al                        # AL = cpu extended model
     shr     $8,  %bx                        # BL = CPUID Fn0000_0001_EBX[LocalApicId]
 //    cmp    $1,  %al                        # Is This TN?
 //    jz     4f
 //    cmp    $3,  %al
-//    jnz    node_core_f15_AP_not_TN
+//    jnz    node_core_f15_AP_not_TN\@
     mov     %bx, %si
-    jmp     node_core_f15_shared
+    jmp     node_core_f15_shared\@
     #
     # This is an AP. Routing tables have been enabled by the HT Init process.
     # Also, the MailBox register was set by the BSP during early init
@@ -764,7 +757,7 @@ node_core_f15_AP:
     #         UINT32 ModuleType:2;    // Single Module = 0, Multi-module = 1.
     #         UINT32 :20;             // Reserved
     #
-#node_core_f15_AP_not_TN:
+#node_core_f15_AP_not_TN\@:
 #    mov     $0x0C0000408, %ecx             # Read the family 15h mailbox
 #    _RDMSR                              #      MC4_MISC1[63:32]
 #    mov     %dx, %si                      # SI = raw mailbox contents (will extract node# from this)
@@ -812,7 +805,7 @@ node_core_f15_AP:
       #
       #   determine if this core shares MTRRs
       #
-node_core_f15_shared:
+node_core_f15_shared\@:
     mov     $0x8000C580, %eax              # Compute Unit Status
     mov     %si, %bx
     shl     $3, %bh                       # Move node# to PCI Dev# field
@@ -875,7 +868,7 @@ node_core_f15_shared:
     #.endif
     2:
 
-node_core_f15_exit:
+node_core_f15_exit\@:
 
 .endm
 
@@ -947,10 +940,6 @@ node_core_f15_exit:
 .macro  AMD_ENABLE_STACK
 
 # These are local labels. Declared so linker doesn't cause 'redefined label' errors
-    LOCAL   SetupStack
-    LOCAL   Real16bMode
-    LOCAL   Protected32Mode
-    LOCAL   ClearTheStack
 
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
@@ -964,14 +953,14 @@ node_core_f15_exit:
     # It is =0 after reset; CAR setup sets it to enable the MTRRs
     mov     %cr0, %eax
     test    $CR0_MASK, %eax              # Is cache disabled? (CD & NW bits)
-    jnz     SetupStack                  # Jump if yes
+    jnz     SetupStack\@                  # Jump if yes
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR
     test    $MSR_MASK, %eax                     # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
-    jz      SetupStack                  # Jump if no
+    jz      SetupStack\@                  # Jump if no
     or      $FLAG_STACK_REENTRY, %esi             # Bit25, indicate stack has already been initialized
 
-SetupStack:
+SetupStack\@:
     # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
     mov     %esi, %ebx                    # Get my Node/Core info
     xor     %bl, %bl
@@ -1214,12 +1203,12 @@ w64k_here:
     mov     %cr0, %ecx                    # Check for 32-bit protect mode
     bt      $CR0_PE, %ecx                 #
     #.if (!carry?)                       # PE=0 means real mode
-    jc      Protected32Mode
+    jc      Protected32Mode\@
     mov     %cs, %cx                      # PE=1
     cmp     $0x0D000, %cx                  # Check for CS
-    jb      Protected32Mode             # If CS < D000, it is a selector instead of a segment
+    jb      Protected32Mode\@             # If CS < D000, it is a selector instead of a segment
             # alter SS:ESP for 16b Real Mode:
-Real16bMode:
+Real16bMode\@:
     mov     %edi, %eax
     shr     $4, %eax                      # Create a Real Mode segment for ss, ds, es
     mov     %ax, %ss
@@ -1234,7 +1223,7 @@ Real16bMode:
     #   Default is to use Protected 32b Mode
     #.endif
     ;
-Protected32Mode:
+Protected32Mode\@:
     #
     # Clear The Stack
     #   Now that we have set the location and the MTRRs, initialize the cache by
@@ -1247,7 +1236,7 @@ Protected32Mode:
     #       edi -  address of start of stack block
     #
 
-ClearTheStack:                          # Stack base is in SS, stack pointer is in ESP
+ClearTheStack\@:                          # Stack base is in SS, stack pointer is in ESP
     shr     $2, %ebx                      # ebx = stack block size in dwords
     mov     %bx, %cx                      #
     # Check our flags - Don't clear an existing stack
@@ -1322,4 +1311,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
 
 .endm
-
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index ef08c87761..3218a64265 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -281,7 +281,6 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
 *     SI[31:27]= reserved, =0
 ****************************************************************************/
 .macro  GET_NODE_ID_CORE_ID
-    LOCAL  node_core_exit
 
     mov     $-1, %si
     GET_NODE_ID_CORE_ID_F16
@@ -290,16 +289,16 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
      * Check for unrecognized Family
      */
     cmp     $-1, %si                      # Has family (node/core) already been discovered?
-    jnz     node_core_exit              # Br if yes
+    jnz     node_core_exit\@              # Br if yes
 
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
 
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jc      node_core_exit              # Br if yes
+    jc      node_core_exit\@              # Br if yes
     hlt                                 # Kill APs
-node_core_exit:
+node_core_exit\@:
 
 .endm
 
@@ -335,13 +334,12 @@ Family 16h requirements (BKDG #48751 section 2.3.3):
 	*/
 
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK_F16
-    LOCAL   fam16_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                # Save revision info to EBX
     shr     $20, %eax                 # AL = cpu extended family
     cmp     $0x07, %al                     # Is this family 16h?
-    jnz     fam16_enable_stack_hook_exit # Br if no
+    jnz     fam16_enable_stack_hook_exit\@ # Br if no
 
     bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
     jc      fam16_skipClearingBit4
@@ -373,7 +371,7 @@ fam16_skipClearingBit4:
     bts     $CACHE_IC_ATTR_DIS, %eax
     _WRMSR
 
-fam16_enable_stack_hook_exit:
+fam16_enable_stack_hook_exit\@:
 .endm
 
 /*
@@ -400,15 +398,12 @@ fam16_enable_stack_hook_exit:
 ;---------------------------------------------------
 */
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F16
-    LOCAL   fam16_disable_stack_hook_exit
-    LOCAL   fam16_disable_stack_remote_read_exit
-#    LOCAL   fam16_invd_done_remote_read_exit
 
     AMD_CPUID   $CPUID_MODEL
     mov     %eax, %ebx                    # Save revision info to EBX
     shr     $20, %eax                     # AL = cpu extended family
     cmp     $0x07, %al                     # Is this family 16h?
-    jnz     fam16_disable_stack_hook_exit # Br if no
+    jnz     fam16_disable_stack_hook_exit\@ # Br if no
 
     mov     %ebx, %edi                    # Save revision info to EDI
     AMD_CPUID  $AMD_CPUID_APIC
@@ -510,7 +505,7 @@ fam16_enable_stack_hook_exit:
             #.while (carry?)
 7:          jnc     6f
                 dec     %ch                   #Check the timeout
-                jz      fam16_disable_stack_remote_read_exit
+                jz      fam16_disable_stack_remote_read_exit\@
                 mov     %es:(%ebx), %eax      # ax = 0000000000020338
                 bt      $DELIVERY_STS_BIT, %eax
             jmp     7b
@@ -524,7 +519,7 @@ fam16_enable_stack_hook_exit:
                     cmp     $REMOTE_DELIVERY_PEND, %eax
                     jnz      8f
                     dec     %ch               # Check the timeout
-                    jz      fam16_disable_stack_hook_exit # Branch if there is an unreponsive core
+                    jz      fam16_disable_stack_hook_exit\@ # Branch if there is an unreponsive core
                     stc
                 jmp     9f
 8:              #.else
@@ -549,13 +544,13 @@ fam16_enable_stack_hook_exit:
             jmp     7f
 6:          #.else
                 dec     %ch
-                jz      fam16_disable_stack_remote_read_exit
+                jz      fam16_disable_stack_remote_read_exit\@
                 stc
 7:          #.endif
         jmp     5b
 4:      #.endw
 
-fam16_disable_stack_remote_read_exit:
+fam16_disable_stack_remote_read_exit\@:
         rol   $8, %ecx                 # Restore ECX
 
 1:  #.endif
@@ -660,7 +655,7 @@ fam16_disable_stack_remote_read_exit:
             #.while (carry?)
 7:          jnc     6f
                 dec     %ch                   #Check the timeout
-                jz      fam16_invd_done_remote_read_exit
+                jz      fam16_invd_done_remote_read_exit\@
                 mov     %es:(%ebx), %eax      # ax = 0000000000020338
                 bt      $DELIVERY_STS_BIT, %eax
             jmp     7b
@@ -674,7 +669,7 @@ fam16_disable_stack_remote_read_exit:
                     cmp     $REMOTE_DELIVERY_PEND, %eax
                     jnz      8f
                     dec     %ch               # Check the timeout
-                    jz      fam16_invd_done_remote_read_exit # Branch if there is an unreponsive core
+                    jz      fam16_invd_done_remote_read_exit\@ # Branch if there is an unreponsive core
                     stc
                 jmp     9f
 8:              #.else
@@ -699,14 +694,14 @@ fam16_disable_stack_remote_read_exit:
             jmp     7f
 6:          #.else
                 dec     %ch
-                jz      fam16_invd_done_remote_read_exit
+                jz      fam16_invd_done_remote_read_exit\@
                 stc
 7:          #.endif
         jmp     5b
 4:      #.endw
 
      jmp  2f
-fam16_invd_done_remote_read_exit:
+fam16_invd_done_remote_read_exit\@:
 1: #.else
      mov    $APIC_BASE_ADDRESS, %ecx
      _RDMSR
@@ -722,17 +717,13 @@ fam16_invd_done_remote_read_exit:
     btr     $30, %edx
     _WRMSR
 
-fam16_disable_stack_hook_exit:
+fam16_disable_stack_hook_exit\@:
 .endm
 
 /*
 */
 .macro  GET_NODE_ID_CORE_ID_F16
 
-    LOCAL   node_core_f16_exit
-    LOCAL   node_core_f16_AP
-    LOCAL   node_core_f16_shared
-    LOCAL node_core_f16_AP_not_TN
 
 #define F16_L2Size	1024
 #define F16_ShareCores  4
@@ -741,12 +732,12 @@ fam16_disable_stack_hook_exit:
 #define F16_SzAddrBus   40
 #define F16_pad         0
     cmp     $-1, %si                      # Has node/core already been discovered?
-    jnz     node_core_f16_exit          # Br if yes
+    jnz     node_core_f16_exit\@          # Br if yes
 
     AMD_CPUID   $CPUID_MODEL
     shr     $12, %eax                     # AL = cpu extended family
     cmp     $07, %ah                     # Is this family 16h?
-    jnz     node_core_f16_exit          # Br if no
+    jnz     node_core_f16_exit\@          # Br if no
     shr     $4,  %al                     # AL = cpu extended model
     shr     $16, %ebx                    # BH = LocalApicId
     mov     %al, %bl                     # BL = cpu extended model
@@ -758,7 +749,7 @@ fam16_disable_stack_hook_exit:
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
-    jnc      node_core_f16_AP            # Br if no
+    jnc      node_core_f16_AP\@            # Br if no
 
     # This is the BSP.
     # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
@@ -769,9 +760,9 @@ fam16_disable_stack_hook_exit:
     in      %dx, %eax
     btr     $0, %eax                      # Set LinkInitializationControl[RouteTblDis] = 0
     out     %eax, %dx
-    jmp     6f         #node_core_f16_shared        #
+    jmp     6f         #node_core_f16_shared\@        #
 
-node_core_f16_AP:
+node_core_f16_AP\@:
     mov     %bl, %al                        # AL = cpu extended model
     shr     $8,  %bx                        # BL = CPUID Fn0000_0001_EBX[LocalApicId]
     #.if (al == 0)
@@ -780,14 +771,14 @@ node_core_f16_AP:
     #.else
 4:  mov     %bx, %si
     jmp     6f
-5:  #node_core_f16_AP_not_KB
+5:  #node_core_f16_AP_not_KB\@
          bts $FLAG_CORE_NOT_IDENTIFIED, %esi
     #.endif
     #.endif
       #
       #   determine if this core shares MTRRs
       #
-6:	#node_core_f16_shared
+6:	#node_core_f16_shared\@
     mov     $COMPUTE_UNIT_STATUS, %eax              # Compute Unit Status
     mov     %si, %bx
     shl     $3, %bh                       # Move node# to PCI Dev# field
@@ -860,7 +851,7 @@ node_core_f16_AP:
     #.endif
     2:
 
-node_core_f16_exit:
+node_core_f16_exit\@:
 
 .endm
 
@@ -932,10 +923,6 @@ node_core_f16_exit:
 .macro  AMD_ENABLE_STACK
 
 # These are local labels. Declared so linker doesn't cause 'redefined label' errors
-    LOCAL   SetupStack
-    LOCAL   Real16bMode
-    LOCAL   Protected32Mode
-    LOCAL   ClearTheStack
 
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
@@ -949,14 +936,14 @@ node_core_f16_exit:
     # It is =0 after reset; CAR setup sets it to enable the MTRRs
     mov     %cr0, %eax
     test    $CR0_MASK, %eax              # Is cache disabled? (CD & NW bits)
-    jnz     SetupStack                  # Jump if yes
+    jnz     SetupStack\@                  # Jump if yes
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR
     test    $MSR_MASK, %eax                     # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
-    jz      SetupStack                  # Jump if no
+    jz      SetupStack\@                  # Jump if no
     or      $FLAG_STACK_REENTRY, %esi             # Bit25, indicate stack has already been initialized
 
-SetupStack:
+SetupStack\@:
     # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
     mov     %esi, %ebx                    # Get my Node/Core info
     xor     %bl, %bl
@@ -1194,12 +1181,12 @@ SetupStack:
     mov     %cr0, %ecx                    # Check for 32-bit protect mode
     bt      $CR0_PE, %ecx                 #
     #.if (!carry?)                       # PE=0 means real mode
-    jc      Protected32Mode
+    jc      Protected32Mode\@
     mov     %cs, %cx                      # PE=1
     cmp     $0x0D000, %cx                  # Check for CS
-    jb      Protected32Mode             # If CS < D000, it is a selector instead of a segment
+    jb      Protected32Mode\@             # If CS < D000, it is a selector instead of a segment
             # alter SS:ESP for 16b Real Mode:
-Real16bMode:
+Real16bMode\@:
     mov     %edi, %eax
     shr     $4, %eax                      # Create a Real Mode segment for ss, ds, es
     mov     %ax, %ss
@@ -1214,7 +1201,7 @@ Real16bMode:
     #   Default is to use Protected 32b Mode
     #.endif
     ;
-Protected32Mode:
+Protected32Mode\@:
     #
     # Clear The Stack
     #   Now that we have set the location and the MTRRs, initialize the cache by
@@ -1227,7 +1214,7 @@ Protected32Mode:
     #       edi -  address of start of stack block
     #
 
-ClearTheStack:                          # Stack base is in SS, stack pointer is in ESP
+ClearTheStack\@:                          # Stack base is in SS, stack pointer is in ESP
     shr     $2, %ebx                      # ebx = stack block size in dwords
     mov     %bx, %cx                      #
     # Check our flags - Don't clear an existing stack
@@ -1303,4 +1290,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
 
 .endm
-