AGESA f12 vendorcode: Keep only Liano refcode

The only subtree we build is /LN.

Change-Id: I035932a4be41fa0451a3f3c7be33442afeeb5571
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

108 files changed, 0 insertions, 31437 deletions

diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c
deleted file mode 100644
index 8fa80299df..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/marc32_3.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * marc32_3.c
- *
- * Memory Controller, registered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_C32_MARC32_3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA C32RDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
-
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA C32RDdr3CKETri[] = {0x55, 0xAA};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for C32 DDR3 L1 system
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID        Socket number
- *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to C32 MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to C32 CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to C32 ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to C32 CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRC32_3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  //
-  // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
-  //
-  // Code searches table for matching speed, then matches the current dimm
-  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
-  //
-  // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
-  //                 in SPD Byte 63.
-  //                 Bits 15-12       RC2 if One register
-  //                 Bits 11-8        RC8 if One register
-  //                 Bits 7-4         RC2 for more than one register
-  //                 Bits 3-0         RC8 for more than one register
-  //
-  // Frequency, Dimm Config ,
-  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
-     {DDR667_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x00000000, 0x4004, 2},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00000000, 0x0000, 1},
-     {DDR800_FREQUENCY, QR_DIMM1, \
-       0x00000000, 0x0040, 1},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00000000, 0x4004, 2},
-     {DDR800_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
-       0x00000000, 0x4004, 2},
-     {DDR800_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
-       0x00000000, 0x4004, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003C3C3C, 0x0000,1},
-     {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x003C3C3C, 0x0040, 1},
-     {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003A3A3A, 0x0000, 1},
-     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x003A3A3A, 0x0040, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00383A38, 0x4040, 2},
-  };
-  //
-  // Address Timings and Drive Strengths for 3 DIMMs per channel
-  //
-  // Code searches table for matching speed, then matches the current dimm
-  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
-  //
-  // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
-  //                 in SPD Byte 63.
-  //                 Bits 15-12       RC2 if One register
-  //                 Bits 11-8        RC8 if One register
-  //                 Bits 7-4         RC2 for more than one register
-  //                 Bits 3-0         RC8 for more than one register
-  //
-  // Frequency, Dimm Config ,
-  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
-     {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x0000, 1},
-     {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4040, 2},
-     {DDR667_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4004, 2},
-     {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00380038, 0x4004, 3},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x0000, 1},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4040, 2},
-     {DDR800_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4004, 2},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00380038, 0x4004, 3},
-     {DDR800_FREQUENCY, QR_DIMM1, \
-       0x00000000, 0x0040, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003C3C3C, 0x0000, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3C3A, 0x4040, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1 + SR_DIMM2, \
-       0x00373C37, 0x4040, 3},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3A3A, 0x0000, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
-       0x00383A38, 0x4040, 2},
-  };
-
-  //
-  // DIMM ODT Pattern (1 or 2 DIMMs per channel)
-  //
-  // Dimm Config ,
-  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
-  //
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
-    {SR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
-    {DR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
-    {QR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
-    {SR_DIMM1, \
-      0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
-    {DR_DIMM1, \
-      0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
-    {QR_DIMM1, \
-      0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-      0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
-      0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
-    {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-      0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
-    {QR_DIMM0 + QR_DIMM1, \
-      0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
-  };
-  // DIMM ODT Pattern (3 DIMMs per channel)
-  //
-  // Dimm Config ,
-  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
-  //
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
-    {SR_DIMM2 + DR_DIMM2, \
-      0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
-    {SR_DIMM0 + DR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
-      0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-      0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
-    {QR_DIMM1, \
-      0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
-    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-      0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
-      0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-      0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
-  };
-  //
-  // DIMM ODT Pattern (4 DIMMs per channel)
-  //
-  // Dimm Config ,
-  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
-  //
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
-    {ANY_DIMM3, \
-      0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
-    {ANY_DIMM2 + ANY_DIMM3, \
-      0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
-    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
-      0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
-    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
-      0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
-  };
-  //
-  // DIMM Write Leveling ODT Pattern 1 or 2 Dimms Per Channel
-  //
-  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {QR_DIMM0,            {0x05, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {QR_DIMM1,            {0x00, 0x0A, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
-    {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
-    {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
-    {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
-  };
-  //
-  // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
-  //
-  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
-    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
-    {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
-    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
-  };
-  //
-  // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
-  //
-  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
-    {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
-    {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
-    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
-    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
-  };
-
-
-  UINT16 i;
-  UINT16 j;
-  UINT8  MaxDimmPerCH;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT16 RC2RC8;
-  UINT32 PhyRODTCSLow;
-  UINT32 PhyRODTCSHigh;
-  UINT32 PhyWODTCSLow;
-  UINT32 PhyWODTCSHigh;
-  BOOLEAN SlowMode;
-  UINT8 PSCfgSize;
-  UINT8 PSCfgODTSize;
-  UINT8 PSCfgWlODTSize;
-  UINT8 PhyWLODT[4];
-
-  CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
-  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
-  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
-  UINT8 *DimmsPerChPtr;
-
-  ASSERT (MemData != NULL);
-  ASSERT (CurrentChannel != NULL);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  RC2RC8 = 0;
-  PhyRODTCSLow = 0;
-  PhyRODTCSHigh = 0;
-  PhyWODTCSLow = 0;
-  PhyWODTCSHigh = 0;
-  SlowMode = FALSE;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  // Prepare inputs
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if (MaxDimmPerCH == 4) {
-    PSCfgPtr = NULL;
-    PSCfgSize = NULL;
-    PSCfgODTPtr = PSCfg4DIMMsODT;
-    PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else if (MaxDimmPerCH == 3) {
-    PSCfgPtr = PSCfg3DIMMs;
-    PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
-    PSCfgODTPtr = PSCfg3DIMMsODT;
-    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else {
-    PSCfgPtr = PSCfg2DIMMs;
-    PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
-    PSCfgODTPtr = PSCfg2DIMMsODT;
-    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  }
-
-  // AddrTmgCTL and DctOdcCtl
-  if (MaxDimmPerCH != 4) {
-    for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
-      if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
-        continue;
-      }
-      DimmTpMatch = 0;
-      _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
-      for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-        if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-          DimmTpMatch++;
-        }
-      }
-      if (DimmTpMatch == PSCfgPtr->Dimms) {
-        AddrTmgCTL = PSCfgPtr->AddrTmg;
-        DctOdcCtl = 0x00223222;
-        RC2RC8 = PSCfgPtr->RC2RC8;
-        break;
-      }
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  //
-  // Count slots with SR/DR poulated.
-  //
-  DimmTpMatch = 0;
-  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-    if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
-      DimmTpMatch++;
-    }
-  }
-  //
-  // DimmTpMatch is equal to the count of  slot that have either an SR or DR
-  // installed.
-  //
-  if (MaxDimmPerCH == 4) {
-    //
-    // Any SR/DR in 4 DPCH
-    //
-    if (DimmTpMatch > 0) {
-      DctOdcCtl = 0x00223222;
-      if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
-        DctOdcCtl = 0x00113222;
-      }
-    }
-    //
-    // At Least 3 SR/DR in 4 DPCH
-    //
-    if (DimmTpMatch >= 3) {
-      AddrTmgCTL |= 0x002F0000;
-    }
-    // At Least 2 SR/DR in 4 DPCH
-    if (DimmTpMatch >= 2) {
-      RC2RC8 = 0x4040;
-    }
-  } else {
-    //
-    // Less than 4 DPCH
-    //
-    //
-    // Only 1 Dimm Populated and its a SR or DR OR
-    //   3 Dimms Populated and Frequency is 800 MHz
-    //
-    if (((Dimms == 1) && (DimmTpMatch == 1)) ||
-      ((Dimms == 3) && ((Speed == DDR800_FREQUENCY) ||
-       (Speed == DDR1066_FREQUENCY)))) {
-        DctOdcCtl = 0x00113222;
-    }
-  }
-
-  //RC2 and RC8
-  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-    // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
-    if (CurrentChannel->CtrlWrd02[j] > 0) {
-      if (CurrentChannel->CtrlWrd02[j] == 1) {
-        // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
-        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
-        CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
-      } else {
-        // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
-        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
-        CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
-      }
-    }
-  }
-
-  //Programmable ODT
-  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
-    if (Dimms != PSCfgODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
-      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
-      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
-      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
-      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
-      break;
-    }
-  }
-
-  //WLODT
-  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
-    if (Dimms != PSCfgWlODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
-      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  // Set ProcODT
-  DctOdcCtl |= 0x20000000;
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) C32RDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) C32RDdr3CKETri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) C32RDdr3CSTri;
-
-  switch (MaxDimmPerCH) {
-  case 3:
-    CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri3D;
-    break;
-  case 4:
-    CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri4D;
-    break;
-  default:
-    CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri2D;  // Most conservative
-  }
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
-  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
-  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
-  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c
deleted file mode 100644
index cc3b739d7b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/C32/mauc32_3.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauc32_3.c
- *
- * Platform specific settings for C32 DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_C32_MAUC32_3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA C32UDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA C32UDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to C32 MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to C32 CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to C32 ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to C32 CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUC32_3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
-    {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
-    {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
-    {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
-    {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
-    {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
-    //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
-    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
-    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
-    //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
-    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8  MaxDimmPerCH;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT32 PhyRODTCSLow;
-  UINT32 PhyRODTCSHigh;
-  UINT32 PhyWODTCSLow;
-  UINT32 PhyWODTCSHigh;
-  UINT8 PhyWLODT[4];
-  UINT8 PSCfgODTSize;
-  UINT8 PSCfgWlODTSize;
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
-  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
-  UINT8 *DimmsPerChPtr;
-
-  ASSERT (MemData != NULL);
-  ASSERT (CurrentChannel != NULL);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyRODTCSLow = 0;
-  PhyRODTCSHigh = 0;
-  PhyWODTCSLow = 0;
-  PhyWODTCSHigh = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-
-  ASSERT (i < GET_SIZE_OF (PSCfg));
-
-  if (MaxDimmPerCH == 3) {
-    PSCfgODTPtr = PSCfg3DIMMsODT;
-    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else {
-    PSCfgODTPtr = PSCfg2DIMMsODT;
-    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  }
-
-  // Programmable ODT
-  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
-    if (Dimms != PSCfgODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
-      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
-      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
-      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
-      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
-      break;
-    }
-  }
-
-  // WL ODT
-  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
-    if (Dimms != PSCfgWlODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
-      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (Dimms == 1) {
-    if (Loads >= 16) {
-      if (Speed == DDR800_FREQUENCY) {
-        AddrTmgCTL = 0x003B0000;
-      } else if (Speed == DDR1066_FREQUENCY) {
-        AddrTmgCTL = 0x00380000;
-      } else if (Speed == DDR1333_FREQUENCY) {
-        AddrTmgCTL = 0x00360000;
-      } else {
-        AddrTmgCTL = 0x00340000;
-        SlowMode = TRUE;
-      }
-    } else {
-      AddrTmgCTL = 0;
-    }
-    DctOdcCtl = 0x20113222;
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) C32UDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) C32UDdr3CKETri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) C32UDdr3CSTri;
-
-  switch (MaxDimmPerCH) {
-  case 3:
-    CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri3D;
-    break;
-  default:
-    CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri2D;  // Most conservative
-  }
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
-  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
-  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
-  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c
deleted file mode 100644
index 1be73e41e6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda2.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masda2.c
- *
- * Platform specific settings for DA DDR2 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support S1g3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DA_MASDA2_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DASDdr2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DASDdr2CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for DA DDR2 SO-dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSDA2 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR400_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
-    {DDR533_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
-    {DDR667_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
-    {DDR800_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
-  };
-
-  UINT16 i;
-  UINT8 Loads;
-  UINT8 Ranks;
-  UINT16 Speed;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  BOOLEAN SlowMode;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Ranks = CurrentChannel->Ranks;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  SlowMode = FALSE;  // 1T
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-  ASSERT (i < GET_SIZE_OF (PSCfg));
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (Loads == 16) {
-    if ((Speed == DDR533_FREQUENCY) && (Ranks == 2)) {
-      AddrTmgCTL = 0x002C2C2C;
-    } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 1)) {
-      AddrTmgCTL = 0x00272727;
-    } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 2)) {
-      AddrTmgCTL = 0x00002828;
-      SlowMode = TRUE;   // 2T
-    } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 1)) {
-      AddrTmgCTL = 0x00292929;
-    } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 2)) {
-      AddrTmgCTL = 0x00002F2F;
-      SlowMode = TRUE;   // 2T
-    }
-  }
-  CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr2CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) DASDdr2CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) DASDdr2ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr2CSTri;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c
deleted file mode 100644
index 06e2c302f2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/masda3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masda3.c
- *
- * Platform specific settings for DA DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support S1g4 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DA_MASDA3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DASDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DASDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for DA DDR3 SO-dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSDA3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
-    {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8  MaxDimmPerCH;
-  UINT8 *DimmsPerChPtr;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-  SlowMode = FALSE;  // 1T
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (MaxDimmPerCH == 2) {
-    if (Dimms == 2) {
-      DctOdcCtl = 0x20223323;
-      SlowMode = TRUE;
-      if (Speed == DDR800_FREQUENCY) {
-        AddrTmgCTL = 0x00000039;
-      } else if (Speed == DDR1066_FREQUENCY) {
-        AddrTmgCTL = 0x00000037;
-      }
-    } else {
-      DctOdcCtl = 0x20113222;
-    }
-  } else {
-    if (CurrentChannel->DimmSRPresent != 0) {
-      PhyWLODT[0] = 1;
-    } else if (CurrentChannel->DimmDrPresent != 0) {
-      PhyWLODT[0] = 4;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) DASDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) DASDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr3CSTri;
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c
deleted file mode 100644
index dc5a24d2ba..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DA/mauda3.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * mauda3.c
- *
- * Platform specific settings for DA DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DA_MAUDA3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DAUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DAUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUDA3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
-    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
-    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
-    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
-    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
-  };
-  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  if (Dimms == 1) {
-    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
-      if (Speed == PSCfg1Dimm[i].Speed) {
-        if (Loads >= PSCfg1Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg1Dimm[i].Odc;
-        } else {
-          DctOdcCtl = 0x20113222;
-        }
-        break;
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
-  } else {
-    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
-      if (Speed == PSCfg2Dimm[i].Speed) {
-        if (Loads <= PSCfg2Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg2Dimm[i].Odc;
-          break;
-        }
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) DAUDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) DAUDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) DAUDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) DAUDdr3CSTri;
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c
deleted file mode 100644
index b66244fe46..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr2.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mardr2.c
- *
- * Platform specific settings for DR DDR2 L1 system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DR_MARDR2_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DrRDdr2CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
-
-// Chip select 0, 1, 4, 5 maps to M[B,A]_CKE[0]
-// Chip select 2, 3, 6, 7 maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DrRDdr2CKETri[] = {0x33, 0xCC};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for DR DDR2 L1 system
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRDr2 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST ADV_PSCFG_ENTRY PSCfg4D[] = {
-    {ANY_, ANY_, 0x00000000, 0x00111222, 1},
-    {ANY_, ANY_, 0x00370000, 0x00111222, 2}
-  };
-
-  STATIC CONST ADV_PSCFG_ENTRY PSCfg8D[] = {
-    {ANY_, ANY_, 0x00000000, 0x00111222, 1},
-    {ANY_, ANY_, 0x00370000, 0x00111222, 2},
-    {ANY_, ANY_, 0x002F0000, 0x00111222, ANY_}
-  };
-
-  CONST ADV_PSCFG_ENTRY *PSCfgPtr;
-  UINT16 i;
-  UINT8  MaxDimmPerCH;
-  UINT16 TabSize;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT16 QRPresent;
-  UINT16 DRx4Present;
-  BOOLEAN SlowMode;
-  UINT8 *DimmsPerChPtr;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-  QRPresent = CurrentChannel->DimmQrPresent;
-  DRx4Present = CurrentChannel->DimmDrPresent & CurrentChannel->Dimmx4Present;
-  if (QRPresent) {
-    Dimms = (Dimms + 1) / 2;
-  }
-
-  // Table look up
-  if (MaxDimmPerCH <= 2) {
-    PSCfgPtr = PSCfg4D;
-    TabSize = GET_SIZE_OF (PSCfg4D);
-  } else {
-    PSCfgPtr = PSCfg8D;
-    TabSize = GET_SIZE_OF (PSCfg8D);
-  }
-  DctOdcCtl = 0;
-  AddrTmgCTL = 0;
-  for (i = 0; i < TabSize; i++) {
-    if ((PSCfgPtr[i].Dimms == ANY_) || (PSCfgPtr[i].Dimms == Dimms)) {
-      if ((PSCfgPtr[i].Speed == ANY_) || (PSCfgPtr[i].Speed == Speed)) {
-        if ((PSCfgPtr[i].Loads == ANY_) || (PSCfgPtr[i].Loads >= Loads)) {
-          AddrTmgCTL = PSCfgPtr[i].AddrTmg;
-          DctOdcCtl = PSCfgPtr[i].Odc;
-          break;
-        }
-      }
-    }
-  }
-  ASSERT (i == TabSize);
-  SlowMode = FALSE;  // 1T
-
-  //
-  // Overrides and/or exceptions
-  //
-
-  if (QRPresent == 0x55) {
-    // QR for 4DIMM case only
-    AddrTmgCTL = 0x002F0000;
-    if (Speed >= DDR667_FREQUENCY) {
-      DctOdcCtl = 0x00331222;
-    }
-  }
-
-  if (Speed >= DDR667_FREQUENCY) {
-    if ((QRPresent != 0) || (DRx4Present != 0)) {
-      AddrTmgCTL |= 0x00002F00;
-    }
-    if (Dimms >= 3) {
-      AddrTmgCTL |= 0x0000002F;
-    }
-    if (Dimms == 3 || Dimms == 4) {
-      DctOdcCtl = 0x00331222;
-    }
-  }
-
-  // Adjust Processor ODT
-  if (Dimms == 1) {
-    DctOdcCtl |= 0x20000000;        // 75ohms
-  } else {
-    DctOdcCtl |= 0x10000000;        // 150ohms
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr2CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) DrRDdr2CKETri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr2CSTri;
-
-  switch (MaxDimmPerCH) {
-  case 3:
-    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri3D;
-    break;
-  case 4:
-    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri4D;
-    break;
-  default:
-    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri2D;
-  }
-
-  CurrentChannel->DctEccDqsLike = 0x0504;
-  CurrentChannel->DctEccDqsScale = 0;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c
deleted file mode 100644
index ca887d2263..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/mardr3.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mardr3.c
- *
- * Memory Controller, registered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DR_MARDR3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DrRDdr3CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
-
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DrRDdr3CKETri[] = {0x55, 0xAA};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for DR DDR3 L1 system
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRDr3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00000000, 0x0000, 1},
-     {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x00000000, 0x0040, 1},
-     {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x00000000, 0x4004, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003C3C3C, 0x0000,1},
-     {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x003C3C3C, 0x0040, 1},
-     {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003A3A3A, 0x0000, 1},
-     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x003A3A3A, 0x0040, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00383A38, 0x4040, 2},
-     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x00383A38, 0x4004, 2},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00373937, 0x0000, 1},
-     {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x00373937, 0x0040, 1},
-     {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x00353935, 0x4004, 2}
-  };
-
-  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x0000, 1},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4040, 2},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00380038, 0x4004, 3},
-     {DDR800_FREQUENCY, QR_DIMM1, \
-       0x00000000, 0x0040, 1},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4004, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003C3C3C, 0x0000, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3C3A, 0x4040, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00373C37, 0x4040, 3},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00373C37, 0x4004, 3},
-     {DDR1066_FREQUENCY, QR_DIMM1, \
-       0x003C3C3C, 0x0040, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3A3A, 0x0000, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00383A38, 0x4040, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00343A34, 0x4004, 3},
-     {DDR1333_FREQUENCY, QR_DIMM1, \
-       0x003A3A3A, 0x0040, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00383A38, 0x4004, 2},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00393939, 0x0000, 1},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00363936, 0x4040, 2},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00303930, 0x4004, 3},
-     {DDR1600_FREQUENCY, QR_DIMM1, \
-       0x00393939, 0x0040, 1},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00363936, 0x4004, 2}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {QR_DIMM1,            {0x00, 0x0A, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
-    {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
-    {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
-    {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
-    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
-    {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
-    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
-    {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
-    {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
-    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
-    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
-  };
-  UINT16 i;
-  UINT16 j;
-  UINT8  MaxDimmPerCH;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT16 RC2RC8;
-  BOOLEAN SlowMode;
-  UINT8 PSCfgSize;
-  UINT8 PSCfgWlODTSize;
-  UINT8 PhyWLODT[4];
-  CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
-  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
-  UINT8 *DimmsPerChPtr;
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  RC2RC8 = 0;
-  SlowMode = FALSE;
-  ASSERT (MemData != NULL);
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if (MaxDimmPerCH == 4) {
-    PSCfgPtr = NULL;
-    PSCfgSize = NULL;
-    PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
-    PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else if (MaxDimmPerCH == 3) {
-    PSCfgPtr = PSCfg3DIMMs;
-    PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
-    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
-    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else {
-    PSCfgPtr = PSCfg2DIMMs;
-    PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
-    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
-    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  }
-
-  // AddrTmgCTL and DctOdcCtl
-  if (MaxDimmPerCH != 4) {
-    for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
-      if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
-        continue;
-      }
-      DimmTpMatch = 0;
-      _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
-      for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-        if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-          DimmTpMatch++;
-        }
-      }
-      if (DimmTpMatch == PSCfgPtr->Dimms) {
-        AddrTmgCTL = PSCfgPtr->AddrTmg;
-        DctOdcCtl = 0x00223222;
-        RC2RC8 = PSCfgPtr->RC2RC8;
-        break;
-      }
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  DimmTpMatch = 0;
-  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-    if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
-      DimmTpMatch++;
-    }
-  }
-  if (MaxDimmPerCH == 4) {
-    if (DimmTpMatch > 0) {
-      DctOdcCtl = 0x00223222;
-      if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
-        DctOdcCtl = 0x00113222;
-      }
-    }
-    if (DimmTpMatch >= 3) {
-      AddrTmgCTL |= 0x002F0000;
-    }
-    if (DimmTpMatch >= 2) {
-      RC2RC8 = 0x4040;
-    }
-  } else {
-    if ((Dimms == 1) && (DimmTpMatch == 1)) {
-      DctOdcCtl = 0x00113222;
-    }
-  }
-
-  //RC2 and RC8
-  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-    // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
-    if (CurrentChannel->CtrlWrd02[j] > 0) {
-      if (CurrentChannel->CtrlWrd02[j] == 1) {
-        // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
-        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
-        CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
-      } else {
-        // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
-        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
-        CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
-      }
-    }
-  }
-
-
-  //WLODT
-  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
-    if (Dimms != PSCfgWlODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
-      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  // Set ProcODT
-  DctOdcCtl |= 0x20000000;
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) DrRDdr3CKETri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr3CSTri;
-
-  switch (MaxDimmPerCH) {
-  case 3:
-    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri3D;
-    break;
-  case 4:
-    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri4D;
-    break;
-  default:
-    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri2D;
-  }
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c
deleted file mode 100644
index 0d67898443..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/DR/maudr3.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * maudr3.c
- *
- * Platform specific settings for DR DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DR_MAUDR3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DrUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DrUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUDr3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
-    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
-    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
-    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
-    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
-  };
-  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent != 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  if (Dimms == 1) {
-    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
-      if (Speed == PSCfg1Dimm[i].Speed) {
-        if (Loads >= PSCfg1Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg1Dimm[i].Odc;
-        } else {
-          DctOdcCtl = 0x20113222;
-        }
-        break;
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
-  } else {
-    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
-      if (Speed == PSCfg2Dimm[i].Speed) {
-        if (Loads <= PSCfg2Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg2Dimm[i].Odc;
-          break;
-        }
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) DrUDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) DrUDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) DrUDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) DrUDdr3CSTri;
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c
deleted file mode 100644
index aaf40a3988..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/marhy3.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * marhy3.c
- *
- * Memory Controller, registered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_HY_MARHY3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA HyRDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
-
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA HyRDdr3CKETri[] = {0x55, 0xAA};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for HY DDR3 L1 system
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID        Socket number
- *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to HY MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to HY CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to HY ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to HY CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRHy3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  //
-  // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
-  //
-  // Code searches table for matching speed, then matches the current dimm
-  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
-  //
-  // Frequency, Dimm Config ,
-  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00000000, 0x0000, 1},
-     {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x00000000, 0x0040, 1},
-     {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x00000000, 0x4004, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003C3C3C, 0x0000,1},
-     {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x003C3C3C, 0x0040, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1066_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1066_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x003A3A3A, 0x0000, 1},
-     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x003A3A3A, 0x0040, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00383A38, 0x4040, 2},
-     {DDR1333_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
-       0x00383A38, 0x4004, 2},
-     {DDR1333_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
-       0x00383A38, 0x4004, 2},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-       0x00373937, 0x0000, 1},
-     {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
-       0x00373937, 0x0040, 1},
-     {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
-       0x00353935, 0x4004, 2}
-  };
-  //
-  // Address Timings and Drive Strengths for 3 DIMMs per channel
-  //
-  // Code searches table for matching speed, then matches the current dimm
-  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
-  //
-  // Frequency, Dimm Config ,
-  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x0000, 1},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4040, 2},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00380038, 0x4004, 3},
-     {DDR800_FREQUENCY, QR_DIMM1, \
-       0x00000000, 0x0040, 1},
-     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00000000, 0x4004, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003C3C3C, 0x0000, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3C3A, 0x4040, 2},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00373C37, 0x4040, 3},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00373C37, 0x4004, 3},
-     {DDR1066_FREQUENCY, QR_DIMM1, \
-       0x003C3C3C, 0x0040, 1},
-     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3C3A, 0x4004, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x003A3A3A, 0x0000, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00383A38, 0x4040, 2},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00343A34, 0x4004, 3},
-     {DDR1333_FREQUENCY, QR_DIMM1, \
-       0x003A3A3A, 0x0040, 1},
-     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00383A38, 0x4004, 2},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00393939, 0x0000, 1},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00363936, 0x4040, 2},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00303930, 0x4004, 3},
-     {DDR1600_FREQUENCY, QR_DIMM1, \
-       0x00393939, 0x0040, 1},
-     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-       0x00363936, 0x4004, 2}
-  };
-  //
-  // DIMM ODT Pattern (1 or 2 DIMMs per channel)
-  //
-  // Dimm Config ,
-  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
-  //
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
-    {SR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
-    {DR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
-    {QR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
-    {SR_DIMM1, \
-      0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
-    {DR_DIMM1, \
-      0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
-    {QR_DIMM1, \
-      0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-      0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
-      0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
-    {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
-      0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
-    {QR_DIMM0 + QR_DIMM1, \
-      0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
-  };
-  // DIMM ODT Pattern (3 DIMMs per channel)
-  //
-  // Dimm Config ,
-  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
-  //
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
-    {SR_DIMM2 + DR_DIMM2, \
-      0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
-    {SR_DIMM0 + DR_DIMM0, \
-      0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
-      0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-      0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
-    {QR_DIMM1, \
-      0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
-    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-      0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
-      0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
-      0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
-  };
-  //
-  // DIMM ODT Pattern (4 DIMMs per channel)
-  //
-  // Dimm Config ,
-  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
-  //
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
-    {ANY_DIMM3, \
-      0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
-    {ANY_DIMM2 + ANY_DIMM3, \
-      0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
-    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
-      0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
-    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
-      0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
-  };
-  //
-  // DIMM Write Leveling ODT Pattern for 1 or 2 Dimms Per Channel
-  //
-  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {QR_DIMM0,            {0x05, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {QR_DIMM1,            {0x00, 0x0A, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
-    {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
-    {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
-    {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
-  };
-  //
-  // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
-  //
-  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
-    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
-    {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
-    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
-    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
-  };
-  //
-  // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
-  //
-  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
-  //
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
-    {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
-    {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
-    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
-    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8  MaxDimmPerCH;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT16 RC2RC8;
-  UINT32 PhyRODTCSLow;
-  UINT32 PhyRODTCSHigh;
-  UINT32 PhyWODTCSLow;
-  UINT32 PhyWODTCSHigh;
-  BOOLEAN SlowMode;
-  UINT8 PSCfgSize;
-  UINT8 PSCfgODTSize;
-  UINT8 PSCfgWlODTSize;
-  UINT8 PhyWLODT[4];
-
-  CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
-  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
-  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
-  UINT8 *DimmsPerChPtr;
-
-  ASSERT (MemData != NULL);
-  ASSERT (CurrentChannel != NULL);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  RC2RC8 = 0;
-  PhyRODTCSLow = 0;
-  PhyRODTCSHigh = 0;
-  PhyWODTCSLow = 0;
-  PhyWODTCSHigh = 0;
-  SlowMode = FALSE;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  // Prepare inputs
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if (MaxDimmPerCH == 4) {
-    PSCfgPtr = NULL;
-    PSCfgSize = NULL;
-    PSCfgODTPtr = PSCfg4DIMMsODT;
-    PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else if (MaxDimmPerCH == 3) {
-    PSCfgPtr = PSCfg3DIMMs;
-    PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
-    PSCfgODTPtr = PSCfg3DIMMsODT;
-    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else {
-    PSCfgPtr = PSCfg2DIMMs;
-    PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
-    PSCfgODTPtr = PSCfg2DIMMsODT;
-    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  }
-
-  // AddrTmgCTL and DctOdcCtl
-  if (MaxDimmPerCH != 4) {
-    for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
-      if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
-        continue;
-      }
-      DimmTpMatch = 0;
-      _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
-      for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-        if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-          DimmTpMatch++;
-        }
-      }
-      if (DimmTpMatch == PSCfgPtr->Dimms) {
-        AddrTmgCTL = PSCfgPtr->AddrTmg;
-        DctOdcCtl = 0x00223222;
-        RC2RC8 = PSCfgPtr->RC2RC8;
-        break;
-      }
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  DimmTpMatch = 0;
-  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-    if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
-      DimmTpMatch++;
-    }
-  }
-  if (MaxDimmPerCH == 4) {
-    if (DimmTpMatch > 0) {
-      DctOdcCtl = 0x00223222;
-      if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
-        DctOdcCtl = 0x00113222;
-      }
-    }
-    if (DimmTpMatch >= 3) {
-      AddrTmgCTL |= 0x002F0000;
-    }
-    if (DimmTpMatch >= 2) {
-      RC2RC8 = 0x4040;
-    }
-  } else if ((MaxDimmPerCH == 3) && (CurrentChannel->Dimms == 3)) {
-    DctOdcCtl = 0x00113222;
-  } else {
-    if ((Dimms == 1) && (DimmTpMatch == 1)) {
-      DctOdcCtl = 0x00113222;
-    }
-  }
-
-  //RC2 and RC8
-  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-    // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
-    if (CurrentChannel->CtrlWrd02[j] > 0) {
-      if (CurrentChannel->CtrlWrd02[j] == 1) {
-        // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
-        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
-        CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
-      } else {
-        // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
-        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
-        CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
-      }
-    }
-  }
-
-  //Programmable ODT
-  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
-    if (Dimms != PSCfgODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
-      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
-      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
-      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
-      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
-      break;
-    }
-  }
-
-  //WLODT
-  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
-    if (Dimms != PSCfgWlODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
-      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  // Set ProcODT
-  DctOdcCtl |= 0x20000000;
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) HyRDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) HyRDdr3CKETri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) HyRDdr3CSTri;
-
-  switch (MaxDimmPerCH) {
-  case 3:
-    CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri3D;
-    break;
-  case 4:
-    CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri4D;
-    break;
-  default:
-    CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri2D;  // Most conservative
-  }
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
-  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
-  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
-  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c
deleted file mode 100644
index c3da8133b7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/HY/mauhy3.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauhy3.c
- *
- * Platform specific settings for HY DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_HY_MAUHY3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA HyUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA HyUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for HY DDR3 unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to HY MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to HY CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to HY ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to HY CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUHy3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
-    {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
-    {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
-    {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
-    {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
-    {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
-    //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
-    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
-    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
-    //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
-    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8  MaxDimmPerCH;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT32 PhyRODTCSLow;
-  UINT32 PhyRODTCSHigh;
-  UINT32 PhyWODTCSLow;
-  UINT32 PhyWODTCSHigh;
-  UINT8 PhyWLODT[4];
-  UINT8 PSCfgODTSize;
-  UINT8 PSCfgWlODTSize;
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
-  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
-  UINT8 *DimmsPerChPtr;
-
-  ASSERT (MemData != NULL);
-  ASSERT (CurrentChannel != NULL);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyRODTCSLow = 0;
-  PhyRODTCSHigh = 0;
-  PhyWODTCSLow = 0;
-  PhyWODTCSHigh = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->RegDimmPresent) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-
-  ASSERT (i < GET_SIZE_OF (PSCfg));
-
-  if (MaxDimmPerCH == 3) {
-    PSCfgODTPtr = PSCfg3DIMMsODT;
-    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  } else {
-    PSCfgODTPtr = PSCfg2DIMMsODT;
-    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
-    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
-    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
-  }
-
-  // Programmable ODT
-  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
-    if (Dimms != PSCfgODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
-      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
-      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
-      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
-      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
-      break;
-    }
-  }
-
-  // WL ODT
-  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
-    if (Dimms != PSCfgWlODTPtr->Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
-      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (Dimms == 1) {
-    if (Loads >= 16) {
-      if (Speed == DDR800_FREQUENCY) {
-        AddrTmgCTL = 0x003B0000;
-      } else if (Speed == DDR1066_FREQUENCY) {
-        AddrTmgCTL = 0x00380000;
-      } else if (Speed == DDR1333_FREQUENCY) {
-        AddrTmgCTL = 0x00360000;
-      } else {
-        AddrTmgCTL = 0x00340000;
-        SlowMode = TRUE;
-      }
-    } else {
-      AddrTmgCTL = 0;
-    }
-    DctOdcCtl = 0x20113222;
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) HyUDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) HyUDdr3CKETri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) HyUDdr3CSTri;
-
-  switch (MaxDimmPerCH) {
-  case 3:
-    CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri3D;
-    break;
-  default:
-    CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri2D;  // Most conservative
-  }
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
-  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
-  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
-  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c
deleted file mode 100644
index 0b29304665..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/masNi3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masNi3.c
- *
- * Platform specific settings for Ni DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support ASB2 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_NI_MASNI3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA NiSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA NiSDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for Ni DDR3 SO-dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSNi3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
-    {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8  MaxDimmPerCH;
-  UINT8 *DimmsPerChPtr;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-  SlowMode = FALSE;  // 1T
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (MaxDimmPerCH == 2) {
-    if (Dimms == 2) {
-      DctOdcCtl = 0x20223323;
-      SlowMode = TRUE;
-      if (Speed == DDR800_FREQUENCY) {
-        AddrTmgCTL = 0x00000039;
-      } else if (Speed == DDR1066_FREQUENCY) {
-        AddrTmgCTL = 0x00000037;
-      }
-    } else {
-      DctOdcCtl = 0x20113222;
-    }
-  } else {
-    if (CurrentChannel->DimmSRPresent != 0) {
-      PhyWLODT[0] = 1;
-    } else if (CurrentChannel->DimmDrPresent != 0) {
-      PhyWLODT[0] = 4;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) NiSDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) NiSDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) NiSDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) NiSDdr3CSTri;
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c
deleted file mode 100644
index c84f4858a7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/NI/mauNi3.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * mauNi3.c
- *
- * Platform specific settings for Ni DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_NI_MAUNI3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA NiUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA NiUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUNi3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
-    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
-    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
-    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
-    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
-  };
-  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  if (Dimms == 1) {
-    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
-      if (Speed == PSCfg1Dimm[i].Speed) {
-        if (Loads >= PSCfg1Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg1Dimm[i].Odc;
-        } else {
-          DctOdcCtl = 0x20113222;
-        }
-        break;
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
-  } else {
-    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
-      if (Speed == PSCfg2Dimm[i].Speed) {
-        if (Loads <= PSCfg2Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg2Dimm[i].Odc;
-          break;
-        }
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) NiUDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) NiUDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) NiUDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) NiUDdr3CSTri;
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c
deleted file mode 100644
index 6b5384e527..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/masph3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masph3.c
- *
- * Platform specific settings for PH DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/PH)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support S1g4 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_PH_MASPH3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA PhSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA PhSDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA PhSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA PhSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for PH DDR3 SO-dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSPh3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
-    {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8  MaxDimmPerCH;
-  UINT8 *DimmsPerChPtr;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-  SlowMode = FALSE;  // 1T
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (MaxDimmPerCH == 2) {
-    if (Dimms == 2) {
-      DctOdcCtl = 0x20223323;
-      SlowMode = TRUE;
-      if (Speed == DDR800_FREQUENCY) {
-        AddrTmgCTL = 0x00000039;
-      } else if (Speed == DDR1066_FREQUENCY) {
-        AddrTmgCTL = 0x00000037;
-      }
-    } else {
-      DctOdcCtl = 0x20113222;
-    }
-  } else {
-    if (CurrentChannel->DimmSRPresent != 0) {
-      PhyWLODT[0] = 1;
-    } else if (CurrentChannel->DimmDrPresent != 0) {
-      PhyWLODT[0] = 4;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) PhSDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) PhSDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) PhSDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) PhSDdr3CSTri;
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c
deleted file mode 100644
index 29f4e9c2da..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/PH/mauPh3.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauph3.c
- *
- * Platform specific settings for PH DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/PH)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_PH_MAUPH3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA PhUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA PhUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA PhUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA PhUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for PH DDR3 unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to PH MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to PH CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to PH ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to PH CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUPh3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
-    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
-    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
-    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
-    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
-  };
-  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  if (Dimms == 1) {
-    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
-      if (Speed == PSCfg1Dimm[i].Speed) {
-        if (Loads >= PSCfg1Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg1Dimm[i].Odc;
-        } else {
-          DctOdcCtl = 0x20113222;
-        }
-        break;
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
-  } else {
-    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
-      if (Speed == PSCfg2Dimm[i].Speed) {
-        if (Loads <= PSCfg2Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg2Dimm[i].Odc;
-          break;
-        }
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) PhUDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) PhUDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) PhUDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) PhUDdr3CSTri;
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c
deleted file mode 100644
index fc80bef9f6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/masRb3.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masRb3.c
- *
- * Platform specific settings for RB DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/RB)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_RB_MASRB3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA RbSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA RbSDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA RbSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA RbSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for RB DDR3 SO-dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSRb3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
-    {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8  MaxDimmPerCH;
-  UINT8 *DimmsPerChPtr;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-  SlowMode = FALSE;  // 1T
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
-    if (Speed == PSCfg[i].Speed) {
-      if (Loads <= PSCfg[i].Loads) {
-        AddrTmgCTL = PSCfg[i].AddrTmg;
-        DctOdcCtl = PSCfg[i].Odc;
-        break;
-      }
-    }
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  //
-  // Overrides and/or exceptions
-  //
-  if (MaxDimmPerCH == 2) {
-    if (Dimms == 2) {
-      DctOdcCtl = 0x20223323;
-      SlowMode = TRUE;
-      if (Speed == DDR800_FREQUENCY) {
-        AddrTmgCTL = 0x00000039;
-      } else if (Speed == DDR1066_FREQUENCY) {
-        AddrTmgCTL = 0x00000037;
-      }
-    } else {
-      DctOdcCtl = 0x20113222;
-    }
-  } else {
-    if (CurrentChannel->DimmSRPresent != 0) {
-      PhyWLODT[0] = 1;
-    } else if (CurrentChannel->DimmDrPresent != 0) {
-      PhyWLODT[0] = 4;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) RbSDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) RbSDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) RbSDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) RbSDdr3CSTri;
-
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c
deleted file mode 100644
index 63db725196..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/RB/mauRb3.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauRb3.c
- *
- * Platform specific settings for RB DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/RB)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_RB_MAURB3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA RbUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA RbUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA RbUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA RbUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *         This is function sets the platform specific settings for RB DDR3 Unbuffered dimms
- *
- *
- *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
- *     @param[in]       SocketID          Socket number
- *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
- *
- *     @return          AGESA_SUCCESS
- *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
- *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
- *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
- *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
- *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
- *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
- *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
- *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
- *     @return          CurrentChannel->SlowMode             Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgURb3 (
-  IN OUT   MEM_DATA_STRUCT *MemData,
-  IN       UINT8 SocketID,
-  IN OUT   CH_DEF_STRUCT *CurrentChannel
-  )
-{
-  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
-    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
-    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
-    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
-    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
-  };
-  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
-    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
-    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
-    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
-    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
-  };
-
-  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
-    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
-    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
-    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
-    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
-    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
-  };
-
-  UINT16 i;
-  UINT16 j;
-  UINT8 Loads;
-  UINT8 Dimms;
-  UINT16 Speed;
-  UINT16 DIMMRankType;
-  UINT16 _DIMMRankType;
-  UINT32 AddrTmgCTL;
-  UINT32 DctOdcCtl;
-  UINT8 PhyWLODT[4];
-  BOOLEAN SlowMode;
-  UINT8 DimmTpMatch;
-
-  ASSERT (MemData != 0);
-  ASSERT (CurrentChannel != 0);
-
-  AddrTmgCTL = 0;
-  DctOdcCtl = 0;
-  PhyWLODT[0] = 0x0F;
-  PhyWLODT[1] = 0x0F;
-  PhyWLODT[2] = 0x0F;
-  PhyWLODT[3] = 0x0F;
-
-  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  // Prepare inputs
-  Loads = CurrentChannel->Loads;
-  Dimms = CurrentChannel->Dimms;
-  Speed = CurrentChannel->DCTPtr->Timings.Speed;
-  DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
-  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
-    SlowMode = TRUE;   // 2T
-  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
-    SlowMode = TRUE;   // 2T
-  } else {
-    SlowMode = FALSE;  // 1T
-  }
-
-  if (Dimms == 1) {
-    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
-      if (Speed == PSCfg1Dimm[i].Speed) {
-        if (Loads >= PSCfg1Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg1Dimm[i].Odc;
-        } else {
-          DctOdcCtl = 0x20113222;
-        }
-        break;
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
-  } else {
-    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
-      if (Speed == PSCfg2Dimm[i].Speed) {
-        if (Loads <= PSCfg2Dimm[i].Loads) {
-          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
-          DctOdcCtl = PSCfg2Dimm[i].Odc;
-          break;
-        }
-      }
-    }
-    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
-  }
-
-  // WL ODT
-  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
-    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
-      continue;
-    }
-    DimmTpMatch = 0;
-    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
-    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
-      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
-        DimmTpMatch++;
-      }
-    }
-    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
-      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
-      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
-      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
-      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
-      break;
-    }
-  }
-
-  CurrentChannel->MemClkDisMap = (UINT8 *) RbUDdr3CLKDis;
-  CurrentChannel->CKETriMap = (UINT8 *) RbUDdr3CKETri;
-  CurrentChannel->ODTTriMap = (UINT8 *) RbUDdr3ODTTri;
-  CurrentChannel->ChipSelTriMap = (UINT8 *) RbUDdr3CSTri;
-
-  CurrentChannel->DctEccDqsLike = 0x0403;
-  CurrentChannel->DctEccDqsScale = 0x70;
-  CurrentChannel->DctAddrTmg = AddrTmgCTL;
-  CurrentChannel->DctOdcCtl = DctOdcCtl;
-  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
-    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
-  }
-  CurrentChannel->SlowMode = SlowMode;
-
-  return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c
deleted file mode 100644
index ebde8186ab..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/C32/mmflowC32.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowC32.c
- *
- * Main Memory initialization sequence for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/C32)
- * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function defines the memory initialization flow for
- *      systems that only support C32 processors.
- *
- *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- *     @return          AGESA_STATUS
- *                          - AGESA_ALERT
- *                          - AGESA_FATAL
- *                          - AGESA_SUCCESS
- *                          - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowC32 (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  )
-{
-  UINT8   Node;
-  UINT8   NodeCnt;
-  MEM_NB_BLOCK  *NBPtr;
-  MEM_TECH_BLOCK *TechPtr;
-  MEM_DATA_STRUCT *MemPtr;
-
-  NBPtr = MemMainPtr->NBPtr;
-  TechPtr = MemMainPtr->TechPtr;
-  NodeCnt = MemMainPtr->DieCount;
-  MemPtr = MemMainPtr->MemPtr;
-
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
-    MemPtr->IsFlowControlSupported = FALSE;
-    return AGESA_FATAL;
-  } else {
-    MemPtr->IsFlowControlSupported = TRUE;
-  }
-
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Initialize MCT
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Low voltage DDR3
-  //----------------------------------------------------------------
-  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
-  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Initialize DRAM and DCTs, and Create Memory Map
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    // Initialize Memory Controller and Dram
-    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
-      return AGESA_FATAL; //fatalexit
-    }
-
-    // Create memory map
-    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
-    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------
-  // If there is no dimm on the system, do fatal exit
-  //----------------------------------------------------
-  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
-    ASSERT (FALSE);
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Synchronize DCTs
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // CpuMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
-  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Before Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Restore
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemRestore (MemMainPtr)) {
-    // Do DQS training only if memory context restore fails
-
-    //----------------------------------------------------------------
-    // Training
-    //----------------------------------------------------------------
-    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
-    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
-    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
-      if (!MemFeatMain.Training (MemMainPtr)) {
-        return AGESA_FATAL;
-      }
-    }
-    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
-  }
-
-  //----------------------------------------------------------------
-  // Disable chipselects that fail training
-  //----------------------------------------------------------------
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
-  MemFeatMain.ExcludeDIMM (MemMainPtr);
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
-  //----------------------------------------------------------------
-  // OtherTiming
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
-  }
-
-  //----------------------------------------------------------------
-  // SetDqsEccTimings
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Online Spare
-  //----------------------------------------------------------------
-  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave banks
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Interleave Nodes
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave channels
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Programming Interleave registers
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
-  }
-
-  //----------------------------------------------------------------
-  // UMA Allocation & UMAMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  // ECC
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InitEcc (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Memory Clear
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.MemClr (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // OnDimm Thermal
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Save
-  //----------------------------------------------------------------
-  MemFeatMain.MemSave (MemMainPtr);
-
-  //----------------------------------------------------------------
-  // Memory DMI support
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemDmi (MemMainPtr)) {
-    return AGESA_CRITICAL;
-  }
-
-  return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c
deleted file mode 100644
index fb3419526e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DA/mmflowda.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowda.c
- *
- * Main Memory initialization sequence for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/DA)
- * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function defines the memory initialization flow for
- *      systems that only support RB processors.
- *
- *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- *     @return          AGESA_STATUS
- *                          - AGESA_ALERT
- *                          - AGESA_FATAL
- *                          - AGESA_SUCCESS
- *                          - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowDA (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  )
-{
-  UINT8   Node;
-  UINT8   NodeCnt;
-  MEM_NB_BLOCK  *NBPtr;
-  MEM_TECH_BLOCK *TechPtr;
-  MEM_DATA_STRUCT *MemPtr;
-
-  NBPtr = MemMainPtr->NBPtr;
-  TechPtr = MemMainPtr->TechPtr;
-  NodeCnt = MemMainPtr->DieCount;
-  MemPtr = MemMainPtr->MemPtr;
-
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
-    MemPtr->IsFlowControlSupported = FALSE;
-    return AGESA_FATAL;
-  } else {
-    MemPtr->IsFlowControlSupported = TRUE;
-  }
-
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Initialize MCT
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Low voltage DDR3
-  //----------------------------------------------------------------
-  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
-  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Initialize DRAM and DCTs, and Create Memory Map
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    // Initialize Memory Controller and Dram
-    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
-    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
-      return AGESA_FATAL; // fatalexit
-    }
-
-    // Create memory map
-    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
-    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------
-  // If there is no dimm on the system, do fatal exit
-  //----------------------------------------------------
-  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
-    ASSERT (FALSE);
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Synchronize DCTs
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // CpuMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
-  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Before Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Restore
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemRestore (MemMainPtr)) {
-    // Do DQS training only if memory context restore fails
-
-    //----------------------------------------------------------------
-    // Training
-    //----------------------------------------------------------------
-    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
-    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
-    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
-      if (!MemFeatMain.Training (MemMainPtr)) {
-        return AGESA_FATAL;
-      }
-    }
-    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
-  }
-
-  //----------------------------------------------------------------
-  // Disable chipselects that fail training
-  //----------------------------------------------------------------
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
-  MemFeatMain.ExcludeDIMM (MemMainPtr);
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
-  //----------------------------------------------------------------
-  // OtherTiming
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
-  }
-
-  //----------------------------------------------------------------
-  // SetDqsEccTimings
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Online Spare
-  //----------------------------------------------------------------
-  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave banks
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Interleave Nodes
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave channels
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Programming Interleave registers
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
-  }
-
-  //----------------------------------------------------------------
-  // UMA Allocation & UMAMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave region
-  //----------------------------------------------------------------
-  NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
-
-  //----------------------------------------------------------------
-  // ECC
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InitEcc (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Memory Clear
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.MemClr (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // OnDimm Thermal
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Save
-  //----------------------------------------------------------------
-  MemFeatMain.MemSave (MemMainPtr);
-
-  //----------------------------------------------------------------
-  // Memory DMI support
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemDmi (MemMainPtr)) {
-    return AGESA_CRITICAL;
-  }
-
-  return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c
deleted file mode 100644
index 6563da2ccb..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/DR/mmflowdr.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowdr.c
- *
- * Main Memory initialization sequence for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/DR)
- * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function defines the memory initialization flow for
- *      systems that only support RB processors.
- *
- *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- *     @return          AGESA_STATUS
- *                          - AGESA_ALERT
- *                          - AGESA_FATAL
- *                          - AGESA_SUCCESS
- *                          - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowDr (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  )
-{
-  UINT8   Node;
-  UINT8   NodeCnt;
-  MEM_NB_BLOCK  *NBPtr;
-  MEM_TECH_BLOCK *TechPtr;
-  MEM_DATA_STRUCT *MemPtr;
-
-  NBPtr = MemMainPtr->NBPtr;
-  TechPtr = MemMainPtr->TechPtr;
-  NodeCnt = MemMainPtr->DieCount;
-  MemPtr = MemMainPtr->MemPtr;
-
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
-    MemPtr->IsFlowControlSupported = FALSE;
-    return AGESA_FATAL;
-  } else {
-    MemPtr->IsFlowControlSupported = TRUE;
-  }
-
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Initialize MCT
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Low voltage DDR3
-  //----------------------------------------------------------------
-  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
-  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Initialize DRAM and DCTs, and Create Memory Map
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    // Initialize Memory Controller and Dram
-    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
-    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
-      return AGESA_FATAL; //fatalexit
-    }
-
-    // Create memory map
-    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
-    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------
-  // If there is no dimm on the system, do fatal exit
-  //----------------------------------------------------
-  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
-    ASSERT (FALSE);
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Synchronize DCTs
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // CpuMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
-  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Before Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Restore
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemRestore (MemMainPtr)) {
-    // Do DQS training only if memory context restore fails
-
-    //----------------------------------------------------------------
-    // Training
-    //----------------------------------------------------------------
-    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
-    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
-    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
-      if (!MemFeatMain.Training (MemMainPtr)) {
-        return AGESA_FATAL;
-      }
-    }
-    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
-  }
-
-  //----------------------------------------------------------------
-  // Disable chipselects that fail training
-  //----------------------------------------------------------------
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
-  MemFeatMain.ExcludeDIMM (MemMainPtr);
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
-  //----------------------------------------------------------------
-  // OtherTiming
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
-  }
-
-  //----------------------------------------------------------------
-  // SetDqsEccTimings
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Online Spare
-  //----------------------------------------------------------------
-  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave banks
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Interleave Nodes
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave channels
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Programming Interleave registers
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
-  }
-
-  //----------------------------------------------------------------
-  // UMA Allocation & UMAMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  // ECC
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InitEcc (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Memory Clear
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.MemClr (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // OnDimm Thermal
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Save
-  //----------------------------------------------------------------
-  MemFeatMain.MemSave (MemMainPtr);
-
-  //----------------------------------------------------------------
-  // Memory DMI support
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemDmi (MemMainPtr)) {
-    return AGESA_CRITICAL;
-  }
-
-  return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c
deleted file mode 100644
index 38925cb095..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/HY/mmflowhy.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowhy.c
- *
- * Main Memory initialization sequence for HY
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/HY)
- * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function defines the memory initialization flow for
- *      systems that only support HY processors.
- *
- *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- *     @return          AGESA_STATUS
- *                          - AGESA_ALERT
- *                          - AGESA_FATAL
- *                          - AGESA_SUCCESS
- *                          - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowHy (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  )
-{
-  UINT8   Node;
-  UINT8   NodeCnt;
-  MEM_NB_BLOCK  *NBPtr;
-  MEM_TECH_BLOCK *TechPtr;
-  MEM_DATA_STRUCT *MemPtr;
-
-  NBPtr = MemMainPtr->NBPtr;
-  TechPtr = MemMainPtr->TechPtr;
-  NodeCnt = MemMainPtr->DieCount;
-  MemPtr = MemMainPtr->MemPtr;
-
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
-    MemPtr->IsFlowControlSupported = FALSE;
-    return AGESA_FATAL;
-  } else {
-    MemPtr->IsFlowControlSupported = TRUE;
-  }
-
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Initialize MCT
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Low voltage DDR3
-  //----------------------------------------------------------------
-  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
-  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Initialize DRAM and DCTs, and Create Memory Map
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    // Initialize Memory Controller and Dram
-    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
-      return AGESA_FATAL; //fatalexit
-    }
-
-    // Create memory map
-    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
-    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------
-  // If there is no dimm on the system, do fatal exit
-  //----------------------------------------------------
-  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
-    ASSERT (FALSE);
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Synchronize DCTs
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // CpuMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
-  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Before Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Restore
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemRestore (MemMainPtr)) {
-    // Do DQS training only if memory context restore fails
-
-    //----------------------------------------------------------------
-    // Training
-    //----------------------------------------------------------------
-    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
-    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
-    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
-      if (!MemFeatMain.Training (MemMainPtr)) {
-        return AGESA_FATAL;
-      }
-    }
-    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
-  }
-
-  //----------------------------------------------------------------
-  // Disable chipselects that fail training
-  //----------------------------------------------------------------
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
-  MemFeatMain.ExcludeDIMM (MemMainPtr);
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
-  //----------------------------------------------------------------
-  // OtherTiming
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
-  }
-
-  //----------------------------------------------------------------
-  // SetDqsEccTimings
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Online Spare
-  //----------------------------------------------------------------
-  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave banks
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Interleave Nodes
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave channels
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Programming Interleave registers
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
-  }
-
-  //----------------------------------------------------------------
-  // UMA Allocation & UMAMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  // ECC
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InitEcc (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Memory Clear
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.MemClr (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // OnDimm Thermal
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Save
-  //----------------------------------------------------------------
-  MemFeatMain.MemSave (MemMainPtr);
-
-  //----------------------------------------------------------------
-  // Memory DMI support
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemDmi (MemMainPtr)) {
-    return AGESA_CRITICAL;
-  }
-
-  return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c
deleted file mode 100644
index 6f4d6af4ed..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/PH/mmflowPh.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowPh.c
- *
- * Main Memory initialization sequence for PH
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/PH)
- * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnPh.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function defines the memory initialization flow for
- *      systems that only support PH processors.
- *
- *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- *     @return          AGESA_STATUS
- *                          - AGESA_ALERT
- *                          - AGESA_FATAL
- *                          - AGESA_SUCCESS
- *                          - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowPh (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  )
-{
-  UINT8   Node;
-  UINT8   NodeCnt;
-  MEM_NB_BLOCK  *NBPtr;
-  MEM_TECH_BLOCK *TechPtr;
-  MEM_DATA_STRUCT *MemPtr;
-
-  NBPtr = MemMainPtr->NBPtr;
-  TechPtr = MemMainPtr->TechPtr;
-  NodeCnt = MemMainPtr->DieCount;
-  MemPtr = MemMainPtr->MemPtr;
-
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
-    MemPtr->IsFlowControlSupported = FALSE;
-    return AGESA_FATAL;
-  } else {
-    MemPtr->IsFlowControlSupported = TRUE;
-  }
-
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Initialize MCT
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Low voltage DDR3
-  //----------------------------------------------------------------
-  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
-  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Initialize DRAM and DCTs, and Create Memory Map
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    // Initialize Memory Controller and Dram
-    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
-    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
-      return AGESA_FATAL; // fatalexit
-    }
-
-    // Create memory map
-    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
-    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------
-  // If there is no dimm on the system, do fatal exit
-  //----------------------------------------------------
-  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
-    ASSERT (FALSE);
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Synchronize DCTs
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // CpuMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
-  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Before Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Restore
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemRestore (MemMainPtr)) {
-    // Do DQS training only if memory context restore fails
-
-    //----------------------------------------------------------------
-    // Training
-    //----------------------------------------------------------------
-    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
-    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
-    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
-      if (!MemFeatMain.Training (MemMainPtr)) {
-        return AGESA_FATAL;
-      }
-    }
-    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
-  }
-
-  //----------------------------------------------------------------
-  // Disable chipselects that fail training
-  //----------------------------------------------------------------
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
-  MemFeatMain.ExcludeDIMM (MemMainPtr);
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
-  //----------------------------------------------------------------
-  // OtherTiming
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
-  }
-
-  //----------------------------------------------------------------
-  // SetDqsEccTimings
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Online Spare
-  //----------------------------------------------------------------
-  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave banks
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Interleave Nodes
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave channels
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Programming Interleave registers
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
-  }
-
-  //----------------------------------------------------------------
-  // UMA Allocation & UMAMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave region
-  //----------------------------------------------------------------
-  NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
-
-  //----------------------------------------------------------------
-  // ECC
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InitEcc (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Memory Clear
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.MemClr (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // OnDimm Thermal
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Save
-  //----------------------------------------------------------------
-  MemFeatMain.MemSave (MemMainPtr);
-
-  //----------------------------------------------------------------
-  // Memory DMI support
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemDmi (MemMainPtr)) {
-    return AGESA_CRITICAL;
-  }
-
-  return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c
deleted file mode 100644
index cf0a3af630..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/RB/mmflowRb.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowRb.c
- *
- * Main Memory initialization sequence for RB
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/RB)
- * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnRb.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function defines the memory initialization flow for
- *      systems that only support RB processors.
- *
- *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- *     @return          AGESA_STATUS
- *                          - AGESA_ALERT
- *                          - AGESA_FATAL
- *                          - AGESA_SUCCESS
- *                          - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowRb (
-  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
-  )
-{
-  UINT8   Node;
-  UINT8   NodeCnt;
-  MEM_NB_BLOCK  *NBPtr;
-  MEM_TECH_BLOCK *TechPtr;
-  MEM_DATA_STRUCT *MemPtr;
-
-  NBPtr = MemMainPtr->NBPtr;
-  TechPtr = MemMainPtr->TechPtr;
-  NodeCnt = MemMainPtr->DieCount;
-  MemPtr = MemMainPtr->MemPtr;
-
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
-    MemPtr->IsFlowControlSupported = FALSE;
-    return AGESA_FATAL;
-  } else {
-    MemPtr->IsFlowControlSupported = TRUE;
-  }
-
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Initialize MCT
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Low voltage DDR3
-  //----------------------------------------------------------------
-  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
-  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Initialize DRAM and DCTs, and Create Memory Map
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    // Initialize Memory Controller and Dram
-    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
-    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
-      return AGESA_FATAL; // fatalexit
-    }
-
-    // Create memory map
-    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
-    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------
-  // If there is no dimm on the system, do fatal exit
-  //----------------------------------------------------
-  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
-    ASSERT (FALSE);
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Synchronize DCTs
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // CpuMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
-  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Before Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Restore
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemRestore (MemMainPtr)) {
-    // Do DQS training only if memory context restore fails
-
-    //----------------------------------------------------------------
-    // Training
-    //----------------------------------------------------------------
-    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
-    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
-    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
-      if (!MemFeatMain.Training (MemMainPtr)) {
-        return AGESA_FATAL;
-      }
-    }
-    IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
-  }
-
-  //----------------------------------------------------------------
-  // Disable chipselects that fail training
-  //----------------------------------------------------------------
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
-  MemFeatMain.ExcludeDIMM (MemMainPtr);
-  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
-  //----------------------------------------------------------------
-  // OtherTiming
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Training Table values
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
-  }
-
-  //----------------------------------------------------------------
-  // SetDqsEccTimings
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Online Spare
-  //----------------------------------------------------------------
-  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave banks
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Interleave Nodes
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave channels
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Programming Interleave registers
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
-  }
-
-  //----------------------------------------------------------------
-  // UMA Allocation & UMAMemTyping
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Interleave region
-  //----------------------------------------------------------------
-  NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
-
-  //----------------------------------------------------------------
-  // ECC
-  //----------------------------------------------------------------
-  if (!MemFeatMain.InitEcc (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // Memory Clear
-  //----------------------------------------------------------------
-  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
-  if (!MemFeatMain.MemClr (MemMainPtr)) {
-    return AGESA_FATAL;
-  }
-
-  //----------------------------------------------------------------
-  // OnDimm Thermal
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
-      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
-        return AGESA_FATAL;
-      }
-    }
-  }
-
-  //----------------------------------------------------------------
-  // Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
-      return AGESA_FATAL;
-    }
-  }
-
-  //----------------------------------------------------------------
-  // After Finalize MCT
-  //----------------------------------------------------------------
-  for (Node = 0; Node < NodeCnt; Node++) {
-    MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
-  }
-
-  //----------------------------------------------------------------
-  // Memory Context Save
-  //----------------------------------------------------------------
-  MemFeatMain.MemSave (MemMainPtr);
-
-  //----------------------------------------------------------------
-  // Memory DMI support
-  //----------------------------------------------------------------
-  if (!MemFeatMain.MemDmi (MemMainPtr)) {
-    return AGESA_CRITICAL;
-  }
-
-  return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c
deleted file mode 100644
index aae30e0a32..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnParTrainc32.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainc32.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the C32 specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE
-/*-----------------------------------------------------------------------------
-*                                EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-);
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *       This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  Launch training on AP successfully.
- *     @return          FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  AMD_CONFIG_PARAMS *StdHeader;
-  DIE_STRUCT *MCTPtr;
-  REMOTE_TRAINING_ENV *EnvPtr;
-  AP_TASK TrainingTask;
-  UINT8 Socket;
-  UINT8 Module;
-  UINT8 APCore;
-  UINT8 p;
-  UINT32 LowCore;
-  UINT32 HighCore;
-  UINT32 BspSocket;
-  UINT32 BspModule;
-  UINT32 BspCore;
-  AGESA_STATUS Status;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-  UINT16 MctDataSize;
-  StdHeader = &(NBPtr->MemPtr->StdHeader);
-  MCTPtr = NBPtr->MCTPtr;
-  Socket = MCTPtr->SocketId;
-  Module = MCTPtr->DieId;
-
-  //
-  // Allocate buffer for REMOTE_TRAINING_ENV
-  //
-  MctDataSize = MAX_DCTS_PER_NODE_C32 * (
-                  sizeof (DCT_STRUCT) + (
-                    MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                  )
-                );
-  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
-    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
-    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
-    //
-    // Setup Remote training environment
-    //
-    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
-    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
-    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
-      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
-    }
-    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
-    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockC32;
-    EnvPtr->FeatPtr = NBPtr->FeatPtr;
-    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
-    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
-    EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
-    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
-    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
-    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
-    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
-    //
-    // Get Socket, Core of the BSP
-    //
-    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
-    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
-    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
-    //
-    // Set up the remote task structure
-    //
-    TrainingTask.DataTransfer.DataPtr = EnvPtr;
-    TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
-    TrainingTask.DataTransfer.DataTransferFlags = 0;
-    TrainingTask.ExeFlags = 0;
-    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
-    //
-    // Get Target AP Core
-    //
-    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
-    APCore = (UINT8) (LowCore & 0x000000FF);
-
-    //
-    // Launch Remote Training
-    //
-    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
-    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-
-    return TRUE;
-  } else {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
-    return FALSE;
-  }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-  )
-{
-  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
-  MemNInitNBDataC32 (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  //----------------------------------------------------------------------------
-  // Get TSC rate of the this AP
-  //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
-  FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c
deleted file mode 100644
index ff2218058a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.c
+++ /dev/null
@@ -1,729 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3c32.c
- *
- * C32 memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnc32.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3c32.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_C32_MNS3C32_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstC32 (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegC32 (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncC32[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegC32},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorC32[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefC32 = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorC32) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorC32,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorC32[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA4,  0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefC32 = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorC32,
-  PciSpecialCaseFuncC32
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorC32[] = {
-  // DCT0
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-
-    // DCT1
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefC32 = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorC32,
-  PciSpecialCaseFuncC32
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorC32[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefC32 = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorC32) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorC32,
-  NULL
-};
-
-VOID *MemS3RegListC32[] = {
-  (VOID *)&S3PciPreSelfRefC32,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefC32,
-  (VOID *)&S3CPciPostSelfRefC32,
-  (VOID *)&S3MSRPreSelfRefC32,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *     @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemS3ResumeConstructNBBlockC32 (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for C32
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[PCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_C32 + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CPCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_C32 + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[MSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_C32 + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CMSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_C32 + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstC32 (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListC32) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListC32[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListC32[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in, out]  *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegC32 (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_C32);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegC32[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_C32);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegC32[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.h
deleted file mode 100644
index dbfaab86cf..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnS3c32.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3c32.h
- *
- * S3 resume memory related function for C32.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3C32_H_
-#define _MNS3C32_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of C32
-typedef enum {
-  PCI_LST_ESR_C32,  ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_C32,      ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_C32, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_C32,     ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_C32,  ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_C32,      ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_C32, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_C32      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDC32;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3C32_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
deleted file mode 100644
index f46d5010fe..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnc32.c
- *
- * Common Northbridge  functions for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 46997 $ @e \$Date: 2011-02-12 15:40:19 +0800 (Sat, 12 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNC32_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
-  }
-
-  MemNInitNBDataC32 (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_C32;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_256B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0x1FF;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->InitializeMCT = MemNInitializeMctC32;
-  NBPtr->FinalizeMCT = MemNFinalizeMctC32;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdC32;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternC32;
-  NBPtr->ReadPattern = MemNReadPatternC32;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = MemNAutoConfigC32;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingC32;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->OtherTiming = MemNOtherTimingC32;
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
-  NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  MemNInitNBDataNb (NBPtr);
-
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitC32;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompC32;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecC32;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitC32;
-  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[SetDllShutDown] = TRUE;
-  NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
-  NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
-  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
-  NBPtr->IsSupported[CheckODTControls] = TRUE;
-  NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-
-  NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrC32;
-  NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsC32 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-  //
-
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedC32 (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h
deleted file mode 100644
index cc739af560..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnc32.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnc32.h
- *
- * Northbridge C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNC32_H_
-#define _MNC32_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_C32    2
-#define MAX_DCTS_PER_NODE_C32          2
-#define MAX_CHANNELS_PER_DCT_C32       1
-#define MAX_NODES_SUPPORTED_C32        8
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemConstructNBBlockC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsC32 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-BOOLEAN
-MemNInitializeMctC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNFinalizeMctC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNSendMrsCmdC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNAutoConfigC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNOtherTimingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitPhyCompC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNWritePatternC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-VOID
-InitNBRegTableC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  );
-
-UINT8
-MemNGetSocketRelativeChannelC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Dct,
-  IN       UINT8 Channel
-  );
-
-BOOLEAN
-MemNIsIdSupportedC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  );
-
-VOID
-MemNBeforeDramInitC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNEnDLLShutDownC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-UINT32
-MemNCmnGetSetFieldC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  );
-
-VOID
-MemNBeforePlatformSpecC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-memNEnableTrainSequenceC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNInitExtMMIOAddrC32  (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *OptParam
-  );
-
-VOID
-MemNBeforeDQSTrainingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNForceLvDimmVoltageC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *MemMainPtr
-  );
-
-#endif  /* _MNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c
deleted file mode 100644
index 7a1feb490b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mndctc32.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctc32.c
- *
- * Northbridge DCT support for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "merrhdl.h"
-#include "cpuFamRegisters.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_NB_C32_MNDCTC32_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function programs the memory controller with configuration parameters
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - An Error value lower than AGESA_ERROR may have occurred
- *     @return          FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
- *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-MemNAutoConfigC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 PowerDownMode;
-  UINT32 Value32;
-  DIE_STRUCT *MCTPtr;
-  DCT_STRUCT *DCTPtr;
-  MEM_PARAMETER_STRUCT *RefPtr;
-
-  RefPtr = NBPtr->RefPtr;
-  MCTPtr = NBPtr->MCTPtr;
-  DCTPtr = NBPtr->DCTPtr;
-  //======================================================================
-  // Build Dram Control Register Value (F2x78)
-  //======================================================================
-  //
-  //It is recommended that these bits remain in the default state.
-  //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5);
-
-  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
-  //======================================================================
-  // Build Dram Config Lo Register Value
-  //======================================================================
-  //
-
-  if (MCTPtr->Status[SbParDimms]) {
-    //
-    // SbParDimms should be set for all DDR3 RDIMMS
-    // Cannot turn off ParEn for DDR3
-    //
-    //@attention - add debug option for parity control
-    MemNSetBitFieldNb (NBPtr, BFParEn, 1);
-  }
-
-  if (MCTPtr->GangedMode) {
-    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
-  if (!MCTPtr->Status[SbRegistered]) {
-    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
-  }
-
-  if (MCTPtr->Status[SbEccDimms]) {
-    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
-  }
-
-  //======================================================================
-  // Build Dram Config Hi Register Value
-  //======================================================================
-  //
-
-  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
-  if (MCTPtr->Status[SbRegistered]) {
-    if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) {
-      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
-    }
-  }
-
-  if (RefPtr->EnableBankSwizzle) {
-    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
-  }
-
-  if (DCTPtr->Timings.DimmQrPresent) {
-    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
-    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
-    }
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
-  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
-  //======================================================================
-  // Build Dram Config Misc Register Value
-  //======================================================================
-  //
-  if (MCTPtr->Status[SbRegistered]) {
-    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
-      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
-    }
-  }
-  //======================================================================
-  // Build Dram Config Misc 2 Register Value
-  //======================================================================
-  //
-  //
-  // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms
-  //
-  if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) {
-    MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1);
-  }
-  //
-  // DTaxTxFifpWrDly
-  //
-  Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
-  if ((Value32 >= 2) && (Value32 <= 5)) {
-    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32));
-  }
-
-  //
-  // ProgOdtEn
-  //
-  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
-    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1);
-  } else {
-    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0);
-  }
-  //
-  // OdtSwizzle
-  //
-  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) {
-    PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode);
-    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
-    if (PowerDownMode == 1) {
-      MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
-    }
-  }
-
-
-  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sends an MRS command
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSwapBitsNb (NBPtr);
-
-  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
-  // 1.Set SendMrsCmd=1
-  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
-  // 2.Wait for SendMrsCmd=0
-  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This is a general purpose function that executes before DRAM init
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
-    MemNSwitchDCTNb (NBPtr, Dct);
-    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-      //Set PllLockTime and DllLockTime to default.
-      MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
-      MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
-      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Enable DLL Shut down
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNEnDLLShutDownC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  BOOLEAN DllShutDownEn;
-
-  DllShutDownEn = TRUE;
-  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
-
-  if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
-    if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) {
-      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-        MemNSwitchDCTNb (NBPtr, Dct);
-        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-          MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
-          MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
-          MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
-        }
-      }
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Workaround for erratum 322 and 263
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  // Errata 263
-  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
-  } else {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
-  }
-
-  // Errata 322
-  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
-  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
-  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
-  //    greater than or equal to 011b (DDR-800 and higher),
-  //    then write 00000080h to F2x[1,0]9C_xD02E001,
-  //    else write 00000090h to F2x[1,0]9C_xD02E001.
-  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *    Initializes extended MMIO address space
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   OptParam - Optional parameter
- *
- *     @return    TRUE
- */
-BOOLEAN
-MemNInitExtMMIOAddrC32  (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *OptParam
-  )
-{
-  UINT8  Index;
-  UINT32 Value;
-  PCI_ADDR PciAddr;
-
-  if (NBPtr->RefPtr->SysLimit >= _1TB_RJ16) {
-    // Initialize all indices of F1x114_x2 and F1x114_x3.
-    for (Index = 0; Index < 32; Index++) {
-      PciAddr = NBPtr->PciAddr;
-      PciAddr.Address.Function = 1;
-
-      PciAddr.Address.Register = 0x110;
-      Value = 0x20000000 | Index;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-
-      PciAddr.Address.Register = 0x114;
-      Value = 0;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-
-      PciAddr.Address.Register = 0x110;
-      Value = 0x30000000 | Index;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-
-      PciAddr.Address.Register = 0x114;
-      Value = 0;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-    }
-  }
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *    Force LvDimm voltage to 1.5V for D0 part
- *
- *     @param[in,out]   *NBPtr       - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemMainPtr  - Pointer to MEM_MAIN_DATA_BLOCK
- *
- *     @return    TRUE
- */
-BOOLEAN
-MemNForceLvDimmVoltageC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *MemMainPtr
-  )
-{
-  MEM_PARAMETER_STRUCT *ParameterPtr;
-  MEM_SHARED_DATA *mmSharedPtr;
-
-  mmSharedPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->mmSharedPtr;
-  ParameterPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->MemPtr->ParameterListPtr;
-
-  if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D0) != 0) {
-    IDS_HDT_CONSOLE (MEM_FLOW, "\n\nC32 D0 on socket %d.\n", NBPtr->MCTPtr->SocketId);
-    if (((1 << CONVERT_VDDIO_TO_ENCODED (VOLT1_5)) & mmSharedPtr->VoltageMap) != 0) {
-      IDS_HDT_CONSOLE (MEM_FLOW, "\nDimms are 1.5V capable. Adjust voltage to 1.5V.\n");
-      ParameterPtr->DDR3Voltage = VOLT1_5;
-    } else {
-      if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_LVDIMM_VOLT1_5_SUPPORT, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) {
-        IDS_HDT_CONSOLE (MEM_FLOW, "\nDimms are not 1.5V capable. Adjust voltage to 1.5V based on customer's choice.\n\n");
-        ParameterPtr->DDR3Voltage = VOLT1_5;
-      } else {
-        IDS_HDT_CONSOLE (MEM_FLOW, "\nDimms are not 1.5V capable. Do not adjust voltage based on customer's choice.\n\n");
-        PutEventLog (AGESA_FATAL, MEM_ERROR_VDDIO_UNSUPPORTED, NBPtr->Node, 0, 0, 0, &(NBPtr->MemPtr->StdHeader));
-        SetMemError (AGESA_FATAL, NBPtr->MCTPtr);
-      }
-    }
-  }
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
deleted file mode 100644
index d9609ca6be..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnflowc32.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowc32.c
- *
- * C32 initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNFLOWC32_FILECODE
-/* features */
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledC32[f] != NULL);
-        if (memPlatSpecFFInstalledC32[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c
deleted file mode 100644
index 59949487ef..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnidendimmc32.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmc32.c
- *
- * C32 northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Ganged = FALSE;
-  InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32;
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c
deleted file mode 100644
index 7235b1c6da..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnmctc32.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmctc32.c
- *
- * Northbridge C32 MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNMCTC32_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets final values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-  UINT16 Speed;
-  UINT32 ExtMctCfgLoRegVal;
-
-  MemPtr = NBPtr->MemPtr;
-  Speed = NBPtr->DCTPtr->Timings.Speed;
-  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);
-
-  ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
-  ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;
-
-  ExtMctCfgLoRegVal &= 0x0FFFFFFF;
-  if (Speed == DDR667_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x40000000;
-  } else if (Speed == DDR800_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x50000000;
-  } else if (Speed == DDR1066_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x60000000;
-  } else if (Speed == DDR1333_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x80000000;
-  } else {
-    ExtMctCfgLoRegVal |= 0x90000000;
-  }
-  MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);
-
-  if (NBPtr->Node == BSP_DIE) {
-    if (!NBPtr->ClToNbFlag) {
-      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
-      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    }
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets initial values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-
-  MemPtr = NBPtr->MemPtr;
-
-  if (NBPtr->Node == BSP_DIE) {
-    LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    if (SMsr.lo & ((UINT32)1 << 15)) {
-      NBPtr->ClToNbFlag = 1;
-    }
-    SMsr.lo |= (UINT32)1 << 15;                   // ClLinesToNbDis
-    LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi |= (UINT32)1 << (48 - 32);              // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c
deleted file mode 100644
index cf8ba2a682..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnotc32.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnotc32.c
- *
- * Northbridge Non-SPD timings for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNOTC32_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-UINT32
-STATIC
-MemNGetODTDelaysC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSwitchDCTNb (NBPtr, 0);
-  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
-    MemNSetOtherTimingC32 (NBPtr);
-    MemNPowerDownCtlNb (NBPtr);
-    MemNEnDLLShutDownC32 (NBPtr);
-  }
-
-  MemNSwitchDCTNb (NBPtr, 1);
-  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
-    MemNSetOtherTimingC32 (NBPtr);
-    MemNPowerDownCtlNb (NBPtr);
-    MemNEnDLLShutDownC32 (NBPtr);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings  in PCI registers
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-
-  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function gets the ODT delays
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-UINT32
-STATIC
-MemNGetODTDelaysC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  INT8 Ld;
-  UINT32 ODTDelays;
-  //
-  // On revision D processors, the BIOS must additionally configure the ODT pattern
-  // and the ODT switching delays.
-  //
-  // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
-  //     -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
-  //     -Value of 2, BL = 4 else assume BL=8.
-  //     -Initialize ODTDelays based on BL value
-  //     -WrOdtOnDuration [14:12] = BL / 2 + 1
-  //     -WrOdtTrnOnDly [10:8] = 0
-  //     -RdOdtOnDuration [6:4] = BL / 2 + 1
-  //
-  ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
-
-  // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
-  // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
-  Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
-  if (Ld < 0) {
-    Ld = 0;
-  }
-  if (Ld > 7) {
-    Ld = 7;
-  }
-  ODTDelays += Ld;
-  return ODTDelays;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function enables power down mode
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_PARAMETER_STRUCT *RefPtr;
-  UINT8 PowerDownMode;
-
-  RefPtr = NBPtr->RefPtr;
-
-  // we can't enable powerdown mode when doing WL
-  if (RefPtr->EnablePowerDown) {
-    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
-    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
-    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
-    if (PowerDownMode) {
-      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c
deleted file mode 100644
index 3756a2449e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnphyc32.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnphyc32.c
- *
- * Northbridge Phy support for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 46120 $ @e \$Date: 2011-01-28 16:00:01 +0800 (Fri, 28 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNPHYC32_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the DDR phy compensation logic
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitPhyCompC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
-  CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
-  CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
-  CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
-  UINT8 i;
-  UINT8 j;
-  UINT8 CurrDct;
-  CurrDct = NBPtr->Dct;
-  // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
-  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
-  // DisAutoComp will be cleared after Dram init has completed
-  //
-  MemNSwitchDCTNb (NBPtr, 0);
-  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
-  MemUWait10ns (500, NBPtr->MemPtr);
-  MemNSwitchDCTNb (NBPtr, CurrDct);
-
-  // 3. For each normalized driver strength code read from
-  // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
-  // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
-  //
-  // 4. For each normalized driver strength code read from
-  // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
-  // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
-  // D3Cmp2PCal].
-  //
-  j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
-  i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  ASSERT (j <= 3);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
-
-  if ((NBPtr->ChannelPtr->Dimms == 3) &&
-      ((NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) ||
-       (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY))) {
-    //
-    // Special Case for 3 Dimms @ 800MHz or 1066MHz
-    //
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 1);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 1);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 1);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 1);
-  } else {
-    ASSERT (i <= 3);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
-  }
-  MemNSwitchDCTNb (NBPtr, CurrDct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This is a general purpose function that executes before DRAM training
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDQSTrainingC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 ChipSel;
-  UINT32 TestAddrRJ16;
-  UINT32 RealAddr;
-
-  MemTBeginTraining (NBPtr->TechPtr);
-
-  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-    MemNSwitchDCTNb (NBPtr, Dct);
-    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
-        if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
-
-          RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
-
-          MemUDummyCLRead (RealAddr);
-
-          MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
-          MemUWait10ns (60, NBPtr->MemPtr);   // Wait 300ns
-          MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
-          MemUWait10ns (400, NBPtr->MemPtr);  // Wait 2us
-          MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
-          break;
-        }
-      }
-    }
-    if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
-      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
-        MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
-      }
-      if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
-        MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
-      }
-    }
-  }
-
-  MemTEndTraining (NBPtr->TechPtr);
-
-  MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnprotoc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnprotoc32.c
deleted file mode 100644
index 39d0a0e140..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnprotoc32.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotoc32.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNPROTOC32_FILECODE
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c
deleted file mode 100644
index ebf73e052b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregc32.c
- *
- * Common Northbridge register related functions for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 47676 $ @e \$Date: 2011-02-25 06:29:57 +0800 (Fri, 25 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNREGC32_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- *     MemNIsIdSupportedC32
- *      This function matches the CPU_LOGICAL_ID with certain criteria to
- *      determine if it is supported by this NBBlock.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- *     @return          TRUE -  This node is a C32.
- *     @return          FALSE - This node is not a C32.
- *
- */
-BOOLEAN
-MemNIsIdSupportedC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  )
-{
-  if (((LogicalIdPtr->Family & AMD_FAMILY_10_C32) != 0) && ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0)) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *      This function calculates the memory channel index relative to the
- *      socket, taking the Die number, the Dct, and the channel.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Dct
- *     @param[in] Channel
- *
- */
-UINT8
-MemNGetSocketRelativeChannelC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Dct,
-  IN       UINT8 Channel
-  )
-{
-  return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_C32) + Dct);
-}
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function gets or sets a value to a bit field in a PCI register.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]   FieldName - Bit Field to be programmed
- *     @param[in]   Field - Value to be programmed
- *     @param[in]   IsSet - Indicates if the function will set or get
- *
- *     @return      value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  )
-{
-  TSEFO Address;
-  PCI_ADDR PciAddr;
-  UINT8 Type;
-  UINT8 IsLinked;
-  UINT32 Value;
-  UINT32 Highbit;
-  UINT32 Lowbit;
-  UINT32 Mask;
-
-  Value = 0;
-  if (FieldName < BFEndOfList) {
-    Address = NBPtr->NBRegTable[FieldName];
-    if (Address) {
-      Lowbit = TSEFO_END (Address);
-      Highbit = TSEFO_START (Address);
-      Type = (UINT8) TSEFO_TYPE (Address);
-      IsLinked = (UINT8) TSEFO_LINKED (Address);
-
-      // If Fn2 and DCT1 selected, set Address to be 1xx
-      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
-        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
-          Address |= 0x0100;
-        }
-      }
-
-      ASSERT ((Address & ((UINT32) 1) << 28) == 0);   // Phy direct access method is not supported
-
-      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
-        // Special DCT Phy access
-        Address &= 0x0FFFFFFF;
-        Lowbit = 0;
-        Highbit = 16;
-        IsLinked = 0;
-      } else {
-        // Normal DCT Phy access
-        Address = TSEFO_OFFSET (Address);
-      }
-
-      if (Type == NB_ACCESS) {
-        PciAddr.AddressValue = Address;
-        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-        Address = PciAddr.AddressValue;
-        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-        if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-            (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value);
-        }
-      } else if (Type == DCT_PHY_ACCESS) {
-        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-        IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
-      } else if (Type == DCT_EXTRA) {
-        MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
-        MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-        Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
-        IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
-      } else {
-        IDS_ERROR_TRAP;
-      }
-
-      if (IsSet) {
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        } else {
-          Mask = (UINT32)0xFFFFFFFF;
-        }
-        Value &= ~(Mask << Lowbit);
-        Value |= (Field & Mask) << Lowbit;
-
-        if (Type == NB_ACCESS) {
-          PciAddr.AddressValue = Address;
-          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-          if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-              (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-            IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field);
-          }
-        } else if (Type == DCT_PHY_ACCESS) {
-          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
-          Address |= DCT_ACCESS_WRITE;
-          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
-        } else if (Type == DCT_EXTRA) {
-          MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
-          Address |= DCT_ACCESS_WRITE;
-          MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
-          MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
-        } else {
-          IDS_ERROR_TRAP;
-        }
-        if (IsLinked) {
-          MemNCmnGetSetFieldC32 (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
-        }
-      } else {
-        Value = Value >> Lowbit;  // Shift
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        }
-        if (IsLinked) {
-          Value |= MemNCmnGetSetFieldC32 (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
-        }
-      }
-    }
-  } else {
-    IDS_ERROR_TRAP;   // Invalid bit field index
-  }
-  return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes bit field translation table
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   NBRegTable[]  - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableC32 (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  )
-{
-  UINT16 i;
-
-  // Allocate heap for NB register table
-  if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabC32)) {
-    return;     // escape if fails
-  }
-  NBRegTable = NBPtr->NBRegTable;
-
-  for (i = 0; i < BFEndOfList; i++) {
-    NBRegTable[i] = 0;
-  }
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31,  0, BFDctExtraOffsetReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31,  0, BFExtMctCfgLoReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFDisableL3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  7,  7, BFProgOdtEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31,  0, BFUSPLLCtlAll);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31,  0, BFDSPLLCtlAll);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606,  0,  0, BFUSNibbleAlignEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690,  2,  2, BFChnLinitClkEn);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x180, 31, 0, BFPhyRODTCSLow);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x181, 31, 0, BFPhyRODTCSHigh);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x182, 31, 0, BFPhyWODTCSLow);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x183, 31, 0, BFPhyWODTCSHigh);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  9,  9, BFTS2BitLockEn);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  8,  8, BFTS2En);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  4,  4, BFTS1En);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  1,  1, BFTS0LinkStarEn);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  0,  0, BFTS0En);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15,  0, BFLinkTrainData);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010,  1,  1, BFRstTxFifoPtrs);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010,  0,  0, BFTxFifoPtrInit);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15,  0, BFLpbkData);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014,  9,  4, BFLnkLpBkLat);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014,  1,  1, BFLpbkRndTripLatDone);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014,  0,  0, BFLnkLatTrainEn);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020,  1,  1, BFDsPhyReset);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020,  0,  0, BFLinkReset);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
-  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
-  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
-  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c
deleted file mode 100644
index 4abd8dd97b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnParTrainDa.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainDa.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the Deerhound specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/HCTRN)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE
-
-/*-----------------------------------------------------------------------------
-*                                EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-);
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *       This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  Launch training on AP successfully.
- *     @return          FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  AMD_CONFIG_PARAMS *StdHeader;
-  DIE_STRUCT *MCTPtr;
-  REMOTE_TRAINING_ENV *EnvPtr;
-  AP_TASK TrainingTask;
-  UINT8 Socket;
-  UINT8 Module;
-  UINT8 APCore;
-  UINT8 p;
-  UINT32 LowCore;
-  UINT32 HighCore;
-  UINT32 BspSocket;
-  UINT32 BspModule;
-  UINT32 BspCore;
-  AGESA_STATUS Status;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-  UINT16 MctDataSize;
-  StdHeader = &(NBPtr->MemPtr->StdHeader);
-  MCTPtr = NBPtr->MCTPtr;
-  Socket = MCTPtr->SocketId;
-  Module = MCTPtr->DieId;
-
-  //
-  // Allocate buffer for REMOTE_TRAINING_ENV
-  //
-  MctDataSize = MAX_DCTS_PER_NODE_DA * (
-                  sizeof (DCT_STRUCT) + (
-                    MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                  )
-                );
-  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
-    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
-    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
-    //
-    // Setup Remote training environment
-    //
-    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
-    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
-    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
-      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
-    }
-    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
-    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDA;
-    EnvPtr->FeatPtr = NBPtr->FeatPtr;
-    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
-    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
-    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
-    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
-    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
-    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
-    //
-    // Get Socket, Core of the BSP
-    //
-    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
-    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
-    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
-    //
-    // Set up the remote task structure
-    //
-    TrainingTask.DataTransfer.DataPtr = EnvPtr;
-    TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) ((AllocHeapParams.RequestedBufferSize + 3) / 4);
-    TrainingTask.DataTransfer.DataTransferFlags = 0;
-    TrainingTask.ExeFlags = 0;
-    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
-    //
-    // Get Target AP Core
-    //
-    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
-    APCore = (UINT8) (LowCore & 0x000000FF);
-
-    //
-    // Launch Remote Training
-    //
-    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
-    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-    return TRUE;
-  } else {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
-    return FALSE;
-  }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-  )
-{
-  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
-  MemNInitNBDataDA (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  //----------------------------------------------------------------------------
-  // Get TSC rate of the this AP
-  //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
-  FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c
deleted file mode 100644
index a186efd98d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.c
+++ /dev/null
@@ -1,746 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3da.c
- *
- * DA memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3da.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_DA_MNS3DA_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDA (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDA (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncDA[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDA},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDA[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDA = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorDA) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorDA,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDA[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT0,   BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Dll regulator disable
-  {{2, 2, 1}, DCT1,   BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDA = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorDA,
-  PciSpecialCaseFuncDA
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDA[] = {
-  // DCT0
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-    // DCT1
-  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // DllShutDown
-  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDA = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorDA,
-  PciSpecialCaseFuncDA
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDA[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDA = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorDA) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorDA,
-  NULL
-};
-
-VOID *MemS3RegListDA[] = {
-  (VOID *)&S3PciPreSelfRefDA,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefDA,
-  (VOID *)&S3CPciPostSelfRefDA,
-  (VOID *)&S3MSRPreSelfRefDA,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *      @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockDA (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDA;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDA;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDA;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for DA
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDA (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListDA) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListDA[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListDA[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in]   *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *      @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDA (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegDA[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegDA[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.h
deleted file mode 100644
index b3eb37472e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnS3da.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3da.h
- *
- * S3 resume memory related function for DA.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3DA_H_
-#define _MNS3DA_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of DA
-typedef enum {
-  PCI_LST_ESR_DA,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_DA,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_DA,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_DA,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_DA,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_DA,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_DA,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_DA,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3DA_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
deleted file mode 100644
index ed2ae37140..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnda.c
- *
- * Common Northbridge functions for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_NB_DA_MNDA_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL   (UINT32) 0x20000000
-#define CHANNEL_SELECT  (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
-  }
-
-  MemNInitNBDataDA (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  INT32 i;
-
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_72B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0xFF;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->InitializeMCT = MemNInitializeMctDA;
-  NBPtr->FinalizeMCT = MemNFinalizeMctDA;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternDA;
-  NBPtr->ReadPattern = MemNReadPatternDA;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = memNAutoConfigDA;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->OtherTiming = MemNOtherTimingDA;
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  MemNInitNBDataNb (NBPtr);
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
-  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[SetDllShutDown] = TRUE;
-  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[Check1GAlign] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
-  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
-  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
-  NBPtr->IsSupported[CheckDllStdBy] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->IsSupported[CheckDllRegDis] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsDA (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedDA (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h
deleted file mode 100644
index 8bf710f608..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnda.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnda.h
- *
- * Northbridge DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNDA_H_
-#define _MNDA_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_DA    2
-#define MAX_DCTS_PER_NODE_DA          2
-#define MAX_CHANNELS_PER_DCT_DA       1
-#define MAX_NODES_SUPPORTED_DA        8
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsDA (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-BOOLEAN
-MemNInitializeMctDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNFinalizeMctDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNSendMrsCmdDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-memNAutoConfigDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNOtherTimingDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNWritePatternDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemPNodeMemBoundaryDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   UINT32 *NodeSysLimit
-  );
-
-VOID
-InitNBRegTableDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  );
-
-VOID
-MemNBeforeDramInitDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNBeforePlatformSpecDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNIsIdSupportedDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  );
-
-BOOLEAN
-MemNChangeAvgValue3DA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNChangeAvgValue8DA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNEnDLLShutDownDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-UINT32
-MemNCmnGetSetFieldDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  );
-
-VOID
-MemNCapSpeedBatteryLifeDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-memNEnableTrainSequenceDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-#endif  /* _MNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c
deleted file mode 100644
index 38d8d0f7c9..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mndctda.c
+++ /dev/null
@@ -1,467 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctda.c
- *
- * Northbridge DA DCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuRegisters.h"
-#include "mport.h"
-#include "F10PackageType.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNDCTDA_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This is a general purpose function that executes before DRAM init
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-
-  //Setting the reset value of Phy DLL standby and shutdown registers.
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MemNSwitchDCTNb (NBPtr, Dct);
-    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-      //Set PllLockTime and DllLockTime to default.
-      MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
-      MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
-      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
-
-      //Clear PHY PLL Control Register before doing fence training and reset DLL
-      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0x00002000);
-      MemNSetBitFieldNb (NBPtr, BFPhyDLLControl, 0);
-      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0);
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function programs the memory controller with configuration parameters
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
- *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-memNAutoConfigDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  DIE_STRUCT *MCTPtr;
-  DCT_STRUCT *DCTPtr;
-  MEM_PARAMETER_STRUCT *RefPtr;
-
-  RefPtr = NBPtr->RefPtr;
-  MCTPtr = NBPtr->MCTPtr;
-  DCTPtr = NBPtr->DCTPtr;
-  //======================================================================
-  // Build Dram Control Register Value (F2x78)
-  //======================================================================
-  //
-
-  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
-  //======================================================================
-  // Build Dram Config Lo Register Value
-  //======================================================================
-  //
-
-  if (MCTPtr->Status[SbParDimms]) {
-    //
-    // SbParDimms should be set for all DDR3 RDIMMS
-    // Cannot turn off ParEn for DDR3
-    //
-    //@attention - add debug option for parity control
-    MemNSetBitFieldNb (NBPtr, BFParEn, 1);
-  }
-
-
-  if (MCTPtr->GangedMode) {
-    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
-  if (!MCTPtr->Status[SbRegistered]) {
-    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
-  }
-
-  if (MCTPtr->Status[SbEccDimms]) {
-    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
-  }
-
- //======================================================================
-  // Build Dram Config Hi Register Value
-  //======================================================================
-  //
-
-  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
-  if (MCTPtr->Status[SbRegistered]) {
-    if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) {
-      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
-    }
-  }
-
-  if (RefPtr->EnableBankSwizzle) {
-    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
-  }
-
-  if (DCTPtr->Timings.DimmQrPresent) {
-    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
-    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
-    }
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
-
-  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
-
-  //======================================================================
-  // Build Dram Config Misc Register Value
-  //======================================================================
-  //
-  MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
-  // For DDR3 Registered Dimms
-  if (MCTPtr->Status[SbRegistered]) {
-    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
-      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
-    }
-  }
-  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sends an MRS command
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSwapBitsNb (NBPtr);
-
-  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
-  // 1.Set SendMrsCmd=1
-  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
-  // 2.Wait for SendMrsCmd=0
-  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Workaround for erratum 322 and 263
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  // Errata 263
-  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
-  } else {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
-  }
-
-  // Errata 322
-  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
-  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
-  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
-  //    greater than or equal to 011b (DDR-800 and higher),
-  //    then write 00000080h to F2x[1,0]9C_xD02E001,
-  //    else write 00000090h to F2x[1,0]9C_xD02E001.
-  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Change Average Value of 3
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-BOOLEAN
-MemNChangeAvgValue3DA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/**
- *
- *
- *   Change Average Value of 8
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-BOOLEAN
-MemNChangeAvgValue8DA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C1) != 0) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Enable DLL Shut down
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNEnDLLShutDownDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  BOOLEAN DllShutDownEn;
-
-  DllShutDownEn = TRUE;
-  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
-
-  if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
-    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-      MemNSwitchDCTNb (NBPtr, Dct);
-      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-        MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
-        MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
-        MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
-      }
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function caps speed based on batter life check.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- */
-VOID
-MemNCapSpeedBatteryLifeDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST UINT16 SupportedFreq[] = {
-    DDR1600_FREQUENCY,
-    DDR1333_FREQUENCY,
-    DDR1066_FREQUENCY,
-    DDR800_FREQUENCY,
-    DDR667_FREQUENCY,
-    DDR533_FREQUENCY,
-    DDR400_FREQUENCY
-  };
-  UINT32 NBFreq;
-  UINT8 j;
-  UINT16 DdrFreq;
-  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
-  UINT32                  ProcessorPackageType;
-
-  FamilySpecificServices = NULL;
-  DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
-  ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
-  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
-  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
-    NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100;  // Calculate the Nb P1 frequency (NbFreq / 2)
-    for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
-      if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
-        // Pick Max MEMCLK that is less than or equal to (NCLK_P1 / 2)
-        DdrFreq = SupportedFreq[j];
-        break;
-      }
-    }
-    if (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife) {
-      if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
-        NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
-      }
-    } else {
-      PutEventLog (AGESA_WARNING, MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-      DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
-      NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;  // Calculate the Nb P0 frequency
-      for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
-        if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
-          // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2)
-          DdrFreq = SupportedFreq[j];
-          break;
-        }
-      }
-      if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
-        NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
-      }
-    }
-    if (((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C3) != 0) && (ProcessorPackageType == PACKAGE_TYPE_S1G3_S1G4 || ProcessorPackageType == PACKAGE_TYPE_ASB2)) {
-      MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 4);
-      MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 1);
-    } else {
-      MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
-      MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
-    }
-  } else {
-    NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;  // Calculate the Nb P0 frequency
-    for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
-      if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
-        // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2)
-        DdrFreq = SupportedFreq[j];
-        break;
-      }
-    }
-    if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
-      NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
-    }
-    MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
-    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
deleted file mode 100644
index 9a95b97f24..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnflowda.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowda.c
- *
- * Deerhound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNFLOWDA_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledDA[f] != NULL);
-        if (memPlatSpecFFInstalledDA[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c
deleted file mode 100644
index bac5693747..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnidendimmda.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmda.c
- *
- * DA northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Ganged = FALSE;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c
deleted file mode 100644
index d54018da97..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnmctda.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmctda.c
- *
- * Northbridge DA MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNMCTDA_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets final values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-
-  MemPtr = NBPtr->MemPtr;
-  MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
-  MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
-  MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
-  MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
-  // Recommended settings for F2x11C
-  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
-  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
-  MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
-  MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
-  // For power saving
-  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-      if (NBPtr->ChannelPtr->Dimmx4Present == 0) {
-        MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80));
-      }
-      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
-        MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0830, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0830) | 0x10));
-      }
-      MemNSetBitFieldNb (NBPtr, BFPhy0x0D07812F, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D07812F) | 0x01));
-    }
-  }
-
-  if (NBPtr->Node == BSP_DIE) {
-    if (!NBPtr->ClToNbFlag) {
-      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
-      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    }
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets initial values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-
-  MemPtr = NBPtr->MemPtr;
-
-  if (NBPtr->Node == BSP_DIE) {
-    LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    if (SMsr.lo & ((UINT32)1 << 15)) {
-      NBPtr->ClToNbFlag = 1;
-    }
-    SMsr.lo |= (UINT32)1 << 15;                   // ClLinesToNbDis
-    LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi |= (UINT32)1 << (48 - 32);              // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
deleted file mode 100644
index 1038dbfe0f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnotda.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnotda.c
- *
- * Northbridge Non-SPD timings for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNOTDA_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemNPowerDownCtlDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSwitchDCTNb (NBPtr, 0);
-  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
-    MemNSetOtherTimingDA (NBPtr);        // Set DA Timings
-    MemNPowerDownCtlNb (NBPtr);
-    MemNEnDLLShutDownDA (NBPtr);
-  }
-
-  MemNSwitchDCTNb (NBPtr, 1);
-  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
-    MemNSetOtherTimingDA (NBPtr);                // Set DA Timings
-    MemNPowerDownCtlNb (NBPtr);
-    MemNEnDLLShutDownDA (NBPtr);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings into the PCI registers
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function enables power down mode
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_PARAMETER_STRUCT *RefPtr;
-  UINT8 PowerDownMode;
-
-  RefPtr = NBPtr->RefPtr;
-
-  // we can't enable powerdown mode when doing WL
-  if (RefPtr->EnablePowerDown) {
-    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
-    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
-    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
-    if (PowerDownMode) {
-      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
-    }
-  }
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
deleted file mode 100644
index 8ad203f99a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnprotoda.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotoda.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function executes Node memory 1GB boundary alignment.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *NodeSysLimit   - Pointer to the NodeSysLimit
- *
- */
-
-VOID
-MemPNodeMemBoundaryDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   UINT32 *NodeSysLimit
-  )
-{
-  if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
-    // only apply to DDR2.
-    if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) {
-      // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node
-      *NodeSysLimit += 1;
-      *NodeSysLimit &= 0xFFFFC000;
-      *NodeSysLimit -= 1;
-    }
-  }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c
deleted file mode 100644
index c721618b49..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c
+++ /dev/null
@@ -1,579 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregda.c
- *
- * Common Northbridge register related functions for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 47676 $ @e \$Date: 2011-02-25 06:29:57 +0800 (Fri, 25 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNREGDA_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- *     MemNIsIdSupportedDA
- *      This function matches the CPU_LOGICAL_ID with certain criteria to
- *      determine if it is supported by this NBBlock.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- *     @return          TRUE -  This node is a RB.
- *     @return          FALSE - This node is not a RB.
- *
- */
-BOOLEAN
-MemNIsIdSupportedDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  )
-{
-
-  if (((LogicalIdPtr->Family & (AMD_FAMILY_10_BL | AMD_FAMILY_10_DA)) != 0)
-      && ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0)) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function gets or sets a value to a bit field in a PCI register.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]   FieldName - Bit Field to be programmed
- *     @param[in]   Field - Value to be programmed
- *     @param[in]   IsSet - Indicates if the function will set or get
- *
- *     @return      value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  )
-{
-  TSEFO Address;
-  PCI_ADDR PciAddr;
-  UINT8 Type;
-  UINT8 IsLinked;
-  UINT32 Value;
-  UINT32 Highbit;
-  UINT32 Lowbit;
-  UINT32 Mask;
-
-  Value = 0;
-  if (FieldName < BFEndOfList) {
-    Address = NBPtr->NBRegTable[FieldName];
-    if (Address) {
-      Lowbit = TSEFO_END (Address);
-      Highbit = TSEFO_START (Address);
-      Type = (UINT8) TSEFO_TYPE (Address);
-      IsLinked = (UINT8) TSEFO_LINKED (Address);
-
-      // If Fn2 and DCT1 selected, set Address to be 1xx
-      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
-        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
-          Address |= 0x0100;
-        }
-      }
-
-      ASSERT ((Address & ((UINT32) 1) << 28) == 0);   // Phy direct access method is not supported
-
-      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
-        // Special DCT Phy access
-        Address &= 0x0FFFFFFF;
-        Lowbit = 0;
-        Highbit = 16;
-        IsLinked = 0;
-      } else {
-        // Normal DCT Phy access
-        Address = TSEFO_OFFSET (Address);
-      }
-
-      if (Type == NB_ACCESS) {
-        PciAddr.AddressValue = Address;
-        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-        Address = PciAddr.AddressValue;
-        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-        if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-            (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value);
-        }
-      } else if (Type == DCT_PHY_ACCESS) {
-        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-        IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
-      } else {
-        IDS_ERROR_TRAP;
-      }
-
-      if (IsSet) {
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        } else {
-          Mask = (UINT32)0xFFFFFFFF;
-        }
-        Value &= ~(Mask << Lowbit);
-        Value |= (Field & Mask) << Lowbit;
-
-        if (Type == NB_ACCESS) {
-          PciAddr.AddressValue = Address;
-          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-          if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-              (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-            IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field);
-          }
-        } else if (Type == DCT_PHY_ACCESS) {
-          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
-          Address |= DCT_ACCESS_WRITE;
-          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-          IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
-        } else {
-          IDS_ERROR_TRAP;
-        }
-        if (IsLinked) {
-          MemNCmnGetSetFieldDA (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
-        }
-      } else {
-        Value = Value >> Lowbit;  // Shift
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        }
-        if (IsLinked) {
-          Value |= MemNCmnGetSetFieldDA (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
-        }
-      }
-    }
-  } else {
-    IDS_ERROR_TRAP;   // Invalid bit field index
-  }
-  return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes bit field translation table
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   NBRegTable[]   - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableDA (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  )
-{
-  UINT16 i;
-
-  // Allocate heap for NB register table
-  if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabDA)) {
-    return;     // escape if fails
-  }
-  NBRegTable = NBPtr->NBRegTable;
-
-  for (i = 0; i < BFEndOfList; i++) {
-    NBRegTable[i] = 0;
-  }
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFDisableL3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  0,  0, BFIntLvRgnSwapEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  9,  3, BFIntLvRgnBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  17, 11, BFIntLvRgnLmtAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  26, 20, BFIntLvRgnSize);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D, 31,  0, BFPhyDLLControl);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F0C);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D040F3E);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D042F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D042F3E);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D048F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D048F3E);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D04DF3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D04DF3E);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0F13, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0F13);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0830, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0830);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D07812F, _NOT_USED_, _NOT_USED_, BFPhy0x0D07812F);
-
-  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
-  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
-  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c
deleted file mode 100644
index f348f51900..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnParTrainDr.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainDr.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the Deerhound specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/HCTRN)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE
-
-/*-----------------------------------------------------------------------------
-*                                EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-);
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *       This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  Launch training on AP successfully.
- *     @return          FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  AMD_CONFIG_PARAMS *StdHeader;
-  DIE_STRUCT *MCTPtr;
-  REMOTE_TRAINING_ENV *EnvPtr;
-  AP_TASK TrainingTask;
-  UINT8 Socket;
-  UINT8 Module;
-  UINT8 APCore;
-  UINT8 p;
-  UINT32 LowCore;
-  UINT32 HighCore;
-  UINT32 BspSocket;
-  UINT32 BspModule;
-  UINT32 BspCore;
-  AGESA_STATUS Status;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-  UINT16 MctDataSize;
-
-  StdHeader = &(NBPtr->MemPtr->StdHeader);
-  MCTPtr = NBPtr->MCTPtr;
-  Socket = MCTPtr->SocketId;
-  Module = MCTPtr->DieId;
-
-  //
-  // Allocate buffer for REMOTE_TRAINING_ENV
-  //
-  MctDataSize = MAX_DCTS_PER_NODE_DR * (
-                  sizeof (DCT_STRUCT) + (
-                    MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                  )
-                );
-  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
-    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
-    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
-    //
-    // Setup Remote training environment
-    //
-    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
-    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
-    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
-      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
-    }
-    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
-    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDR;
-    EnvPtr->FeatPtr = NBPtr->FeatPtr;
-    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
-    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
-    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
-    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
-    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
-    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
-    //
-    // Get Socket, Core of the BSP
-    //
-    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
-    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
-    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
-    //
-    // Set up the remote task structure
-    //
-    TrainingTask.DataTransfer.DataPtr = EnvPtr;
-    TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
-    TrainingTask.DataTransfer.DataTransferFlags = 0;
-    TrainingTask.ExeFlags = 0;
-    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
-    //
-    // Get Target AP Core
-    //
-    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
-    APCore = (UINT8) (LowCore & 0x000000FF);
-
-    //
-    // Launch Remote Training
-    //
-    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
-    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-    return TRUE;
-  } else {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
-    return FALSE;
-  }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-  )
-{
-  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
-  MemNInitNBDataDr (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  //----------------------------------------------------------------------------
-  // Get TSC rate of the this AP
-  //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
-  FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c
deleted file mode 100644
index 897f825af0..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3dr.c
- *
- * DR memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mndr.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3dr.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_DR_MNS3DR_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDr (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDr (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncDr[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDr},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDr[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDr = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorDr) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorDr,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDr[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDr = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorDr,
-  PciSpecialCaseFuncDr
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDr[] = {
-  // DCT0
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-
-    // DCT1
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDr = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorDr,
-  PciSpecialCaseFuncDr
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDr[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDr = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorDr) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorDr,
-  NULL
-};
-
-VOID *MemS3RegListDr[] = {
-  (VOID *)&S3PciPreSelfRefDr,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefDr,
-  (VOID *)&S3CPciPostSelfRefDr,
-  (VOID *)&S3MSRPreSelfRefDr,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *      @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockDr (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableDr (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = FALSE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDr;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDr;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDr;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDr;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for DR
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[PCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DR + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CPCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DR + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[MSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DR + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CMSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DR + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDr (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListDr) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListDr[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListDr[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in]   *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *      @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDr (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DR);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegDr[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DR);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegDr[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.h
deleted file mode 100644
index db47c31197..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnS3dr.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3dr.h
- *
- * S3 resume memory related function for DR.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3DR_H_
-#define _MNS3DR_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of DR
-typedef enum {
-  PCI_LST_ESR_DR,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_DR,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_DR,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_DR,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_DR,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_DR,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_DR,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_DR,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDr;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3DR_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
deleted file mode 100644
index b443b765a6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndctdr.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctdr.c
- *
- * Northbridge DR DCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "merrhdl.h"
-#include "OptionMemory.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNDCTDR_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTCtlOnDimmMirrorDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       BOOLEAN SetFlag
-  );
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function programs the memory controller with configuration parameters
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
- *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-memNAutoConfigDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  DIE_STRUCT *MCTPtr;
-  DCT_STRUCT *DCTPtr;
-  MEM_PARAMETER_STRUCT *RefPtr;
-
-  RefPtr = NBPtr->RefPtr;
-  MCTPtr = NBPtr->MCTPtr;
-  DCTPtr = NBPtr->DCTPtr;
-  //======================================================================
-  // Build Dram Control Register Value (F2x78)
-  //======================================================================
-  //
-
-  MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
-  MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
-
-  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
-  //======================================================================
-  // Build Dram Config Lo Register Value
-  //======================================================================
-  //
-
-
-  if (MCTPtr->Status[SbParDimms]) {
-    //
-    // SbParDimms should be set for all DDR3 RDIMMS or DDR2 that support parity
-    // Cannot turn off ParEn for DDR3
-    //
-    //@attention - add debug option for parity control
-    if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) || (RefPtr->EnableParity)) {
-      MemNSetBitFieldNb (NBPtr, BFParEn, 1);
-    }
-  }
-
-  if (MCTPtr->GangedMode) {
-    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
-  if (!MCTPtr->Status[SbRegistered]) {
-    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
-  }
-
-  if (MCTPtr->Status[SbEccDimms]) {
-    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
-  }
-
-  //======================================================================
-  // Build Dram Config Hi Register Value
-  //======================================================================
-  //
-
-  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
-  if (MCTPtr->Status[SbRegistered]) {
-    if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) {
-      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
-    }
-  }
-
-  if (RefPtr->EnableBankSwizzle) {
-    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
-  }
-
-  if (DCTPtr->Timings.DimmQrPresent) {
-    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
-    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
-    }
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
-
-  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
-
-  //======================================================================
-  // Build Dram Config Misc Register Value
-  //======================================================================
-  //
-  MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
-  // For DDR3 Registered Dimms
-  if (MCTPtr->Status[SbRegistered]) {
-    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
-      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
-    }
-  }
-  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This is a general purpose function that executes before DRAM init
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sends an MRS command
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN ClearODM;
-
-  ClearODM = FALSE;
-  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
-    if (MemNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) {
-      // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS
-      MemTCtlOnDimmMirrorDr (NBPtr, FALSE);
-      ClearODM = TRUE;
-    }
-  }
-
-  MemNSwapBitsNb (NBPtr);
-
-  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
-  // 1.Set SendMrsCmd=1
-  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
-  // 2.Wait for SendMrsCmd=0
-  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-
-  if (ClearODM) {
-    // Restore ODM if necessary
-    MemTCtlOnDimmMirrorDr (NBPtr, TRUE);
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Workaround for erratum 322 and 263
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  // Errata 263
-  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
-  } else {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
-  }
-
-  // Errata 322
-  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
-  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
-  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
-  //    greater than or equal to 011b (DDR-800 and higher),
-  //    then write 00000080h to F2x[1,0]9C_xD02E001,
-  //    else write 00000090h to F2x[1,0]9C_xD02E001.
-  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *      This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]   SetFlag   - Enable or disable flag - TRUE - Enable, FALSE - DISABLE
- *
- */
-
-VOID
-STATIC
-MemTCtlOnDimmMirrorDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       BOOLEAN SetFlag
-  )
-{
-  UINT8 Chipsel;
-  UINT32 CSBaseAddrReg;
-
-  for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) {
-    CSBaseAddrReg = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel);
-    if ((CSBaseAddrReg & 1) == 1) {
-      if (SetFlag && ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) {
-        CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror);
-      } else {
-        CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror);
-      }
-      MemNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg);
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function adjusts Avg PRE value of Phy fence training according to specific CPU family.
- *
- *     @param[in,out]   *NBPtr  - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *Value16 - Pointer to the value that we want to adjust
- *
- */
-
-VOID
-MemNPFenceAdjustDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   INT16 *Value16
-  )
-{
-  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
-    *Value16 += 5; //for RB C0, the Avg PRE value is subtracted by 3 only.
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function uses calculated values from DCT.Timings structure to
- *      program its RB registers.
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNProgramCycTimingsDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CTENTRY DDR3TmgAdjTab[] = {
-    // BitField, Min, Max, Bias, Ratio_x2
-    {BFTcl, 4, 12, 4, 2},
-    {BFTrcd, 5, 12, 5, 2},
-    {BFTrp, 5, 12, 5, 2},
-    {BFTrtp, 4, 7, 4, 2},
-    {BFTras, 15, 30, 15, 2},
-    {BFTrc, 11, 42, 11, 2},
-    {BFTwrDDR3, 5, 12, 4, 2},
-    {BFTrrd, 4, 7, 4, 2},
-    {BFTwtr, 4, 7, 4, 2},
-    {BFFourActWindow, 16, 32, 14, 1}
-  };
-
-  CTENTRY DDR2TmgAdjTab[] = {
-    // BitField, Min, Max, Bias, Ratio_x2
-    {BFTcl, 3, 7, 1, 2},
-    {BFTrcd, 3, 6, 3, 2},
-    {BFTrp, 3, 6, 3, 4},
-    {BFTrtp, 2, 3, 2, 4},
-    {BFTras, 5, 18, 3, 2},
-    {BFTrc, 11, 26, 11, 2},
-    {BFTwr, 3, 6, 3, 2},
-    {BFTrrd, 2, 5, 2, 2},
-    {BFTwtr, 5, 8, 4, 2},
-    {BFFourActWindow, 8, 20, 7, 2}
-  };
-
-  CTENTRY *TmgAdjTab;
-  DCT_STRUCT *DCTPtr;
-  UINT8  *MiniMaxTmg;
-  UINT8  *MiniMaxTrfc;
-  UINT8  Value8;
-  UINT8  j;
-  UINT8  BurstMode;
-  BIT_FIELD_NAME BitField;
-
-  DCTPtr = NBPtr->DCTPtr;
-
-  //======================================================================
-  // Program DRAM Timing values
-  //======================================================================
-  //
-  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
-    TmgAdjTab = DDR3TmgAdjTab;
-  } else if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
-    // DDR2-1066 uses DDR3 table but differs in tCL
-    TmgAdjTab = DDR3TmgAdjTab;
-    TmgAdjTab[0].Min = 3;
-    TmgAdjTab[0].Max = 7;
-    TmgAdjTab[0].Bias = 1;
-  } else {
-    TmgAdjTab = DDR2TmgAdjTab;
-  }
-
-  MiniMaxTmg = &DCTPtr->Timings.CasL;
-  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
-    BitField = TmgAdjTab[j].BitField;
-
-    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
-      MiniMaxTmg[j] = TmgAdjTab[j].Min;
-    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
-      MiniMaxTmg[j] = TmgAdjTab[j].Max;
-    }
-
-    Value8 = (UINT8) MiniMaxTmg[j];
-
-    if (BitField == BFTwrDDR3) {
-      Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8;
-    } else if (BitField == BFTrtp) {
-      Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6;
-    }
-
-    Value8 = Value8 - TmgAdjTab[j].Bias;
-    Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
-
-    MemNSetBitFieldNb (NBPtr, BitField, Value8);
-  }
-
-  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
-  for (j = 0; j < 4; j++) {
-    MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // 7.8 us
-
-  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
-    //======================================================================
-    // DDR3 additional settings
-    //======================================================================
-
-    MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ?
-                                       (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0));
-
-    MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF);
-
-    MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
-
-    // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
-    MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
-
-    // burst length control
-    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
-      MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2);
-    }
-
-    // ASR=1, auto self refresh; SRT=0
-    MemNSetBitFieldNb (NBPtr, BFASR, 1);
-  } else {
-    //======================================================================
-    // DDR2 additional settings
-    //======================================================================
-
-    MemNSetBitFieldNb (NBPtr, BFNonSPD, 0xFF77);
-
-    BurstMode = UserOptions.CfgUseBurstMode;
-    IDS_OPTION_HOOK (IDS_BURST_LENGTH32, &BurstMode, &(NBPtr->MemPtr->StdHeader));
-    if (BurstMode) {
-      if (!NBPtr->MCTPtr->GangedMode) {
-        NBPtr->SetBitField (NBPtr, BFBurstLength32, 1);
-      }
-    }
-  }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c
deleted file mode 100644
index 84d45b0104..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndr.c
- *
- * Common Northbridge functions for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "mu.h"
-#include "merrhdl.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNDR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL   (UINT32) 0x20000000
-#define CHANNEL_SELECT  (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
-  }
-
-  MemNInitNBDataDr (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableDr (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DR;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_72B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0xFF;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->InitializeMCT = MemNInitializeMctDr;
-  NBPtr->FinalizeMCT = MemNFinalizeMctDr;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdDr;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternDr;
-  NBPtr->ReadPattern = MemNReadPatternDr;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = memNAutoConfigDr;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsDr;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->OtherTiming = (BOOLEAN (*) (MEM_NB_BLOCK *)) MemMDefRet;    //@attention - due to build issue with MemNOtherTimingDr
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  MemNInitNBDataNb (NBPtr);
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDr;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDr;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemPPhyFenceTrainingDr;
-  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDr;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDr;
-  NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustDr;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[Check1GAlign] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
-  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsDR (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-  //
-
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedDr (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.h
deleted file mode 100644
index 0ca679361c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mndr.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndr.h
- *
- * Northbridge DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNDR_H_
-#define _MNDR_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_DR    2
-#define MAX_DCTS_PER_NODE_DR          2
-#define MAX_CHANNELS_PER_DCT_DR       1
-#define MAX_NODES_SUPPORTED_DR        8
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsDR (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-BOOLEAN
-MemNInitializeMctDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNFinalizeMctDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNSendMrsCmdDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-memNAutoConfigDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNOtherTimingDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNWritePatternDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemPNodeMemBoundaryDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   UINT32 *NodeSysLimit
-  );
-
-VOID
-InitNBRegTableDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  );
-
-BOOLEAN
-MemNIsIdSupportedDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  );
-
-VOID
-MemNBeforeDramInitDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNBeforePlatformSpecDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemPPhyFenceTrainingDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-UINT32
-MemNCmnGetSetFieldDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  );
-
-VOID
-MemNPFenceAdjustDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   INT16 *Value16
-  );
-
-VOID
-MemNProgramCycTimingsDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-memNEnableTrainSequenceDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-#endif  /* _MNDR_H_ */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
deleted file mode 100644
index 0e100c8f56..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnflowdr.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowdr.c
- *
- * Deerhound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mndr.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNFLOWDR_FILECODE
-/* features */
-#include "mftds.h"
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledDR[f] != NULL);
-        if (memPlatSpecFFInstalledDR[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c
deleted file mode 100644
index 9847e97ad3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnidendimmdr.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmdr.c
- *
- * DR northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Ganged = FALSE;
-  InitNBRegTableDr (NBPtr, NBPtr->NBRegTable);
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c
deleted file mode 100644
index 9d7ac9ed19..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnmctdr.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmctdr.c
- *
- * Northbridge DR MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNMCTDR_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets final values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-
-  MemPtr = NBPtr->MemPtr;
-
-  MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
-  MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
-  MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
-  MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
-  // Recommended settings for F2x11C
-  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
-  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
-  MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
-  MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
-
-  if (NBPtr->Node == BSP_DIE) {
-    if (!NBPtr->ClToNbFlag) {
-      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
-      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    }
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets initial values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-
-  MemPtr = NBPtr->MemPtr;
-
-  if (NBPtr->Node == BSP_DIE) {
-    LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    if (SMsr.lo & ((UINT32)1 << 15)) {
-      NBPtr->ClToNbFlag = 1;
-    }
-    SMsr.lo |= (UINT32)1 << 15;                   // ClLinesToNbDis
-    LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi |= (UINT32)1 << (48 - 32);              // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
deleted file mode 100644
index 37a2e3605b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnotdr.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnotdr.c
- *
- * Northbridge Non-SPD timings for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNOTDR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemNPowerDownCtlDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
-    MemNSetOtherTimingDR (NBPtr);        // Set DR Timings
-    MemNPowerDownCtlNb (NBPtr);
-  }
-
-  MemNSwitchDCTNb (NBPtr, 1);
-  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
-    MemNSetOtherTimingDR (NBPtr);                // Set DR Timings
-    MemNPowerDownCtlNb (NBPtr);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings into the PCI registers
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function enables power down mode
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlDR (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_PARAMETER_STRUCT *RefPtr;
-  UINT8 PowerDownMode;
-
-  RefPtr = NBPtr->RefPtr;
-
-  // we can't enable powerdown mode when doing WL
-  if (RefPtr->EnablePowerDown) {
-    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
-    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
-    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
-    if (PowerDownMode) {
-      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
-    }
-  }
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
deleted file mode 100644
index 2dfb5dc7f8..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnprotodr.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotodr.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNPROTODR_FILECODE
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNTrainFenceWHardCodeValDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function conditionally executes specific Phy fence training function.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemPPhyFenceTrainingDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
-    //DDR2 specific.
-    if (NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) {
-      MemNTrainFenceWHardCodeValDr (NBPtr);
-    } else {
-      MemNTrainPhyFenceNb (NBPtr);
-    }
-  } else {
-    //DDR3 specific.
-    MemNTrainPhyFenceNb (NBPtr);
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function executes hardcoded Phy fence training.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNTrainFenceWHardCodeValDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 CurDct;
-  UINT16 Speed;
-
-  CurDct = NBPtr->Dct;
-  if (NBPtr->MCTPtr->NodeMemSize) {
-    for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
-      NBPtr->SwitchDCT (NBPtr, Dct);
-      Speed = NBPtr->DCTPtr->Timings.Speed;
-      NBPtr->SetBitField (NBPtr, BFPhyFence, ((Speed == DDR800_FREQUENCY) || (Speed == DDR1066_FREQUENCY)) ? 20 : 20);
-      NBPtr->SetBitField (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0);
-      NBPtr->SetBitField (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
-      NBPtr->SetBitField (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
-    }
-  }
-
-  NBPtr->SwitchDCT (NBPtr, CurDct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function executes Node memory 1GB boundary alignment.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *NodeSysLimit   - Pointer to the NodeSysLimit
- *
- */
-
-VOID
-MemPNodeMemBoundaryDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   UINT32 *NodeSysLimit
-  )
-{
-  if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
-    // only apply to DDR2.
-    if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) {
-      // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node
-      *NodeSysLimit += 1;
-      *NodeSysLimit &= 0xFFFFC000;
-      *NodeSysLimit -= 1;
-    }
-  }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c
deleted file mode 100644
index 9b871f2784..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregdr.c
- *
- * Common Northbridge register related functions for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 47676 $ @e \$Date: 2011-02-25 06:29:57 +0800 (Fri, 25 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNREGDR_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- *     MemNIsIdSupportedDr
- *      This function matches the CPU_LOGICAL_ID with certain criteria to
- *      determine if it is supported by this NBBlock.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- *     @return          TRUE -  This node is a RB.
- *     @return          FALSE - This node is not a RB.
- *
- */
-BOOLEAN
-MemNIsIdSupportedDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  )
-{
-
-  if (((LogicalIdPtr->Family & (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA)) != 0)
-      && ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL | AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0)) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function gets or sets a value to a bit field in a PCI register.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]   FieldName - Bit Field to be programmed
- *     @param[in]   Field - Value to be programmed
- *     @param[in]   IsSet - Indicates if the function will set or get
- *
- *     @return      value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  )
-{
-  TSEFO Address;
-  PCI_ADDR PciAddr;
-  UINT8 Type;
-  UINT8 IsLinked;
-  UINT32 Value;
-  UINT32 Highbit;
-  UINT32 Lowbit;
-  UINT32 Mask;
-
-  Value = 0;
-  if (FieldName < BFEndOfList) {
-    Address = NBPtr->NBRegTable[FieldName];
-    if (Address) {
-      Lowbit = TSEFO_END (Address);
-      Highbit = TSEFO_START (Address);
-      Type = (UINT8) TSEFO_TYPE (Address);
-      IsLinked = (UINT8) TSEFO_LINKED (Address);
-
-      // If Fn2 and DCT1 selected, set Address to be 1xx
-      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
-        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
-          Address |= 0x0100;
-        }
-      }
-
-      ASSERT ((Address & ((UINT32) 1) << 28) == 0);   // Phy direct access method is not supported
-
-      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
-        // Special DCT Phy access
-        Address &= 0x0FFFFFFF;
-        Lowbit = 0;
-        Highbit = 16;
-        IsLinked = 0;
-      } else {
-        // Normal DCT Phy access
-        Address = TSEFO_OFFSET (Address);
-      }
-
-      if (Type == NB_ACCESS) {
-        PciAddr.AddressValue = Address;
-        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-        Address = PciAddr.AddressValue;
-        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-        if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-            (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value);
-        }
-      } else if (Type == DCT_PHY_ACCESS) {
-        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-        IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
-      } else {
-        IDS_ERROR_TRAP;
-      }
-
-      if (IsSet) {
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        } else {
-          Mask = (UINT32)0xFFFFFFFF;
-        }
-        Value &= ~(Mask << Lowbit);
-        Value |= (Field & Mask) << Lowbit;
-
-        if (Type == NB_ACCESS) {
-          PciAddr.AddressValue = Address;
-          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-          if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-              (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-            IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field);
-          }
-        } else if (Type == DCT_PHY_ACCESS) {
-          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
-          Address |= DCT_ACCESS_WRITE;
-          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-          IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
-        } else {
-          IDS_ERROR_TRAP;
-        }
-        if (IsLinked) {
-          MemNCmnGetSetFieldDr (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
-        }
-      } else {
-        Value = Value >> Lowbit;  // Shift
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        }
-        if (IsLinked) {
-          Value |= MemNCmnGetSetFieldDr (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
-        }
-      }
-    }
-  } else {
-    IDS_ERROR_TRAP;   // Invalid bit field index
-  }
-  return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes bit field translation table
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   NBRegTable[]   - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableDr (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  )
-{
-  UINT16 i;
-
-  // Allocate heap for NB register table
-  if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabDR)) {
-    return;     // escape if fails
-  }
-  NBRegTable = NBPtr->NBRegTable;
-
-  for (i = 0; i < BFEndOfList; i++) {
-    NBRegTable[i] = 0;
-  }
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFDisableL3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-
-  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
-  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
-  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c
deleted file mode 100644
index 399249c774..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnParTrainHy.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainHy.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the Hydra specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/HCTRN)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE
-/*-----------------------------------------------------------------------------
-*                                EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-);
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *       This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  Launch training on AP successfully.
- *     @return          FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  AMD_CONFIG_PARAMS *StdHeader;
-  DIE_STRUCT *MCTPtr;
-  REMOTE_TRAINING_ENV *EnvPtr;
-  AP_TASK TrainingTask;
-  UINT8 Socket;
-  UINT8 Module;
-  UINT8 APCore;
-  UINT8 p;
-  UINT32 LowCore;
-  UINT32 HighCore;
-  UINT32 BspSocket;
-  UINT32 BspModule;
-  UINT32 BspCore;
-  AGESA_STATUS Status;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-  UINT16 MctDataSize;
-  StdHeader = &(NBPtr->MemPtr->StdHeader);
-  MCTPtr = NBPtr->MCTPtr;
-  Socket = MCTPtr->SocketId;
-  Module = MCTPtr->DieId;
-
-  //
-  // Allocate buffer for REMOTE_TRAINING_ENV
-  //
-  MctDataSize = MAX_DCTS_PER_NODE_HY * (
-                  sizeof (DCT_STRUCT) + (
-                    MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                  )
-                );
-  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
-    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
-    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
-    //
-    // Setup Remote training environment
-    //
-    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
-    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
-    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
-      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
-    }
-    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
-    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY;
-    EnvPtr->FeatPtr = NBPtr->FeatPtr;
-    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
-    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
-    EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
-    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
-    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
-    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
-    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
-    //
-    // Get Socket, Core of the BSP
-    //
-    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
-    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
-    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
-    //
-    // Set up the remote task structure
-    //
-    TrainingTask.DataTransfer.DataPtr = EnvPtr;
-    TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
-    TrainingTask.DataTransfer.DataTransferFlags = 0;
-    TrainingTask.ExeFlags = 0;
-    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
-    //
-    // Get Target AP Core
-    //
-    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
-    APCore = (UINT8) (LowCore & 0x000000FF);
-
-    //
-    // Launch Remote Training
-    //
-    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
-    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-
-    return TRUE;
-  } else {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
-    return FALSE;
-  }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       DIE_STRUCT *MCTPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr
-  )
-{
-  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
-  MemNInitNBDataHy (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  //----------------------------------------------------------------------------
-  // Get TSC rate of the this AP
-  //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
-  FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c
deleted file mode 100644
index bd1870eca2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.c
+++ /dev/null
@@ -1,738 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3hy.c
- *
- * HY memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnhy.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3hy.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstHy (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegHy (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorHy,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA4,  0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorHy,
-  PciSpecialCaseFuncHy
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = {
-  // DCT0
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-
-    // DCT1
-  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-
-  // DllShutDown
-  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorHy,
-  PciSpecialCaseFuncHy
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorHy,
-  NULL
-};
-
-VOID *MemS3RegListHy[] = {
-  (VOID *)&S3PciPreSelfRefHy,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefHy,
-  (VOID *)&S3CPciPostSelfRefHy,
-  (VOID *)&S3MSRPreSelfRefHy,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *     @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemS3ResumeConstructNBBlockHy (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableHy (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for HY
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstHy (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListHy[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListHy[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in, out]  *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegHy (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_HY);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegHy[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_HY);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegHy[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.h
deleted file mode 100644
index 83ee7c5173..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnS3hy.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3hy.h
- *
- * S3 resume memory related function for HY.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3HY_H_
-#define _MNS3HY_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of HY
-typedef enum {
-  PCI_LST_ESR_HY,  ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_HY,      ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_HY,     ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_HY,  ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_HY,      ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_HY      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDHy;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3HY_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c
deleted file mode 100644
index b0acf3dc83..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mndcthy.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctHy.c
- *
- * Northbridge DCT support for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "merrhdl.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function programs the memory controller with configuration parameters
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
- *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-MemNAutoConfigHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 PowerDownMode;
-  UINT32 Value32;
-  DIE_STRUCT *MCTPtr;
-  DCT_STRUCT *DCTPtr;
-  MEM_PARAMETER_STRUCT *RefPtr;
-
-  RefPtr = NBPtr->RefPtr;
-  MCTPtr = NBPtr->MCTPtr;
-  DCTPtr = NBPtr->DCTPtr;
-  //======================================================================
-  // Build Dram Control Register Value (F2x78)
-  //======================================================================
-  //
-  //It is recommended that these bits remain in the default state.
-  //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5);
-
-  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
-  //======================================================================
-  // Build Dram Config Lo Register Value
-  //======================================================================
-  //
-
-  if (MCTPtr->Status[SbParDimms]) {
-    //
-    // SbParDimms should be set for all DDR3 RDIMMS
-    // Cannot turn off ParEn for DDR3
-    //
-    //@attention - add debug option for parity control
-    MemNSetBitFieldNb (NBPtr, BFParEn, 1);
-  }
-
-
-  if (MCTPtr->GangedMode) {
-    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
-  if (!MCTPtr->Status[SbRegistered]) {
-    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
-  }
-
-  if (MCTPtr->Status[SbEccDimms]) {
-    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
-  }
-
-  //======================================================================
-  // Build Dram Config Hi Register Value
-  //======================================================================
-  //
-
-  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
-  if (MCTPtr->Status[SbRegistered]) {
-    if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) {
-      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
-    }
-  }
-
-  if (RefPtr->EnableBankSwizzle) {
-    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
-  }
-
-  if (DCTPtr->Timings.DimmQrPresent) {
-    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
-    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
-      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
-    }
-  }
-
-  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
-  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
-  //======================================================================
-  // Build Dram Config Misc Register Value
-  //======================================================================
-  //
-  if (MCTPtr->Status[SbRegistered]) {
-    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
-      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
-    }
-  }
-  //======================================================================
-  // Build Dram Config Misc 2 Register Value
-  //======================================================================
-  //
-  //
-  // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms
-  //
-  if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) {
-    MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1);
-  }
-  //
-  // DTaxTxFifpWrDly
-  //
-  Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
-  if ((Value32 >= 2) && (Value32 <= 5)) {
-    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32));
-  }
-
-  //
-  // ProgOdtEn
-  //
-  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
-    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1);
-  } else {
-    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0);
-  }
-  //
-  // OdtSwizzle
-  //
-  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) {
-    PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode);
-    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
-    if (PowerDownMode == 1) {
-      MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
-    }
-  }
-
-
-  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sends an MRS command
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSwapBitsNb (NBPtr);
-
-  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
-              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
-  // 1.Set SendMrsCmd=1
-  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
-  // 2.Wait for SendMrsCmd=0
-  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sends an MRS command to all CS of all channels
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *DummyPtr - Unused pointer
- *
- *     @return    TRUE
- */
-
-BOOLEAN
-MemNSendMrsCmdPerCsHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *DummyPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 ChipSel;
-  UINT32 Dummy;
-
-  if (!NBPtr->MCTPtr->Status[SbRegistered]) {
-    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-      NBPtr->SwitchDCT (NBPtr, Dct);
-      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-        IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
-        for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
-          if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
-            IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
-            // if chip select present
-            NBPtr->TechPtr->SendAllMRCmds (NBPtr->TechPtr, ChipSel);
-            // NOTE: wait 512 clocks for DLL-relock
-            MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
-          }
-        }
-      }
-    }
-  }
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This is a general purpose function that executes before DRAM init
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
-    MemNSwitchDCTNb (NBPtr, Dct);
-    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-      //Set PllLockTime and DllLockTime to default.
-      MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
-      MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
-      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Enable DLL Shut down
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNEnDLLShutDownHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  BOOLEAN DllShutDownEn;
-
-  DllShutDownEn = TRUE;
-  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
-
-  if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
-    if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) {
-      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-        MemNSwitchDCTNb (NBPtr, Dct);
-        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-          MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
-          MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
-          MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
-        }
-      }
-    }
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   Workaround for erratum 322 and 263
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  // Errata 263
-  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
-  } else {
-    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
-  }
-
-  // Errata 322
-  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
-  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
-  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
-  //    greater than or equal to 011b (DDR-800 and higher),
-  //    then write 00000080h to F2x[1,0]9C_xD02E001,
-  //    else write 00000090h to F2x[1,0]9C_xD02E001.
-  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *    Initializes extended MMIO address space
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   OptParam - Optional parameter
- *
- *     @return    TRUE
- */
-BOOLEAN
-MemNInitExtMMIOAddrHy  (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *OptParam
-  )
-{
-  UINT8  Index;
-  UINT32 Value;
-  PCI_ADDR PciAddr;
-
-  if (NBPtr->RefPtr->SysLimit >= _1TB_RJ16) {
-    // Initialize all indices of F1x114_x2 and F1x114_x3.
-    for (Index = 0; Index < 32; Index++) {
-      PciAddr = NBPtr->PciAddr;
-      PciAddr.Address.Function = 1;
-
-      PciAddr.Address.Register = 0x110;
-      Value = 0x20000000 | Index;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-
-      PciAddr.Address.Register = 0x114;
-      Value = 0;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-
-      PciAddr.Address.Register = 0x110;
-      Value = 0x30000000 | Index;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-
-      PciAddr.Address.Register = 0x114;
-      Value = 0;
-      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-    }
-  }
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
deleted file mode 100644
index 5f9357cd75..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnflowhy.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowhy.c
- *
- * Hydra initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE
-/* features */
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledHy[f] != NULL);
-        if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
deleted file mode 100644
index 72274b3d4d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnhy.c
- *
- * Common Northbridge  functions for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL   (UINT32) 0x20000000
-#define CHANNEL_SELECT  (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
-  }
-
-  MemNInitNBDataHy (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableHy (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_256B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0x1FF;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->InitializeMCT = MemNInitializeMctHy;
-  NBPtr->FinalizeMCT = MemNFinalizeMctHy;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdHy;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternHy;
-  NBPtr->ReadPattern = MemNReadPatternHy;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = MemNAutoConfigHy;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingHy;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->OtherTiming = MemNOtherTimingHy;
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
-  NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  MemNInitNBDataNb (NBPtr);
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompHy;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy;
-  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[SetDllShutDown] = TRUE;
-  NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
-  NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
-  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
-  NBPtr->IsSupported[CheckODTControls] = TRUE;
-  NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-
-  NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] = MemNSendMrsCmdPerCsHy;
-  NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrHy;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsHY (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-  //
-
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedHy (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h
deleted file mode 100644
index 472474f67f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnhy.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnhy.h
- *
- * Northbridge Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNHY_H_
-#define _MNHY_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_HY    4
-#define MAX_DCTS_PER_NODE_HY          2
-#define MAX_CHANNELS_PER_DCT_HY       1
-#define MAX_NODES_SUPPORTED_HY        8
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemConstructNBBlockHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsHY (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-BOOLEAN
-MemNInitializeMctHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNFinalizeMctHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNSendMrsCmdHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNAutoConfigHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNOtherTimingHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitPhyCompHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNWritePatternHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-VOID
-InitNBRegTableHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  );
-
-UINT8
-MemNGetSocketRelativeChannelHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Dct,
-  IN       UINT8 Channel
-  );
-
-BOOLEAN
-MemNIsIdSupportedHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  );
-
-VOID
-MemNBeforeDramInitHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNEnDLLShutDownHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-UINT32
-MemNCmnGetSetFieldHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  );
-
-VOID
-MemNBeforePlatformSpecHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-memNEnableTrainSequenceHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNSendMrsCmdPerCsHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *DummyPtr
-  );
-
-BOOLEAN
-MemNInitExtMMIOAddrHy  (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   VOID *OptParam
-  );
-
-VOID
-MemNBeforeDQSTrainingHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-#endif  /* _MNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c
deleted file mode 100644
index 79ff3145aa..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnidendimmhy.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmhy.c
- *
- * Hy northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Ganged = FALSE;
-  InitNBRegTableHy (NBPtr, NBPtr->NBRegTable);
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy;
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c
deleted file mode 100644
index cb41835dfb..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnmcthy.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmcthy.c
- *
- * Northbridge Hydra MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets final values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-  UINT16 Speed;
-  UINT32 ExtMctCfgLoRegVal;
-
-  MemPtr = NBPtr->MemPtr;
-  Speed = NBPtr->DCTPtr->Timings.Speed;
-  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);
-
-  ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
-  ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;
-
-  ExtMctCfgLoRegVal &= 0x0FFFFFFF;
-  if (Speed == DDR667_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x40000000;
-  } else if (Speed == DDR800_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x50000000;
-  } else if (Speed == DDR1066_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x60000000;
-  } else if (Speed == DDR1333_FREQUENCY) {
-    ExtMctCfgLoRegVal |= 0x80000000;
-  } else {
-    ExtMctCfgLoRegVal |= 0x90000000;
-  }
-  MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);
-
-  if (NBPtr->Node == BSP_DIE) {
-    if (!NBPtr->ClToNbFlag) {
-      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
-      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    }
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets initial values in BUCFG and BUCFG2
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_DATA_STRUCT *MemPtr;
-  S_UINT64 SMsr;
-
-  MemPtr = NBPtr->MemPtr;
-
-  if (NBPtr->Node == BSP_DIE) {
-    LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    if (SMsr.lo & ((UINT32)1 << 15)) {
-      NBPtr->ClToNbFlag = 1;
-    }
-    SMsr.lo |= (UINT32)1 << 15;                   // ClLinesToNbDis
-    LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
-    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    SMsr.hi |= (UINT32)1 << (48 - 32);              // WbEnhWsbDis
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c
deleted file mode 100644
index 58e21186fd..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnothy.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnothy.c
- *
- * Northbridge Non-SPD timings for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-UINT32
-STATIC
-MemNGetODTDelaysHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE -  No fatal error occurs.
- *     @return          FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MemNSwitchDCTNb (NBPtr, 0);
-  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
-    MemNSetOtherTimingHY (NBPtr);
-    MemNPowerDownCtlNb (NBPtr);
-    MemNEnDLLShutDownHy (NBPtr);
-  }
-
-  MemNSwitchDCTNb (NBPtr, 1);
-  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
-    MemNSetOtherTimingHY (NBPtr);
-    MemNPowerDownCtlNb (NBPtr);
-    MemNEnDLLShutDownHy (NBPtr);
-  }
-  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function sets the non-SPD timings  in PCI registers
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-
-  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
-  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function gets the ODT delays
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-UINT32
-STATIC
-MemNGetODTDelaysHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  INT8 Ld;
-  UINT32 ODTDelays;
-  //
-  // On revision D processors, the BIOS must additionally configure the ODT pattern
-  // and the ODT switching delays.
-  //
-  // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
-  //     -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
-  //     -Value of 2, BL = 4 else assume BL=8.
-  //     -Initialize ODTDelays based on BL value
-  //     -WrOdtOnDuration [14:12] = BL / 2 + 1
-  //     -WrOdtTrnOnDly [10:8] = 0
-  //     -RdOdtOnDuration [6:4] = BL / 2 + 1
-  //
-  ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
-
-  // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
-  // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
-  Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
-  if (Ld < 0) {
-    Ld = 0;
-  }
-  if (Ld > 7) {
-    Ld = 7;
-  }
-  ODTDelays += Ld;
-  return ODTDelays;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function enables power down mode
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlHY (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  MEM_PARAMETER_STRUCT *RefPtr;
-  UINT8 PowerDownMode;
-
-  RefPtr = NBPtr->RefPtr;
-
-  // we can't enable powerdown mode when doing WL
-  if (RefPtr->EnablePowerDown) {
-    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
-    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
-    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
-    if (PowerDownMode) {
-      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c
deleted file mode 100644
index 6f032cf862..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnphyhy.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnphyHy.c
- *
- * Northbridge Phy support for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 46120 $ @e \$Date: 2011-01-28 16:00:01 +0800 (Fri, 28 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "ma.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the DDR phy compensation logic
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitPhyCompHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
-  CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
-  CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
-  CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
-  UINT8 i;
-  UINT8 j;
-  UINT8 CurrDct;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-
-  CurrDct = NBPtr->Dct;
-
-  //
-  // Get Platform Information
-  //
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
-  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
-  // DisAutoComp will be cleared after Dram init has completed
-  //
-  MemNSwitchDCTNb (NBPtr, 0);
-  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
-  MemUWait10ns (500, NBPtr->MemPtr);
-  MemNSwitchDCTNb (NBPtr, CurrDct);
-
-  // 3. For each normalized driver strength code read from
-  // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
-  // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
-  //
-  // 4. For each normalized driver strength code read from
-  // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
-  // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
-  // D3Cmp2PCal].
-  //
-  j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
-  i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  ASSERT (j <= 3);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
-
-  ASSERT (i <= 3);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
-  MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
-
-  //
-  // Special Case for certain configs
-  //
-  // 3DPCH Fully populated.
-  if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) {
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3);
-    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5);
-  }
-
-  MemNSwitchDCTNb (NBPtr, CurrDct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This is a general purpose function that executes before DRAM training
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDQSTrainingHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 ChipSel;
-  UINT32 TestAddrRJ16;
-  UINT32 RealAddr;
-
-  MemTBeginTraining (NBPtr->TechPtr);
-
-  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
-    MemNSwitchDCTNb (NBPtr, Dct);
-    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
-        if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
-
-          RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
-
-          MemUDummyCLRead (RealAddr);
-
-          MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
-          MemUWait10ns (60, NBPtr->MemPtr);   // Wait 300ns
-          MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
-          MemUWait10ns (400, NBPtr->MemPtr);  // Wait 2us
-          MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
-          break;
-        }
-      }
-    }
-    if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
-      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
-        MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
-      }
-      if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
-        MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
-      }
-    }
-  }
-
-  MemTEndTraining (NBPtr->TechPtr);
-
-  MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnprotohy.c
deleted file mode 100644
index 23abf3fb58..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnprotohy.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotohy.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c
deleted file mode 100644
index 61cf26b537..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c
+++ /dev/null
@@ -1,635 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnreghy.c
- *
- * Common Northbridge register related functions for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 47676 $ @e \$Date: 2011-02-25 06:29:57 +0800 (Fri, 25 Feb 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- *     MemNIsIdSupportedHy
- *      This function matches the CPU_LOGICAL_ID with certain criteria to
- *      determine if it is supported by this NBBlock.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- *     @return          TRUE -  This node is a Hydra.
- *     @return          FALSE - This node is not a Hydra.
- *
- */
-BOOLEAN
-MemNIsIdSupportedHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  )
-{
-  if (((LogicalIdPtr->Family & AMD_FAMILY_10_HY) != 0)
-      && ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0)) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *      This function calculates the memory channel index relative to the
- *      socket, taking the Die number, the Dct, and the channel.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Dct
- *     @param[in] Channel
- *
- */
-UINT8
-MemNGetSocketRelativeChannelHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Dct,
-  IN       UINT8 Channel
-  )
-{
-  return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct);
-}
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function gets or sets a value to a bit field in a PCI register.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]   FieldName - Bit Field to be programmed
- *     @param[in]   Field - Value to be programmed
- *     @param[in]   IsSet - Indicates if the function will set or get
- *
- *     @return      value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 IsSet,
-  IN       BIT_FIELD_NAME FieldName,
-  IN       UINT32 Field
-  )
-{
-  TSEFO Address;
-  PCI_ADDR PciAddr;
-  UINT8 Type;
-  UINT8 IsLinked;
-  UINT32 Value;
-  UINT32 Highbit;
-  UINT32 Lowbit;
-  UINT32 Mask;
-
-  Value = 0;
-  if (FieldName < BFEndOfList) {
-    Address = NBPtr->NBRegTable[FieldName];
-    if (Address) {
-      Lowbit = TSEFO_END (Address);
-      Highbit = TSEFO_START (Address);
-      Type = (UINT8) TSEFO_TYPE (Address);
-      IsLinked = (UINT8) TSEFO_LINKED (Address);
-
-      // If Fn2 and DCT1 selected, set Address to be 1xx
-      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
-        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
-          Address |= 0x0100;
-        }
-      }
-
-      ASSERT ((Address & ((UINT32) 1) << 28) == 0);   // Phy direct access method is not supported
-
-      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
-        // Special DCT Phy access
-        Address &= 0x0FFFFFFF;
-        Lowbit = 0;
-        Highbit = 16;
-        IsLinked = 0;
-      } else {
-        // Normal DCT Phy access
-        Address = TSEFO_OFFSET (Address);
-      }
-
-      if (Type == NB_ACCESS) {
-        PciAddr.AddressValue = Address;
-        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-        Address = PciAddr.AddressValue;
-        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-        if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-            (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value);
-        }
-      } else if (Type == DCT_PHY_ACCESS) {
-        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-        IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
-      } else if (Type == DCT_EXTRA) {
-        MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
-        MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-        Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
-        IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
-      } else {
-        IDS_ERROR_TRAP;
-      }
-
-      if (IsSet) {
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        } else {
-          Mask = (UINT32)0xFFFFFFFF;
-        }
-        Value &= ~(Mask << Lowbit);
-        Value |= (Field & Mask) << Lowbit;
-
-        if (Type == NB_ACCESS) {
-          PciAddr.AddressValue = Address;
-          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
-          if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
-              (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
-            IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field);
-          }
-        } else if (Type == DCT_PHY_ACCESS) {
-          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
-          Address |= DCT_ACCESS_WRITE;
-          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-          IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
-        } else if (Type == DCT_EXTRA) {
-          MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
-          Address |= DCT_ACCESS_WRITE;
-          MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
-          MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-          IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
-        } else {
-          IDS_ERROR_TRAP;
-        }
-        if (IsLinked) {
-          MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
-        }
-      } else {
-        Value = Value >> Lowbit;  // Shift
-        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-        if ((Highbit - Lowbit) != 31) {
-          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
-        }
-        if (IsLinked) {
-          Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
-        }
-      }
-    }
-  } else {
-    IDS_ERROR_TRAP;   // Invalid bit field index
-  }
-  return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes bit field translation table
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   NBRegTable[]  - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableHy (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   TSEFO NBRegTable[]
-  )
-{
-  UINT16 i;
-
-  // Allocate heap for NB register table
-  if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabHY)) {
-    return;     // escape if fails
-  }
-  NBRegTable = NBPtr->NBRegTable;
-
-  for (i = 0; i < BFEndOfList; i++) {
-    NBRegTable[i] = 0;
-  }
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31,  0, BFDctExtraOffsetReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31,  0, BFExtMctCfgLoReg);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFDisableL3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  7,  7, BFProgOdtEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
-
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
-  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31,  0, BFUSPLLCtlAll);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31,  0, BFDSPLLCtlAll);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606,  0,  0, BFUSNibbleAlignEn);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690,  2,  2, BFChnLinitClkEn);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x180, 31, 0, BFPhyRODTCSLow);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x181, 31, 0, BFPhyRODTCSHigh);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x182, 31, 0, BFPhyWODTCSLow);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x183, 31, 0, BFPhyWODTCSHigh);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  9,  9, BFTS2BitLockEn);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  8,  8, BFTS2En);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  4,  4, BFTS1En);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  1,  1, BFTS0LinkStarEn);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000,  0,  0, BFTS0En);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15,  0, BFLinkTrainData);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010,  1,  1, BFRstTxFifoPtrs);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010,  0,  0, BFTxFifoPtrInit);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15,  0, BFLpbkData);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014,  9,  4, BFLnkLpBkLat);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014,  1,  1, BFLpbkRndTripLatDone);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014,  0,  0, BFLnkLatTrainEn);
-
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020,  1,  1, BFDsPhyReset);
-  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020,  0,  0, BFLinkReset);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime);
-  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime);
-
-  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
-  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
-  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
deleted file mode 100644
index aed7aa5f7f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnNi.c
- *
- * Common Northbridge functions for Nile
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnNi.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_NI_MNNI_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL   (UINT32) 0x20000000
-#define CHANNEL_SELECT  (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
-  }
-
-  MemNInitNBDataNi (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  INT32 i;
-
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_72B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0xFF;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->InitializeMCT = MemNInitializeMctDA;
-  NBPtr->FinalizeMCT = MemNFinalizeMctDA;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternDA;
-  NBPtr->ReadPattern = MemNReadPatternDA;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = memNAutoConfigDA;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
-  NBPtr->OtherTiming = MemNOtherTimingDA;
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  MemNInitNBDataNb (NBPtr);
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitNi;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
-  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
-  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[SetDllShutDown] = TRUE;
-  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[Check1GAlign] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
-  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
-  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
-  NBPtr->IsSupported[CheckDllStdBy] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->IsSupported[CheckDllRegDis] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsNi (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedDA (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h
deleted file mode 100644
index e25956d306..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnNi.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnNi.h
- *
- * Northbridge Ni for Nile
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNNI_H_
-#define _MNNI_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsNi (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-VOID
-MemNWritePatternNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-BOOLEAN
-memNEnableTrainSequenceNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-#endif  /* _MNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c
deleted file mode 100644
index 05bbf16b7a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.c
+++ /dev/null
@@ -1,745 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3Ni.c
- *
- * Ni memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3Ni.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_NI_MNS3NI_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstNi (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegNi (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncNi[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegNi},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorNi[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefNi = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorNi) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorNi,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorNi[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT0,   BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT1,   BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefNi = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorNi,
-  PciSpecialCaseFuncNi
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorNi[] = {
-  // DCT0
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-    // DCT1
-  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // DllShutDown
-  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefNi = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorNi,
-  PciSpecialCaseFuncNi
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorNi[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefNi = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorNi) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorNi,
-  NULL
-};
-
-VOID *MemS3RegListNi[] = {
-  (VOID *)&S3PciPreSelfRefNi,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefNi,
-  (VOID *)&S3CPciPostSelfRefNi,
-  (VOID *)&S3MSRPreSelfRefNi,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *      @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockNi (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegNi;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrNi;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstNi;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for Ni
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstNi (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListNi) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListNi[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListNi[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in]   *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *      @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegNi (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegNi[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegNi[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.h
deleted file mode 100644
index 7a7f45a33c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnS3Ni.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3Ni.h
- *
- * S3 resume memory related function for Ni.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3DA_H_
-#define _MNS3DA_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of HY
-typedef enum {
-  PCI_LST_ESR_DA,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_DA,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_DA,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_DA,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_DA,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_DA,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_DA,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_DA,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3DA_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
deleted file mode 100644
index 0991ad6c3d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/NI/mnflowNi.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowNi.c
- *
- * Deerhound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "mnNi.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_NI_MNFLOWNI_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitNi (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledNi[f] != NULL);
-        if (memPlatSpecFFInstalledNi[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
deleted file mode 100644
index 12c4aa5edb..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnPh.c
- *
- * Common Northbridge functions for Pharaoh Hound
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_PH_MNPH_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL   (UINT32) 0x20000000
-#define CHANNEL_SELECT  (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
-  }
-
-  MemNInitNBDataPh (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  INT32 i;
-
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_72B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0xFF;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->InitializeMCT = MemNInitializeMctDA;
-  NBPtr->FinalizeMCT = MemNFinalizeMctDA;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternDA;
-  NBPtr->ReadPattern = MemNReadPatternDA;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = memNAutoConfigDA;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
-  NBPtr->OtherTiming = MemNOtherTimingDA;
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  MemNInitNBDataNb (NBPtr);
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitPh;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
-  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
-  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[SetDllShutDown] = TRUE;
-  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[Check1GAlign] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
-  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
-  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
-  NBPtr->IsSupported[CheckDllStdBy] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->IsSupported[CheckDllRegDis] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsPh (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequencePh (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedPh (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h
deleted file mode 100644
index 8d3892f645..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnPh.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnPh.h
- *
- * Northbridge Ph for Pharaoh Hound
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNPH_H_
-#define _MNPH_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemNIsIdSupportedPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  );
-
-BOOLEAN
-MemConstructNBBlockPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsPh (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-VOID
-MemNWritePatternPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-BOOLEAN
-memNEnableTrainSequencePh (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-#endif  /* _MNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c
deleted file mode 100644
index d8ba71e642..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3Ph.c
- *
- * Ph memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3Ph.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_PH_MNS3PH_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstPh (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegPh (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncPh[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegPh},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorPh[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefPh = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorPh) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorPh,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorPh[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT0,   BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT1,   BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefPh = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorPh) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorPh,
-  PciSpecialCaseFuncPh
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorPh[] = {
-  // DCT0
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-    // DCT1
-  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // DllShutDown
-  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefPh = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorPh) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorPh,
-  PciSpecialCaseFuncPh
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorPh[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefPh = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorPh) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorPh,
-  NULL
-};
-
-VOID *MemS3RegListPh[] = {
-  (VOID *)&S3PciPreSelfRefPh,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefPh,
-  (VOID *)&S3CPciPostSelfRefPh,
-  (VOID *)&S3MSRPreSelfRefPh,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegPh[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- *     MemNIsIdSupportedPh
- *      This function matches the CPU_LOGICAL_ID with certain criteria to
- *      determine if it is supported by this NBBlock.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- *     @return          TRUE -  This node is a PH.
- *     @return          FALSE - This node is not a PH.
- *
- */
-BOOLEAN
-MemNIsIdSupportedPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  )
-{
-
-  if (((LogicalIdPtr->Family & AMD_FAMILY_10_PH) != 0)
-      && ((LogicalIdPtr->Revision & AMD_F10_PH_ALL) != 0)) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *      @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockPh (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedPh;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegPh;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrPh;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstPh;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for Ph
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListPh[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListPh[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListPh[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListPh[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstPh (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListPh) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListPh[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListPh[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in]   *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *      @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegPh (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegPh[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegPh[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.h
deleted file mode 100644
index f6632393ce..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnS3Ph.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3Ph.h
- *
- * S3 resume memory related function for Ph.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3PH_H_
-#define _MNS3PH_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of PH
-typedef enum {
-  PCI_LST_ESR_DA,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_DA,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_DA,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_DA,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_DA,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_DA,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_DA,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_DA,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3PH_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
deleted file mode 100644
index e187680576..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnflowPh.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowPh.c
- *
- * Pharaoh Hound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_PH_MNFLOWPH_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledPh[f] != NULL);
-        if (memPlatSpecFFInstalledPh[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c
deleted file mode 100644
index ae6e92ba78..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/PH/mnidendimmPh.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmPh.c
- *
- * PH northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "mnPh.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorPh (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Ganged = FALSE;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
deleted file mode 100644
index 2829aa7031..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnRb.c
- *
- * Common Northbridge functions for Ridgeback
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_RB_MNRB_FILECODE
-
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL   (UINT32) 0x20000000
-#define CHANNEL_SELECT  (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
- *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
- *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
- *
- *     @return     Boolean indicating that this is the correct memory
- *                 controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  )
-{
-  UINT8 Dct;
-  UINT8 Channel;
-  UINT8 SpdSocketIndex;
-  UINT8 SpdChannelIndex;
-  DIE_STRUCT *MCTPtr;
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->RefPtr = MemPtr->ParameterListPtr;
-  NBPtr->SharedPtr = SharedPtr;
-
-  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->MCTPtr = MCTPtr;
-  NBPtr->MCTPtr->NodeId = NodeID;
-  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
-  //
-  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
-  //
-  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
-                                          sizeof (DCT_STRUCT) + (
-                                            MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
-                                          )
-                                        );
-  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
-    SetMemError (AGESA_FATAL, MCTPtr);
-    return FALSE;
-  }
-
-  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
-  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MCTPtr->DctData[Dct].Dct = Dct;
-    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
-    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
-    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
-  }
-  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
-  //
-  // Initialize Socket List
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
-    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
-    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
-  }
-
-  MemNInitNBDataRb (NBPtr);
-
-  FeatPtr->InitCPG (NBPtr);
-  NBPtr->FeatPtr = FeatPtr;
-  FeatPtr->InitHwRxEn (NBPtr);
-
-  //
-  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
-  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
-  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
-  // dimm types(QR or not) are known. This is done in the Technology block constructor.
-  //
-  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
-  // This will facilitate modifications due to some processors that might
-  // map the DCT-CHANNEL differently.
-  //
-  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
-  //
-  // Traverse the Dct/Channel structures
-  //
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
-      //
-      // Calculate the number of Dimms on this channel using the
-      //   die/dct/channel to Socket/channel conversion.
-      //
-      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
-                                            NBPtr->MCTPtr->SocketId,
-                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
-                                            &MemPtr->StdHeader);
-      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
-    }
-  }
-
-  MemNSwitchDCTNb (NBPtr, 0);
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initializes member functions and variables of NB block.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  INT32 i;
-
-  NBPtr->DctCachePtr = NBPtr->DctCache;
-  NBPtr->PsPtr = NBPtr->PSBlock;
-
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->Ganged = FALSE;
-  NBPtr->PosTrnPattern = POS_PATTERN_72B;
-  NBPtr->MemCleared = FALSE;
-  NBPtr->StartupSpeed = DDR800_FREQUENCY;
-  NBPtr->RcvrEnDlyLimit = 0xFF;
-  NBPtr->DefDctSelIntLvAddr = 3;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
-  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
-  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->InitializeMCT = MemNInitializeMctDA;
-  NBPtr->FinalizeMCT = MemNFinalizeMctDA;
-  NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
-  NBPtr->sendZQCmd = MemNSendZQCmdNb;
-  NBPtr->WritePattern = MemNWritePatternDA;
-  NBPtr->ReadPattern = MemNReadPatternDA;
-  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
-  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
-  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
-  NBPtr->StitchMemory = MemNStitchMemoryNb;
-  NBPtr->AutoConfig = memNAutoConfigDA;
-  NBPtr->PlatformSpec = MemNPlatformSpecNb;
-  NBPtr->InitMCT = MemNInitMCTNb;
-  NBPtr->DisableDCT = MemNDisableDCTNb;
-  NBPtr->StartupDCT = MemNStartupDCTNb;
-  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
-  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
-  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
-  NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
-  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
-  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
-  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
-  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
-  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
-  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
-  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
-  NBPtr->OtherTiming = MemNOtherTimingDA;
-  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
-  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
-  NBPtr->TrainingFlow = MemNTrainingFlowNb;
-  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
-  MemNInitNBDataNb (NBPtr);
-  NBPtr->PollBitField = MemNPollBitFieldNb;
-  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
-  NBPtr->BrdcstSet = MemNBrdcstSetNb;
-  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
-  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
-  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
-  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
-  NBPtr->RankEnabled = MemNRankEnabledNb;
-  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
-  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitRb;
-  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
-  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
-  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
-  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
-  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
-  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
-  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
-  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
-  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
-  NBPtr->CSPerChannel = MemNCSPerChannelNb;
-  NBPtr->CSPerDelay = MemNCSPerDelayNb;
-  NBPtr->FlushPattern = MemNFlushPatternNb;
-  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
-  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
-  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
-  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
-  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
-  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
-  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
-  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
-  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
-  NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
-  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
-  NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
-  NBPtr->IsSupported[SetSpareEn] = TRUE;
-  NBPtr->IsSupported[CheckSpareEn] = TRUE;
-  NBPtr->IsSupported[SetDllShutDown] = TRUE;
-  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
-  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
-  NBPtr->IsSupported[Check1GAlign] = TRUE;
-  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
-  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
-  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
-  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
-  NBPtr->IsSupported[CheckDllStdBy] = TRUE;
-  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->IsSupported[CheckDllRegDis] = TRUE;
-  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the default values in the MEM_DATA_STRUCT
- *
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsRb (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  )
-{
-  UINT8 Socket;
-  UINT8 Channel;
-  MEM_PARAMETER_STRUCT *RefPtr;
-  ASSERT (MemPtr != NULL);
-  RefPtr = MemPtr->ParameterListPtr;
-
-  // Memory Map/Mgt.
-  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
-  RefPtr->BottomIo = 0xE0;
-  RefPtr->UmaMode = UserOptions.CfgUmaMode;
-  RefPtr->UmaSize = UserOptions.CfgUmaSize;
-  RefPtr->MemHoleRemapping = TRUE;
-  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
-
-  // Dram Timing
-  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
-  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
-  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
-    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
-      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
-      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
-    }
-  }
-
-  // Memory Clear
-  RefPtr->EnableMemClr = TRUE;
-
-  // TableBasedAlterations
-  RefPtr->TableBasedAlterations = NULL;
-
-  // Platform config table
-  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
-  // Memory Restore
-  RefPtr->MemRestoreCtl = FALSE;
-  RefPtr->SaveMemContextCtl = FALSE;
-  AmdS3ParamsInitializer (&RefPtr->MemContext);
-
-  // Dram Configuration
-  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
-  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
-  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
-  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
-  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
-  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
-  // Dram Power
-  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
-  // ECC
-  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function writes training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Pattern[] - Pattern to write
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- *      This function reads training pattern
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in] Buffer[] - Buffer to fill
- *     @param[in] Address - System Address [47:16]
- *     @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  )
-{
-  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-  MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *   This function initiates DQS training for Server NB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  BOOLEAN Retval;
-  Retval = TRUE;
-  if (!MemNIsIdSupportedRb (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
-    Retval = FALSE;
-  }
-  return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h
deleted file mode 100644
index 1748f75b87..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnRb.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnRb.h
- *
- * Northbridge RB for RidgeBack
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-#ifndef _MNRB_H_
-#define _MNRB_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemNIsIdSupportedRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  );
-
-BOOLEAN
-MemConstructNBBlockRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
-  IN       MEM_SHARED_DATA *SharedPtr,
-  IN       UINT8 NodeID
-  );
-
-VOID
-MemNInitNBDataRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-MemNInitDefaultsRb (
-  IN OUT   MEM_DATA_STRUCT *MemPtr
-  );
-
-VOID
-MemNWritePatternRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT32 Address,
-  IN       UINT8 Pattern[],
-  IN       UINT16 ClCount
-  );
-
-VOID
-MemNReadPatternRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       UINT8 Buffer[],
-  IN       UINT32 Address,
-  IN       UINT16 ClCount
-  );
-
-BOOLEAN
-memNEnableTrainSequenceRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-#endif  /* _MNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c
deleted file mode 100644
index a3a08a0acf..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3Rb.c
- *
- * RB memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/Rb)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3Rb.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_RB_MNS3RB_FILECODE
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstRb (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegRb (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncRb[] = {
-  {MemNS3GetCSRNb, MemNS3SetCSRNb},
-  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegRb},
-  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorRb[] = {
-  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
-  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
-  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
-  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
-  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
-  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
-  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
-  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
-  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
-  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefRb = {
-  0,
-  (sizeof (S3PciPreSelfRefDescriptorRb) / sizeof (PCI_REG_DESCRIPTOR)),
-  S3PciPreSelfRefDescriptorRb,
-  NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorRb[] = {
-   // DCT 0
-  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 322
-  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  //errata 263
-  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT0,   BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-   // DCT 1
-  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 322
-  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // errata 263
-  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  // Dll regulator disable
-  {{2, 2, 1}, DCT1,   BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore F2x[1,0]94 right before exit self refresh
-  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefRb = {
-  0,
-  (sizeof (S3CPciPreSelfDescriptorRb) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPreSelfDescriptorRb,
-  PciSpecialCaseFuncRb
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorRb[] = {
-  // DCT0
-  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
-    // DCT1
-  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
-  // DllShutDown
-  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
-  // Restore scrubber related registers after restoring training related registers
-  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefRb = {
-  0,
-  (sizeof (S3CPciPostSelfDescriptorRb) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
-  S3CPciPostSelfDescriptorRb,
-  PciSpecialCaseFuncRb
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorRb[] = {
-  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
-  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
-  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefRb = {
-  0,
-  (sizeof (S3MSRPreSelfRefDescriptorRb) / sizeof (MSR_REG_DESCRIPTOR)),
-  S3MSRPreSelfRefDescriptorRb,
-  NULL
-};
-
-VOID *MemS3RegListRb[] = {
-  (VOID *)&S3PciPreSelfRefRb,
-  NULL,
-  (VOID *)&S3CPciPreSelfRefRb,
-  (VOID *)&S3CPciPostSelfRefRb,
-  (VOID *)&S3MSRPreSelfRefRb,
-  NULL,
-  NULL,
-  NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegRb[] = {
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
-  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- *     MemNIsIdSupportedRb
- *      This function matches the CPU_LOGICAL_ID with certain criteria to
- *      determine if it is supported by this NBBlock.
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- *     @return          TRUE -  This node is a RB.
- *     @return          FALSE - This node is not a RB.
- *
- */
-BOOLEAN
-MemNIsIdSupportedRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       CPU_LOGICAL_ID *LogicalIdPtr
-  )
-{
-
-  if (((LogicalIdPtr->Family & AMD_FAMILY_10_RB) != 0)
-      && ((LogicalIdPtr->Revision & AMD_F10_RB_ALL) != 0)) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for S3 resume
- *
- *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
- *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
- *     @param[in]       NodeID   - Node ID of the target node.
- *
- *      @return         BOOLEAN
- *                         TRUE - This is the correct constructor for the targeted node.
- *                         FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockRb (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  INT32 i;
-  MEM_NB_BLOCK *NBPtr;
-
-  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Dct = 0;
-  NBPtr->Channel = 0;
-  NBPtr->Ganged = FALSE;
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
-  for (i = 0; i < EnumSize; i++) {
-    NBPtr->IsSupported[i] = FALSE;
-  }
-
-  for (i = 0; i < NumberOfHooks; i++) {
-    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
-  }
-
-  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
-  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
-  NBPtr->SwitchDCT = MemNSwitchDCTNb;
-  NBPtr->SwitchChannel = MemNSwitchChannelNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedRb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegRb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrRb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstRb;
-  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)) * sizeof (UINT32);
-
-  MemNSwitchDCTNb (NBPtr, 0);
-
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function returns the register list for each device for RB
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- *     @return          UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
-  )
-{
-  UINT8 i;
-  UINT16 Size;
-  Size = 0;
-  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
-    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
-    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListRb[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
-      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
-    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
-    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListRb[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
-    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListRb[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
-      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
-    }
-    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
-    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
-    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListRb[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
-      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
-      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
-    }
-  }
-  return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function return the register list according to the register ID.
- *
- *     @param[in]   RegisterLstID - value of the Register list ID.
- *     @param[out]  **RegisterHeader - pointer to the address of the register list.
- *     @return      none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstRb (
-  IN       UINT32 RegisterLstID,
-     OUT   VOID **RegisterHeader
-  )
-{
-  if (RegisterLstID >= (sizeof (MemS3RegListRb) / sizeof (VOID *))) {
-    ASSERT(FALSE); // RegisterListID exceeded size of Register list
-    return AGESA_FATAL;
-  }
-  if (MemS3RegListRb[RegisterLstID] != NULL) {
-    *RegisterHeader = MemS3RegListRb[RegisterLstID];
-    return AGESA_SUCCESS;
-  }
-  ASSERT(FALSE); // Device register list error
-  return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in]   AccessWidth - Access width of the register
- *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
- *     @param[in]   *Value - Pointer to the value be read.
- *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
- *      @return         none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegRb (
-  IN       ACCESS_WIDTH AccessWidth,
-  IN       PCI_ADDR Address,
-  IN       VOID *Value,
-  IN OUT   VOID *ConfigPtr
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (Address.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Save the value in the heap at appropriate offset based on the index
-    // of the target register in the special case array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)); i ++) {
-        if (SpecialCasePCIRegRb[i] == Address.Address.Register) {
-          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
-        }
-      }
-    }
-  }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function stores special case register on the heap.
- *
- *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
- *     @param[in,out]  *StdHeader - Config handle for library and services.
- *     @return         none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  LOCATE_HEAP_PTR LocateBufferPtr;
-  UINT8 i;
-  PCI_ADDR PciAddr;
-  UINT32 Value;
-  UINT8 NodeID;
-  UINT8 Offset;
-  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
-  Offset = 0;
-  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
-  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
-  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
-  PciAddr.Address.Function = 2;
-  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
-  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
-    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
-    // Get the node ID of the target die.
-    NodeID = (UINT8) (PciAddr.Address.Device - 24);
-    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
-      if (SpecialHeapHeader[i].Node == NodeID) {
-        // Get the offset in the heap for the target die.
-        Offset = SpecialHeapHeader[i].Offset;
-        break;
-      }
-    }
-    ASSERT (i < MAX_NODES_SUPPORTED_DA);
-    // Restore the value one by one in the sequence of the special case register array.
-    if (Offset != 0) {
-      for (i = 0; i < (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)); i ++) {
-        PciAddr.Address.Register = SpecialCasePCIRegRb[i];
-        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
-        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
-      }
-    }
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.h
deleted file mode 100644
index 499cf2143f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnS3Rb.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3Rb.h
- *
- * S3 resume memory related function for RB.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _MNS3RB_H_
-#define _MNS3RB_H_
-
-/*----------------------------------------------------------------------------
- *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of RB
-typedef enum {
-  PCI_LST_ESR_DA,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
-  PCI_LST_DA,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
-  CPCI_LST_ESR_DA,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
-  CPCI_LST_DA,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
-  MSR_LST_ESR_DA,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
-  MSR_LST_DA,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
-  CMSR_LST_ESR_DA,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
-  CMSR_LST_DA,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- *                         DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                         TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3RB_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
deleted file mode 100644
index 3d085355d6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnflowRb.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowRb.c
- *
- * RidgeBack initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_RB_MNFLOWRB_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *      This function initializes the platform specific block
- *
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *
- *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
- *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 Dct;
-  UINT8 f;
-  UINT8 ErrUnSuppFFCount;
-  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
-    NBPtr->SwitchDCT (NBPtr, Dct);
-    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
-      ErrUnSuppFFCount = 0;
-      for (f = 0; f < MAX_FF_TYPES; f++) {
-        ASSERT (memPlatSpecFFInstalledRb[f] != NULL);
-        if (memPlatSpecFFInstalledRb[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
-          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
-        } else {
-          break;
-        }
-      }
-      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
-        return FALSE; // No FF types are supported
-      }
-    }
-  }
-  return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- *                              LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c
deleted file mode 100644
index 7270f8ab69..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/RB/mnidendimmRb.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmRb.c
- *
- * RB northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "mnRb.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE
-
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorRb (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  //
-  // Determine if this is the expected NB Type
-  //
-  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-  if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
-    return FALSE;
-  }
-
-  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
-  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-  NBPtr->CsRegMsk = 0x1FF83FE0;
-  NBPtr->MemPtr = MemPtr;
-  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
-  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
-  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
-  NBPtr->Ganged = FALSE;
-  InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
-  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
-  NBPtr->SetBitField = MemNSetBitFieldNb;
-  NBPtr->GetBitField = MemNGetBitFieldNb;
-  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
-  return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c
deleted file mode 100644
index 1f352577d4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mprc32_3.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprc32_3.c
- *
- * Platform specific settings for C32 DDR3 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_C32_MPRC32_3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define AMD_FAMILY_10_C32    AMD_FAMILY_10_HY
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitRC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*
- * ODT Settings for 1 or 2 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm2D[] = {
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
-  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
-  {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
-  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
-  {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
-};
-/*
- * ODT Settings for 3 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm3D[] = {
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
-  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit1D[] = {
-  {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit2D[] = {
-  {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0},
-  {SR_DIMM0 + SR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
-  {QR_DIMM0 + ANY_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0},
-  {ANY_DIMM0 + QR_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
-  {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {SR_DIMM0 + SR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
-  {QR_DIMM1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
-  {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0},
-  {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
-
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRC32_3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsRC32_3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRC32_3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for R-DDR3 C32 DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) {
-    DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm2D);
-    DramTermPtr = C32RDdr3DramTerm2D;
-  } else if (MaxDimmsPerChannel == 3) {
-    DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm3D);
-    DramTermPtr = C32RDdr3DramTerm3D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-  //
-  // Special Cases for certain configs not covered by the table
-  //
-  // SR-SR-SR 1.5v @1066 (Currently only 3DPCH config at 1066)
-  if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3) &&
-      (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY)) {
-    NBPtr->PsPtr->DramTerm = 5; //30 Ohms
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for R-DDR3 C32 DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitRC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT8 FreqLimitSize;
-  UINT16 SpeedLimit;
-  CONST POR_SPEED_LIMIT *FreqLimitPtr;
-  DCT_STRUCT *DCTPtr;
-
-  DCTPtr = NBPtr->DCTPtr;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 4) {
-    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-    return;
-  } else if (MaxDimmPerCH == 3) {
-    FreqLimitPtr = C32RDdr3PSPorFreqLimit3D;
-    FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit3D);
-  } else if (MaxDimmPerCH == 2) {
-    FreqLimitPtr = C32RDdr3PSPorFreqLimit2D;
-    FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit2D);
-  } else {
-    FreqLimitPtr = C32RDdr3PSPorFreqLimit1D;
-    FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit1D);
-  }
-
-  SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr);
-
-  if (SpeedLimit != 0) {
-    if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-      DCTPtr->Timings.TargetSpeed = SpeedLimit;
-    }
-  } else {
-    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c
deleted file mode 100644
index 1038cec27b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/C32/mpuc32_3.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuc32_3.c
- *
- * Platform specific settings for C32 DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define AMD_FAMILY_10_C32    AMD_FAMILY_10_HY
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUC32_3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsUC32_3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 C32 DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for SO-DDR3 C32
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUC32_3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT16 MaxSpeed;
-  //
-  // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066
-  //
-  if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) {
-    MaxSpeed = DDR1066_FREQUENCY;
-  } else {
-    //
-    // Highest POR supported speed for Unbuffered dimm is 1333
-    //
-    MaxSpeed = DDR1333_FREQUENCY;
-  }
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
-  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
-    // Unbuffered DDR3 at 333MHz is not supported
-    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
deleted file mode 100644
index 84153f8fa5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda2.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsda2.c
- *
- * Platform specific settings for DA DDR2 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support S1g3 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DA_MPSDA2_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSDA2 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
-  {DDR533 + DDR667 + DDR800, ONE_DIMM, ANY_NUM, 2, 0, 0},
-  {DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO-DIMM DA DDR2
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSDA2 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsSDA2;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for SO-DIMM DA DDR2
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSDA2 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DaSDdr2DramTerm), DaSDdr2DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c
deleted file mode 100644
index f684be035e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpsda3.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsda3.c
- *
- * Platform specific settings for DA DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DA_MPSDA3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm1D[] = {
-  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
-  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO-DIMM DA DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSDA3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsSDA3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSDA3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for SO-DIMM DA DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 1) {
-    DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm1D);
-    DramTermPtr = DaSDdr3DramTerm1D;
-  } else if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm2D);
-    DramTermPtr = DaSDdr3DramTerm2D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for SO-DDR3 DA
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT16 SpeedLimit;
-
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 1) {
-    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-      //
-      // Highest POR supported speed for SODimm is 1333
-      //
-      SpeedLimit = DDR1333_FREQUENCY;
-    } else {
-      //
-      // Max LV DDR3 Speed is 1066 for this silicon
-      //
-      SpeedLimit = DDR1066_FREQUENCY;
-    }
-  } else {
-    //
-    // Highest supported speed in 2DPC configuration is 1066
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-    //
-    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
-    //
-    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
-       (NBPtr->ChannelPtr->Dimms == 2)) {
-      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
-      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
-    }
-  }
-
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c
deleted file mode 100644
index 008c1a16f2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DA/mpuda3.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuda3.c
- *
- * Platform specific settings for DA DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DA_MPUDA3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDA3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsUDA3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUDA3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 DA DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for U-DDR3 DA
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUDA3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT16 SpeedLimit;
-
-  if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-    //
-    // Highest POR supported speed for Unbuffered dimm is 1333
-    //
-    SpeedLimit = DDR1333_FREQUENCY;
-  } else {
-    //
-    // Max LV DDR3 Speed is 1066 for this silicon
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-  }
-
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
-    // Unbuffered DDR3 at 333MHz is not supported
-    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
deleted file mode 100644
index 059d854ad2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr2.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprdr2.c
- *
- * Platform specific settings for DR DDR2 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPRDR2_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRDr2 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
-  {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
-  {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
-  {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRDr2 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsRDr2;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for R-DDR2 DR DDR2
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRDr2 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
deleted file mode 100644
index 589fd37f58..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mprdr3.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprdr3.c
- *
- * Platform specific settings for DR DDR3 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPRDR3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRDr3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
-  {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
-  {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
-  {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
-  {DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
-};
-
-STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
-  {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRDr3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsRDr3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for R-DDR3 DR DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRDr3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm2D);
-    DramTermPtr = DrRDdr3DramTerm2D;
-  } else if (MaxDimmsPerChannel == 3) {
-    DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm3D);
-    DramTermPtr = DrRDdr3DramTerm3D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
deleted file mode 100644
index a30fbf9f68..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpsdr3.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsdr3.c
- *
- * Platform specific settings for DR DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPSDR3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSDr3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm1D[] = {
-  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
-  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSDr3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsSDr3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for S-DDR3 DR DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSDr3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 1) {
-    DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm1D);
-    DramTermPtr = DrSDdr3DramTerm1D;
-  } else if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm2D);
-    DramTermPtr = DrSDdr3DramTerm2D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
deleted file mode 100644
index f08fd345b7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr2.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpudr2.c
- *
- * Platform specific settings for DR DDR2 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPUDR2_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUDr2 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
-  {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
-  {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
-  {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
-  {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDr2 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsUDr2;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR2 DR DDR2
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUDr2 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
deleted file mode 100644
index 778f4b907d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/DR/mpudr3.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpudr3.c
- *
- * Platform specific settings for DR DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPUDR3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUDr3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDr3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsUDr3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 DR DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUDr3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c
deleted file mode 100644
index 7ef0d0a59c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mprhy3.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprhy3.c
- *
- * Platform specific settings for HY DDR3 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "GeneralServices.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_HY_MPRHY3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitRHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*
- * ODT Settings for 1 Dimm or 2 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm2D[] = {
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
-  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
-  {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
-  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
-  {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
-};
-/*
- * ODT Settings for 3 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm3D[] = {
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
-  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
-  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
-  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit1D[] = {
-  {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit2D[] = {
-  {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {QR_DIMM0 + ANY_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
-  {ANY_DIMM0 + QR_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
-  {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
-  {QR_DIMM1, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
-  {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
-  {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
-  {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRHy3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsRHy3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRHy3;
-
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for R-DDR3 HY DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) {
-    DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm2D);
-    DramTermPtr = HyRDdr3DramTerm2D;
-  } else if (MaxDimmsPerChannel == 3) {
-    DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm3D);
-    DramTermPtr = HyRDdr3DramTerm3D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-  //
-  // Special Cases for certain configs not covered by the table
-  //
-  // 3DPCH Fully populated.
-  if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) {
-    NBPtr->PsPtr->DramTerm = 5; //30 Ohms
-    NBPtr->PsPtr->QR_DramTerm = 1; // 60 Ohms
-  }
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for R-DDR3 HY
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitRHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT8 FreqLimitSize;
-  UINT16 SpeedLimit;
-  CONST POR_SPEED_LIMIT *FreqLimitPtr;
-  DCT_STRUCT *DCTPtr;
-
-  DCTPtr = NBPtr->DCTPtr;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 4) {
-    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-    return;
-  } else if (MaxDimmPerCH == 3) {
-    FreqLimitPtr = HyRDdr3PSPorFreqLimit3D;
-    FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D);
-  } else if (MaxDimmPerCH == 2) {
-    FreqLimitPtr = HyRDdr3PSPorFreqLimit2D;
-    FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D);
-  } else {
-    FreqLimitPtr = HyRDdr3PSPorFreqLimit1D;
-    FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D);
-  }
-
-  SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr);
-
-  if (SpeedLimit != 0) {
-    if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-      DCTPtr->Timings.TargetSpeed = SpeedLimit;
-    }
-  } else {
-    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c
deleted file mode 100644
index 41698ac758..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpshy3.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpshy3.c
- *
- * Platform specific settings for HY DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = {
-  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
-  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSHy3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsSHy3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for S-DDR3 HY DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 1) {
-    DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D);
-    DramTermPtr = HySDdr3DramTerm1D;
-  } else if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D);
-    DramTermPtr = HySDdr3DramTerm2D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for SO-DDR3 HY
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT16  MaxSpeed;
-  //
-  // Highest POR supported speed for SODimm is 1333
-  //
-  MaxSpeed = DDR1333_FREQUENCY;
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c
deleted file mode 100644
index 7cfc9c56e7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/HY/mpuhy3.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuhy3.c
- *
- * Platform specific settings for HY DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUhy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUHy3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-  PsPtr->MemPDoPs = MemPDoPsUhy3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 HY DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUhy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for U-DDR3 HY
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUHy3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT16  MaxSpeed;
-  //
-  // Highest POR supported speed for Unbuffered dimm is 1333
-  //
-  MaxSpeed = DDR1333_FREQUENCY;
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
-  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
-    // Unbuffered DDR3 at 333MHz is not supported
-    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c
deleted file mode 100644
index 37ab15997f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpsNi3.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsNi3.c
- *
- * Platform specific settings for Ni DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_NI_MPSNI3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm1D[] = {
-  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
-  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO-DIMM Ni DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSNi3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsSNi3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSNi3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for SO-DIMM Ni DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 1) {
-    DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm1D);
-    DramTermPtr = NiSDdr3DramTerm1D;
-  } else if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm2D);
-    DramTermPtr = NiSDdr3DramTerm2D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for SO-DDR3 Ni
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT16 SpeedLimit;
-
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 1) {
-    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-      //
-      // Highest POR supported speed for SODimm is 1333
-      //
-      SpeedLimit = DDR1333_FREQUENCY;
-    } else {
-      //
-      // Max LV DDR3 Speed is 1066 for this silicon
-      //
-      SpeedLimit = DDR1066_FREQUENCY;
-    }
-  } else {
-    //
-    // Highest supported speed in 2DPC configuration is 1066
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-    //
-    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
-    //
-    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
-       (NBPtr->ChannelPtr->Dimms == 2)) {
-      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
-      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
-    }
-  }
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c
deleted file mode 100644
index 004b7f872b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/NI/mpuNi3.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuNi3.c
- *
- * Platform specific settings for Ni DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_NI_MPUNI3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUNi3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsUNi3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUNi3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 Ni DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for U-DDR3 Ni
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUNi3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT16 SpeedLimit;
-
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 1) {
-    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-      //
-      // Highest POR supported speed for Unbuffered dimm is 1333
-      //
-      SpeedLimit = DDR1333_FREQUENCY;
-    } else {
-      //
-      // Max LV DDR3 Speed is 1066 for this silicon
-      //
-      SpeedLimit = DDR1066_FREQUENCY;
-    }
-  } else {
-    //
-    // Highest supported speed in 2DPC configuration is 1066
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-    //
-    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
-    //
-    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
-       (NBPtr->ChannelPtr->Dimms == 2)) {
-      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
-      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
-    }
-  }
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
-    // Unbuffered DDR3 at 333MHz is not supported
-    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c
deleted file mode 100644
index 89e469881b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpsph3.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsPh3.c
- *
- * Platform specific settings for Ph DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_PH_MPSPH3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm1D[] = {
-  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
-  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO-DIMM Ph DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSPh3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsSPh3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSPh3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for SO-DIMM Ph DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 1) {
-    DramTermSize = GET_SIZE_OF (PhSDdr3DramTerm1D);
-    DramTermPtr = PhSDdr3DramTerm1D;
-  } else if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (PhSDdr3DramTerm2D);
-    DramTermPtr = PhSDdr3DramTerm2D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for SO-DDR3 Ph
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT16 SpeedLimit;
-
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 1) {
-    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-      //
-      // Highest POR supported speed for SODimm is 1333
-      //
-      SpeedLimit = DDR1333_FREQUENCY;
-    } else {
-      //
-      // Max LV DDR3 Speed is 1066 for this silicon
-      //
-      SpeedLimit = DDR1066_FREQUENCY;
-    }
-  } else {
-    //
-    // Highest supported speed in 2DPC configuration is 1066
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-    //
-    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
-    //
-    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
-       (NBPtr->ChannelPtr->Dimms == 2)) {
-      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
-      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
-    }
-  }
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c
deleted file mode 100644
index ea5901c7ba..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/PH/mpuph3.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuPh3.c
- *
- * Platform specific settings for Ph DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_PH_MPUPH3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 Ph DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUPh3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsUPh3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUPh3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 Ph DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for U-DDR3 Ph
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUPh3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT16 SpeedLimit;
-
-  if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-    //
-    // Highest POR supported speed for Unbuffered dimm is 1333
-    //
-    SpeedLimit = DDR1333_FREQUENCY;
-  } else {
-    //
-    // Max LV DDR3 Speed is 1066 for this silicon
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-  }
-
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
-    // Unbuffered DDR3 at 333MHz is not supported
-    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c
deleted file mode 100644
index 6890f65b8d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpsRb3.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsRb3.c
- *
- * Platform specific settings for RB DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_RB_MPSRB3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSRb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSRb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm1D[] = {
-  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
-  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm2D[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor the platform specific settings for SO-DIMM RB DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSRb3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsSRb3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSRb3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for SO-DIMM RB DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSRb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  CONST DRAM_TERM_ENTRY *DramTermPtr;
-  UINT8 MaxDimmsPerChannel;
-  UINT8 *DimmsPerChPtr;
-  UINT8 DramTermSize;
-
-  DramTermSize = 0;
-  DramTermPtr = NULL;
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmsPerChannel = *DimmsPerChPtr;
-  } else {
-    MaxDimmsPerChannel = 2;
-  }
-
-  if (MaxDimmsPerChannel == 1) {
-    DramTermSize = GET_SIZE_OF (RbSDdr3DramTerm1D);
-    DramTermPtr = RbSDdr3DramTerm1D;
-  } else if (MaxDimmsPerChannel == 2) {
-    DramTermSize = GET_SIZE_OF (RbSDdr3DramTerm2D);
-    DramTermPtr = RbSDdr3DramTerm2D;
-  } else {
-    IDS_ERROR_TRAP;
-  }
-
-  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for SO-DDR3 RB
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSRb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT8 *DimmsPerChPtr;
-  UINT8 MaxDimmPerCH;
-  UINT16 SpeedLimit;
-
-  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
-  if (DimmsPerChPtr != NULL) {
-    MaxDimmPerCH = *DimmsPerChPtr;
-  } else {
-    MaxDimmPerCH = 2;
-  }
-
-  if (MaxDimmPerCH == 1) {
-    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-      //
-      // Highest POR supported speed for SODimm is 1333
-      //
-      SpeedLimit = DDR1333_FREQUENCY;
-    } else {
-      //
-      // Max LV DDR3 Speed is 1066 for this silicon
-      //
-      SpeedLimit = DDR1066_FREQUENCY;
-    }
-  } else {
-    //
-    // Highest supported speed in 2DPC configuration is 1066
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-    //
-    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
-    //
-    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
-       (NBPtr->ChannelPtr->Dimms == 2)) {
-      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
-      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
-    }
-  }
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c
deleted file mode 100644
index 03790609cd..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/RB/mpuRb3.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuRb3.c
- *
- * Platform specific settings for RB DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-  *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * ***************************************************************************
-  *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_RB_MPURB3_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsURb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-VOID
-STATIC
-MemPGetPORFreqLimitURb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  );
-
-/*
- *-----------------------------------------------------------------------------
- *                                EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
-  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
-  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
-  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
-  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This function is the constructor for the platform specific settings for U-DDR3 RB DDR3
- *
- *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
- *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
- *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
- *
- *     @return          AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsURb3 (
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN OUT   CH_DEF_STRUCT *ChannelPtr,
-  IN OUT   MEM_PS_BLOCK *PsPtr
-  )
-{
-  ASSERT (MemPtr != 0);
-  ASSERT (ChannelPtr != 0);
-
-  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
-    return AGESA_UNSUPPORTED;
-  }
-  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
-    return AGESA_UNSUPPORTED;
-  }
-  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
-    return AGESA_UNSUPPORTED;
-  }
-
-  PsPtr->MemPDoPs = MemPDoPsURb3;
-  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitURb3;
-  return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function sets the platform specific settings for U-DDR3 RB DDR3
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *     @return          TRUE - Find settings for corresponding platform and dimm population.
- *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsURb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *     This is function gets the POR speed limit for U-DDR3 RB
- *
- *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitURb3 (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  UINT16 SpeedLimit;
-
-  if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
-    //
-    // Highest POR supported speed for Unbuffered dimm is 1333
-    //
-    SpeedLimit = DDR1333_FREQUENCY;
-  } else {
-    //
-    // Max LV DDR3 Speed is 1066 for this silicon
-    //
-    SpeedLimit = DDR1066_FREQUENCY;
-  }
-
-  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
-    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
-  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
-    // Unbuffered DDR3 at 333MHz is not supported
-    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
-    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
-    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
-    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
-    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
-  }
-}