diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-04-23 12:22:59 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-04-26 20:55:34 +0000 |
| commit | 029d997b6eb0c784b844bf554dec5c33286b6507 (patch) | |
| tree | 7838228ee200825c6ccde28d679eceb958401e6d /src/vendorcode | |
| parent | 109c4d05d6495dd3a6c480b1ccbd3183109eb63e (diff) | |
amd/cezanne: Add slow_ppt_time & thermctl_limit to UPD
These values will be added in the upcoming STAPM configuration update.
BUG=b:185209734
TEST=Build & Boot guybrush
Cq-Depend: chrome-internal:3780259
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index dd59d52ac6..6e9a1f0969 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -65,7 +65,9 @@ typedef struct __packed { /** Offset 0x0405**/ uint8_t cppc_preferred_cores; /** Offset 0x0406**/ uint8_t stapm_boost; /** Offset 0x0407**/ uint32_t stapm_time_constant; - /** Offset 0x040B**/ uint8_t smu_soc_tuning_reserved[17]; + /** Offset 0x040B**/ uint32_t slow_ppt_time_constant; + /** Offset 0x040F**/ uint32_t thermctl_limit; + /** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9]; /** Offset 0x041C**/ uint8_t iommu_support; /** Offset 0x041D**/ uint8_t pspp_policy; /** Offset 0x041E**/ uint8_t enable_nb_azalia; |