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authorFelix Held <felix-coreboot@felixheld.de>2024-01-30 15:40:53 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-01 11:39:01 +0000
commitdde265f5a22c7b75a2d502a66ae706e6b1e04561 (patch)
tree2a9a1ff5441cd998376649fefa03e67cc64d9c27 /src/vendorcode
parentfbda323e8af2b0556abb0c76beca4482c58af8a2 (diff)
soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the legacy PCI config space access is needed on all AMD SoCs, implement a common add_pci_cfg_resources function that reports both and gets called from amd_pci_domain_read_resources and don't report those in the SoC- specific code any more. The only functional change is that on Genoa now the IO ports used for the legacy PCI config space access get reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/amd/opensil/genoa_poc/memmap.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c
index 1e633d9d7d..39b27ec293 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c
@@ -114,8 +114,6 @@ void add_opensil_memmap(struct device *dev, unsigned long *idx)
if (mem_usable != top_mem)
reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem);
- mmconf_resource(dev, (*idx)++);
-
// Check if we're done
if (top_of_mem <= 0x100000000)
return;