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authorRyan Chuang <ryan.chuang@mediatek.corp-partner.google.com>2021-07-06 17:12:27 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-07-07 14:49:15 +0000
commitc6ed254835a731625cb2a7d0c7b91e98f518a3d6 (patch)
tree822937b84b44b9d424fca43bfac579b5210ae921 /src/vendorcode
parente53cbfdbf40332ce766ecd8490e97e986a057c45 (diff)
vc/mediatek/mt8195: Improve settings of duty calibration
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c26
-rw-r--r--src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h2
2 files changed, 18 insertions, 10 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
index cea83a06fe..16f16ff0e4 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
@@ -14804,18 +14804,26 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p)
#endif
#endif
{
+ U8 u1ChannelIdx;
+ U8 u1backup_channel = vGetPHY2ChannelMapping(p);
+
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
if(p->femmc_Ready==1)
{
- DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
- DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
- #if __LP5_COMBO__
- WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]);
- #endif
- #if APPLY_DQDQM_DUTY_CALIBRATION
- DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
- DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
- #endif
+ for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){
+ vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
+ DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
+ DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
+ #if __LP5_COMBO__
+ WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]);
+ #endif
+ #if APPLY_DQDQM_DUTY_CALIBRATION
+ DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
+ DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
+ #endif
+ }
+ vSetPHY2ChannelMapping(p, u1backup_channel);
vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K);
return;
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
index a40f290520..d27d7ea96f 100644
--- a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
@@ -123,7 +123,7 @@
#else
#define ENABLE_EYESCAN_GRAPH 1
#endif
-#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
+#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
#define EYESCAN_GRAPH_RX_VREF_STEP 2
#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127
#define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10