vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81

Update header files for FSP for Meteor Lake platform to version 3194_81,
previous version being 3165_81.

FSPM:
1. Add 'PchPcieRpEnableMask' UPD
2. Address offset changes

Add "FspProducerDataHeader.h" file to support MRC version Info

BUG=b:284803304
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

2 files changed, 88 insertions, 4 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h
new file mode 100644
index 0000000000..aa96b3a162
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h
@@ -0,0 +1,78 @@
+/** @file
+
+  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#ifndef _FSP_PRODUCER_DATA_HEADER_H_
+#define _FSP_PRODUCER_DATA_HEADER_H_
+
+#include <Guid/FspHeaderFile.h>
+
+//
+// FSP Header Data structure from FspHeader driver.
+//
+#pragma pack(1)
+///
+/// FSP Producer Data Subtype - 1
+///
+typedef struct {
+  ///
+  /// Byte 0x00: Length of this FSP producer data type record.
+  ///
+  UINT16  Length;
+  ///
+  /// Byte 0x02: FSP producer data type.
+  ///
+  UINT8   Type;
+  ///
+  /// Byte 0x03: Revision of this FSP producer data type.
+  ///
+  UINT8   Revision;
+  ///
+  /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
+  ///
+  UINT32  RcVersion;
+  ///
+  /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
+  ///
+  UINT8  BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
+} FSP_PRODUCER_DATA_TYPE1;
+
+///
+/// FSP Producer Data Subtype - 2
+///
+typedef struct {
+  ///
+  /// Byte 0x00: Length of this FSP producer data type record.
+  ///
+  UINT16  Length;
+  ///
+  /// Byte 0x02: FSP producer data type.
+  ///
+  UINT8   Type;
+  ///
+  /// Byte 0x03: Revision of this FSP producer data type.
+  ///
+  UINT8   Revision;
+  ///
+  /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
+  ///
+  UINT8  MrcVersion [4];
+} FSP_PRODUCER_DATA_TYPE2;
+
+typedef struct {
+  FSP_INFO_HEADER          FspInfoHeader;
+  FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
+  FSP_PRODUCER_DATA_TYPE1  FspProduceDataType1;
+  FSP_PRODUCER_DATA_TYPE2  FspProduceDataType2;
+  FSP_PATCH_TABLE          FspPatchTable;
+} FSP_PRODUCER_DATA_TABLES;
+#pragma pack()
+
+#endif // _FSP_PRODUCER_DATA_HEADER_H
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
index ac6b6c7828..f8edff8351 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
@@ -1740,7 +1740,13 @@ typedef struct {
 
 /** Offset 0x0AB9 - Reserved
 **/
-  UINT8                       Reserved39[59];
+  UINT8                       Reserved39[55];
+
+/** Offset 0x0AF0 - Enable PCH PCIE RP Mask
+  Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port,
+  bit0 for port1, bit1 for port2, and so on.
+**/
+  UINT32                      PchPcieRpEnableMask;
 
 /** Offset 0x0AF4 - Enable SOC/IOE PCIE RP Mask
   Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each
@@ -2998,7 +3004,7 @@ typedef struct {
 
 /** Offset 0x0DEC - Reserved
 **/
-  UINT8                      Reserved78[172];
+  UINT8                      Reserved78[188];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -3017,11 +3023,11 @@ typedef struct {
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0E98
+/** Offset 0x0EA8
 **/
   UINT8                       Rsvd500[6];
 
-/** Offset 0x0E9E
+/** Offset 0x0EAE
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;