diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-10-30 11:36:15 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-11-02 04:43:39 +0000 |
| commit | b57f22fc5b79bcd21b8976cd4e7b368cb9b0c50c (patch) | |
| tree | 4157179293df1ad049cb3cff46212f7a83d5100e /src/vendorcode | |
| parent | 184c7940866703598a9fcbdb7f1be1dd31ff2718 (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP
version 3425. Previous version was 3373.
BUG=b:172045149
BRANCH=none
TEST=build and boot delbin
Cq-Depend:chrome-internal:3373431
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 28592cd47c..6038b13eff 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ typedef struct { /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[12]; + UINT8 Reserved45[36]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0928 +/** Offset 0x0940 **/ UINT8 UnusedUpdSpace27[6]; -/** Offset 0x092E +/** Offset 0x0946 **/ UINT16 UpdTerminator; } FSPM_UPD; |