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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-02-20 09:43:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-02 13:06:09 +0000 |
| commit | eede5a24959139639a0156ccb3795d1468e996bc (patch) | |
| tree | ea4cc006139d643d9e20456cfd2404baced3acc3 /src/vendorcode/siemens | |
| parent | 9edaccd922af346bba59ce32668fd91f051af1d6 (diff) | |
soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC support
Add a new parameter STT_ALPHA_APU' for each DPTC mode.
BUG=b:257149501
BRANCH=None
TEST=Check if the STT value matches the expected setting.
Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Diffstat (limited to 'src/vendorcode/siemens')
0 files changed, 0 insertions, 0 deletions