soc/intel/alderlake: Drop 100ms delay and do not poll Link Active

Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.

BUG=None
TEST=Built Alderlake coreboot image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions