diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2018-11-01 14:02:57 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:06:55 +0000 |
| commit | 392d69957038b26ce1de5c3a88bb0828fec4c0d4 (patch) | |
| tree | 980319b0da4c9fb7eb169708db4f3294715352a4 /src/vendorcode/siemens/hwilib | |
| parent | fe701ee3982f8c921390aacc45d50871dc86d119 (diff) | |
src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage
soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/siemens/hwilib')
0 files changed, 0 insertions, 0 deletions