diff options
| author | Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> | 2021-10-26 20:01:01 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-01 15:57:11 +0000 |
| commit | 39277554a43df5614cbadb9e2bd8f918d3554e1e (patch) | |
| tree | a628583c38137bd540ab1cd154ec0e37421e1ad7 /src/vendorcode/mediatek | |
| parent | 19b3102910f813e71efaa61c86e683afd48899a1 (diff) | |
vc/mediatek/mt8195: Remove unused code and comments
Remove unused code and comment to align with the latest MTK memory
reference code which is from MTK internal dram driver code without
upstream.
version: Ib59134533ced8de09d23dd9f347c934d315166e2
TEST=boot to kernel
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/mediatek')
24 files changed, 5041 insertions, 15461 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c b/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c index e09f5ea8b4..05d0eb903b 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c +++ b/src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c @@ -3,19 +3,19 @@ #include "dramc_dv_init.h" #include "dramc_common.h" #include "dramc_top.h" -//========================== -//PLL config -//========================== + + + static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate) { U32 XTAL_FREQ = 26; - U8 PREDIV = 1; //0/1/2 - U8 POSDIV = 0; //0/1/2 - U8 FBKSEL = 0; //over 3800 1 otherwise 0 + U8 PREDIV = 1; + U8 POSDIV = 0; + U8 FBKSEL = 0; U32 PCW; U8 DIV16_CK_SEL = 0; -#if EMI_LPBK_USE_DDR_800 // For Pe_trus DDR1600, sedalpbk DDR800 thru io +#if EMI_LPBK_USE_DDR_800 if(p->frequency==800) { POSDIV = 1; @@ -25,7 +25,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate) #if (fcFOR_CHIP_ID == fc8195) if(A_D->DQ_CA_OPEN == 1) { - DIV16_CK_SEL = 0; // For open loop mode DDR400 = 1600/div4, confirm with WL Lee + DIV16_CK_SEL = 0; } else #endif @@ -39,7 +39,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate) mcSHOW_DBG_MSG6(("=================================== \n")); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL1), P_Fld(0, PHYPLL1_RG_RPHYPLL_TST_EN) | P_Fld(0, PHYPLL1_RG_RPHYPLL_TSTOP_EN)); - // @Darren, Mp settings sync @WL + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0) , P_Fld(0 , SHU_PHYPLL0_RG_RPHYPLL_RESERVED ) \ | P_Fld(0 , SHU_PHYPLL0_RG_RPHYPLL_ICHP )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL0) , P_Fld(0 , SHU_CLRPLL0_RG_RCLRPLL_RESERVED ) \ @@ -52,25 +52,25 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate) | P_Fld(POSDIV , SHU_CLRPLL2_RG_RCLRPLL_POSDIV )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL1) , P_Fld(PCW , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW ) \ | P_Fld(1 , SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG ) \ - | P_Fld(0 , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN )); //for DV could set 1 to solve clock jitter issue. + | P_Fld(0 , SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL1) , P_Fld(PCW , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW ) \ | P_Fld(1 , SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG ) \ - | P_Fld(0 , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN )); //for DV could set 1 to solve clock jitter issue. + | P_Fld(0 , SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL1) , P_Fld(1 , SHU_PLL1_RG_RPHYPLLGP_CK_SEL ) \ - | P_Fld(1 , SHU_PLL1_R_SHU_AUTO_PLL_MUX )); //notice here. TODO. should create another function to manage the SPM related + | P_Fld(1 , SHU_PLL1_R_SHU_AUTO_PLL_MUX )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld(0 , SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN ) \ | P_Fld(1 , SHU_PHYPLL3_RG_RPHYPLL_RST_DLY ) \ | P_Fld(FBKSEL , SHU_PHYPLL3_RG_RPHYPLL_FBKSEL )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld(0 , SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN ) \ | P_Fld(1 , SHU_CLRPLL3_RG_RCLRPLL_RST_DLY ) \ | P_Fld(FBKSEL , SHU_CLRPLL3_RG_RCLRPLL_FBKSEL )); - //if(A_D->DQ_CA_OPEN == 1) + { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_CLK_CTRL0), P_Fld( A_D->DQ_CA_OPEN , SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL3) , P_Fld( A_D->DQ_CA_OPEN , SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN ) \ - | P_Fld( DIV16_CK_SEL , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee + | P_Fld( DIV16_CK_SEL , SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CLRPLL3) , P_Fld( A_D->DQ_CA_OPEN , SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN ) \ - | P_Fld( DIV16_CK_SEL , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee + | P_Fld( DIV16_CK_SEL , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL )); } // vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld(1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n")); @@ -79,8 +79,8 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate) static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg) { - U8 TX_ARDQ_SERMODE=0; //DQ_P2S_RATIO - U8 TX_ARCA_SERMODE=0; //CA_P2S_RATIO + U8 TX_ARDQ_SERMODE=0; + U8 TX_ARCA_SERMODE=0; U8 ARDLL_SERMODE_B=0; U8 ARDLL_SERMODE_C=0; BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -99,7 +99,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld( TX_ARDQ_SERMODE , SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld( TX_ARDQ_SERMODE , SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1)); - //Justin confirm that DES_MODE -> Deserializer mode, while DQ_P2S_RATIO=16 setting 3 others 2. in fact ANA could support some other mode, Here is an propsal option + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld( (tr->DQ_P2S_RATIO == 16 ) ? 3 : 2 , SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1)); @@ -116,14 +116,14 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to switch (tr->DQ_AAMCK_DIV) { - case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; } //for DSC semi-open B1 has to set 2 and B0 don't care + case 0 : { ARDLL_SERMODE_B = (isLP4_DSC)?2:0; break; } case 2 : { ARDLL_SERMODE_B = 1; break; } case 4 : { ARDLL_SERMODE_B = 2; break; } case 8: { ARDLL_SERMODE_B = 3; break; } default: mcSHOW_ERR_MSG(("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV)); } vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0)); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));//TODO:check + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1)); switch (tr->CA_ADMCK_DIV) { @@ -136,13 +136,13 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), P_Fld(ARDLL_SERMODE_C , SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA)); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - //DQ SEMI-OPEN register control + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0 ) \ | P_Fld( tr->DQ_CA_OPEN , SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1 ) \ | P_Fld( tr->DQ_CA_OPEN , SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1 )); - //CA SEMI-OPEN register control + if(tr->CA_SEMI_OPEN == 0) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( 0 , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA ) \ @@ -154,7 +154,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to } else { - // @Darren, for DDR800semi + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6 , P_Fld( 1 , SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA ) \ | P_Fld( 1 , SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA ) \ @@ -163,17 +163,17 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to | P_Fld( 1 , SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN )); if(!isLP4_DSC) { - //CHA CA as master + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ); - //CHB CA as slave + vSetPHY2ChannelMapping(p, CHANNEL_B); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ); #if (CHANNEL_NUM>2) if (channel_num_auxadc > 2) { vSetPHY2ChannelMapping(p, CHANNEL_C); - //CHC CA as master + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ); - //CHD CA as slave + vSetPHY2ChannelMapping(p, CHANNEL_D); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3), 0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA ); } @@ -181,17 +181,17 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to } else { - //CHA CA as master + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 ); - //CHB CA as slave + vSetPHY2ChannelMapping(p, CHANNEL_B); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 ); #if (CHANNEL_NUM>2) if (channel_num_auxadc > 2) { vSetPHY2ChannelMapping(p, CHANNEL_C); - //CHC CA as master + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 ); - //CHD CA as slave + vSetPHY2ChannelMapping(p, CHANNEL_D); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3), 0, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 ); } @@ -201,21 +201,6 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to vSetPHY2ChannelMapping(p, CHANNEL_A); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); -//--------TODO ---20190721 WAITING DPHY KaiHsin & Alucary confirm this RG setting. -// if(a_cfg->DLL_ASYNC_EN == 1) -// { -// //CA as all master -// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); -// } else { -// DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); -// //CHA CA as master -// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); -// //CHB CA as slave -// vSetPHY2ChannelMapping(p, CHANNEL_B); -// vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld(0, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA )); -// vSetPHY2ChannelMapping(p, CHANNEL_A); -// DramcBroadcastOnOff(DRAMC_BROADCAST_ON); -// } } vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6) , P_Fld( tr->DQ_CA_OPEN , SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA )); @@ -236,9 +221,9 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n")); } -//========================== -//DLL config -//========================== + + + static void ANA_DLL_non_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) { U8 u1PDZone = (p->frequency >= 2133) ? 0x2 : 0x3; @@ -349,14 +334,14 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg) BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; if(p->frequency<=1600) { - u1Gain = 1;//checked by WL + u1Gain = 1; mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain)); } mcSHOW_DBG_MSG6((">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n")); - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL0) , P_Fld( 7+u1Gain , SHU_B0_DLL0_RG_ARDLL_GAIN_B0 ) \ | P_Fld( 7 , SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0 ) \ | P_Fld( 0 , SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 ) \ @@ -372,7 +357,7 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg) | P_Fld( 0 , SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 )); if (isLP4_DSC) { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL0) , P_Fld( 7+u1Gain , SHU_CA_DLL0_RG_ARDLL_GAIN_CA ) \ | P_Fld( 7 , SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA ) \ | P_Fld( 0 , SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA ) \ @@ -481,7 +466,7 @@ if (isLP4_DSC) } else { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL0) , P_Fld( 7+u1Gain , SHU_B1_DLL0_RG_ARDLL_GAIN_B1 ) \ | P_Fld( 7 , SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1 ) \ | P_Fld( 0 , SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 ) \ @@ -595,7 +580,7 @@ else static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_DVFS_CORE_T *tr) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI3) , P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 ) \ | P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 ) \ | P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 ) \ @@ -612,7 +597,7 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D | P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 ) \ | P_Fld( 0 , SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 )); - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI3) , P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 ) \ | P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 ) \ | P_Fld( !((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)), SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 ) \ @@ -630,7 +615,7 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D | P_Fld( 0 , SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 )); - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI3) , P_Fld( isLP4_DSC&&(!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN ) \ | P_Fld( (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN ) \ | P_Fld( (!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN))), SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN )); @@ -644,9 +629,9 @@ static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_D vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW ) \ | P_Fld( 0 , SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW )); } -//========================== -//ANA_TX_CONFIG -//========================== + + + static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -660,7 +645,7 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) | P_Fld(!(a_cfg->LP45_APHY_COMB_EN) , B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 ) \ | P_Fld(a_cfg->LP45_APHY_COMB_EN , B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 )); mcSHOW_DBG_MSG6(("<<<<<< [CONFIGURE PHASE]: ANA_TX\n")); - //enable TX OE + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2) , P_Fld(0 , B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 ) \ | P_Fld(0 , B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 ) \ | P_Fld(0 , B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 ) \ @@ -714,13 +699,13 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL),P_Fld(1, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)) ; vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARDQ_CTRL), P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ6_OE_TIE_EN_C0) \ - | P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ; //Sync MP setting WL C0 DQ6 and DQ7 is no use + | P_Fld(1, CA_TX_ARDQ_CTRL_RG_TX_ARDQ7_OE_TIE_EN_C0)) ; vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1) \ - | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ; //Sync MP setting WL EMCP: B1 CS1 and CKE is no use + | P_Fld(1, B1_TX_CKE_CTRL_RG_TX_ARCS1_OE_TIE_EN_B1)) ; } - //enable TX & reset + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3) , P_Fld(1 , CA_CMD3_RG_TX_ARCMD_EN ) \ | P_Fld(1 , CA_CMD3_RG_ARCMD_RESETB )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3) , P_Fld(1 , B0_DQ3_RG_ARDQ_RESETB_B0 ) \ @@ -733,7 +718,7 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - //ODTEN & DQS control + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld(isLP4_DSC , SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA ) \ | P_Fld(isLP4_DSC , SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA ) | P_Fld(0 , SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA ) @@ -767,28 +752,28 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ14) , P_Fld( 0 , SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1 ) \ | P_Fld( 0 , SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1 )); - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) \ | P_Fld(a_cfg->NEW_RANK_MODE, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)); if(!isLP4_DSC) { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \ | P_Fld(a_cfg->NEW_RANK_MODE, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \ | P_Fld(0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)); } else { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ2), P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) \ | P_Fld(0, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD2), P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) \ | P_Fld(a_cfg->NEW_RANK_MODE, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)); @@ -796,7 +781,7 @@ static void ANA_TX_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 grou #if SA_CONFIG_EN - // enable after runtime configs + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ2) , P_Fld( 0 , SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0 )); if(!isLP4_DSC) @@ -823,12 +808,12 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id) #if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION) RDQS_SE_EN = DFS(group_id)->data_rate<=1600 ? 1 : 0; #else - RDQS_SE_EN = 0; //TODO for LPDDR5 + RDQS_SE_EN = 0; #endif DQSIEN_MODE = DFS(group_id)->DQSIEN_MODE; NEW_RANK_MODE = A_T->NEW_RANK_MODE; - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10) , P_Fld( RDQS_SE_EN , SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0 ) \ | P_Fld(DQSIEN_MODE , SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0 ) \ | P_Fld(1 , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 ) \ @@ -838,7 +823,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id) | P_Fld(NEW_RANK_MODE , SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 ) ); if(isLP4_DSC){ - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10) , P_Fld( RDQS_SE_EN , SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA ) \ | P_Fld(DQSIEN_MODE , SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA ) \ | P_Fld(1 , SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA ) \ @@ -849,7 +834,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id) } else { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10) , P_Fld( RDQS_SE_EN , SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1 ) \ | P_Fld(DQSIEN_MODE , SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1 ) \ | P_Fld(1 , SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1 ) \ @@ -859,7 +844,7 @@ static void ANA_RX_shuffle_config(DRAMC_CTX_T *p,U8 group_id) | P_Fld(NEW_RANK_MODE , SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 )); } #if SA_CONFIG_EN - // enable after runtime configs + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10) , P_Fld( 0 , SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 )); if(isLP4_DSC){ @@ -885,7 +870,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5) , P_Fld( 1 , B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 ) \ @@ -898,7 +883,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3) , P_Fld( 1 , B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 ) \ | P_Fld( 1 , B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 )); - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5) , P_Fld( (!isLP4_DSC) , B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 ) \ @@ -911,7 +896,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3) , P_Fld( (!isLP4_DSC) , B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 ) \ | P_Fld( (!isLP4_DSC) , B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 )); - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), P_Fld(isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6) , P_Fld( 0 , CA_CMD6_RG_RX_ARCMD_DDR3_SEL ) \ @@ -924,7 +909,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN) \ | P_Fld(isLP4_DSC, CA_CMD3_RG_RX_ARCMD_SMT_EN)); - //RX reset + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 1 , CA_CMD9_RG_RX_ARCMD_STBEN_RESETB ) \ | P_Fld( 1 , CA_CMD9_RG_RX_ARCLK_STBEN_RESETB )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 ) \ @@ -932,16 +917,16 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 ) \ | P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 )); - //Justin confirm that: All set 1 for improving internal timing option + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8) , P_Fld( 1 , CA_CMD8_RG_RX_ARCLK_SER_RST_MODE )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8) , P_Fld( 1 , B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8) , P_Fld( 1 , B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 )); } -//============================================ -// RESET -//============================================ + + + void RESETB_PULL_DN(DRAMC_CTX_T *p) { mcSHOW_DBG_MSG6(("============ PULL DRAM RESETB DOWN ============\n")); @@ -957,9 +942,9 @@ void RESETB_PULL_DN(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11) , P_Fld( 0 , CA_CMD11_RG_TX_RRESETB_PULL_DN )); mcSHOW_DBG_MSG6(("========== PULL DRAM RESETB DOWN end =========\n")); } -//============================================ -// SUSPEND_OFF_control -//============================================ + + + static void SUSPEND_ON(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_LP_CTRL0) , P_Fld( 0 , B0_LP_CTRL0_RG_ARDMSUS_10_B0 )); @@ -968,9 +953,9 @@ static void SUSPEND_ON(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_LP_CTRL0) , P_Fld( 0 , CA_LP_CTRL0_RG_ARDMSUS_10_CA )); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } -//============================================ -// SPM_control -//============================================ + + + static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -1069,10 +1054,10 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) | P_Fld( 1 , CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL) \ | P_Fld( 1 , CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL) \ | P_Fld( 1 , CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC) \ - | P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL )); //use CA as DQ set 1 + | P_Fld( 0 , CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL )); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - REG_TRANSFER_T MS_SLV_LP_SEL_Reg;//TODO:check + REG_TRANSFER_T MS_SLV_LP_SEL_Reg; if (isLP4_DSC){ MS_SLV_LP_SEL_Reg.u4Addr = DDRPHY_REG_B1_LP_CTRL0; MS_SLV_LP_SEL_Reg.u4Fld = B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL; @@ -1106,7 +1091,7 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - //FOR DDR400 OPEN-LOOP MODE + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL9), P_Fld( 1 , MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN ) \ | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN ) \ | P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF ) \ @@ -1116,7 +1101,7 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) | P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF ) \ | P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON ) \ | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF )); -#if 0 // @Darren-, new APHY remove 45/135 phases +#if 0 | P_Fld( 1 , MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN ) \ | P_Fld( 1 , MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF ) \ | P_Fld( 0 , MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON ) \ @@ -1126,31 +1111,13 @@ static void SPM_control(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) static void DIG_DCM_nonshuffle_config(DRAMC_CTX_T *p) { - //RX DCM + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL), P_Fld(3 , MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY )); } static void DIG_PHY_SHU_MISC_CG_CTRL(DRAMC_CTX_T *p) { - //bit 0 : DPHY_NAO_GLUE_B0.mck_dq_cg_ctrl - //bit 1 : DPHY_NAO_GLUE_B1.mck_dq_cg_ctrl - //bit 2 : DPHY_NAO_GLUE_CA.mck_ca_cg_ctrl - //bit 4 : DPHY_NAO_GLUE_B0.rx_mck_dq_cg_ctrl - //bit 5 : DPHY_NAO_GLUE_B1.rx_mck_dq_cg_ctrl - //bit 6 : DPHY_NAO_GLUE_CA.rx_mck_ca_cg_ctrl - //bit [9 : 8] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle - //bit [11:10] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_dq - //bit [13:12] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_cmd - //bit [17:16] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b0 - //bit [19:18] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_tx_b1 - //bit [22:20] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_cmd - //bit [26:24] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b0 - //bit [30:28] : DPHY_TX_BRIDGE_GLUE.ddrphy_idle_rx_b1 - -// vIO32Write4B (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x333f3f00); -// //1. ignore NAO_GLUE cg ctrl, -// 2.00:ddrphy_idle/_ca/b0/b1 01: ddrphy_idle_shuopt 10: ddrphy_idle_shuopt_pinmux - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000);//rx_cmd_idle tie 1 others DCM control depend on CA B0 B1 independtly -- could save more power + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_CG_CTRL0), 0x33400000); } static void ANA_IMP_configure(DRAMC_CTX_T *p) @@ -1167,18 +1134,14 @@ static void ANA_IMP_configure(DRAMC_CTX_T *p) static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p) { - //OPENLOOP MODE. w_chg_mem_mck1x + if(A_D->DQ_CA_OPEN) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); mcDELAY_XNS(100); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); } - //mem_sel _____|------------------------------------ - //w_chg_mem ______________|------------|______________ - //BLCK __|---|___|---|____________|-|_|-|_|-|_|- - // |<- 26M ->|<- MUTE ->|<- MCK4X ->| - //before DLL enable switch feedback clock + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL) , P_Fld( 1 , MISC_CKMUX_SEL_R_PHYCTRLDCM ) \ | P_Fld( 1 , MISC_CKMUX_SEL_R_PHYCTRLMUX )); @@ -1186,12 +1149,11 @@ static void ANA_CLOCK_SWITCH(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_CLK_MEM_SEL ) \ | P_Fld( 1 , MISC_CG_CTRL0_W_CHG_MEM )); - mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + mcDELAY_XNS(100); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_W_CHG_MEM )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RG_FREERUN_MCK_CG )); - //after clock change, if OPEN LOOP MODE should change clock to 1x. bit7 is RG_dvfs_clk_mem_mck1x_sel if(A_D->DQ_CA_OPEN) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7)); @@ -1221,15 +1183,10 @@ void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id) DIG_PHY_SHU_MISC_CG_CTRL(p); ANA_CLK_DIV_config_setting(p,A_D,a_cfg); ANA_DLL_shuffle_Config(p,a_cfg); -// ANA_sequence_shuffle_colletion(p,&ana_core_p); } static void ANA_PHY_Config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg) { - //RESET DPM - //vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN), 32'h1000_0001 ); - -// SC_DPY_MODE_SW(PULL_UP); ANA_Config_nonshuffle(p,a_cfg); ANA_Config_shuffle(p,a_cfg,0); } @@ -1253,8 +1210,6 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1) , 1, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1 ); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , 1, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA ); - //ASVA 2-6 - //step1: CG high. --disable 8 phase clk output vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) , P_Fld( 1 , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 ) \ | P_Fld( 1 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2) , P_Fld( 1 , SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 ) \ @@ -1262,7 +1217,6 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2) , P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA ) \ | P_Fld( 1 , SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA )); - //CG vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) @@ -1291,12 +1245,11 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN) | P_Fld(0x1, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA)); - //step2:PLLGP_CK_SEL -- Initial no need it - //step3: PLLCK_EN disable - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 0 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2 + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 0 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld( 0 , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN ) \ | P_Fld( 0 , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN )); - //step4:MIDPI_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1) , P_Fld((!((tr->DQ_SEMI_OPEN)||(tr->DQ_CA_OPEN)))&&(!(tr->DQ_CKDIV4_EN)), SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0 ) \ | P_Fld((!(tr->DQ_SEMI_OPEN))&&(tr->DQ_CKDIV4_EN), SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0 ) \ | P_Fld( tr->PH8_DLY , SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0 )); @@ -1314,7 +1267,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) } - else// for DSC semi-open CHA B1 and CHB B1 is different + else { DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1) , P_Fld((!tr->DQ_CA_OPEN)&&(!(tr->CA_CKDIV4_EN)), SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1 ) \ @@ -1353,7 +1306,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - // for both EMCP and DSC semi-open CHA CA and CHB CA settings are needed + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1) , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA ) \ | P_Fld( tr->CA_CKDIV4_EN , SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA ) | P_Fld( tr->PH8_DLY , SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA )); @@ -1361,7 +1314,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_SHU_MIDPI_CTRL) , P_Fld( (!(tr->DQ_CA_OPEN))&&(!(tr->CA_CKDIV4_EN)), CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA ) \ | P_Fld( tr->CA_CKDIV4_EN , CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA )); - //step5:PI_RESETB + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0) , P_Fld( 0 , CA_DLL_ARPI0_RG_ARPI_RESETB_CA )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0) , P_Fld( 0 , B0_DLL_ARPI0_RG_ARPI_RESETB_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0) , P_Fld( 0 , B1_DLL_ARPI0_RG_ARPI_RESETB_B1 )); @@ -1369,12 +1322,11 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0) , P_Fld( 1 , CA_DLL_ARPI0_RG_ARPI_RESETB_CA )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0) , P_Fld( 1 , B0_DLL_ARPI0_RG_ARPI_RESETB_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0) , P_Fld( 1 , B1_DLL_ARPI0_RG_ARPI_RESETB_B1 )); - //step6: PLLCK_EN enable - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2 + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2) , P_Fld( 1 , PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN ) \ | P_Fld( 1 , PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN )); - //step7: release CG 8 Phase clk enable - //CG + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) | P_Fld(0x0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) @@ -1431,11 +1383,11 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T ALL_SLAVE_EN = a_cfg->ALL_SLAVE_EN; mcSHOW_DBG_MSG6(("[ANA_INIT] DLL >>>>>>>> \n")); - //step1: DLL_RESETB + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8) , P_Fld( 1 , CA_CMD8_RG_ARDLL_RESETB_CA )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8) , P_Fld( 1 , B0_DQ8_RG_ARDLL_RESETB_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ8) , P_Fld( 1 , B1_DQ8_RG_ARDLL_RESETB_B1 )); - //step2: master DLL_EN + if(ALL_SLAVE_EN == 1) { if (tr->DQ_SEMI_OPEN) @@ -1446,7 +1398,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T mcDELAY_XNS(300); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld( 0 , SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1) , P_Fld( 0 , SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1)); - mcDELAY_XNS(400); //2nd DLL > 77TMCK + mcDELAY_XNS(400); } else { @@ -1456,7 +1408,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T mcDELAY_XNS(300); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr) , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld)); - mcDELAY_XNS(400); //2nd DLL > 77TMCK + mcDELAY_XNS(400); } } else @@ -1466,47 +1418,42 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld)); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - mcDELAY_XNS(300); //1st DLL > 55 TMCK + mcDELAY_XNS(300); } else { DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld)); - mcDELAY_XNS(300); //1st DLL >55T MCK + mcDELAY_XNS(300); vSetPHY2ChannelMapping(p, CHANNEL_B); vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld)); #if (CHANNEL_NUM>2) if (channel_num_auxadc > 2) { vSetPHY2ChannelMapping(p, CHANNEL_C); vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld)); - mcDELAY_XNS(300); //1st DLL >55T MCK + mcDELAY_XNS(300); vSetPHY2ChannelMapping(p, CHANNEL_D); vIO32WriteFldMulti(DRAMC_REG_ADDR(MS_DLL_PHDET_EN_Reg.u4Addr) , P_Fld( 1 , MS_DLL_PHDET_EN_Reg.u4Fld)); } #endif - mcDELAY_XNS(300); //1st DLL >55T MCK + mcDELAY_XNS(300); vSetPHY2ChannelMapping(p, CHANNEL_A); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1) , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(SLV_DLL_PHDET_EN_Reg.u4Addr) , P_Fld(!(tr->DQ_SEMI_OPEN), SLV_DLL_PHDET_EN_Reg.u4Fld )); - mcDELAY_XNS(400); //2nd DLL > 77TMCK + mcDELAY_XNS(400); mcSHOW_DBG_MSG6(("[ANA_INIT] DLL <<<<<<<< \n")); } } -//shuffle register for ANA initial flow control -//It is not easy for initial sequence SA/DV coding --- same register for different group. need two different method to manage it -//1. for seqeunce -//2. for another shuffle group need to DMA to SRAM void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - //PLL - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); //refer to MISC_DVFSCTRL2 - //MIDPI + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2) , P_Fld( 1 , SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU )); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2) , P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 ) \ | P_Fld( 0 , SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 ) \ | P_Fld( tr->DQ_SEMI_OPEN , SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)); @@ -1550,24 +1497,20 @@ void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr) static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - /* Dynamic CKE to let HW disable CLK_TXD, avoiding CLK parking state violation during CKE high - * Note: BROADCAST is ON here - */ + CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ONE_CHANNEL); mcDELAY_US(1); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL) | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM)); - mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + mcDELAY_XNS(100); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM); - // @Darren, Fix 26M clock issue after DDR400 open loop mode (fail case: 26M/4) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 1 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); mcDELAY_XNS(100); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( 0 , MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1)); - //DLL Off vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), 0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0); if (!isLP4_DSC) { @@ -1584,7 +1527,6 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p) DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - //CG vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) @@ -1637,12 +1579,10 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p) | P_Fld(0x1, SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1)); } - //PLLCK - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); //refer to MISC_DVFSCTRL2 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2), 0, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), P_Fld(0, PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN) | P_Fld(0, PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN)); - //PLL vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0), 0, PHYPLL0_RG_RPHYPLL_EN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2), 0, PHYPLL2_RG_RPHYPLL_RESETB); @@ -1655,11 +1595,11 @@ static void TransferToSPM_Sequence(DRAMC_CTX_T *p) mcDELAY_XUS(20); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL), 0x1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_LPIF_FSM_CFG_1), - /* TBA set control mux in DV initial */ - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | // 0: DPM, 1: SPM - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | // 0: DPM, 1: SPM - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | // 0: DPM, 1: SPM - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND)); // 0: DPM, 1: SPM + + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND)); } static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg) @@ -1667,7 +1607,7 @@ static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_ mcSHOW_DBG_MSG6(("[ANA_INIT] flow start \n")); ANA_PLL_sequence(p); ANA_MIDPI_sequence(p,tr); - ANA_CLOCK_SWITCH(p); //clock switch supply correct FB clk. have to do this before DLL + ANA_CLOCK_SWITCH(p); ANA_DLL_sequence(p,tr,a_cfg); mcSHOW_DBG_MSG6(("[ANA_INIT] flow end \n")); } @@ -1676,7 +1616,7 @@ void ANA_init(DRAMC_CTX_T *p) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; #if (fcFOR_CHIP_ID == fc8195) - DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux; // 0: EMCP, 1: DSC, 2: MCP, 3:DSC_REV + DRAM_PINMUX DRAM_Pinmux = p->DRAMPinmux; #endif DRAMC_SUBSYS_PRE_CONFIG(p, &DV_p); @@ -1687,7 +1627,6 @@ void ANA_init(DRAMC_CTX_T *p) #endif vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL) , P_Fld( isLP4_DSC, MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL )); - //Disable CMD CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL); #if REPLACE_DFS_RG_MODE TransferToSPM_Sequence(p); @@ -1695,7 +1634,7 @@ void ANA_init(DRAMC_CTX_T *p) ANA_ClockOff_Sequence(p); ANA_PHY_Config(p,A_T); ANA_init_sequence(p,A_D,A_T); - //Enable CMD + CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL); LP4_single_end_DRAMC_post_config(p, M_LP4->LP4Y_EN); mcSHOW_DBG_MSG6(("[ANA_INIT] <<<<<<<<<<<<< \n")); diff --git a/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c b/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c index 95581e9e81..6d7f0476e1 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c +++ b/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c @@ -5,9 +5,6 @@ Gating_confg_T Gat_p; -//============================================ -// digital PHY config -//============================================ static void DIG_PHY_config(DRAMC_CTX_T *p) { #if ENABLE_PINMUX_FOR_RANK_SWAP @@ -43,7 +40,7 @@ static void DIG_PHY_config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFS_EMI_CLK) , P_Fld( 1 , MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( (!isLP4_DSC) , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 ));//TODO:check + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( (!isLP4_DSC) , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( isLP4_DSC , CA_CMD9_R_DMRXFIFO_STBENCMP_EN_CA )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld(RK_SWAP_EN, MISC_CTRL1_R_RK_PINMUXSWAP_EN )); @@ -52,21 +49,21 @@ static void DIG_PHY_config(DRAMC_CTX_T *p) if(A_T->NEW_RANK_MODE==0) { - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 4 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \ | P_Fld( 0 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 0 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 ));//TODO:check + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 0 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 )); if (isLP4_DSC) { - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 4 , CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA ) \ | P_Fld( 0 , CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 0 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA ));//TODO:check + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 0 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA )); } else { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 4 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \ | P_Fld( 0 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 0 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 )); @@ -74,24 +71,24 @@ static void DIG_PHY_config(DRAMC_CTX_T *p) } else { - //B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \ | P_Fld( 1 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 1 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 )); if (isLP4_DSC) { - //CA + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD9) , P_Fld( 0 , CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA ) \ | P_Fld( 1 , CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 1 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA ));//TODO:check + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD10) , P_Fld( 1 , CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA )); } else { - //B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \ | P_Fld( 1 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 1 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 ));//TODO:check + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 1 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 )); } } @@ -109,11 +106,11 @@ static void DIG_PHY_config(DRAMC_CTX_T *p) static void GATING_MODE_CFG(Gating_confg_T *tr) { tr->GAT_TRACK_EN = ((A_D->DQ_SEMI_OPEN == 1)||(A_D->DQ_CA_OPEN==1))?0:1; - tr->RX_GATING_MODE = 2; //fix 7UI mode under LPDDR4 - tr->RX_GATING_TRACK_MODE = 2; //fix FIFO mode under LPDDR4 - tr->PICG_EARLY_EN = 1; //fix under LPDDR4, if LPDDR5 have to set 1 - tr->SELPH_MODE = 1; //random inside {0,1} //for improve APHY XRTR2R. NEW_APHY MODE with 1. - tr->VALID_LAT_VALUE = 1; //random inside {0,1} + tr->RX_GATING_MODE = 2; + tr->RX_GATING_TRACK_MODE = 2; + tr->PICG_EARLY_EN = 1; + tr->SELPH_MODE = 1; + tr->VALID_LAT_VALUE = 1; mcSHOW_DBG_MSG6(("============================================================== \n")); mcSHOW_DBG_MSG6(("Gating Mode config\n" )); @@ -132,9 +129,9 @@ static void GATING_MODE_CFG(Gating_confg_T *tr) mcSHOW_DBG_MSG6(("============================================================== \n")); } -//====================================== -//gating widnow mode -//====================================== + + + static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -155,12 +152,9 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 1 , MISC_STBCAL2_STB_PICG_EARLY_1T_EN )); } - //================================ - //gating Mode config - //================================ switch (gat_c->RX_GATING_MODE) { - //Pulse Mode + case 0: { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); @@ -170,7 +164,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( 0 , MISC_SHU_STBCAL_DQSIEN_BURST_MODE )); break; } - // Burst Mode (8UI) + case 1: { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); @@ -179,7 +173,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)); break; } - // Burst Mode (7UI) + case 2: { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); @@ -189,7 +183,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_DQSIEN_7UI_EN )); break; } - // Oringinal Burst + case 3: { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 )); @@ -205,15 +199,12 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) } } - //================================ - //Gating tracking Mode config - //================================ switch (gat_c->RX_GATING_TRACK_MODE) { - //Valid DLY Mode + case 0: { - //TODO SHU1_DQSG if -like mode should set STB_UPDMASKCYC = 0 STB_UPDMASK_EN=0 others STB_UPDMASKCYC=9 STB_UPDMASK_EN=1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \ | P_Fld( 1 , MISC_STBCAL_PICHGBLOCK_NORD ) \ | P_Fld( 0 , MISC_STBCAL_REFUICHG ) \ @@ -231,7 +222,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) | P_Fld( 2 , MISC_CTRL0_R_DMVALID_DLY ) \ | P_Fld( 1 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \ | P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \ - | P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); //TODO + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \ | P_Fld( 0 , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 )); @@ -246,7 +237,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) } break; } - //-like Mode + case 1: { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 0 , MISC_STBCAL_STB_DQIEN_IG ) \ @@ -281,7 +272,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) } break; } - //FIFO Mode + case 2: { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \ @@ -301,7 +292,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) | P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY ) \ | P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \ | P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \ - | P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); // @Darren, func no use sync MP settings from HJ + | P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \ | P_Fld( 0+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 )); @@ -341,7 +332,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) | P_Fld( 0 , MISC_STBCAL2_STB_GERR_RST ) \ | P_Fld( 1 , MISC_STBCAL2_STB_GERR_B01 ) \ | P_Fld( 0 , MISC_STBCAL2_STB_GERR_B23 )); - //PICG_MODE only support new mode so here fix 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), P_Fld(1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), P_Fld(1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT )); @@ -356,17 +347,17 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c) static void RX_INTPUT_Config(DRAMC_CTX_T *p) { - U8 VALID_LAT = 1;// TODO inside {0,1} - U8 RDSEL_LAT = 2;// TODO alywas VALID_LAT+1; + U8 VALID_LAT = 1; + U8 RDSEL_LAT = 2; U8 dq_min = 0; U8 dq_max = 0xff; U8 scale = 3; U8 threadhold = 0; U32 dqs_min = 0; U32 dqs_max = 0x1ff; - U8 RX_force_upd = 0; //TODO - U8 F_LEADLAG = 0; //TODO - U8 RG_MODE_EN = 0; //TODO + U8 RX_force_upd = 0; + U8 F_LEADLAG = 0; + U8 RG_MODE_EN = 0; U8 irank = 0; U8 backup_rank = 0; BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -404,7 +395,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p) for(irank = RANK_0; irank < p->support_rank_num; irank++) { vSetRank(p, irank); - //RK0--B0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS3 ) , P_Fld( dq_min , RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0 ) \ | P_Fld( dq_max , RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS4 ) , P_Fld( dqs_min , RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0 ) \ @@ -421,7 +412,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p) | P_Fld( threadhold , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD )); - //RK0--B1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS3 ) , P_Fld( dq_min , RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1 ) \ | P_Fld( dq_max , RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS4 ) , P_Fld( dqs_min , RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1 ) \ @@ -440,7 +431,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p) vSetRank(p, backup_rank); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 ) , 0xffffffff , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL ); //TODO + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 ) , 0xffffffff , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL ); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1 ) , P_Fld( F_LEADLAG , B0_RXDVS1_F_LEADLAG_TRACK_B0 )); @@ -481,13 +472,13 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p) } vSetRank(p, backup_rank); - //Enable RX input delay tracking.. - //TODO notice here if SA should not enbale it before RX perbit calibration + + if (RG_MODE_EN == 1) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 1 , MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN )); } else { -// `TBA_TOP.dvfs_spm_vif.sc_dphy_reserved[1:0] = 2'b11; //TODO + } mcSHOW_DBG_MSG6(("[RX_INPUT] configuration <<<<< \n")); @@ -495,9 +486,9 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p) static void DDRPHY_PICG_Config(DRAMC_CTX_T *p) { - U8 PICG_MODE = 1; // only support new Mode under + U8 PICG_MODE = 1; U8 MISC_CG_EN = 1; - U8 MISC_CG_REVERSE_DEFAULT_ON = 0; //for default CG enable. + U8 MISC_CG_REVERSE_DEFAULT_ON = 0; mcSHOW_DBG_MSG6(("Enter into PICG configuration >>>> \n")); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4) , P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_MPDIV_CG ) \ @@ -512,7 +503,7 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p) | P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQS_OPT ) \ | P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQ_OPT )); - //Notice here: MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE = 1 will leading other_shuffle_group before register settle down latch ->error. can not set to 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE ) \ | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE ) \ | P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE ) \ @@ -536,8 +527,8 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p) | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_PI_DCM_EN ) \ | P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_CA_PI_DCM_EN )); - //defualt DCM enable, if we wanner to test CG enable, modified default CG condition. - //disable DCM.--- I think just for debug + + if(MISC_CG_REVERSE_DEFAULT_ON == 1) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_CG_SET0) , P_Fld( 1 , RX_CG_SET0_RDATCKAR ) \ @@ -565,7 +556,7 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p) DramcBroadcastOnOff(DRAMC_BROADCAST_ON); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1) , P_Fld( 1 , MISC_DUTYSCAN1_EYESCAN_DQS_OPT )); - //TODO -- for DPHY shuffle RG have to set to different Group into SRAM or not.--here just conf0 but not all frequency group + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8) , P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 ) \ | P_Fld( 1 , SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0 ) \ | P_Fld( 1 , SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 ) \ @@ -610,19 +601,19 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p) static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) { - U8 RD2MRR_EXTEND_EN = 1; // for fix Samsung RD2MRR seamless error, If the samsung fix that bug, this could set 0 + U8 RD2MRR_EXTEND_EN = 1; U8 EBG_EN = 0 ; - U8 TMRRI_MODE = 1; // !!!Notice here: 0: Old Mode, 1: New Mode --- FIX NEW MODE. Pertrus not support old mode anymore + U8 TMRRI_MODE = 1; U8 NOBLOCKALE_EN = 1; U8 RUNTIME_MRR = 1; - //pre configuration calculate + if(TMRRI_MODE == 1) { NOBLOCKALE_EN = 1; RUNTIME_MRR = 1; } else { - //TODO + mcSHOW_DBG_MSG6(("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it.")); } @@ -634,7 +625,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0) , P_Fld( 1 , DDRCOMMON0_BK8EN ) \ | P_Fld( LPDDR5_EN_S , DDRCOMMON0_LPDDR5EN ) \ | P_Fld( LPDDR4_EN_S , DDRCOMMON0_LPDDR4EN ) \ - | P_Fld( 0 , DDRCOMMON0_TRCDEARLY )); //if LPDDR5 set1 HEFF mode ACT -> R/W delay-1 + | P_Fld( 0 , DDRCOMMON0_TRCDEARLY )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 0 , RX_SET0_DM4TO1MODE )); @@ -769,7 +760,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) | P_Fld( TMRRI_MODE , SCSMCTRL_SC_PG_UPD_OPT )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1) , P_Fld( 0x1a , SHUCTRL1_FC_PRDCNT )); //TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1) , P_Fld( 0x1a , SHUCTRL1_FC_PRDCNT )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFPEND1) , P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH0 ) \ | P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH1 ) \ @@ -789,7 +780,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_OE_DOWNGRADE )); } - //@Jouling, UI reloade path is updated. (DQSOSCR_SREF_TXUI_RELOAD_OPT) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR) , P_Fld( 0 , DQSOSCR_SREF_TXUI_RELOAD_OPT ) \ | P_Fld( 1 , DQSOSCR_SREF_TXPI_RELOAD_OPT )); @@ -805,7 +796,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT2 ) \ | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT1 ) \ | P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT0 )); - //Byte Mode choose + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_0] , RK_DQSOSC_RK0_BYTE_MODE )); vSetRank(p, RANK_1); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_1] , RK_DQSOSC_RK0_BYTE_MODE )); @@ -814,7 +805,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0) , P_Fld( 0 , TX_TRACKING_SET0_TX_TRACKING_OPT )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0) , P_Fld( 1 , TX_CG_SET0_SELPH_4LCG_DIS )); - //DVFS support SRAM_EN only + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), P_Fld(DV_p.SRAM_EN, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1) , P_Fld( 1 , SWCMD_CTRL1_WRFIFO_MODE2 )); @@ -826,14 +817,14 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 1 , RX_SET0_PRE_DLE_VLD_OPT ) \ | P_Fld( 7 , RX_SET0_DATLAT_PDLE_TH )); - //TODO SRAM DPM control - // @Darren, sync MP settings from Joe (APB will be available when SRAM DMA access) + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0) , P_Fld( 1 , MISC_SRAM_DMA0_PENABLE_LAT_WR ) \ | P_Fld( 1 , MISC_SRAM_DMA0_KEEP_APB_ARB_ENA ) \ | P_Fld( 1 , MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_MCLK_DIV), P_Fld( 1 , SSPM_MCLK_DIV_MCLK_DCM_EN )); - //Indivial random sync + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL1), 0xFFFFFFFF); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL4), 0xFFFFFFFF); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7), 0xFFFFFFFF); @@ -881,8 +872,8 @@ static void IO_Release(DRAMC_CTX_T *p) | P_Fld( 0 , B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 ) \ | P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 ) \ | P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 )); - //for dram spec CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA will help to fix CKE=0 before for meet 10ns tINIT2 - //Assert DRAM reset PIN + + #if !SA_CONFIG_EN vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDA_RRESETB_I )); #endif @@ -891,9 +882,9 @@ static void IO_Release(DRAMC_CTX_T *p) static void DVFS_PRE_config(DRAMC_CTX_T *p) { #if (fcFOR_CHIP_ID == fc8195) - U32 MCP_EN = 0; //remove for MCP timing issue + U32 MCP_EN = 0; #else - U32 MCP_EN = 1; //for MCP should adjust some setting between CHs (A-B/C-D) + U32 MCP_EN = 1; #endif U32 REF_104M_EN = 1; BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -904,21 +895,21 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p) | P_Fld( 0 , DVFS_CTRL0_DVFS_SYNC_MASK ) \ | P_Fld( 1 , DVFS_CTRL0_MR13_SHU_EN ) \ | P_Fld( 1 , DVFS_CTRL0_HWSET_WLRL ) \ - | P_Fld( 0 , DVFS_CTRL0_MRWWOPRA )); //Have to fix 0, 1 with bug (some bank without precharge) - //for DVFS sync - vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 0 , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL ));//SPM mode TODO should random 0 for SPM mode default + | P_Fld( 0 , DVFS_CTRL0_MRWWOPRA )); + + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 0 , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL )); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0 ) , P_Fld( 0 , MISC_SRAM_DMA0_DMA_TIMER_EN )); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA1 ) , P_Fld( 0x1ffff , MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN )); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL7 ) , P_Fld( 1 , MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL )); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld( 1 , MISC_DVFSCTL_R_DVFS_PICG_POSTPONE ) \ | P_Fld( 1 , MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT )); - //for channel balance + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2) , P_Fld( 0 , MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION ) \ | P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL )); - //Could be randomed + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0 ) , P_Fld( 0 , DVFS_CTRL0_DVFS_CKE_OPT ) \ | P_Fld( 1 , DVFS_CTRL0_SCARB_PRI_OPT )); - //here is a flow??--TODO + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 1 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK ) \ | P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK ) \ | P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK ) \ @@ -933,7 +924,7 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p) | P_Fld( 1 , MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN )); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 0x10 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK)); - //flow end?? + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT )\ | P_Fld( 1 , DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT )); @@ -945,8 +936,8 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( REF_104M_EN , MISC_CKMUX_SEL_RG_52M_104M_SEL )); - //notice here: - //*SHU_PHDET_SPM_EN = 1 means during DFS period as master. 2 means slave. + + U32 MS_DLL_PHDET_FLD, SLV_DLL_PHDET_FLD; if (!isLP4_DSC) { @@ -1035,12 +1026,12 @@ void DIG_STATIC_SETTING(DRAMC_CTX_T *p) GATING_MODE_CFG(&Gat_p); DPHY_GAT_TRACK_Config(p,&Gat_p); DRAMC_COMMON_Config(p); - #if 1//!SA_CONFIG_EN - DVFS_PRE_config(p);//for DVFS initial config.-- bring-up no need this code. but DVFS will need this + #if 1 + DVFS_PRE_config(p); #endif DDRPHY_PICG_Config(p); IO_Release(p); - RX_INTPUT_Config(p);//TODO dummy write trigger + RX_INTPUT_Config(p); } #if FOR_DV_SIMULATION_USED diff --git a/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c b/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c index 1dfd9676b2..04656a05fa 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c +++ b/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c @@ -2,13 +2,7 @@ #include "dramc_dv_init.h" -//==================================== -//TX CA delay configuration -//------------------------------------ -//Notice: -//TX config with shuffle register with all data_rate the same -//if under real IC , need to banlance the PI/Dline calibrated result -//==================================== + static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id) { mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id)); @@ -17,7 +11,7 @@ static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id) u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; u8 TX_UI; - TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; //TODO -- LPDDR5 need confirm + TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; vSetPHY2ChannelMapping(p, ch_id); @@ -93,18 +87,12 @@ static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id) mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id)); } -//==================================== -//Impdance configuration -//------------------------------------ -//Notice: -//ANA result depend on calibration -//==================================== static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id) { mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id)); U8 IPM_ODT_EN; - U8 CHKCYCLE = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking - U8 TXDLY_CMD = 8; //Need algrithm support .. RL . TODO + U8 CHKCYCLE = 7; + U8 TXDLY_CMD = 8; U8 backup_ch_id = p->channel; u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; vSetPHY2ChannelMapping(p, ch_id); @@ -134,18 +122,13 @@ static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id) mcSHOW_DBG_MSG6(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id)); } -//==================================== -//RX input delay configuration by mode choose -//------------------------------------ -//Notice: -// -//==================================== + static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id) { - U8 PERBYTE_TRACK_EN = 1;//TODO - U8 DQM_TRACK_EN = 0;//TODO --following RD DBI - U8 DQM_FLOW_DQ_SEL = 3;//TODO - U8 RX_force_upd = 0;//TODO + U8 PERBYTE_TRACK_EN = 1; + U8 DQM_TRACK_EN = 0; + U8 DQM_FLOW_DQ_SEL = 3; + U8 RX_force_upd = 0; U8 backup_ch_id = p->channel; u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; @@ -206,20 +189,14 @@ static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT) } #endif -//==================================== -// MISC shuffle register fit -//------------------------------------ -//Notice: -// MISC shuffle reigster should be fixed -//==================================== static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) { U8 PICG_MODE = 1; - U8 LP5_HEFF = 0;//TODO - U8 LP5WRAPEN = 1;//Could random 1bit + U8 LP5_HEFF = 0; + U8 LP5WRAPEN = 1; U8 DQSIEN_DQSSTB_MODE=0; U8 irank = 0; - U8 LP5_CASMODE = 1; //TODO Impact AC timing 1,2,3 three mode support 1:Low Power; 2:Low Freq; 3:High Eff; + U8 LP5_CASMODE = 1; U8 WCKDUAL = 0; U8 NEW_RANK_MODE = 1; U8 DUALSCHEN = 1; @@ -274,7 +251,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) | P_Fld( (A_D->DQ_P2S_RATIO==8) , SHU_COMMON0_FREQDIV4 ) \ | P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_FDIV2 ) \ | P_Fld( LPDDR4_EN_S , SHU_COMMON0_BC4OTF ) \ - | P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN ));//TODO + | P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN )); if(LPDDR5_EN_S == 1) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( (A_D->DQ_P2S_RATIO==16) , SHU_COMMON0_FREQDIV8 ) \ @@ -285,8 +262,8 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) | P_Fld( LP5WRAPEN , SHU_COMMON0_LP5WRAPEN ) \ | P_Fld( LP5_HEFF , SHU_COMMON0_LP5HEFF_MODE )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL) , P_Fld( WCKDUAL , SHU_WCKCTRL_WCKDUAL )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));//TODO - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN ));//TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN )); } vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIMING_CONF), P_Fld( 1 , SHU_ACTIMING_CONF_TREFBWIG ) \ @@ -300,24 +277,24 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MATYPE) , P_Fld( 2 , SHU_MATYPE_MATYPE )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCHEDULER) , P_Fld( DUALSCHEN , SHU_SCHEDULER_DUALSCHEN )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_WPRE2T )); - //TODO SHU_TX_SET0_WPST1P5T OVER3200 DRAM spec need 1 but in TBA should random - //OE_EXT2UI strange rule.--TODO + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0) , P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_TX_SET0_WDATRGO ) \ | P_Fld( (DFS(group_id)->data_rate>=3200) , SHU_TX_SET0_WPST1P5T ) \ | P_Fld( DQOE_OPT , SHU_TX_SET0_DQOE_OPT ) \ | P_Fld( DQOE_CNT , SHU_TX_SET0_DQOE_CNT ) \ | P_Fld( LPDDR5_EN_S , SHU_TX_SET0_OE_EXT2UI ) \ - | P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL )); //TODO + | P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL1), P_Fld( 0x30 , MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO) \ | P_Fld( 1 , MISC_SHU_STBCAL1_STB_UPDMASK_EN ) \ | P_Fld( 9 , MISC_SHU_STBCAL1_STB_UPDMASKCYC ) \ - | P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); //TODO + | P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STBCALEN ) \ | P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STB_SELPHCALEN ) \ - | P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); //TODO + | P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); + - //@Darren, NOTE: Fix gating error or fifo mismatch => DMSTBLAT date_rate=1866 >= 3 : 1 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( (((Gat_p.GAT_TRACK_EN)&&(DFS(group_id)->data_rate>=1866))?(2+Gat_p.VALID_LAT_VALUE):(0+Gat_p.VALID_LAT_VALUE)) , MISC_SHU_STBCAL_DMSTBLAT ) \ | P_Fld( 1 , MISC_SHU_STBCAL_PICGLAT ) \ | P_Fld( 1 , MISC_SHU_STBCAL_DQSG_MODE ) \ @@ -333,7 +310,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) } vSetRank(p, backup_rank); - //RODT offset TODO + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN ) \ | P_Fld( 0 , MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE ) \ | P_Fld( (NEW_RANK_MODE)?1:PICG_MODE , MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE ) \ @@ -342,8 +319,8 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) | P_Fld( ((A_D->DQ_P2S_RATIO == 4)?1:4) , MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET ) \ | P_Fld( ((A_D->DQ_P2S_RATIO == 16)?19:((A_D->DQ_P2S_RATIO == 8)?13:10)) , MISC_SHU_RODTENSTB_RODTENSTB_EXT )); - //[SV] //SHL, fix RODT rd_period low 1T issue - // @Darren, confirm MP settings w/ Chau-Wei Wang (Jason) + + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?1:0) , MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?2:1) , MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD )); @@ -397,26 +374,26 @@ static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id) mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_EN ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ONCE ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_1RANK ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN ) \ - | P_Fld( 0 /*@Darren, sync MP settings by YT (DFS(group_id)->data_rate>=3733)*/ , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \ + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE ) \ | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK ) \ - | P_Fld( 0 /*@Jimmy, sync MP settings by YT*/ , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE )); + | P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE )); vSetPHY2ChannelMapping(p, backup_ch_id); p->ShuRGAccessIdx = backup_ShuRGAccessIdx; @@ -425,8 +402,8 @@ static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id) static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id) { - U8 RD_DBI_EN = 1;//TODO - U8 WR_DBI_EN = 1;//TODO + U8 RD_DBI_EN = 1; + U8 WR_DBI_EN = 1; U8 backup_ch_id = p->channel; u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; @@ -456,7 +433,7 @@ static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id) mcSHOW_DBG_MSG6(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n", group_id)); } -//TODO LPDDR5 + static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id) { U8 backup_ch_id = p->channel; @@ -476,7 +453,7 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id) LP4_DRAM_config (DFS(group_id)->data_rate,&LP4_temp); - HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); //DMI default enable + HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6); HWSET_MR2_OP_Value = ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7); } else { @@ -494,13 +471,6 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id) } -//================================================= -//Jump ratio calculate and setting -//------------------------------------------------ -//notice: 400 800 not support tracking TODO -// should confirm it with DQ_SEMI_OPEN =1 or not but not data_rate as condition -// -//================================================ #if 0 void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id) { @@ -515,19 +485,17 @@ void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id) mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id)); for(tar = 0; tar<DFS_GROUP_NUM;tar++) { - if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking + if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) { result[tar] = 0; } else { - result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup + result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); } mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar])); } - //============================= - //setting - //============================= + p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET0), P_Fld( result[0] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) \ @@ -557,12 +525,6 @@ static void DIG_CONFIG_DVFS_DEPENDENCE(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) | P_Fld( 0 , MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL )); } -//==================================== -// Digital shuffle configuration entry -//------------------------------------ -//Notice: -// -//==================================== void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) { DIG_CONFIG_SHUF_ALG_TXCA(p,ch_id,group_id); @@ -581,12 +543,12 @@ static void OTHER_GP_INIT(DRAMC_CTX_T *p,U32 ch_id, U32 group_id) U8 backup_ch_id = p->channel; U8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx; - //notice here. Replace the A_D A_T with new frequency auto-generation + ANA_TOP_FUNCTION_CFG(A_T,DFS(group_id)->data_rate); ANA_CLK_DIV_config(A_D,DFS(group_id)); p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1; - ANA_sequence_shuffle_colletion(p,A_D);//these RG will be set during flow,but for DV another GP should be set directly + ANA_sequence_shuffle_colletion(p,A_D); ANA_Config_shuffle(p,A_T,group_id); DIG_CONFIG_SHUF(p,ch_id,group_id); vSetPHY2ChannelMapping(p, backup_ch_id); diff --git a/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c b/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c index 98cd138125..4e27ef6033 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c +++ b/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c @@ -13,11 +13,6 @@ DRAMC_SUBSYS_CONFIG_T DV_p; void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate) { - // tr-> DLL_ASYNC_EN = 0 ; //from DV random - // tr-> NEW_RANK_MODE = 1 ; //from DV random - // tr-> DLL_IDLE_MODE = 1 ; //from DV random - // tr-> LP45_APHY_COMB_EN= 1 ; //from DV define - // tr-> NEW_8X_MODE = 1 ; tr->ALL_SLAVE_EN = (data_rate <= 1866)?1:0; @@ -46,22 +41,22 @@ void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate) void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs) { U32 SEMI_OPEN_FMIN = 300; - U32 SEMI_OPEN_FMAX = 500; //lp4 600 + U32 SEMI_OPEN_FMAX = 500; U32 PI_FMIN = 600; U32 DQ_PICK; - U32 CA_PICK; //U - U32 CA_MCKIO; //S - U32 MCKIO_SEMI; //Q + U32 CA_PICK; + U32 CA_MCKIO; + U32 MCKIO_SEMI; U16 data_rate; data_rate = dfs->data_rate; tr->DQ_P2S_RATIO = dfs->DQ_P2S_RATIO; tr->CKR = dfs->CKR; - //tr->CA_P2S_RATIO + tr->CA_P2S_RATIO = tr->DQ_P2S_RATIO/tr->CKR; - //tr->DQ_CA_OPEN + tr->DQ_CA_OPEN = ( data_rate < (SEMI_OPEN_FMIN * 2) ) ? 1 : 0; tr->DQ_SEMI_OPEN = ( data_rate/2 < PI_FMIN ) ? (1-tr->DQ_CA_OPEN) : ((data_rate <= SEMI_OPEN_FMAX*2) ? (1-tr->DQ_CA_OPEN) : 0); tr->CA_SEMI_OPEN = (( data_rate/(tr->CKR*2) < PI_FMIN ) ? ((data_rate/(tr->CKR*2) > SEMI_OPEN_FMAX) ? 0 : (((tr->CA_P2S_RATIO>2)||(tr->DQ_SEMI_OPEN))*(1-tr->DQ_CA_OPEN))) : tr->DQ_SEMI_OPEN); @@ -79,7 +74,7 @@ void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs) #if SA_CONFIG_EN if(LPDDR4_EN_S) { - // @Darren, for LP4 8PH Delay + if (data_rate <= 1866) tr->PH8_DLY = 0; else if (data_rate <= 2400) @@ -99,28 +94,28 @@ void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs) MCKIO_SEMI = (tr->DQ_SEMI_OPEN * tr->CA_SEMI_OPEN * (data_rate/2)) + (1-tr->DQ_SEMI_OPEN) * tr->CA_SEMI_OPEN * CA_MCKIO; - tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; //need to be improved + tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; tr->DQ_AAMCK_DIV = (tr->DQ_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/2)*(1-tr->DQ_SEMI_OPEN)) : DONT_CARE_VALUE; tr->CA_AAMCK_DIV = (tr->CA_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/(2*tr->CKR))*(1+tr->CA_FULL_RATE)) : DONT_CARE_VALUE; - tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); //need to be improved - //tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; //for Alucary confirm that 'interface timing' sign NOT OK. + tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); + //tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; tr->DQ_TRACK_CA_EN = 0 ; tr->PLL_FREQ = ((DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) > (CA_PICK*2*(tr->CA_CKDIV4_EN+1))) ? (DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) : (CA_PICK*2*(tr->CA_CKDIV4_EN+1)); #if SA_CONFIG_EN //de-sense if(data_rate==2400) - tr->PLL_FREQ = 2366; //DDR2366 + tr->PLL_FREQ = 2366; else if(data_rate==1200) - tr->PLL_FREQ = 2288; //DDR1144 + tr->PLL_FREQ = 2288; else if(data_rate==3200 || data_rate==1600) - tr->PLL_FREQ = 3068; //DDR3068 DDR1534 + tr->PLL_FREQ = 3068; else if(data_rate==800) - tr->PLL_FREQ = 3016; //DDR754 + tr->PLL_FREQ = 3016; else if(data_rate==400) - tr->PLL_FREQ = 1600; //DDR400 1600/div4 + tr->PLL_FREQ = 1600; #endif - tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use + tr->DQ_UI_PI_RATIO = 32; tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32; mcSHOW_DBG_MSG6(("=================================== \n")); @@ -211,17 +206,17 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr) tr->lp4_init->EX_ROW_EN[1] = p->u110GBEn[RANK_1] ; tr->lp4_init->BYTE_MODE[0] = 0 ; tr->lp4_init->BYTE_MODE[1] = 0 ; - tr->lp4_init->LP4Y_EN = 0;//DUT_p.LP4Y_EN ; - tr->lp4_init->WR_PST = 1;//DUT_p.LP4_WR_PST ; - tr->lp4_init->OTF = 1;//DUT_p.LP4_OTF ; - tr->a_cfg->NEW_8X_MODE = 1;//DUT_p.NEW_8X_MODE ; + tr->lp4_init->LP4Y_EN = 0; + tr->lp4_init->WR_PST = 1; + tr->lp4_init->OTF = 1; + tr->a_cfg->NEW_8X_MODE = 1; tr->a_cfg->LP45_APHY_COMB_EN = 1 ; - tr->a_cfg->DLL_IDLE_MODE = 1;//DUT_p.DLL_IDLE_MODE ; - tr->a_cfg->NEW_RANK_MODE = 1;//DUT_p.NEW_RANK_MODE ; - tr->a_cfg->DLL_ASYNC_EN = 0;//DUT_p.DLL_ASYNC_EN ; - tr->MD32_EN = 0;//DUT_p.MD32_EN ; - tr->SRAM_EN = 1;//DUT_p.SRAM_EN ; - tr->GP_NUM = 10;//DUT_p.GP_NUM ; + tr->a_cfg->DLL_IDLE_MODE = 1; + tr->a_cfg->NEW_RANK_MODE = 1; + tr->a_cfg->DLL_ASYNC_EN = 0; + tr->MD32_EN = 0; + tr->SRAM_EN = 1; + tr->GP_NUM = 10; if(p->freq_sel==LP4_DDR4266) { @@ -261,22 +256,12 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr) } #endif -//============================================== -//Oterwise, SA should rebuild Top configuration. -//============================================== + LP4_DRAM_config(tr->DFS_GP[0]->data_rate,tr->lp4_init); } - //TODO for LPDDR5 - //data_rate DQ_P2S_RATIO - //[4800:6400] 16 - //[1600:4800) 8 - //[400 :1600] 4 - //========================= - //data_rate CKR - //[3733:6400] 4 - //[400 :3733) 2 + ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate); ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]); diff --git a/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c b/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c index a537e87952..89978d4fcb 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c +++ b/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c @@ -2,18 +2,18 @@ #include "dramc_dv_init.h" -//DRAM LP4 initial configuration + void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr) { - tr->BYTE_MODE[0] = 0;//TODO - tr->BYTE_MODE[1] = 0;//TODO -#if 0 // @Darren, remove it + tr->BYTE_MODE[0] = 0; + tr->BYTE_MODE[1] = 0; +#if 0 #if SA_CONFIG_EN - tr->EX_ROW_EN[0] = 0;//TODO - tr->EX_ROW_EN[1] = 0;//TODO + tr->EX_ROW_EN[0] = 0; + tr->EX_ROW_EN[1] = 0; #else - tr->EX_ROW_EN[0] = 1;//TODO - tr->EX_ROW_EN[1] = 0;//TODO + tr->EX_ROW_EN[0] = 1; + tr->EX_ROW_EN[1] = 0; #endif #endif tr->MR_WL = LP4_DRAM_INIT_RLWL_MRfield_config(data_rate); @@ -22,7 +22,7 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr) tr->RPST = 0; tr->RD_PRE = 0; tr->WR_PRE = 1; - tr->WR_PST = (data_rate>=2667)?1:0; //TODO + tr->WR_PST = (data_rate>=2667)?1:0; #if SA_CONFIG_EN tr->DBI_WR = 0; tr->DBI_RD = 0; @@ -33,7 +33,7 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr) // tr->DMI = 1; tr->OTF = 1; #if (ENABLE_LP4Y_DFS && LP4Y_BACKUP_SOLUTION) - tr->LP4Y_EN = (data_rate>=1866)?0:1; //TODO, @Darren for LP4Y + tr->LP4Y_EN = (data_rate>=1866)?0:1; #else tr->LP4Y_EN = 0; #endif @@ -60,7 +60,7 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr) mcSHOW_DBG_MSG2(("OTF = 0x%1x\n",tr->OTF )); mcSHOW_DBG_MSG2(("=================================== \n")); } -//LP4 dram initial ModeRegister setting + U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate) { U8 MR2_RLWL; diff --git a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c index f8db890bed..db551fef8a 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c +++ b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c @@ -25,12 +25,12 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_ return u4reg_addr; } - if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register + if (u4RegType >= 2 && u4RegType <= 3) { if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR) eShu = 0; } - else if (u4RegType >= 6 && u4RegType <= 7)// ChA/B Dramc AO Register + else if (u4RegType >= 6 && u4RegType <= 7) { if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR) eShu = 0; @@ -38,7 +38,7 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_ if (eRank == RANK_1) { - if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register + if (u4RegType >= 2 && u4RegType <= 3) { if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR && u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR) @@ -51,52 +51,52 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_ u4Offset += DRAMC_REG_AO_RANK_OFFSET; } } - else if (u4RegType >= 6 && u4RegType <= 7)// PhyA/B AO Register + else if (u4RegType >= 6 && u4RegType <= 7) { - // 0x60~0xE0 + if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x1E0~0x260 + else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x360~0x3E0 + else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x760~0x7E0 + else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x8E0~0x960 + else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0xA60~0xAE0 + else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0xBE0~0xC60 + else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } } - else if (u4RegType <= 1)// ChA/B Dramc NAO Register + else if (u4RegType <= 1) { if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) && u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS)) @@ -109,9 +109,9 @@ U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_ u4Offset += DRAMC_REG_NAO_RANK_OFFSET; } } - else if (u4RegType >= 4 && u4RegType <= 5) // PhyA/B NAO Register + else if (u4RegType >= 4 && u4RegType <= 5) { - // PhyA/B NAO Register + if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START && u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END) { @@ -181,12 +181,12 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 return u4reg_addr; } - if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register + if (u4RegType >= 4 && u4RegType <= 7) { if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR) eShu = 0; } - else if (u4RegType >= 12 && u4RegType <= 15)// ChA/B Phy AO Register + else if (u4RegType >= 12 && u4RegType <= 15) { if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR) eShu = 0; @@ -194,7 +194,7 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 if (eRank == RANK_1) { - if (u4RegType >= 4 && u4RegType <= 7)// ChA/B Dramc AO Register + if (u4RegType >= 4 && u4RegType <= 7) { if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR && u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR) @@ -207,52 +207,52 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4Offset += DRAMC_REG_AO_RANK_OFFSET; } } - else if (u4RegType >= 12 && u4RegType <= 15)// PhyA/B AO Register + else if (u4RegType >= 12 && u4RegType <= 15) { - // 0x60~0xE0 + if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x1E0~0x260 + else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x360~0x3E0 + else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x760~0x7E0 + else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0x8E0~0x960 + else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0xA60~0xAE0 + else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } - // 0xBE0~0xC60 + else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR && u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR) { u4Offset += DDRPHY_AO_RANK_OFFSET; } } - else if (u4RegType <= 3)// ChA/B Dramc NAO Register + else if (u4RegType <= 3) { if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) && u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS)) @@ -260,9 +260,9 @@ static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4Offset += 0x100; } } - else if (u4RegType >= 8 && u4RegType <= 11) // PhyA/B NAO Register + else if (u4RegType >= 8 && u4RegType <= 11) { - // PhyA/B NAO Register + if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START && u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END) { @@ -358,30 +358,22 @@ inline U32 _u4Dram_Register_Read(U64 u4reg_addr) #if QT_GUI_Tool ucDramRegRead_1(u4reg_addr, &u4reg_value); -#elif (FOR_DV_SIMULATION_USED == 1) //DV +#elif (FOR_DV_SIMULATION_USED == 1) u4reg_value = register_read_c(u4reg_addr); -#else // real chip +#else u4reg_value = *((volatile unsigned int *)u4reg_addr); #endif return u4reg_value; } -//------------------------------------------------------------------------- -/** ucDram_Register_Read - * DRAM register read (32-bit). - * @param u4reg_addr register address in 32-bit. - * @param pu4reg_value Pointer of register read value. - * @retval 0: OK, 1: FAIL - */ -//------------------------------------------------------------------------- -// This function need to be porting by BU requirement + U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr) { U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf; #if (fcFOR_CHIP_ID == fc8195) - //ignore CH-B + if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL)) { if(u4RegType%2!=0) @@ -397,15 +389,6 @@ U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr) } -//------------------------------------------------------------------------- -/** ucDram_Register_Write - * DRAM register write (32-bit). - * @param u4reg_addr register address in 32-bit. - * @param u4reg_value register write value. - * @retval 0: OK, 1: FAIL - */ -//------------------------------------------------------------------------- - #if REG_ACCESS_NAO_DGB #if (fcFOR_CHIP_ID == fcCervino) U8 Check_RG_Not_AO(U32 u4reg_addr) @@ -439,8 +422,8 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value) ucDramRegWrite_1(u4reg_addr, u4reg_value); #elif (FOR_DV_SIMULATION_USED == 1) //DV register_write_c(u4reg_addr, u4reg_value); -#else // real chip - (*(volatile unsigned int *)u4reg_addr) = u4reg_value;//real chip +#else + (*(volatile unsigned int *)u4reg_addr) = u4reg_value; #if !defined(__DPM__) dsb(); #endif @@ -451,7 +434,7 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value) { mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value)); gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0; - mcDELAY_MS(1); // to receive log for log + mcDELAY_MS(1); gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1; } #endif @@ -464,13 +447,13 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value) #endif } -//This function need to be porting by BU requirement + void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value) { U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf; #if (fcFOR_CHIP_ID == fc8195) - //ignore CH-B + if ((p->support_channel_num == CHANNEL_SINGLE) && (u4reg_addr >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && u4reg_addr < MAX_BASE_VIRTUAL)) { if(u4RegType%2!=0) @@ -495,7 +478,7 @@ void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32) U32 u4Val; U32 u4RegType = ((reg32 - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf; - //ignore CH-B + #if (fcFOR_CHIP_ID == fc8195) if ((p->support_channel_num == CHANNEL_SINGLE) && (reg32 >= Channel_A_DRAMC_NAO_BASE_VIRTUAL && reg32 <= MAX_BASE_VIRTUAL)) { @@ -520,30 +503,30 @@ void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32) U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); U8 u1BCSupport = TRUE; - reg32 &= 0xffff; // remove channel information + reg32 &= 0xffff; - u1AllCount = p->support_channel_num; // for all dramC and PHY + u1AllCount = p->support_channel_num; - if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM + if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL) { reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; if (u1AllCount > 1) u1AllCount >>= 1; u1BCSupport = FALSE; } - else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO + else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL) { reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL; } - else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO + else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL) { reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL; } - else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO + else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL) { reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL; } - else // DramC NAO + else { reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL; } @@ -570,30 +553,30 @@ void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32) U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); U8 u1BCSupport = TRUE; - reg32 &= 0xffff; // remove channel information + reg32 &= 0xffff; - u1AllCount = p->support_channel_num; // for all dramC and PHY + u1AllCount = p->support_channel_num; - if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM + if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL) { reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; if (u1AllCount > 1) u1AllCount >>= 1; u1BCSupport = FALSE; } - else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO + else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL) { reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL; } - else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO + else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL) { reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL; } - else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO + else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL) { reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL; } - else // DramC NAO + else { reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL; } diff --git a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c index 447ecb04d5..6634e48e67 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c +++ b/src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c @@ -11,7 +11,7 @@ void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank) default: mcSHOW_ERR_MSG(("ERROR: CKE FIX ON error. Unexpected Rank \n")); } } -//[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank); + static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank) { U8 temp_MRS_RESPONSE ; @@ -37,13 +37,11 @@ static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank) static void LP4_FSP_WR_or_OP (DRAMC_CTX_T *p, U8 FSP_WR, U8 FSP_OP, U8 rank) { U8 MR13 = 0; - MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4)/*[RRO] for MR4 refresh rate*/; + MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4); LP4_MRS(p, 13, MR13, rank); } -//================================== -//uesage(constraint): DBI = 1 for FSPOP=1 if DBI=0 then FSP_OP =0 -//================================== + static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 rank) { U8 MR1; @@ -54,7 +52,7 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra U8 MR12; U8 MR14; - //default value for LP4 DRAM CONFIG + U8 nWR =5; U8 WR_LEV =0; U8 PDDS =5; @@ -62,9 +60,9 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra U8 PU_CAL =0; U8 WLS =0; - //Notice: DBI default = 0 - //field & configuration adaption + + MR1 = ((tr->RPST & 1)<<7) | ((nWR & 7)<<4) | ((tr->RD_PRE & 1)<<3) | ((tr->WR_PRE & 1)<<2) | ((tr->BL & 3)<<0); MR2 = ((WR_LEV & 1)<<7) | ((WLS & 1)<<6) | ((tr->MR_WL & 7)<<3) | ((tr->MR_RL & 7)<<0); MR3 = ((tr->DBI_WR & 1)<<7) | ((tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); @@ -84,20 +82,20 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra if(p->dram_fsp == FSP_1) MR12 = 0x20; #endif - //temp workaround for global variable of MR + u1MR02Value[tr->WORK_FSP] = MR2; u1MR03Value[tr->WORK_FSP] = MR3; #if ENABLE_LP4_ZQ_CAL - DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency + DramcZQCalibration(p, rank); #endif mcSHOW_DBG_MSG6(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank)); - //first FSP + if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);} else {LP4_FSP_WR_or_OP(p, 1, 0, rank);} - mcDELAY_XNS(15); //TCKFSPE + mcDELAY_XNS(15); LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); @@ -107,17 +105,17 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra LP4_MRS(p, 14, MR14 , rank); if(tr->LP4Y_EN == 1) { LP4_MRS(p, 51, MR51, rank); } - mcDELAY_XNS(15); //TCKFSPX + mcDELAY_XNS(15); + - //2nd FSP if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 1, 0, rank);} else {LP4_FSP_WR_or_OP(p, 0, 1, rank);} - mcDELAY_XNS(15); //TCKFSPE + mcDELAY_XNS(15); LP4_MRS(p, 1, MR1 , rank); LP4_MRS(p, 2, MR2 , rank); - //reverse the DBI + MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0); LP4_MRS(p, 3, MR3 , rank); LP4_MRS(p, 11, MR11 , rank); @@ -145,17 +143,17 @@ void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD0) , P_Fld( 0 , SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ0) , P_Fld( 0 , SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ0) , P_Fld( 0 , SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 )); - vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); //@Darren, debugging for DFS stress fail + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld( LP4Y_EN , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld( LP4Y_EN , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 )); -#if 1//ENABLE_LP4Y_DFS // @Darren, need confirm - // for strong pull low and normal mode +#if 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y )); #else - // for weak pull low mode only + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y )); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y )); @@ -168,22 +166,23 @@ void LP4_DRAM_INIT(DRAMC_CTX_T *p) U8 RANK; -#if SA_CONFIG_EN && DV_SIMULATION_DFS// @Darren, temp workaround +#if SA_CONFIG_EN && DV_SIMULATION_DFS DramcPowerOnSequence(p); #endif - mcDELAY_XNS(200); //tINIT3 = 2ms for DV fastup to 200ns + mcDELAY_XNS(200); for(RANK=0;RANK<2;RANK++) { CKE_FIX_ON(p,1,RANK); - mcDELAY_XNS(400); //tINIT5 fastup to 400ns + mcDELAY_XNS(400); + - //step4 moderegister setting lp4_dram_init_single_rank(p,DV_p.lp4_init,RANK); CKE_FIX_ON(p,0,RANK); } - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); //TODO enable refresh + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); } + diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c index 5ab06f5f75..5fa9bab315 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c @@ -15,21 +15,13 @@ U32 u4Datlat = 0; static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4]; -//static const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5]; -//------------------------------------------------------------------------- -/** u1GetACTimingIdx() - * Retrieve internal ACTimingTbl's index according to dram type, freqGroup, Read DBI status - * @param p Pointer of context created by DramcCtxCreate. - * @retval u1TimingIdx Return ACTimingTbl entry's index - */ -//------------------------------------------------------------------------- + static U8 u1GetACTimingIdx(DRAMC_CTX_T *p) { U8 u1TimingIdx = 0xff, u1TmpIdx; U8 u1TmpDramType = p->dram_type; { - // LP4/LP4P/LP4X use same table if (u1TmpDramType == TYPE_LPDDR4X || u1TmpDramType == TYPE_LPDDR4P) u1TmpDramType = TYPE_LPDDR4; } @@ -38,16 +30,16 @@ static U8 u1GetACTimingIdx(DRAMC_CTX_T *p) for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP4; u1TmpIdx++) { if ((ACTimingTbl_LP4[u1TmpIdx].dramType == u1TmpDramType) && - /* p->frequency may not be in ACTimingTable, use p->freqGroup */ + (ACTimingTbl_LP4[u1TmpIdx].freq == p->freqGroup) && (ACTimingTbl_LP4[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) && - (ACTimingTbl_LP4[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode - (ACTimingTbl_LP4[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming + (ACTimingTbl_LP4[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && + (ACTimingTbl_LP4[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) ) { u1TimingIdx = u1TmpIdx; //mcDUMP_REG_MSG(("match AC timing %d\n", u1TimingIdx)); - //Also for Dump_REG + mcSHOW_DBG_MSG2(("match AC timing %d\n", u1TimingIdx)); mcSHOW_DBG_MSG2(("dramType %d, freq %d, readDBI %d, DivMode %d, cbtMode %d\n", u1TmpDramType, p->freqGroup, p->DBI_R_onoff[p->dram_fsp], vGet_Div_Mode(p), vGet_Dram_CBT_Mode(p))); break; @@ -153,7 +145,7 @@ static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p) { u4CS2RL_start = 7; u4tRPRE_toggle = 0; - u4tDQSCK_Max = 3500; //ps + u4tDQSCK_Max = 3500; u4RL[0] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_0], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2)); u4RL[1] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_1], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2)); u4RLMax = (u4RL[0] > u4RL[1]) ? u4RL[0] : u4RL[1]; @@ -191,21 +183,13 @@ static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p) u4DQSIEN_ser_latency = u1GetDQSIEN_p2s_latency(u4DQ_P2S_Ratio); u4CA_ser_latency = u1GetDQ_CA_p2s_latency(u4CA_p2s_ratio, A_D->CA_FULL_RATE); u4CA_MCKIO_ui_unit = u4DQ_ui_unit * u4CKR / (A_D->CA_FULL_RATE + 1); - u4RX_rdcmdout2rdcmdbus_by_ps = 3 * u4MCK_unit + u4CAdefault_delay * u4CA_ui_unit + u4CA_ser_latency * u4CA_MCKIO_ui_unit /*+ RX_C->ca_default_PI * RX_C->ca_MCKIO_ps / RX_C->ca_ui_pi_ratio*/ ; // 3 is 1.5T pipe to APHY + 0.5T wait posedge then start P2S + 1T read_cmd_out + u4RX_rdcmdout2rdcmdbus_by_ps = 3 * u4MCK_unit + u4CAdefault_delay * u4CA_ui_unit + u4CA_ser_latency * u4CA_MCKIO_ui_unit /*+ RX_C->ca_default_PI * RX_C->ca_MCKIO_ps / RX_C->ca_ui_pi_ratio*/ ; u4Datlat_dsel = A_div_B_Round((u4RX_rdcmdout2rdcmdbus_by_ps + (u4CS2RL_start + u4RLMax * 2 )* u4CKR * u4DQ_ui_unit + u4tDQSCK_Max + u4DQ_2_1stDVI4CK), u4MCK_unit) - u4RDSEL_Offset - u4TxPipeline + u4Datlat_margin; u4Datlat = u4Datlat_dsel + u4TxPipeline + u4RxPipeline - 1; mcSHOW_DBG_MSG(("Calculate Datlat value is %d on freq %d\n", u4Datlat, p->frequency)); } -//------------------------------------------------------------------------- -/** UpdateACTimingReg() - * ACTiming related register field update - * @param p Pointer of context created by DramcCtxCreate. - * @param ACTbl Pointer to correct ACTiming table struct - * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL - */ -//------------------------------------------------------------------------- #if ENABLE_WDQS_MODE_2 static void WDQSMode2AcTimingEnlarge(DRAMC_CTX_T *p, U16 *u2_XRTW2W, U16 *u2_XRTR2W, U16 *u2_XRTW2R, U16 *u2_TRTW) @@ -267,20 +251,20 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 { ACTime_T_LP4 ACTblFinal; U8 backup_rank = p->rank; - DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming) - // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value - // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field + DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; + + #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY U8 u1RANKINCTL = 0; #endif - U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values + U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; #if SAMSUNG_LP4_NWR_WORKAROUND U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0; U8 u1MCKtoTck = 0, u105TtoTck = 0; #endif - // ACTiming regs that aren't currently in ACTime_T struct - U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF) + + U8 u1TREFBW = 0; U8 u1TFAW_05T=0, u1TRRD_05T=0; U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0; U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0; @@ -301,21 +285,21 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 u4Datlat = ACTblFinal.datlat; #endif - // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios-------------------------- + #if ENABLE_TX_WDQS r2w_odt_onoff = ODT_ON; #else r2w_odt_onoff = p->odt_onoff; #endif - // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable - if (r2w_odt_onoff == ODT_ON) //odt_on + + if (r2w_odt_onoff == ODT_ON) { u2TRTW = ACTblFinal.trtw_odt_on; u2TRTW_05T = ACTblFinal.trtw_odt_on_05T; u2XRTW2R = ACTblFinal.xrtw2r_odt_on; u2XRTR2W = ACTblFinal.xrtr2w_odt_on; } - else //odt_off + else { u2TRTW = ACTblFinal.trtw_odt_off; u2TRTW_05T = ACTblFinal.trtw_odt_off_05T; @@ -323,8 +307,8 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 u2XRTR2W = ACTblFinal.xrtr2w_odt_off; } - // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW) - if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY) + + if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) { u2TRTW = ACTblFinal.trtw_odt_on; u2TRTW_05T = ACTblFinal.trtw_odt_on_05T; @@ -358,35 +342,27 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 } #if ENABLE_RODT_TRACKING_SAVE_MCK - // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN) + u1ODT_ON = p->odt_onoff; u1RODT_TRACK = ENABLE_RODT_TRACKING; u1ROEN = u1WDQS_ON | u1ODT_ON; u1ModeSel = u1RODT_TRACK & u1ROEN; - // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting - // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team) + //if (u1RODT_TRACK && (u1ROEN==1)) // RODT_TRACKING_SAVEING_MCK = 1; #endif #if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN)) - /* yr: same code - // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided - if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK - else RODT_TRACKING_SAVEING_MCK = 0; - */ RODT_TRACKING_SAVEING_MCK = 0; #endif - // Update values that are used by RODT_TRACKING_SAVEING_MCK u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK; u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK; #if SAMSUNG_LP4_NWR_WORKAROUND - // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung 1xnm DRAM internal IO precharge time - // Regarding the nWR setting recommandation, it is effective only for D1x LP4x, we changed logic from D1y (1ynm) to prevent that issue. - if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency <= 800)) //LP4X, Samsung, DDR1600 + + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency <= 800)) { if (vGet_Div_Mode(p) == DIV8_MODE) { @@ -399,16 +375,16 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 u105TtoTck= 1; } - u1TWTR_TMP = (ACTblFinal.twtr * u1MCKtoTck - ACTblFinal.twtr_05T * u105TtoTck) + 2; //Convert TWTR to tCK, and add 2tCK - if ((u1TWTR_TMP % u1MCKtoTck) == 0) //TWTR can be transferred to TWTR directly + u1TWTR_TMP = (ACTblFinal.twtr * u1MCKtoTck - ACTblFinal.twtr_05T * u105TtoTck) + 2; + if ((u1TWTR_TMP % u1MCKtoTck) == 0) { u1TWTR = u1TWTR_TMP/u1MCKtoTck; u1TWTR_05T = 0; } - else //Can't be transfered to TWTR directly + else { - u1TWTR = (u1TWTR_TMP + u105TtoTck)/u1MCKtoTck; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T) - u1TWTR_05T = 1; //05T means minus 2tCK + u1TWTR = (u1TWTR_TMP + u105TtoTck)/u1MCKtoTck; + u1TWTR_05T = 1; } ACTblFinal.twtr = u1TWTR; @@ -416,11 +392,11 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 } #endif - //DATLAT related + if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) - u1DATLAT_DSEL = u4Datlat; //ACTblFinal.datlat; + u1DATLAT_DSEL = u4Datlat; else - u1DATLAT_DSEL = u4Datlat - 1; //ACTblFinal.datlat - 1; + u1DATLAT_DSEL = u4Datlat - 1; #if TX_OE_EXTEND u2XRTWTW += 1; @@ -451,7 +427,7 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 ACTblFinal.ckeprd -= 1; #endif - // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)------- + vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS) | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP) @@ -466,7 +442,7 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP) | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI) | P_Fld(u2TFAW, SHU_ACTIM2_TFAW) - | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW + | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP)); vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD) @@ -498,13 +474,13 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT); // vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT) // | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP)); - //tg removed. Only DramcModeRegInit_LP4() setting is preserved. + //vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP); //vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP); - // AC timing 0.5T + vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T) - | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW + | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(u1TFAW_05T, SHU_AC_TIME_05T_TFAW_05T) | P_Fld(u1TRRD_05T, SHU_AC_TIME_05T_TRRD_05T) @@ -554,15 +530,15 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 | P_Fld(ACTblFinal.trcd_derate_05T, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(ACTblFinal.trc_derate_05T, SHU_AC_DERATING_05T_TRC_05T_DERATE)); vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN); - vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing + vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); } #endif - // DQSINCTL related + vSetRank(p, RANK_0); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL); vSetRank(p, RANK_1); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL); vSetRank(p, backup_rank); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT); @@ -585,22 +561,20 @@ static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL); #endif - // DATLAT related, tREFBW + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(u4Datlat, MISC_SHU_RDAT_DATLAT) | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR); - // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------ + #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY - //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1 - //XRTR2R setting will be updated in RxdqsGatingPostProcess u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY); #endif - //Update releated RG of XRTW2W + if (p->frequency <= 800) { if (vGet_Div_Mode(p) == DIV4_MODE) @@ -639,7 +613,7 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p) mcSHOW_DBG_MSG4(("[UpdateACTiming]\n")); - //Retrieve ACTimingTable's corresponding index + u1TimingIdx = u1GetACTimingIdx(p); @@ -648,7 +622,7 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p) #if 0 if (u1TmpDramType = TYPE_LPDDR4) u1TimingIdx = 0; - else // LPDDR3 + else u1TimingIdx = 6; mcSHOW_ERR_MSG(("Error, no match AC timing, use default timing %d\n", u1TimingIdx)); #else @@ -657,7 +631,7 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p) #endif } - //Set ACTiming registers + { DdrUpdateACTimingReg_LP4(p, &ACTimingTbl_LP4[u1TimingIdx]); } @@ -665,28 +639,21 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p) return DRAM_OK; } -/* Optimize all-bank refresh parameters (by density) for LP4 */ + void vDramcACTimingOptimize(DRAMC_CTX_T *p) { - /* TRFC: tRFCab - * Refresh Cycle Time (All Banks) - * TXREFCNT: tXSR max((tRFCab + 7.5ns), 2nCK) - * Min self refresh time (Entry to Exit) - * u1ExecuteOptimize: Indicate if ACTimings are updated at the end of this function - */ + U8 u1RFCabGrpIdx = 0, u1FreqGrpIdx = 0, u1ExecuteOptimize = ENABLE; U8 u1TRFC=101, u1TRFC_05T=0, u1TRFCpb=44, u1TRFCpb_05T=0,u1TXREFCNT=118; typedef struct - { /* Bitfield sizes set to current project register field's size */ + { U8 u1TRFC : 8; U8 u1TRFRC_05T : 1; U8 u1TRFCpb : 8; U8 u1TRFRCpb_05T : 1; U16 u2TXREFCNT : 10; } optimizeACTime; - /* JESD209-4B: tRFCab has 4 settings for 7 density settings (130, 180, 280, 380) - * tRFCAB_NUM: Used to indicate tRFCab group (since some densities share the same tRFCab) - */ + enum tRFCABIdx{tRFCAB_130 = 0, tRFCAB_180, tRFCAB_280, tRFCAB_380, tRFCAB_NUM}; enum ACTimeIdx{GRP_DDR1200_ACTIM, GRP_DDR1600_ACTIM, GRP_DDR1866_ACTIM, GRP_DDR2400_ACTIM, GRP_DDR2667_ACTIM, GRP_DDR3200_ACTIM, GRP_DDR3733_ACTIM, GRP_DDR4266_ACTIM, GRP_ACTIM_NUM}; enum ACTimeIdxDiv4{ @@ -694,78 +661,78 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p) GRP_DDR400_DIV4_ACTIM = 0, #endif GRP_DDR800_DIV4_ACTIM, GRP_DDR1200_DIV4_ACTIM, GRP_DDR1600_DIV4_ACTIM, GRP_ACTIM_NUM_DIV4}; - /* Values retrieved from 1. Alaska ACTiming excel file 2. JESD209-4B Refresh requirement table */ + optimizeACTime *ptRFCab_Opt; optimizeACTime tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] = { - //For freqGroup DDR1200 - {{.u1TRFC = 8, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 21}, //tRFCab = 130, tRFCpb = 60, @Robert Not enough to Optimize - {.u1TRFC = 15, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 30, .u1TRFRC_05T = 1, .u1TRFCpb = 9, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 44}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 45, .u1TRFRC_05T = 1, .u1TRFCpb = 17, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 59}},//tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR1600 - {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR1866 - {{.u1TRFC = 18, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 33}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 30, .u1TRFRC_05T = 0, .u1TRFCpb = 9, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 44}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 53, .u1TRFRC_05T = 1, .u1TRFCpb = 21, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 68}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 77, .u1TRFRC_05T = 0, .u1TRFCpb = 32, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 91}},//tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR2400 - {{.u1TRFC = 27, .u1TRFRC_05T = 1, .u1TRFCpb = 6, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 42}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 42, .u1TRFRC_05T = 1, .u1TRFCpb = 15, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 57}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 72, .u1TRFRC_05T = 1, .u1TRFCpb = 30, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 87}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 102, .u1TRFRC_05T = 1, .u1TRFCpb = 45, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR2667 - {{.u1TRFC = 31, .u1TRFRC_05T = 1, .u1TRFCpb = 8, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 46}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 48, .u1TRFRC_05T = 1, .u1TRFCpb = 18, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 63}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 81, .u1TRFRC_05T = 1, .u1TRFCpb = 35, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 96}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 115, .u1TRFRC_05T = 0, .u1TRFCpb = 51, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 130}}, //tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR3200 - {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR3733 - {{.u1TRFC = 49, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 65}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 72, .u1TRFRC_05T = 0, .u1TRFCpb = 30, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 88}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 119, .u1TRFRC_05T = 0, .u1TRFCpb = 53, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 135}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 165, .u1TRFRC_05T = 1, .u1TRFCpb = 77, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 181}}, //tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR4266 - {{.u1TRFC = 57, .u1TRFRC_05T = 1, .u1TRFCpb = 20, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 74}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 84, .u1TRFRC_05T = 0, .u1TRFCpb = 36, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 100}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 137, .u1TRFRC_05T = 1, .u1TRFCpb = 63, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 154}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 191, .u1TRFRC_05T = 0, .u1TRFCpb = 89, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 207}} //tRFCab = 380, tRFCpb = 190 + + {{.u1TRFC = 8, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 21}, + {.u1TRFC = 15, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, + {.u1TRFC = 30, .u1TRFRC_05T = 1, .u1TRFCpb = 9, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 44}, + {.u1TRFC = 45, .u1TRFRC_05T = 1, .u1TRFCpb = 17, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 59}}, + + {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, + {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, + {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, + {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}}, + + {{.u1TRFC = 18, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 33}, + {.u1TRFC = 30, .u1TRFRC_05T = 0, .u1TRFCpb = 9, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 44}, + {.u1TRFC = 53, .u1TRFRC_05T = 1, .u1TRFCpb = 21, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 68}, + {.u1TRFC = 77, .u1TRFRC_05T = 0, .u1TRFCpb = 32, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 91}}, + + {{.u1TRFC = 27, .u1TRFRC_05T = 1, .u1TRFCpb = 6, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 42}, + {.u1TRFC = 42, .u1TRFRC_05T = 1, .u1TRFCpb = 15, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 57}, + {.u1TRFC = 72, .u1TRFRC_05T = 1, .u1TRFCpb = 30, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 87}, + {.u1TRFC = 102, .u1TRFRC_05T = 1, .u1TRFCpb = 45, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 117}}, + + {{.u1TRFC = 31, .u1TRFRC_05T = 1, .u1TRFCpb = 8, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 46}, + {.u1TRFC = 48, .u1TRFRC_05T = 1, .u1TRFCpb = 18, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 63}, + {.u1TRFC = 81, .u1TRFRC_05T = 1, .u1TRFCpb = 35, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 96}, + {.u1TRFC = 115, .u1TRFRC_05T = 0, .u1TRFCpb = 51, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 130}}, + + {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, + {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, + {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, + {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, + + {{.u1TRFC = 49, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 65}, + {.u1TRFC = 72, .u1TRFRC_05T = 0, .u1TRFCpb = 30, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 88}, + {.u1TRFC = 119, .u1TRFRC_05T = 0, .u1TRFCpb = 53, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 135}, + {.u1TRFC = 165, .u1TRFRC_05T = 1, .u1TRFCpb = 77, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 181}}, + + {{.u1TRFC = 57, .u1TRFRC_05T = 1, .u1TRFCpb = 20, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 74}, + {.u1TRFC = 84, .u1TRFRC_05T = 0, .u1TRFCpb = 36, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 100}, + {.u1TRFC = 137, .u1TRFRC_05T = 1, .u1TRFCpb = 63, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 154}, + {.u1TRFC = 191, .u1TRFRC_05T = 0, .u1TRFCpb = 89, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 207}} }; optimizeACTime tRFCab_Opt_Div4 [GRP_ACTIM_NUM_DIV4][tRFCAB_NUM] = { #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION - // @ tg add for DDR400 - {{.u1TRFC = 1, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 14}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 6, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 19}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 16, .u1TRFRC_05T = 0, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 26, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 39}},//tRFCab = 380, tRFCpb = 190 + + {{.u1TRFC = 1, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 14}, + {.u1TRFC = 6, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 19}, + {.u1TRFC = 16, .u1TRFRC_05T = 0, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, + {.u1TRFC = 26, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 39}}, #endif - //NOTE: @Darren, For freqGroup DDR816 - {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR1200 - {{.u1TRFC = 28, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 42}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 43, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 57}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 73, .u1TRFRC_05T = 0, .u1TRFCpb = 31, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 87}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 103, .u1TRFRC_05T = 0, .u1TRFCpb = 46, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190 - //For freqGroup DDR1600 - {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, //tRFCab = 130, tRFCpb = 60 - {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, //tRFCab = 180, tRFCpb = 90 - {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, //tRFCab = 280, tRFCpb = 140 - {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190 + + {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, + {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, + {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, + {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}}, + + {{.u1TRFC = 28, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 42}, + {.u1TRFC = 43, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 57}, + {.u1TRFC = 73, .u1TRFRC_05T = 0, .u1TRFCpb = 31, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 87}, + {.u1TRFC = 103, .u1TRFRC_05T = 0, .u1TRFCpb = 46, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 117}}, + + {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, + {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, + {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, + {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, }; @@ -778,29 +745,29 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p) while(1); } #endif - /* Set tRFCab group idx p->density = MR8 OP[5:2]*/ + switch (p->density) { - case 0x0: //4Gb per die (2Gb per channel), tRFCab=130 + case 0x0: u1RFCabGrpIdx = tRFCAB_130; break; - case 0x1: //6Gb per die (3Gb per channel), tRFCab=180 - case 0x2: //8Gb per die (4Gb per channel), tRFCab=180 + case 0x1: + case 0x2: u1RFCabGrpIdx = tRFCAB_180; break; - case 0x3: //12Gb per die (6Gb per channel), tRFCab=280 - case 0x4: //16Gb per die (8Gb per channel), tRFCab=280 + case 0x3: + case 0x4: u1RFCabGrpIdx = tRFCAB_280; break; - case 0x5: //24Gb per die (12Gb per channel), tRFCab=380 - case 0x6: //32Gb per die (16Gb per channel), tRFCab=380 + case 0x5: + case 0x6: u1RFCabGrpIdx = tRFCAB_380; break; default: u1ExecuteOptimize = DISABLE; mcSHOW_ERR_MSG(("MR8 density err!\n")); } - /* Set freqGroup Idx */ + switch (p->freqGroup) { #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION @@ -888,7 +855,7 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p) u1TRFCpb_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRCpb_05T; u1TXREFCNT = ptRFCab_Opt[u1RFCabGrpIdx].u2TXREFCNT; - /* Only execute ACTimingOptimize(write to regs) when corresponding values have been found */ + if (u1ExecuteOptimize == ENABLE) { vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFC, SHU_ACTIM3_TRFC); @@ -903,17 +870,12 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p) return; } -/* ACTimingTbl: All freq's ACTiming from ACTiming excel file - * (Some fields don't exist for LP3 -> set to 0) - * Note: !!All ACTiming adjustments should not be set in-table should be moved into UpdateACTimingReg()!! - * Or else preloader's highest freq ACTimings may be set to different values than expected. - */ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { - //----------LPDDR4--------------------------- + #if SUPPORT_LP4_DDR4266_ACTIM - //LP4_DDR4266 ACTiming--------------------------------- + #if (ENABLE_READ_DBI == 1) -//LPDDR4 4X_4266_Div 8_DBI1.csv Read 1 + { .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, .readLat = 40, .writeLat = 18, .DivMode = DIV8_MODE, @@ -975,10 +937,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 16, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 }, -//LPDDR4 4X_4266_BT_Div 8_DBI1.csv Read 1 + { .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, .readLat = 44, .writeLat = 18, .DivMode = DIV8_MODE, @@ -1040,11 +1002,11 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 16, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 }, -#else //ENABLE_READ_DBI == 0) -//LPDDR4 4X_4266_Div 8_DBI0.csv Read 0 +#else + { .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 36, .writeLat = 18, .DivMode = DIV8_MODE, @@ -1106,10 +1068,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 16, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 }, -//LPDDR4 4X_4266_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 40, .writeLat = 18, .DivMode = DIV8_MODE, @@ -1171,15 +1133,15 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 16, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 7, .datlat = 18 }, #endif #endif #if SUPPORT_LP4_DDR3733_ACTIM - //LP4_DDR3733 ACTiming--------------------------------- + #if (ENABLE_READ_DBI == 1) -//LPDDR4 4X_3733_Div 8_DBI1.csv Read 1 + { .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, .readLat = 36, .writeLat = 16, .DivMode = DIV8_MODE, @@ -1241,10 +1203,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 14, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 }, -//LPDDR4 4X_3733_BT_Div 8_DBI1.csv Read 1 + { .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, .readLat = 40, .writeLat = 16, .DivMode = DIV8_MODE, @@ -1306,11 +1268,11 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 14, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 }, -#else //ENABLE_READ_DBI == 0) -//LPDDR4 4X_3733_Div 8_DBI0.csv Read 0 +#else + { .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 32, .writeLat = 16, .DivMode = DIV8_MODE, @@ -1372,10 +1334,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 14, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 }, -//LPDDR4 4X_3733_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 36, .writeLat = 16, .DivMode = DIV8_MODE, @@ -1437,15 +1399,15 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 14, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 6, .datlat = 16 }, #endif #endif #if SUPPORT_LP4_DDR3200_ACTIM - //LP4_DDR3200 ACTiming--------------------------------- + #if (ENABLE_READ_DBI == 1) -//LPDDR4 4X_3200_Div 8_DBI1.csv Read 1 + { .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1, .readLat = 32, .writeLat = 14, .DivMode = DIV8_MODE, @@ -1507,10 +1469,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 12, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 }, -//LPDDR4 4X_3200_BT_Div 8_DBI1.csv Read 1 + { .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1, .readLat = 36, .writeLat = 14, .DivMode = DIV8_MODE, @@ -1572,11 +1534,11 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 12, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 }, -#else //ENABLE_READ_DBI == 0) -//LPDDR4 4X_3200_Div 8_DBI0.csv Read 0 +#else + { .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 28, .writeLat = 14, .DivMode = DIV8_MODE, @@ -1638,10 +1600,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 12, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 }, -//LPDDR4 4X_3200_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 32, .writeLat = 14, .DivMode = DIV8_MODE, @@ -1703,14 +1665,13 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 12, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 }, #endif #endif #if SUPPORT_LP4_DDR2667_ACTIM - //LP4_DDR2667 ACTiming--------------------------------- -//LPDDR4 4X_2667_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 24, .writeLat = 12, .DivMode = DIV8_MODE, @@ -1772,10 +1733,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 11, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD }, -//LPDDR4 4X_2667_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 26, .writeLat = 12, .DivMode = DIV8_MODE, @@ -1837,13 +1798,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 11, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD }, #endif #if SUPPORT_LP4_DDR2400_ACTIM - //LP4_DDR2400 ACTiming--------------------------------- -//LPDDR4 4X_2400_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 24, .writeLat = 12, .DivMode = DIV8_MODE, @@ -1905,10 +1865,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 10, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 4, .datlat = 13 }, -//LPDDR4 4X_2400_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 26, .writeLat = 12, .DivMode = DIV8_MODE, @@ -1970,13 +1930,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 10, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 4, .datlat = 13 }, #endif #if SUPPORT_LP4_DDR1866_ACTIM - //LP4_DDR1866 ACTiming--------------------------------- -//LPDDR4 4X_1866_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 20, .writeLat = 10, .DivMode = DIV8_MODE, @@ -2038,10 +1997,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 7, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 3, .datlat = 13 }, -//LPDDR4 4X_1866_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 22, .writeLat = 10, .DivMode = DIV8_MODE, @@ -2103,13 +2062,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 7, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 3, .datlat = 13 }, #endif #if SUPPORT_LP4_DDR1600_ACTIM - //LP4_DDR1600 ACTiming--------------------------------- -//LPDDR4 4X_1600_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2171,10 +2129,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 12, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 }, -//LPDDR4 4X_1600_BT_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2236,10 +2194,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 12, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 }, -//LPDDR4 4X_1600_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, @@ -2301,10 +2259,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 6, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 }, -//LPDDR4 4X_1600_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, @@ -2366,13 +2324,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 6, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 10 }, #endif #if SUPPORT_LP4_DDR1333_ACTIM - //LP4_DDR1333 ACTiming--------------------------------- -//LPDDR4 4X_1333_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2434,10 +2391,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 10, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD }, -//LPDDR4 4X_1333_BT_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2499,10 +2456,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 10, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD }, -//LPDDR4 4X_1333_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, @@ -2564,10 +2521,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 5, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD }, -//LPDDR4 4X_1333_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, @@ -2629,13 +2586,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 5, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = TBD, .datlat = TBD }, #endif #if SUPPORT_LP4_DDR1200_ACTIM - //LP4_DDR1200 ACTiming--------------------------------- -//LPDDR4 4X_1200_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2697,10 +2653,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 10, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 }, -//LPDDR4 4X_1200_BT_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2762,10 +2718,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 10, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 }, -//LPDDR4 4X_1200_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, @@ -2827,10 +2783,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 5, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 }, -//LPDDR4 4X_1200_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, @@ -2892,13 +2848,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 5, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 9 }, #endif #if SUPPORT_LP4_DDR800_ACTIM - //LP4_DDR800 ACTiming--------------------------------- -//LPDDR4 4X_800_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, @@ -2960,10 +2915,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 6, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 4, .datlat = 15 }, -//LPDDR4 4X_800_BT_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, @@ -3025,10 +2980,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 6, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 4, .datlat = 15 }, -//LPDDR4 4X_800_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE, @@ -3090,10 +3045,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 3, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 }, -//LPDDR4 4X_800_BT_Div 8_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE, @@ -3155,13 +3110,12 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 2, .zqlat2 = 3, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 5, .datlat = 15 }, #endif #if SUPPORT_LP4_DDR400_ACTIM - //LP4_DDR400 ACTiming--------------------------------- -//LPDDR4 4X_400_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0, .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE, @@ -3223,10 +3177,10 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 4, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 15 }, -//LPDDR4 4X_400_BT_Div 4_DBI0.csv Read 0 + { .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0, .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE, @@ -3288,7 +3242,7 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = { .ckelckcnt = 3, .zqlat2 = 4, - //DQSINCTL, DATLAT aren't in ACTiming excel file + .dqsinctl = 2, .datlat = 15 }, #endif diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c index 6684c291c4..2627bb9aaf 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c @@ -10,7 +10,6 @@ #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) #include "dramc_top.h" #ifndef MT6779_FPGA -//#include <pmic.h> #endif #endif @@ -387,7 +386,7 @@ void print_HQA_measure_message(DRAMC_CTX_T *p) if (p->support_rank_num == RANK_DUAL) { - //Preloader LP3 RX/TX only K Rank0, so Rank1 use Rank0's value + if (!u1IsLP4Family(p->dram_type)) { #ifndef LP3_DUAL_RANK_RX_K @@ -401,7 +400,7 @@ void print_HQA_measure_message(DRAMC_CTX_T *p) min_TX_DQ_bit[0][1] = min_TX_DQ_bit[0][0]; #endif - #if 0//(TX_PER_BIT_DELAY_CELL==0) + #if 0 gFinalTXPerbitWin_min_margin[0][1] = gFinalTXPerbitWin_min_margin[0][0]; gFinalTXPerbitWin_min_margin_bit[0][1] = gFinalTXPerbitWin_min_margin_bit[0][0]; #endif @@ -415,34 +414,23 @@ void print_HQA_measure_message(DRAMC_CTX_T *p) HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vcore_HQA = %d\n", read_voltage_value)); if (u1IsLP4Family(p->dram_type)) { - /* LPDDR4 */ + read_voltage_value = vGetVoltage(p, 1); HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdram_HQA = %d\n", read_voltage_value)); read_voltage_value = vGetVoltage(p, 2); HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vddq_HQA = %d\n", read_voltage_value)); read_voltage_value = vGetVoltage(p, 3); - HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdd1_HQA = %d\n", read_voltage_value)); /* confirm with pmic owner¡Athis vio18 is pmic 6359 's vm18, is different with vio18 of system */ + HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdd1_HQA = %d\n", read_voltage_value)); read_voltage_value = vGetVoltage(p, 4); HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vmddr_HQA = %d\n", read_voltage_value)); } else { - /* LPDDR3 */ + read_voltage_value = vGetVoltage(p, 1); HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("Vdram_HQA = %d\n", read_voltage_value)); } mcSHOW_DBG_MSG(("\n")); #endif - /* - [Impedance Calibration] - - freq_region=0 - [HQALOG] Impedance freq_region=0 DRVP 11 - [HQALOG] Impedance freq_region=0 DRVN 7 - - freq_region=1 - [HQALOG] Impedance freq_region=1 DRVP 13 - [HQALOG] Impedance freq_region=1 ODTN 15 - */ if (p->dram_type == TYPE_LPDDR4) { print_imp_option[1] = TRUE; @@ -454,7 +442,7 @@ void print_HQA_measure_message(DRAMC_CTX_T *p) } else { - //TYPE_LPDDR4P, TYPE_LPDDR3 + print_imp_option[0] = TRUE; } @@ -483,15 +471,7 @@ if (gHQALog_flag == 1) if (u1IsLP4Family(p->dram_type)) { - //TO DO: jimmy - //mcSHOW_DBG_MSG(("VrefCA Range : %d\n", gCBT_VREF_RANGE_SEL)); - /* - VrefCA - [HQALOG] 1600 VrefCA Channel0 Rank0 32 - [HQALOG] 1600 VrefCA Channel0 Rank1 24 - [HQALOG] 1600 VrefCA Channel1 Rank0 26 - [HQALOG] 1600 VrefCA Channel1 Rank1 30 - */ + mcSHOW_DBG_MSG(("VrefCA\n")); for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++) { @@ -506,7 +486,7 @@ if (gHQALog_flag == 1) } } -#if 0//(SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) +#if 0 if (p->femmc_Ready == 1 ) { mcSHOW_DBG_MSG(("\n[Cmd Bus Training window bypass calibration]\n")); @@ -514,13 +494,6 @@ if (gHQALog_flag == 1) else #endif { - /* - CA_Window - [HQALOG] 1600 CA_Window Channel0 Rank0 61(bit 2) - [HQALOG] 1600 CA_Window Channel0 Rank1 62(bit 1) - [HQALOG] 1600 CA_Window Channel1 Rank0 60(bit 5) - [HQALOG] 1600 CA_Window Channel1 Rank1 60(bit 5) - */ mcSHOW_DBG_MSG(("CA_Window\n")); #ifdef FOR_HQA_REPORT_USED if (gHQALog_flag == 1) @@ -551,13 +524,6 @@ else } } - /* - CA Min Window(%) - [HQALOG] 1600 CA_Window(%) Channel0 Rank0 96%(PASS) - [HQALOG] 1600 CA_Window(%) Channel0 Rank1 97%(PASS) - [HQALOG] 1600 CA_Window(%) Channel1 Rank0 94%(PASS) - [HQALOG] 1600 CA_Window(%) Channel1 Rank1 94%(PASS) - */ mcSHOW_DBG_MSG(("CA Min Window(%%)\n")); #ifdef FOR_HQA_REPORT_USED if (gHQALog_flag == 1) @@ -594,11 +560,6 @@ else - /* - [RX minimum per bit window] - Delay cell measurement (/100ps) - [HQALOG] 3200 delaycell 892 - */ mcSHOW_DBG_MSG(("\n[RX minimum per bit window]\n")); mcSHOW_DBG_MSG(("Delaycell measurement(/100ps)\n")); @@ -611,15 +572,11 @@ else { if ((gHQALOG_RX_delay_cell_ps_075V < 245) || (gHQALOG_RX_delay_cell_ps_075V > 300)) { - gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 2; //SLT_BIN2 + gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 2; } } #endif - /* - VrefDQ - [HQALOG] 1600 VrefRX Channel0 24 - [HQALOG] 1600 VrefRX Channel1 24 - */ + if (u1IsLP4Family(p->dram_type)) { @@ -664,13 +621,7 @@ else else #endif { - /* - RX_Window - [HQALOG] 1600 RX_Window Channel0 Rank0 52(bit 2) - [HQALOG] 1600 RX_Window Channel0 Rank1 52(bit 2) - [HQALOG] 1600 RX_Window Channel1 Rank0 60(bit 12) - [HQALOG] 1600 RX_Window Channel1 Rank1 62(bit 9) - */ + mcSHOW_DBG_MSG(("RX_Window\n")); #ifdef FOR_HQA_REPORT_USED if (gHQALog_flag == 1) @@ -700,13 +651,7 @@ else } } - /* - RX Min Window(%) - [HQALOG] 1600 RX_Window(%) Channel0 Rank0 43316/100ps(70%)(PASS) - [HQALOG] 1600 RX_Window(%) Channel0 Rank1 43316/100ps(70%)(PASS) - [HQALOG] 1600 RX_Window(%) Channel1 Rank0 49980/100ps(80%)(PASS) - [HQALOG] 1600 RX_Window(%) Channel1 Rank1 51646/100ps(83%)(PASS) - */ + mcSHOW_DBG_MSG(("RX Window(%%)\n")); #ifdef FOR_HQA_REPORT_USED if (gHQALog_flag == 1) @@ -720,7 +665,7 @@ if (gHQALog_flag == 1) if ((((min_rx_value[u1ChannelIdx][u1RankIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000) < 55) { - gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; //SLT_BIN4 + gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; } } } @@ -751,14 +696,6 @@ else - /* [TX minimum per bit window] - VrefDQ Range : 1 - VrefDQ - [HQALOG] 1600 VrefTX Channel0 Rank0 30 - [HQALOG] 1600 VrefTX Channel0 Rank1 25 - [HQALOG] 1600 VrefTX Channel1 Rank0 24 - [HQALOG] 1600 VrefTX Channel1 Rank1 23 - */ mcSHOW_DBG_MSG(("\n[TX minimum per bit window]\n")); if (u1IsLP4Family(p->dram_type)) { @@ -791,13 +728,7 @@ else else #endif { - /* - TX_Window - [HQALOG] 1600 TX_Window Channel0 Rank0 25(bit 2) - [HQALOG] 1600 TX_Window Channel0 Rank1 25(bit 2) - [HQALOG] 1600 TX_Window Channel1 Rank0 22(bit 9) - [HQALOG] 1600 TX_Window Channel1 Rank1 23(bit 9) - */ + mcSHOW_DBG_MSG(("TX_Window\n")); #ifdef FOR_HQA_REPORT_USED if (gHQALog_flag == 1) @@ -842,13 +773,6 @@ else #endif - /* - TX Min Window(%) - [HQALOG] 1600 TX_Window(%) Channel0 Rank0 79%(PASS) - [HQALOG] 1600 TX_Window(%) Channel0 Rank1 79%(PASS) - [HQALOG] 1600 TX_Window(%) Channel1 Rank0 69%(PASS) - [HQALOG] 1600 TX_Window(%) Channel1 Rank1 72%(PASS) - */ mcSHOW_DBG_MSG(("TX Min Window(%%)\n")); #ifdef FOR_HQA_REPORT_USED if (gHQALog_flag == 1) @@ -857,18 +781,13 @@ if (gHQALog_flag == 1) { for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { - /* - Item Data Rate Mode Status - 1 DDR1600 1:4 mode Done - 2 DDR1200 1:4 mode Done - 3 DDR800 1:4 mode 1UI=64PI special case - */ + HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT2, "TX", "_Window(%)", 0, (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32), NULL); HQA_Log_Message_for_Report(p, u1ChannelIdx, u1RankIdx, HQA_REPORT_FORMAT4, "TX", "_Window_PF", 0, 0, (min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP ? 63 : 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP ? 64 : 32) >= 45 ? "PASS" : "FAIL"); if (((min_tx_value[u1ChannelIdx][u1RankIdx] * 100 + (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32)) < 55) { - gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; //SLT_BIN4 + gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; } } } @@ -880,12 +799,7 @@ else { for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { - /* - Item Data Rate Mode Status - 1 DDR1600 1:4 mode Done - 2 DDR1200 1:4 mode Done - 3 DDR800 1:4 mode 1UI=64PI special case - */ + HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("TX_Window(%%) Channel%d " "Rank%d %d%% (%s)\n", @@ -902,12 +816,7 @@ else - /* - [Duty Calibration] - CLK Duty Final Delay Cell - [HQALOG] DUTY CLK_Final_Delay Channel0 0 - [HQALOG] DUTY CLK_Final_Delay Channel1 -2 - */ + #if !defined(RELEASE) && (VENDER_JV_LOG == 0) if (u1IsLP4Family(p->dram_type) && (Get_Duty_Calibration_Mode(p) != DUTY_DEFAULT)) { @@ -918,11 +827,7 @@ else HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY CLK_Final_Delay Channel%d %d\n", u1ChannelIdx, gFinalClkDuty[u1ChannelIdx])); } - /* - CLK Duty MAX - [HQALOG] DUTY CLK_MAX Channel0 4765%(X100) - [HQALOG] DUTY CLK_MAX Channel1 5212%(X100) - */ + mcSHOW_DBG_MSG(("CLK Duty MAX\n")); for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++) { @@ -938,11 +843,7 @@ else } } - /* - CLK Duty MIN - [HQALOG] DUTY CLK_MIN Channel0 4565%(X100) - [HQALOG] DUTY CLK_MIN Channel1 5012%(X100) - */ + mcSHOW_DBG_MSG(("CLK Duty MIN\n")); for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++) { @@ -954,7 +855,7 @@ else if ((gFinalClkDutyMinMax[u1ChannelIdx][1] - gFinalClkDutyMinMax[u1ChannelIdx][0]) > 750) { - gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3; //SLT_BIN3 + gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3; } } else @@ -970,13 +871,7 @@ else - /* - DQS Duty Final Delay Cell - [HQALOG] DUTY DQS_Final_Delay Channel0 DQS0 0 - [HQALOG] DUTY DQS_Final_Delay Channel0 DQS1 1 - [HQALOG] DUTY DQS_Final_Delay Channel1 DQS0 -2 - [HQALOG] DUTY DQS_Final_Delay Channel1 DQS1 -1 - */ + if (u1IsLP4Family(p->dram_type) && (Get_Duty_Calibration_Mode(p) != DUTY_DEFAULT)) { mcSHOW_DBG_MSG(("DQS Duty Final Delay Cell\n")); @@ -986,13 +881,6 @@ else HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("DUTY DQS_Final_Delay Channel%d DQS1 %d\n", u1ChannelIdx, gFinalDQSDuty[u1ChannelIdx][1])); } - /* - DQS Duty MAX - [HQALOG] DUTY DQS_MAX Channel0 DQS0 4765%(X100) - [HQALOG] DUTY DQS_MAX Channel0 DQS1 5212%(X100) - [HQALOG] DUTY DQS_MAX Channel1 DQS0 4765%(X100) - [HQALOG] DUTY DQS_MAX Channel1 DQS1 5212%(X100) - */ mcSHOW_DBG_MSG(("DQS Duty MAX\n")); for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++) { @@ -1010,13 +898,7 @@ else } } - /* - DQS Duty MIN - [HQALOG] DUTY DQS_MIN Channel0 DQS0 4765%(X100) - [HQALOG] DUTY DQS_MIN Channel0 DQS1 5212%(X100) - [HQALOG] DUTY DQS_MIN Channel1 DQS0 4765%(X100) - [HQALOG] DUTY DQS_MIN Channel1 DQS1 5212%(X100) - */ + mcSHOW_DBG_MSG(("DQS Duty MIN\n")); for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < local_channel_num; u1ChannelIdx++) { @@ -1030,7 +912,7 @@ else if (((gFinalDQSDutyMinMax[u1ChannelIdx][0][1] - gFinalDQSDutyMinMax[u1ChannelIdx][0][0]) > 750) || ((gFinalDQSDutyMinMax[u1ChannelIdx][1][1] - gFinalDQSDutyMinMax[u1ChannelIdx][1][0]) > 750)) { - gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3; //SLT_BIN3 + gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 3; } } else @@ -1063,7 +945,7 @@ else if (u1IsLP4Family(p->dram_type)) { mcSHOW_JV_LOG_MSG(("[Cmd Bus Training window]\n")); - //TO DO:jimmy + //mcSHOW_JV_LOG_MSG(("VrefCA Range : %d\n", gCBT_VREF_RANGE_SEL)); #if CHANNEL_NUM == 4 mcSHOW_JV_LOG_MSG(("CHA_VrefCA_Rank0 CHB_VrefCA_Rank0 CHC_VrefCA_Rank0 CHD_VrefCA_Rank0\n")); @@ -1187,7 +1069,7 @@ else #endif - // reset all data + HQA_measure_message_reset_all_data(p); } #ifdef RELEASE @@ -1224,7 +1106,7 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type } else { - //LP3 + local_channel_num = 1; } @@ -1236,14 +1118,14 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type if (print_type == EYESCAN_TYPE_RX) { - if (p->odt_onoff==TRUE) //tern + if (p->odt_onoff==TRUE) { if (p->dram_type==TYPE_LPDDR5) pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T; else pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T; } - else //un-tern + else { if (p->dram_type==TYPE_LPDDR5) pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT; @@ -1258,7 +1140,7 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type { if (u1CBTEyeScanEnable || u1TXEyeScanEnable) { - vddq = vGetVoltage(p, 2) / 1000; //mv + vddq = vGetVoltage(p, 2) / 1000; if (p->dram_type == TYPE_LPDDR4) { @@ -1354,7 +1236,7 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type { if ((Vcent_UpperBound_Window_percent < 30) || (Vcent_LowerBound_Window_percent < 30)) { - gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; //SLT_BIN4 + gHQALog_SLT_BIN[vGet_Current_SRAMIdx(p)] = 4; } } #endif @@ -1373,8 +1255,8 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type Perbit_Window_Upperbond_percent = ((gEyeScan_WinSize[EyeScanVcent[3] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000; Perbit_Window_Lowerbond_percent = ((gEyeScan_WinSize[EyeScanVcent[5] / EYESCAN_GRAPH_RX_VREF_STEP][u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p) * 2) + (1000000 - 1)) / 1000000; - Perbit_Eye_Height = (pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)]) / 100; //RX vref height last - first - Perbit_Eye_Area = gEyeScan_TotalPassCount[u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * (((pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)])) / ((((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff) - (gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)) * 10)) / 1000; //total count*jitter metter delay cell*(1/freq*10^6 ps)*(1330mv) + Perbit_Eye_Height = (pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)]) / 100; + Perbit_Eye_Area = gEyeScan_TotalPassCount[u1BitIdx] * gHQALOG_RX_delay_cell_ps_075V * (((pVref_Voltage_Table[VREF_RANGE_0][((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff)] - pVref_Voltage_Table[VREF_RANGE_0][(gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)])) / ((((gEyeScan_ContinueVrefHeight[u1BitIdx] >> 8) & 0xff) - (gEyeScan_ContinueVrefHeight[u1BitIdx] & 0xff)) * 10)) / 1000; } else //if (print_type==2) { @@ -1383,7 +1265,7 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type Perbit_Window_Upperbond_percent = ((gEyeScan_WinSize[(EyeScanVcent[2] * 30 + EyeScanVcent[3]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32; Perbit_Window_Lowerbond_percent = ((gEyeScan_WinSize[(EyeScanVcent[4] * 30 + EyeScanVcent[5]) / EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx]) * 100 + 31) / 32; Perbit_Eye_Height = (gEyeScan_ContinueVrefHeight[u1BitIdx] - 1) * 6 * vddq / 1000; - Perbit_Eye_Area = (gEyeScan_TotalPassCount[u1BitIdx] * 10 * 3 * vddq / (32 * DDRPhyGetRealFreq(p)))*100; //total count*1/32UI*(1/freq*10^6 ps)*(0.6%vddq) + Perbit_Eye_Area = (gEyeScan_TotalPassCount[u1BitIdx] * 10 * 3 * vddq / (32 * DDRPhyGetRealFreq(p)))*100; } HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, print_EYESCAN_LOG_type(print_type), "_Perbit_Window(%)", u1BitIdx, Perbit_Window_percent, NULL); @@ -1399,16 +1281,6 @@ static void print_EyeScanVcent_for_HQA_report_used(DRAMC_CTX_T *p, U8 print_type void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str) { - // HQA_REPORT_FORMAT0 : [HQALOG] 3200 Gating_Center_2T Channel0 Rank0 Byte0 3 - // HQA_REPORT_FORMAT0_1:[HQALOG] 3200 Gating_Center_2T Channel0 Rank0 Bit0 3 - // HQA_REPORT_FORMAT0_2:[HQALOG] 3200 Gating_Center_2T Channel0 Rank0 CA0 3 - // HQA_REPORT_FORMAT1 : [HQALOG] 3200 WriteLeveling_DQS0 Channel0 Rank0 35 - // HQA_REPORT_FORMAT2 : [HQALOG] 3200 TX_Final_Vref Vcent Channel0 Rank0 16860 - // HQA_REPORT_FORMAT2_1:[HQALOG] 3200 RX_Final_Vref Vcent Channel0 Rank0 B0 16860 - // HQA_REPORT_FORMAT3 : [HQALOG] 3200 DUTY CLK_MAX Channel0 5171 - // HQA_REPORT_FORMAT4 : [HQALOG] 3200 TX_Vcent_LowerBound_Window_PF Channel0 Rank0 PASS - // HQA_REPORT_FORMAT5 : [HQALOG] 3200 AAAAAAAAAAAA BBBBB - // HQA_REPORT_FORMAT6 : [HQALOG] 3200 AAAAAAAAAAAA 0 if (gHQALog_flag == 1) { @@ -1482,14 +1354,14 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, { u2DQDelayStep=4; u2VrefStep=EYESCAN_GRAPH_RX_VREF_STEP; - if (p->odt_onoff==TRUE) //tern + if (p->odt_onoff==TRUE) { if (p->dram_type==TYPE_LPDDR5) pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T; else pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T; } - else //un-tern + else { if (p->dram_type==TYPE_LPDDR5) pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT; @@ -1504,7 +1376,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, FinalDQCaliDelay = (U16)EyeScan_DelayCellPI_value; EyeScan_DelayCellPI_value = 0; - //pass region = 20%UI, = +-10$UI, 1UI=1/freq*10^6, 10%UI=((1/freq*10^6)/10)/delay cell + pass_region_h_value = PI_of_1_UI/10; delay_cell_ps = p->u2DelayCellTimex100; @@ -1519,7 +1391,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, { u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP; - //pass region = 20%UI, = +- 10%UI, 1UI=32PI, 10%UI=3PI + pass_region_h_value = 3; if (p->dram_type == TYPE_LPDDR4) @@ -1695,7 +1567,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, #endif { #if !VENDER_JV_LOG && !defined(RELEASE) - if ((i>=(FinalDQCaliDelay+EyeScan_DelayCellPI_value-(u2DQDelayStep/2)))&&(i<=(FinalDQCaliDelay+EyeScan_DelayCellPI_value+(u2DQDelayStep/2)))) //Final DQ delay + if ((i>=(FinalDQCaliDelay+EyeScan_DelayCellPI_value-(u2DQDelayStep/2)))&&(i<=(FinalDQCaliDelay+EyeScan_DelayCellPI_value+(u2DQDelayStep/2)))) { if (gEye_Scan_color_flag) { @@ -1707,7 +1579,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, } } else - if ((local_VrefIdx >= local_Final_VrefIdx-(u2VrefStep/2))&&(local_VrefIdx <= local_Final_VrefIdx+(u2VrefStep/2))) //Final Vref + if ((local_VrefIdx >= local_Final_VrefIdx-(u2VrefStep/2))&&(local_VrefIdx <= local_Final_VrefIdx+(u2VrefStep/2))) { if (gEye_Scan_color_flag) { @@ -1718,7 +1590,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, mcSHOW_EYESCAN_MSG(("V")); } } - else //spec in margin + else if (local_VrefIdx <= local_Upper_Vcent && local_VrefIdx >= local_Lower_Vcent && i >= (FinalDQCaliDelay + EyeScan_DelayCellPI_value - pass_region_h_value) && i <= (FinalDQCaliDelay + EyeScan_DelayCellPI_value + pass_region_h_value)) { if (gEye_Scan_color_flag) @@ -1730,7 +1602,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, mcSHOW_EYESCAN_MSG(("Q")); } } - else //pass margin + else #endif { #if VENDER_JV_LOG || defined(RELEASE) @@ -1787,7 +1659,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, #endif #endif { - //not valid + #if VENDER_JV_LOG || defined(RELEASE) if (gEye_Scan_color_flag) { @@ -1866,7 +1738,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, mcSHOW_EYESCAN_MSG((" --- ")); } #endif - //window + #if VENDER_JV_LOG || defined(RELEASE) mcSHOW_EYESCAN_MSG(("%dps", Final_EyeScan_winsize * delay_cell_ps / 100)); #else @@ -1898,7 +1770,7 @@ static void EyeScan_Pic_draw_line(DRAMC_CTX_T *p, U8 draw_type, U8 u1VrefRange, mcSHOW_EYESCAN_MSG((" --- ")); } #endif - //window + #if VENDER_JV_LOG || defined(RELEASE) mcSHOW_EYESCAN_MSG(("%dps", Final_EyeScan_winsize * delay_cell_ps / 100)); #else @@ -1953,14 +1825,14 @@ void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type) { u2VrefStep = EYESCAN_GRAPH_RX_VREF_STEP; - if (p->odt_onoff==TRUE) //tern + if (p->odt_onoff==TRUE) { if (p->dram_type==TYPE_LPDDR5) pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_T; else pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P6V_T; } - else //un-tern + else { if (p->dram_type==TYPE_LPDDR5) pVref_Voltage_Table[VREF_RANGE_0] = (U16 *)gRXVref_Voltage_Table_0P5V_UT; @@ -1992,30 +1864,27 @@ void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type) u1RXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_RX); u1TXEyeScanEnable = GetEyeScanEnable(p, EYESCAN_TYPE_TX); -#if 0 //fra test +#if 0 u1CBTEyeScanEnable = u1CBTEyeScanEnable & (p->channel == 0 && p->rank == 0); #endif -/************************************************************************************** - CBT/RX/TX EYESCAN log -***************************************************************************************/ if (print_type == EYESCAN_TYPE_CBT) { - if (p->frequency <= 934) VdlVWTotal = 17500; //VcIVW 175mv - else if (p->frequency <= 1600) VdlVWTotal = 15500; //VcIVW 155mv - else VdlVWTotal = 14500; //VcIVW 145mv + if (p->frequency <= 934) VdlVWTotal = 17500; + else if (p->frequency <= 1600) VdlVWTotal = 15500; + else VdlVWTotal = 14500; } else { #if 0 - if (p->frequency <= 1600) VdlVWTotal = 10000; //14000; //140mv - else VdlVWTotal = 10000; //12000; //120mv + if (p->frequency <= 1600) VdlVWTotal = 10000; + else VdlVWTotal = 10000; #else VdlVWTotal = 10000; #endif } - if (p->dram_type!=TYPE_LPDDR5)//LP5 no range + if (p->dram_type!=TYPE_LPDDR5) { CBTVrefRange = (u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1; TXVrefRange = (u1MR14Value[p->channel][p->rank][p->dram_fsp] >> 6) & 1; @@ -2033,7 +1902,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) #if 1 //#if !VENDER_JV_LOG && !defined(RELEASE) if ((print_type == EYESCAN_TYPE_CBT && u1CBTEyeScanEnable) || (print_type == EYESCAN_TYPE_RX && u1RXEyeScanEnable) || (print_type == EYESCAN_TYPE_TX && u1TXEyeScanEnable)) { - vddq = vGetVoltage(p, 2) / 1000; //mv + vddq = vGetVoltage(p, 2) / 1000; EYESCAN_LOG_Print_Prefix_String(); mcSHOW_DBG_MSG(("VDDQ=%dmV\n", vddq)); if (print_type == EYESCAN_TYPE_CBT) @@ -2054,7 +1923,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) finalVrefRange = 0; finalVref = gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx]; - cal_length = DQS_BIT_NUMBER; //p->data_width; + cal_length = DQS_BIT_NUMBER; } else//if (print_type==2) { @@ -2095,7 +1964,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) } - //find VdlVWHigh first + if (print_type == EYESCAN_TYPE_RX) { VdlVWHigh_Upper_Vcent_Range = 0; @@ -2126,7 +1995,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) { if (pVref_Voltage_Table[vrefrange_i][i] - Vcent_DQ >= VdlVWTotal / 2) { - /* find VdlVWHigh upper bound */ + VdlVWHigh_Upper_Vcent = i; break; } @@ -2135,7 +2004,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) { if (((pVref_Voltage_Table[vrefrange_i][i] * vddq / 100 - Vcent_DQ)) >= VdlVWTotal / 2) { - /* find VdlVWHigh upper bound */ + VdlVWHigh_Upper_Vcent = i; VdlVWHigh_Upper_Vcent_Range = vrefrange_i; break; @@ -2165,7 +2034,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) } - //find VldVWLow first + VdlVWHigh_Lower_Vcent_Range = 0; VdlVWHigh_Lower_Vcent = 0; vrefrange_i = finalVrefRange; @@ -2175,7 +2044,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) { if (Vcent_DQ - pVref_Voltage_Table[vrefrange_i][i] >= VdlVWTotal / 2) { - /* find VdlVWHigh lower bound */ + VdlVWHigh_Lower_Vcent = i; break; } @@ -2184,7 +2053,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) { if (((Vcent_DQ - pVref_Voltage_Table[vrefrange_i][i] * vddq / 100)) >= VdlVWTotal / 2) { - /* find VdlVWHigh lower bound */ + VdlVWHigh_Lower_Vcent = i; VdlVWHigh_Lower_Vcent_Range = vrefrange_i; break; @@ -2238,7 +2107,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) { if (print_type != EYESCAN_TYPE_RX) { - // compare Upper/Lower Vcent pass criterion is pass or fail? + for (u1VrefIdx = finalVref + finalVrefRange * 30; u1VrefIdx <= (S8)(VdlVWHigh_Upper_Vcent + VdlVWHigh_Upper_Vcent_Range * 30); u1VrefIdx += u2VrefStep) { Upper_Vcent_pass_flag = 0; @@ -2251,7 +2120,7 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) Upper_Vcent_pass_flag = 1; } } - if (Upper_Vcent_pass_flag == 0) break; // fail!! + if (Upper_Vcent_pass_flag == 0) break; } for (u1VrefIdx = VdlVWHigh_Lower_Vcent + VdlVWHigh_Lower_Vcent_Range * 30; u1VrefIdx <= (S8)(finalVref + finalVrefRange * 30); u1VrefIdx += u2VrefStep) { @@ -2265,12 +2134,12 @@ for (u1ByteIdx = u1ByteIdx_Begin; u1ByteIdx <= u1ByteIdx_End; u1ByteIdx++) Lower_Vcent_pass_flag = 1; } } - if (Lower_Vcent_pass_flag == 0) break; //fail!! + if (Lower_Vcent_pass_flag == 0) break; } } #ifdef FOR_HQA_TEST_USED - //find VdlVWBest Vref Range and Vref + VdlVWBest_Vcent_Range = 1; VdlVWBest_Vcent = VREF_VOLTAGE_TABLE_NUM_LP4- 1; if (print_type == EYESCAN_TYPE_RX||(print_type != EYESCAN_TYPE_RX&&p->dram_type==TYPE_LPDDR5)) vrefrange_i = 0; @@ -2481,7 +2350,7 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("\n\n[Pin Info Summary] Freqency %d\n", p->frequency)); - for (u1FreqRegionIdx=0;u1FreqRegionIdx<2/*IMP_VREF_MAX*/;u1FreqRegionIdx++) + for (u1FreqRegionIdx=0;u1FreqRegionIdx<2;u1FreqRegionIdx++) { for (u1ImpIdx=0;u1ImpIdx<IMP_DRV_MAX;u1ImpIdx++) { @@ -2498,10 +2367,10 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p) { mcSHOW_DBG_MSG3(("CH %d, Rank %d\n", u1CHIdx, u1RankIdx)); - //CA pin check + for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++) { - #if 1//Transfer to Percentage + #if 1 PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]= (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]* 100 + 63) /64; if ((PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]==0)||(PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]<=PERCENTAGE_THRESHOLD)) #else @@ -2519,15 +2388,15 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p) } - //DQ pin check + for (u1BitIdx =0; u1BitIdx <DQ_DATA_WIDTH; u1BitIdx++) { u1ByteIdx = (u1BitIdx>=8?1:0); u1BitIdx_DQ = uiLPDDR4_O1_Mapping_POP[p->channel][u1BitIdx]; u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0); - //RX - #if 1//Transfer to Percentage + + #if 1 PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = ((PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* gHQALOG_RX_delay_cell_ps_075V * DDRPhyGetRealFreq(p)* 2)+ (1000000 - 1)) / 1000000; if (PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD) #else @@ -2540,8 +2409,8 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p) PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2+1)); } - //TX - #if 1//Transfer to Percentage + + #if 1 PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx] = (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]* 100+ (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 63: 31)) / (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP? 64: 32); if (PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][u1BitIdx]<=PERCENTAGE_THRESHOLD) #else @@ -2577,16 +2446,16 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) { U8 u1CHIdx, u1CHIdx_EMI, u1RankIdx, u1CAIdx, u1ByteIdx, u1BitIdx, u1FreqRegionIdx, u1ImpIdx; - //pErrorTypeInfo = "ERROR TYPE TEST"; + mcSHOW_DBG_MSG3(("\n[Get Pin Error Type Result]\n")); - if (PINInfo_flashtool.TOTAL_ERR==0 && PINInfo_flashtool.IMP_ERR_FLAG==0)//ALL PASS + if (PINInfo_flashtool.TOTAL_ERR==0 && PINInfo_flashtool.IMP_ERR_FLAG==0) { mcSHOW_DBG_MSG3(("ALL PASS\n")); } - //TYPE 1: Impedance calibration fail + if (PINInfo_flashtool.IMP_ERR_FLAG) { mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: Impedance calibration fail\n")); @@ -2594,7 +2463,7 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("Suspect EXTR related resistor contact issue\n")); } - //TYPE 2: ALL CH ALL Cal FAIL + if ((PINInfo_flashtool.TOTAL_ERR == 0xffff) && (PINInfo_flashtool.WL_ERR_FLAG== 0xff)) { mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: ALL calibration fail\n")); @@ -2611,12 +2480,12 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) u1CHIdx_EMI = CHANNEL_C; else if(u1CHIdx == CHANNEL_C) u1CHIdx_EMI = CHANNEL_B; - else //CHANNEL_A,CHANNEL_D + else } #endif u1CHIdx_EMI = u1CHIdx; - //TYPE 3: ONE CH ALL RK ALL Cal FAIL + if ((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4) & 0xf) == 0xf) { mcSHOW_DBG_MSG3(("[CHECK RESULT] FAIL: CH%d all calibration fail\n",u1CHIdx)); @@ -2631,7 +2500,7 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) { for(u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) { - //TYPE 4: ONE CH ONE RK ALL Cal FAIL + if ((((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4+u1RankIdx*2)) & 0x3)==0x3) && \ (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \ (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff)&& \ @@ -2646,7 +2515,7 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) { for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) { - //TYPE 5: ONE CH ONE RK ONE Byte FAIL + if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) &&\ (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff)) { @@ -2654,7 +2523,7 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("Suspect EMI%d_DQS%d_T contact issue\n",u1CHIdx_EMI,u1ByteIdx)); mcSHOW_DBG_MSG3(("Suspect EMI%d_DQS%d_C contact issue\n",u1CHIdx_EMI,u1ByteIdx)); } - //TYPE 6: ONE CH ONE RK ONE Bit FAIL + else if (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]&&\ PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]) { @@ -2668,7 +2537,7 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p) } } } - //TYPE 7: ONE CH ONE RK ONE Byte FAIL(only RX or TX) -->OTHERS + else if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) ||\ (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff)) { @@ -2716,9 +2585,9 @@ void DramcGatingDebugInit(DRAMC_CTX_T *p) } vSetPHY2ChannelMapping(p, backup_channel); - //Disable MR4 MR18/MR19, TxHWTracking, Dummy RD before reset - vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS); //MR4 Disable - vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); //MR18, MR19 Disable + + vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS); + vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); for (shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++) vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV + SHU_GRP_DRAMC_OFFSET * shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS); vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) @@ -2729,7 +2598,7 @@ void DramcGatingDebugInit(DRAMC_CTX_T *p) DramPhyReset(p); - //Restore backup regs + for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) { vSetPHY2ChannelMapping(p, channel_idx); @@ -2742,19 +2611,19 @@ void DramcGatingDebugInit(DRAMC_CTX_T *p) vSetPHY2ChannelMapping(p, backup_channel); - //enable &reset DQS counter + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTEN); - mcDELAY_US(4);//wait 1 auto refresh after DQS Counter enable + mcDELAY_US(4); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_DQSGCNTRST); - mcDELAY_US(1);//delay 2T + mcDELAY_US(1); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTRST); //mcSHOW_DBG_MSG(("DramcGatingDebugInit done\n" )); } void DramcGatingDebugExit(DRAMC_CTX_T *p) { - //enable &reset DQS counter + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_DQSGCNTEN); vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT); } @@ -2779,14 +2648,14 @@ static void DramcGatingDebug(DRAMC_CTX_T *p, U8 u1Channel) u4all_result_R = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8); - // falling + LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK0_F), MISC_STBERR_RK0_F_STBERR_RK0_F)); LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff; LP3_DataPerByte[0] &= 0xff; u4all_result_F = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8); - //read DQS counter + u4DebugCnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DQSGNWCNT0)); u4DebugCnt[1] = (u4DebugCnt[0] >> 16) & 0xffff; u4DebugCnt[0] &= 0xffff; @@ -2804,14 +2673,14 @@ static void DramcGatingDebug(DRAMC_CTX_T *p, U8 u1Channel) if (p->support_rank_num == RANK_DUAL) { - LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_R), MISC_STBERR_RK1_R_STBERR_RK1_R));//PHY_B + LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_R), MISC_STBERR_RK1_R_STBERR_RK1_R)); LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff; LP3_DataPerByte[0] &= 0xff; u4all_result_R = LP3_DataPerByte[0] | (LP3_DataPerByte[2] << 8); - // falling - LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_F), MISC_STBERR_RK1_F_STBERR_RK1_F));//PHY_B + + LP3_DataPerByte[0] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_STBERR_RK1_F), MISC_STBERR_RK1_F_STBERR_RK1_F)); LP3_DataPerByte[2] = (LP3_DataPerByte[0] >> 8) & 0xff; LP3_DataPerByte[0] &= 0xff; @@ -2841,7 +2710,7 @@ static void DramcGatingDebug(DRAMC_CTX_T *p, U8 u1Channel) void DramcDumpDebugInfo(DRAMC_CTX_T *p) { -U8 u1RefreshRate; //mpdivInSel, cali_shu_sel, mpdiv_shu_sel +U8 u1RefreshRate; DRAM_CHANNEL_T channelIdx; @@ -2886,13 +2755,13 @@ DRAM_CHANNEL_T channelIdx; cali_shu_sel = u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL, SHUCTRL_R_OTHER_SHU_GP); mpdiv_shu_sel = u4IO32ReadFldAlign(DRAMC_REG_SHUCTRL, SHUCTRL_R_MPDIV_SHU_GP); - // Read shuffle selection + mcSHOW_DBG_MSG2(("\n\n[DumpDebugInfo]\n" "\tmpdivInSel %d, cali_shu_sel %d, mpdiv_shu_sel %d\n", mpdivInSel, cali_shu_sel, mpdiv_shu_sel)); #if GATING_ONLY_FOR_DEBUG - // Read gating error flag + //DramcGatingDebugInit(p); for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++) { @@ -2901,7 +2770,7 @@ DRAM_CHANNEL_T channelIdx; #endif #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - // Read HW gating tracking + #ifdef HW_GATING for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++) { @@ -2955,10 +2824,10 @@ static void DramcRegDumpRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) { mcSHOW_DBG_MSG(("Reg(0x%xh) Address 0x%X = 0x%X\n", (ii & 0xfff) >> 2, ii, u4Dram_Register_Read(p, DRAMC_REG_ADDR(ii)))); - mcDELAY_US(20000); //Large delay to prevent UART overflow + mcDELAY_US(20000); } } - #if 0//(fcFOR_CHIP_ID == fcLafite) + #if 0 #define DRAMC_NAO_DUMP_RANGE (DRAMC_REG_RK2_B23_STB_DBG_INFO_15 - DRAMC_NAO_BASE_ADDRESS) #define DDRPHY_NAO_DUMP_RANGE (DDRPHY_MISC_MBIST_STATUS2 - DDRPHY_NAO_BASE_ADDR) #define DRAMC_AO_NONSHU_DUMP_RANGE (DRAMC_REG_RK1_PRE_TDQSCK27 - DRAMC_AO_BASE_ADDRESS) @@ -3104,7 +2973,7 @@ void DumpAllChAllShuAllRkRG(DRAMC_CTX_T *p) } static void DumpShuRG(DRAMC_CTX_T *p) { - DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; // from dramc conf shu0 + DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; U8 u1ShuffleIdx; U32 u4DramcShuOffset = 0; U32 u4DDRPhyShuOffset = 0; @@ -3124,24 +2993,24 @@ static void DumpShuRG(DRAMC_CTX_T *p) #endif }; DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); DumpAllRkRG(p,NONSHUFFLE_RG); - for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX) + for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) { if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX) { - vSetDFSTable(p, pFreqTable);//Restore DFS table + vSetDFSTable(p, pFreqTable); u4DramcShuOffset = 0; u4DDRPhyShuOffset = 0; DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); } else { - vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx));//Update DFS table - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting + vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx)); + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);//Trigger DEBUG MODE + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; DumpAllRkRG(p,SHUFFLE_RG); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; @@ -3197,8 +3066,8 @@ void DramcModeReg_Check(DRAMC_CTX_T *p) { U8 backup_channel, backup_rank; U8 u1ChannelIdx, u1RankIdx; - U8 u1MRFsp; //operating_fsp = p->dram_fsp - U8 ii, u1MR[] = {5, 12, 14, 4, 18, 19}; //MR5, MR12, MR14, MR18, MR19 + U8 u1MRFsp; + U8 ii, u1MR[] = {5, 12, 14, 4, 18, 19}; U16 u2MRValue = 0, u2Value = 0; U8 u1match = 0; U8 backup_u1MR13Value[RANK_MAX] = {0}; @@ -3257,9 +3126,9 @@ void DramcModeReg_Check(DRAMC_CTX_T *p) #endif if (u1MRFsp == FSP_1) - u1MR13Value[u1RankIdx] |= 0x40; //Read/Write FSP + u1MR13Value[u1RankIdx] |= 0x40; else - u1MR13Value[u1RankIdx] &= (~0x40); //Read/Write FSP + u1MR13Value[u1RankIdx] &= (~0x40); DramcModeRegWriteByRank(p, u1RankIdx, 13, u1MR13Value[u1RankIdx]); @@ -3268,7 +3137,7 @@ void DramcModeReg_Check(DRAMC_CTX_T *p) DramcModeRegReadByRank(p, u1RankIdx, u1MR[ii], &u2Value); u2Value &= 0xFF; - if ((u1MR[ii] == 12) || (u1MR[ii] == 14)) //need to compare final setting with global variants + if ((u1MR[ii] == 12) || (u1MR[ii] == 14)) { if (u1MR[ii] == 12) { @@ -3310,7 +3179,7 @@ void DramcModeReg_Check(DRAMC_CTX_T *p) const char *str_vender = ""; if (u1MR[ii] == 5) { - //Vendor ID 1: Samsung, 6: Hynix + str_vender = (u2Value == 1)? "Samsung":(u2Value==0xff)?"Micron":(u2Value==0x5)?"Nanya":(u2Value==0x6)?"Hynix":"mismatch"; } mcSHOW_DBG_MSG2(("\t\tMR%d = 0x%x %s\n", u1MR[ii], u2Value, str_vender)); @@ -3319,7 +3188,7 @@ void DramcModeReg_Check(DRAMC_CTX_T *p) } - // resotre MR13 settings + u1MR13Value[u1RankIdx] = backup_u1MR13Value[u1RankIdx]; } } @@ -3382,11 +3251,11 @@ void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p) for (u1MRIdx = 0; u1MRIdx < MR_NUM; u1MRIdx++) { u2MRValue = u2MRRecord[u1CHIdx][u1RankIdx][u1FSPIdx][u1MRIdx]; - if (u2MRValue != 0xffff) //value changed + if (u2MRValue != 0xffff) { mcSHOW_MRW_MSG(("[MR Dump] CH%d Rank%d Fsp%d MR%d =0x%x\n", p->channel, p->rank, gFSPWR_Flag[p->rank], u1MRIdx, u2MRValue)); #if MRW_BACKUP - //MR13(LP4) work around, two RG is not synchronized + { if (u1MRIdx==13) gFSPWR_Flag[p->rank]=u1Backup_Fsp; @@ -3445,15 +3314,15 @@ static void BackupRGBeforeTestMode(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("***CHB\n")); } - u4TestModeV0[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0));//MRS_MRSRK + u4TestModeV0[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); mcSHOW_DBG_MSG5(("DRAMC_REG_MRS[0x%x]\n", u4TestModeV0[i])); u4TestModeV1[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); mcSHOW_DBG_MSG5(("DRAMC_REG_DRAMC_PD_CTRL[0x%x]\n", u4TestModeV1[i])); - u4TestModeV2[i] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL));//STBCAL_DQSIENCG_NORMAL_EN + u4TestModeV2[i] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)); mcSHOW_DBG_MSG5(("DRAMC_REG_STBCAL[0x%x]\n", u4TestModeV2[i])); - u4TestModeV3[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0));//Auto refresh + u4TestModeV3[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)); mcSHOW_DBG_MSG5(("DRAMC_REG_REFCTRL0[0x%x]\n", u4TestModeV3[i])); - u4TestModeV4[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_HMR4));//HW MR4 + u4TestModeV4[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_HMR4)); mcSHOW_DBG_MSG5(("DRAMC_REG_SPCMDCTRL[0x%x]\n", u4TestModeV4[i])); u4TestModeV5[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); mcSHOW_DBG_MSG5(("DRAMC_REG_CKECTRL[0x%x]\n", u4TestModeV5[i])); @@ -3532,12 +3401,12 @@ void ProgramModeEnter(DRAMC_CTX_T *p) } vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); - //Disable dramc and DDRPHY clock gated, let clock freerun + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); - //Disable MR4, refresh + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 1, CKECTRL_CKEFIXON); @@ -3580,7 +3449,7 @@ void ProgramCodeInput(DRAMC_CTX_T *p, U16 u2A_value, U16 u2B_value, U16 u2C_valu BackupRGBeforeTestMode(p); p->channel = CHANNEL_A; - //CA0, CA1, CA2, CA3, CA4, CA5 + U8 PCI_Key[5][6] = { { 0, 0, 0, 0, 0, 0}, @@ -3642,12 +3511,12 @@ void ProgramCodeInput(DRAMC_CTX_T *p, U16 u2A_value, U16 u2B_value, U16 u2C_valu } vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); - //Disable dramc and DDRPHY clock gated, let clock freerun + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); - //Disable MR4, refresh + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), 1, CKECTRL_CKEFIXON); @@ -3681,8 +3550,7 @@ void ProgramCodeInput(DRAMC_CTX_T *p, U16 u2A_value, U16 u2B_value, U16 u2C_valu void vApplyProgramSequence(DRAMC_CTX_T *p) { #if SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 1 - //Buffer sensitivity decrease1 - //test 2. TMRS enter -> 000 -> 390 -> 120 -> 8A7 + ProgramModeEnter(p); ProgramCodeInput(p, 0, 0, 0); ProgramCodeInput(p, 3, 9, 0); @@ -3692,8 +3560,7 @@ void vApplyProgramSequence(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 120 -> 8A7 -> 258\n")); #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 2 - //Buffer sensitivity decrease2 - //test 3. TMRS enter -> 000 -> 390 -> 120 -> 803 + ProgramModeEnter(p); ProgramCodeInput(p, 0, 0, 0); ProgramCodeInput(p, 3, 9, 0); @@ -3703,8 +3570,7 @@ void vApplyProgramSequence(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("Buffer sensitivity decrease1: TMRS enter -> 000 -> 390 -> 120 -> 803 -> 258\n")); #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 3 - //2014 + 2863 - //test 4.TMRS enter -> 000 -> 390 -> 120 -> 014 -> 863 + ProgramModeEnter(p); ProgramCodeInput(p, 0, 0, 0); ProgramCodeInput(p, 3, 9, 0); @@ -3715,8 +3581,7 @@ void vApplyProgramSequence(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("2014 + 2863: test 4.TMRS enter -> 000 -> 390 -> 120 -> 014 -> 863 -> 258\n")); #elif SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER == 4 - //252A - //test 5. TMRS enter -> 000 -> 390 -> 120 -> 52A + ProgramModeEnter(p); ProgramCodeInput(p, 0, 0, 0); ProgramCodeInput(p, 3, 9, 0); @@ -3734,7 +3599,7 @@ void vApplyProgramSequence(DRAMC_CTX_T *p) } #else - //test 1. TMRS enter -> 000 -> 390 -> 021 + ProgramModeEnter(p); ProgramCodeInput(p, 0, 0, 0); ProgramCodeInput(p, 3, 9, 0); @@ -3782,23 +3647,23 @@ void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p) U32 u4RegBackupAddress[] = { - // Rx shmoo backup RG - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5)), //RX Vref - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5)), //RX Vref - //RK0 - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY3)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)), //RX DQM Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)), //RX DQS Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY1)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY2)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY3)), //RX DQ Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)), //RX DQM Delay - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)), //RX DQS Delay - //RK1 + + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ5)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5)), + + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY3)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY1)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY2)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY3)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+DDRPHY_AO_RANK_OFFSET)), (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY1+DDRPHY_AO_RANK_OFFSET)), (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY2+DDRPHY_AO_RANK_OFFSET)), @@ -3813,28 +3678,28 @@ void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p) (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5+DDRPHY_AO_RANK_OFFSET)), - // Tx shmoo backup RG - //RK0 - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI)), //TX tracking DQ PI Delay - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)), //TX DQ MCK Delay - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)), //TX DQM MCK Delay - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)), //TX DQ UI Delay - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)), //TX DQM UI Delay - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1)), //TX Tracking Source DQ - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2)), //TX Tracking Target DQ - (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5)), //TX Tracking Target DQM - - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0)), //TX DQ per bit delay cell bit0~3 - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1)), //TX DQ per bit delay cell bit4~7 - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0)), //TX DQ per bit delay cell bit8~11 - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1)), //TX DQ per bit delay cell bit12~15 - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3)), //TX DQM WCK WCK_B delay cell - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3)), //TX DQM WCK WCK_B delay cell - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), //TX DQ WCK PI Delay (TX Calibration) - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), //TX DQ WCK PI Delay (TX Calibration) - //(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)), //CA CLK Delay - - //RK1 + + + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2)), + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5)), + + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), + + + (DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI+DRAMC_REG_AO_RANK_OFFSET )), (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+DRAMC_REG_AO_RANK_OFFSET)), (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1+DRAMC_REG_AO_RANK_OFFSET)), @@ -3878,7 +3743,7 @@ void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p) } vSetPHY2ChannelMapping(p, channel_backup); - //DramcRegDump(p);//for run time Tx eye scan RG check + //DramcRegDump(p); } #endif @@ -3887,17 +3752,17 @@ void CKEFixOnOff_dbg(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CHANNE { U8 u1CKEOn, u1CKEOff, u1setChannel, u1BackupChannel; - if (option == CKE_DYNAMIC) //if CKE is dynamic, set both CKE fix On and Off as 0 - { //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) + if (option == CKE_DYNAMIC) + { u1CKEOn = u1CKEOff = 0; } - else //if CKE fix on is set as 1, CKE fix off should also be set as 0; vice versa + else { u1CKEOn = option; u1CKEOff = (1 - option); } - if (WriteChannelNUM == TO_ALL_CHANNEL) //write register to all channel + if (WriteChannelNUM == TO_ALL_CHANNEL) { if((u1RankIdx == RANK_0)||(u1RankIdx == TO_ALL_RANK)) { @@ -3934,13 +3799,13 @@ void DramcModeRegWrite_DcmOff(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Value) u4register_dcm = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_MIOCKCTRLOFF);/* MIOCKCTRLOFF = 1 */ - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN2);/* DCMEN2 = 0 */ - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN);/* PHYCLKDYNGEN = 0 */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_MIOCKCTRLOFF); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_DCMEN2); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_PHYCLKDYNGEN); DramcModeRegWrite_111(p, u1MRIdx, u1Value); - vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4register_dcm); //restore DCM setting + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4register_dcm); } #endif @@ -3972,10 +3837,10 @@ void Get_TA2_ErrCnt(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("flag 14C:0x%x\n", u4Value)); { - //Choose which Byte of TA2 error count + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), iByte, TEST2_A3_ERRFLAG_BYTE_SEL); - //Byte by TEST2_A3_ERRFLAG_BYTE_SEL + u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_RF_ERROR_CNT1)); mcSHOW_DBG_MSG(("150:0x%x ", u4Value)); @@ -4019,8 +3884,8 @@ void Modify_TX_Delay_Cell(DRAMC_CTX_T *p, int i) while(1); } - //Choose which Byte of TA2 error count - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u4value, TEST2_A3_ERRFLAG_BYTE_SEL);//Should set before TA2 trigger + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), u4value, TEST2_A3_ERRFLAG_BYTE_SEL); mcSHOW_DBG_MSG(("********** Modify_TX_Delay_Cell %d **********\n", i)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), @@ -4050,7 +3915,7 @@ void Modify_TX_Delay_Cell(DRAMC_CTX_T *p, int i) } #endif -#if 0//1. Test2agent R/F fail flag; Test agent compare error counter +#if 0 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) { int i=0; @@ -4091,11 +3956,10 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) while(u1StopMiniStress){mcDELAY_MS(1000);} #ifdef TA2_STRESS - // HW mode: RKSEL=4, RWOFOEN = from 0 to 1 - //@Darren, If single rank RWOFOEN = 1 (always) and enable tx tracking is available. + TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW); - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Write(p, ENABLE); #endif #ifdef FAKE_ENGINE_STRESS @@ -4108,15 +3972,15 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) Get_TA2_ErrCnt(p); #ifdef TA2_STRESS - TA2_Test_Run_Time_HW_Status(p);//Check TA2 status + TA2_Test_Run_Time_HW_Status(p); #endif - //Error inject + vSetPHY2ChannelMapping(p, (i++) % p->support_channel_num); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ - P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0)) //MCK + P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0)) //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), - // P_Fld(6, SHURK_SELPH_DQ2_DLY_DQ0)); //UI + // P_Fld(6, SHURK_SELPH_DQ2_DLY_DQ0)); //vSetRank(p, RANK_1); //Modify_TX_Delay_Cell(p, (i++)%16); //Delay cell @@ -4126,7 +3990,7 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) } #endif -#if 0 //2. TA2 R/W with identify RID/AID +#if 0 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) { U32 u4BackupDQSOSCENDIS = 0; @@ -4160,7 +4024,7 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) } #endif - TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);//Use worst SI + TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF); do { while(u1StopMiniStress){mcDELAY_MS(1000);} @@ -4170,45 +4034,44 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) { DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); - //Disable MR4 MR18/MR19, TxHWTracking, Dummy RD before reset - vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS); //MR4 Disable + + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS); u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP); u4BackupDQSOSCENDIS = u4IO32Read4B(DRAMC_REG_SHU_DQSOSC_SET0 + (SHU_GRP_DRAMC_OFFSET * u1ShuLevel)); - vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); //MR18, MR19 Disable + vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), 0x1, SHU_DQSOSC_SET0_DQSOSCENDIS); vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)); - // XRT mode: RKSEL=3, RWOFOEN = from 1 to 0 + //TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON); - TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT); //enhance XRT R2R W2W test, TEST2_2_TEST2_OFF=0x400 - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W - TA2_Test_Run_Time_HW_Status(p);//Check TA2 status + TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT); + TA2_Test_Run_Time_HW_Write(p, ENABLE); + TA2_Test_Run_Time_HW_Status(p); } #endif #ifdef TA2_STRESS - // HW mode: RKSEL=4, RWOFOEN = from 0 to 1 - //@Darren, If single rank RWOFOEN = 1 (always) and enable tx tracking is available. + //TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON); TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW); - //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF);//TODO: Need to find out the reason + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF); if (p->support_rank_num==RANK_DUAL) { - //@Darren, Fixed TA2 overnight stress r/w fail (Don't enable tx tracking when RWOFOEN=0) + vIO32Write4B_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), u4BackupDQSOSCENDIS); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); } - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Write(p, ENABLE); #endif #ifdef FAKE_ENGINE_STRESS if(u1IsLP4Family(p->dram_type)) { - //static U8 trans_type = W; + //Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 2); static U8 trans_type = W; Do_Memory_Test_Fake_Engine_Presetting(p, (trans_type++) % 3); @@ -4217,13 +4080,13 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) #endif #if (DRAMC_DFS_MODE != 3) - DFSTestProgram(p, 0); // Should open after DVFS is ready + DFSTestProgram(p, 0); #else - GetPhyPllFrequency(p); // for DPM PST mode + GetPhyPllFrequency(p); #endif #ifdef TA2_STRESS - TA2_Test_Run_Time_HW_Status(p);//Check TA2 status + TA2_Test_Run_Time_HW_Status(p); #endif #ifdef FAKE_ENGINE_STRESS @@ -4277,7 +4140,7 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) } #endif -#if 0 //3. Loop mode (loop time 2^n/ never end/error break) +#if 0 void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) { int i=0; @@ -4295,7 +4158,7 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_TA2_LOOP_EN); vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_LOOP_NV_END); vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, 1, TEST2_A0_ERR_BREAK_EN); - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Write(p, ENABLE); do { while(u1StopMiniStress){mcDELAY_MS(1000);} @@ -4309,13 +4172,13 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) //Get_TA2_ErrCnt(p); Get_TA2_ST(p); - //Error inject + if(i==20) { mcSHOW_DBG_MSG(("!!! Error Injection in CHA\n")); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ - P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0)) //MCK + P_Fld(7, SHURK_SELPH_DQ0_TXDLY_DQ0)) } i++; } while(1); @@ -4323,13 +4186,13 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) } #endif -#if 0 //pst mode +#if 0 typedef enum { SIDLE_SR_S1_S0 = 0, SIDLE_SR_S1, } ETT_STRESS_LPS; -void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 could compare data +void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) { U32 u4BackupDQSOSCENDIS = 0; U8 u1ShuLevel = 0; @@ -4366,20 +4229,20 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 c do { while(u1StopMiniStress){mcDELAY_MS(1000);} -#if 1 //low power OK +#if 1 if(iTestCnt % 10 == 0) { bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0); mcSHOW_DBG_MSG(("*** Stop delay then start\n")); - Reg_Sync_Writel(0x10940020, 0x00000000);// GPR0 //S1, SR, idle - Reg_Sync_Writel(0x10A40020, 0x00000000);// GPR0 + Reg_Sync_Writel(0x10940020, 0x00000000); + Reg_Sync_Writel(0x10A40020, 0x00000000); - Reg_Sync_Writel(0x10940028, 0x00000003);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x00000003);// GPR2 + Reg_Sync_Writel(0x10940028, 0x00000003); + Reg_Sync_Writel(0x10A40028, 0x00000003); - Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX to stop low power flow - Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX to stop low power flow + Reg_Sync_Writel(0x109400A0, 1); + Reg_Sync_Writel(0x10A400A0, 1); mcDELAY_MS(100); @@ -4387,80 +4250,80 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 c { mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n")); - Reg_Sync_Writel(0x10940020, 0x00010203);// GPR0 //S0, S1, SR, idle - Reg_Sync_Writel(0x10A40020, 0x00010203);// GPR0 + Reg_Sync_Writel(0x10940020, 0x00010203); + Reg_Sync_Writel(0x10A40020, 0x00010203); - Reg_Sync_Writel(0x10940028, 0x80000004);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x80000004);// GPR2 + Reg_Sync_Writel(0x10940028, 0x80000004); + Reg_Sync_Writel(0x10A40028, 0x80000004); bTa2_stress_enable = 0; } else { mcSHOW_DBG_MSG(("*** SIDLE_SR_S1 stop then start\n")); - Reg_Sync_Writel(0x10940020, 0x00010200);// GPR0 //S1, SR, idle - Reg_Sync_Writel(0x10A40020, 0x00010200);// GPR0 + Reg_Sync_Writel(0x10940020, 0x00010200); + Reg_Sync_Writel(0x10A40020, 0x00010200); - Reg_Sync_Writel(0x10940028, 0x80000003);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x80000003);// GPR2 + Reg_Sync_Writel(0x10940028, 0x80000003); + Reg_Sync_Writel(0x10A40028, 0x80000003); bTa2_stress_enable = 1; } - Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX - Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX + Reg_Sync_Writel(0x109400A0, 1); + Reg_Sync_Writel(0x10A400A0, 1); } iTestCnt++; #endif -#if 0 //mix ==> bug +#if 0 if(iTestCnt % 10 == 0) { bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0); mcSHOW_DBG_MSG(("*** Stop delay then start\n")); - Reg_Sync_Writel(0x10940020, 0x00000000);// GPR0 //S1, SR, idle - Reg_Sync_Writel(0x10A40020, 0x00000000);// GPR0 + Reg_Sync_Writel(0x10940020, 0x00000000); + Reg_Sync_Writel(0x10A40020, 0x00000000); - Reg_Sync_Writel(0x10940028, 0x00000003);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x00000003);// GPR2 + Reg_Sync_Writel(0x10940028, 0x00000003); + Reg_Sync_Writel(0x10A40028, 0x00000003); - Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX to stop low power flow - Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX to stop low power flow + Reg_Sync_Writel(0x109400A0, 1); + Reg_Sync_Writel(0x10A400A0, 1); if(bLowPwrState == SIDLE_SR_S1_S0) { mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n")); - Reg_Sync_Writel(0x10940020, 0x00010300);// GPR0 //S0 -> S1 -> SR -> idle - Reg_Sync_Writel(0x10A40020, 0x00010300);// GPR0 + Reg_Sync_Writel(0x10940020, 0x00010300); + Reg_Sync_Writel(0x10A40020, 0x00010300); - Reg_Sync_Writel(0x10940024, 0x13121110);// GPR1 //->SHU0 -> SHU1 -> SHU2 -> SHU3 - Reg_Sync_Writel(0x10A40024, 0x13121110);// GPR1 + Reg_Sync_Writel(0x10940024, 0x13121110); + Reg_Sync_Writel(0x10A40024, 0x13121110); - Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2 + Reg_Sync_Writel(0x10940028, 0x80000008); + Reg_Sync_Writel(0x10A40028, 0x80000008); bTa2_stress_enable = 0; } else { mcSHOW_DBG_MSG(("*** SIDLE_SR_S1\n")); - Reg_Sync_Writel(0x10940020, 0x00010200);// GPR0 //S1 -> SR -> idle - Reg_Sync_Writel(0x10A40020, 0x00010200);// GPR0 + Reg_Sync_Writel(0x10940020, 0x00010200); + Reg_Sync_Writel(0x10A40020, 0x00010200); - Reg_Sync_Writel(0x10940024, 0x13121110);// GPR1 //->SHU0 -> SHU1 -> SHU2 -> SHU3 - Reg_Sync_Writel(0x10A40024, 0x13121110);// GPR1 + Reg_Sync_Writel(0x10940024, 0x13121110); + Reg_Sync_Writel(0x10A40024, 0x13121110); - Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2 + Reg_Sync_Writel(0x10940028, 0x80000008); + Reg_Sync_Writel(0x10A40028, 0x80000008); bTa2_stress_enable = 1; } - Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX - Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX + Reg_Sync_Writel(0x109400A0, 1); + Reg_Sync_Writel(0x10A400A0, 1); } iTestCnt++; #endif -#if 0 //DVFS +#if 0 if(iTestCnt % 10 == 0) { bLowPwrState = (bLowPwrState == SIDLE_SR_S1_S0) ? (SIDLE_SR_S1) : (SIDLE_SR_S1_S0); @@ -4468,32 +4331,32 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 c { mcSHOW_DBG_MSG(("*** SIDLE_SR_S1_S0\n")); - Reg_Sync_Writel(0x10940020, 0x12111000);// GPR0 //all SHU - Reg_Sync_Writel(0x10A40020, 0x12111000);// GPR0 + Reg_Sync_Writel(0x10940020, 0x12111000); + Reg_Sync_Writel(0x10A40020, 0x12111000); - Reg_Sync_Writel(0x10940024, 0x16151413);// GPR1 - Reg_Sync_Writel(0x10A40024, 0x16151413);// GPR1 + Reg_Sync_Writel(0x10940024, 0x16151413); + Reg_Sync_Writel(0x10A40024, 0x16151413); - Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2 + Reg_Sync_Writel(0x10940028, 0x80000008); + Reg_Sync_Writel(0x10A40028, 0x80000008); bTa2_stress_enable = 0; } else { mcSHOW_DBG_MSG(("*** SIDLE_SR_S1\n")); - Reg_Sync_Writel(0x10940020, 0x12111000);// GPR0 //all SHU - Reg_Sync_Writel(0x10A40020, 0x12111000);// GPR0 + Reg_Sync_Writel(0x10940020, 0x12111000); + Reg_Sync_Writel(0x10A40020, 0x12111000); - Reg_Sync_Writel(0x10940024, 0x16151413);// GPR1 - Reg_Sync_Writel(0x10A40024, 0x16151413);// GPR1 + Reg_Sync_Writel(0x10940024, 0x16151413); + Reg_Sync_Writel(0x10A40024, 0x16151413); - Reg_Sync_Writel(0x10940028, 0x80000008);// GPR2 - Reg_Sync_Writel(0x10A40028, 0x80000008);// GPR2 + Reg_Sync_Writel(0x10940028, 0x80000008); + Reg_Sync_Writel(0x10A40028, 0x80000008); bTa2_stress_enable = 1; } - Reg_Sync_Writel(0x109400A0, 1);//Tigger MSG BOX - Reg_Sync_Writel(0x10A400A0, 1);//Tigger MSG BOX + Reg_Sync_Writel(0x109400A0, 1); + Reg_Sync_Writel(0x10A400A0, 1); } iTestCnt++; #endif @@ -4507,26 +4370,25 @@ if(bTa2_stress_enable) { DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); - //Disable MR4 MR18/MR19, TxHWTracking, Dummy RD before reset - vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS); //MR4 Disable + + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0x1, HMR4_REFRDIS); u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP); u4BackupDQSOSCENDIS = u4IO32Read4B(DRAMC_REG_SHU_DQSOSC_SET0 + (SHU_GRP_DRAMC_OFFSET * u1ShuLevel)); - vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); //MR18, MR19 Disable + vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), 0x1, SHU_DQSOSC_SET0_DQSOSCENDIS); vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)); - // XRT mode: RKSEL=3, RWOFOEN = from 1 to 0 + TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON); - TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT); //enhance XRT R2R W2W test, TEST2_2_TEST2_OFF=0x400 - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W - TA2_Test_Run_Time_HW_Status(p);//Check TA2 status + TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_XRT); + TA2_Test_Run_Time_HW_Write(p, ENABLE); + TA2_Test_Run_Time_HW_Status(p); } - // HW mode: RKSEL=4, RWOFOEN = from 0 to 1 - //@Darren, If single rank RWOFOEN = 1 (always) and enable tx tracking is available. + TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON); TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW); //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x10, TEST2_A2_TEST2_OFF);//TODO: Need to find out the reason @@ -4534,11 +4396,11 @@ if(bTa2_stress_enable) if (p->support_rank_num==RANK_DUAL) { - //@Darren, Fixed TA2 overnight stress r/w fail (Don't enable tx tracking when RWOFOEN=0) + vIO32Write4B_All(DRAMC_REG_SHU_DQSOSC_SET0+(SHU_GRP_DRAMC_OFFSET*u1ShuLevel), u4BackupDQSOSCENDIS); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); } - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Write(p, ENABLE); } #endif @@ -4557,7 +4419,7 @@ if(bTa2_stress_enable) #ifdef TA2_STRESS if(bTa2_stress_enable) { - TA2_Test_Run_Time_HW_Status(p);//Check TA2 status + TA2_Test_Run_Time_HW_Status(p); } #endif @@ -4594,55 +4456,14 @@ if(bTa2_stress_enable) } #endif -//RX -//if (u1UseTestEngine == PATTERN_TEST_ENGINE) -//{ -// U32 u4B0Tatal =0; -// U32 u4B1Tatal =0; -// mcSHOW_DBG_MSG(("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank)); -// for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) -// { -// mcSHOW_DBG_MSG(("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx])); -// if(u1BitIdx < 8) -// { -// u4B0Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]; -// } -// else -// { -// u4B1Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]; -// } -// } -// mcSHOW_DBG_MSG(("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal)); -//} - -//TX -//static void TxPrintWidnowInfo(DRAMC_CTX_T *p, PASS_WIN_DATA_T WinPerBitData[]) -//{ -// U8 u1BitIdx; -// U32 u4B0Tatal=0; -// U32 u4B1Tatal=0; -// for (u1BitIdx = 0; u1BitIdx < 16; u1BitIdx++) -// { -// if(u1BitIdx < 8) -// { -// u4B0Tatal += WinPerBitData[u1BitIdx].win_size; -// } -// else -// { -// u4B1Tatal += WinPerBitData[u1BitIdx].win_size; -// } -// -// } -// mcSHOW_DBG_MSG(("\ntotal tx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal)); -//} //#ifdef ETT_MINI_STRESS_TEST -#if 0 //Only trigger W once, then R in the loop with TA2 HW mode -//err |= aTA2_Test_Run_Time_HW_Status(p);/* Compare should use TE_OP_READ_CHECK */ +#if 0 +//err |= aTA2_Test_Run_Time_HW_Status(p); unsigned int DPMIsAlive(DRAMC_CTX_T *p); void Ett_Mini_Strss_Test_DPM(DRAMC_CTX_T *p, int iTestCnt, bool *bTa2_stress_enable); -void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 could compare data +void Ett_Mini_Strss_Test(DRAMC_CTX_T *p) { static int sTestCnt = 0; U8 channelIdx, channelBak; @@ -4657,9 +4478,9 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 c } #endif - TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF);//Assign TEST_WORST_SI_PATTERN + TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF); TA2_Test_Run_Time_HW_Presetting(p, TA2_TEST_SIZE, TA2_RKSEL_HW); - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Write(p, ENABLE); do { while(u1StopMiniStress){mcDELAY_MS(1000);} @@ -4668,9 +4489,9 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 c #ifdef TA2_STRESS if(bTa2_stress_enable) { - if(sTestCnt)//after 2rd times + if(sTestCnt) { - TA2_Test_Run_Time_HW_Read(p, ENABLE);//TA2 trigger R + TA2_Test_Run_Time_HW_Read(p, ENABLE); } } #endif @@ -4683,12 +4504,12 @@ void Ett_Mini_Strss_Test(DRAMC_CTX_T *p)//Use the best effort of HW, since TA2 c } #endif - DFSTestProgram(p, 0); // Should open after DVFS is ready + DFSTestProgram(p, 0); #ifdef TA2_STRESS if(bTa2_stress_enable) { - err |= TA2_Test_Run_Time_HW_Status(p);/* Compare should use TE_OP_READ_CHECK */ + err |= TA2_Test_Run_Time_HW_Status(p); } #endif sTestCnt ++; diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c index 1af3490a64..72ab727e76 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c @@ -140,7 +140,7 @@ void CInit_ConfigFromTBA(void) TbaTestListDef.LPDDR4_EN = 1; TbaTestListDef.ESL_LOG_GEN = 1; TbaTestListDef.LP4_X8_on = 0; - TbaTestListDef.LP4_X8_mix_on = 0; //Jeremy + TbaTestListDef.LP4_X8_mix_on = 0; TbaTestListDef.INCLUDE_LP45_COMBO_APHY = 1; TbaTestListDef.LP45_COMBO_APHY_EN = 1; TbaTestListDef.LPDDR5_EN = 0; @@ -160,7 +160,7 @@ void CInit_ConfigFromTBA(void) TbaDramcBenchConfig.rank_swap = 0; TbaDramcBenchConfig.new_uP_spm_mode = 0; TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL = 0; - // CHA, BYTE 0 + TbaDramcBenchConfig.cha_pinmux_anti_order_0 = 0; TbaDramcBenchConfig.cha_pinmux_anti_order_1 = 1; TbaDramcBenchConfig.cha_pinmux_anti_order_2 = 2; @@ -169,7 +169,7 @@ void CInit_ConfigFromTBA(void) TbaDramcBenchConfig.cha_pinmux_anti_order_5 = 5; TbaDramcBenchConfig.cha_pinmux_anti_order_6 = 6; TbaDramcBenchConfig.cha_pinmux_anti_order_7 = 7; - // CHA, BYTE 1 + TbaDramcBenchConfig.cha_pinmux_anti_order_8 = 8; TbaDramcBenchConfig.cha_pinmux_anti_order_9 = 9; TbaDramcBenchConfig.cha_pinmux_anti_order_10 = 10; @@ -178,7 +178,7 @@ void CInit_ConfigFromTBA(void) TbaDramcBenchConfig.cha_pinmux_anti_order_13 = 13; TbaDramcBenchConfig.cha_pinmux_anti_order_14 = 14; TbaDramcBenchConfig.cha_pinmux_anti_order_15 = 15; - // CHB, BYTE 0 + TbaDramcBenchConfig.chb_pinmux_anti_order_0 = 0; TbaDramcBenchConfig.chb_pinmux_anti_order_1 = 1; TbaDramcBenchConfig.chb_pinmux_anti_order_2 = 2; @@ -187,7 +187,7 @@ void CInit_ConfigFromTBA(void) TbaDramcBenchConfig.chb_pinmux_anti_order_5 = 5; TbaDramcBenchConfig.chb_pinmux_anti_order_6 = 6; TbaDramcBenchConfig.chb_pinmux_anti_order_7 = 7; - // CHB, BYTE 1 + TbaDramcBenchConfig.chb_pinmux_anti_order_8 = 8; TbaDramcBenchConfig.chb_pinmux_anti_order_9 = 9; TbaDramcBenchConfig.chb_pinmux_anti_order_10 = 10; @@ -200,7 +200,7 @@ void CInit_ConfigFromTBA(void) mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: rank_swap = %1d\n", TbaDramcBenchConfig.rank_swap)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: new_uP_spm_mode = %1d\n", TbaDramcBenchConfig.new_uP_spm_mode)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: LP_MTCMOS_CONTROL_SEL = %1d\n", TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL)); - // CHA, BYTE 0 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_0 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_0)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_1 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_1)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_2 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_2)); @@ -209,7 +209,7 @@ void CInit_ConfigFromTBA(void) mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_5 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_5)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_6 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_6)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_7 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_7)); - // CHA BYTE 1 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_8 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_8)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_9 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_9)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_10)); @@ -218,7 +218,7 @@ void CInit_ConfigFromTBA(void) mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_13)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_14)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_15)); - // CHB, BYTE 0 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_0 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_0)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_1 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_1)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_2 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_2)); @@ -227,7 +227,7 @@ void CInit_ConfigFromTBA(void) mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_5 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_5)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_6 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_6)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_7 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_7)); - // CHB, BYTE 1 + mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_8 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_8)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_9 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_9)); mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_10)); @@ -256,7 +256,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); - //CBT + DramcCmdUIDelaySetting(p, 0); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), @@ -264,14 +264,14 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK)); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS); - //WL - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay - //Gating + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); + + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) { - // normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -316,7 +316,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) } else { - //mix mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -369,7 +369,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) DramPhyReset(p); - // set dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), P_Fld((U32)0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), @@ -379,7 +379,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), P_Fld((U32)0x46, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); - // set dq delay + U8 u1BitIdx; for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) { @@ -414,7 +414,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); - //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); @@ -437,15 +437,15 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) { U8 u1RankIdx=0; - // WL + U8 u1WLB0_Dly=0, u1WLB1_Dly=0; - // Gating + U8 u1GatingMCKB0_Dly=0, u1GatingMCKB1_Dly=0; U8 u1GatingUIB0_Dly=0, u1GatingUIB1_Dly=0; U8 u1GatingPIB0_Dly=0, u1GatingPIB1_Dly=0; U8 u1B0RodtMCK=0, u1B1RodtMCK=0; U8 u1B0RodtUI=0, u1B1RodtUI=0; - // Rx + U8 u1RxDQS0=0, u1RxDQS1=0; U8 u1RxDQM0=0, u1RxDQM1=0; U8 u1RxRK0B0DQ[8] = {153,147,155,133,149,147,147,143}; @@ -467,7 +467,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) vSetRank(p, u1RankIdx); #if 0 - //CBT + DramcCmdUIDelaySetting(p, 0); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), P_Fld(32, SHU_R0_CA_CMD0_RG_ARPI_CMD) | @@ -476,7 +476,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) #endif #if 1 - //WL + if (p->rank == RANK_0) { u1WLB0_Dly = 29; @@ -487,10 +487,10 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) u1WLB0_Dly = 31; u1WLB1_Dly = 24; } - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); + - //Gating MCK/UI if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) { //if (p->rank == RANK_0) @@ -592,7 +592,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); #endif - //Gating PI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1GatingPIB0_Dly, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); @@ -603,18 +603,18 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) DramPhyReset(p); #if RDSEL_TRACKING_EN - //Byte 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), (u1GatingMCKB0_Dly << 3) | (u1GatingUIB0_Dly), - SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), u1GatingPIB0_Dly, - SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); //PI - //Byte 1 + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), (u1GatingMCKB1_Dly << 3) | (u1GatingUIB1_Dly), - DDRPHY_REG_SHU_R0_B1_INI_UIPI);//UI + DDRPHY_REG_SHU_R0_B1_INI_UIPI); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), - u1GatingPIB1_Dly, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); //PI + u1GatingPIB1_Dly, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); #endif if (p->rank == RANK_0) @@ -632,7 +632,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) pRxB1DQ = u1RxRK1B1DQ; } - // set Rx dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), P_Fld((U32)u1RxDQS0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), @@ -644,7 +644,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) P_Fld((U32)u1RxDQM1, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld((U32)0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); - // set Rx dq delay + U8 u1BitIdx; for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) { @@ -683,7 +683,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi); TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, pTxDQPi); - //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); @@ -706,7 +706,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) vSetRank(p, backup_rank); } #else -void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation +void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p) { U8 u1RankIdx=0; U8 backup_rank=0; @@ -720,7 +720,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); - //CBT + DramcCmdUIDelaySetting(p, 0); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), @@ -728,16 +728,16 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK)); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), 0, SHU_R0_CA_CMD0_RG_ARPI_CS); - //WL - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay - //Gating + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0x20, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0x20, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); + + if((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) { if(p->rank==RANK_0) { - // normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -782,7 +782,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation } else { - // normal mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -828,7 +828,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation } else { - //mix mode + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -881,7 +881,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation DramPhyReset(p); - // set dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), P_Fld((U32)0x45, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), @@ -891,7 +891,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), P_Fld((U32)0x0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); - // set dq delay + U8 u1BitIdx; for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) { @@ -931,7 +931,7 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation TXSetDelayReg_DQ(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); TXSetDelayReg_DQM(p, 1, u1TXMCK, u1TXOENMCK, u1TXUI, u1TXOENUI, u1TXPI); - //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); @@ -951,18 +951,18 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation vSetRank(p, backup_rank); } -void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation +void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p) { U8 u1RankIdx=0; - // WL + U8 u1WLB0_Dly=0, u1WLB1_Dly=0; - // Gating + U8 u1GatingMCKB0_Dly=0, u1GatingMCKB1_Dly=0; U8 u1GatingUIB0_Dly=0, u1GatingUIB1_Dly=0; U8 u1GatingPIB0_Dly=0, u1GatingPIB1_Dly=0; U8 u1B0RodtMCK=0, u1B1RodtMCK=0; U8 u1B0RodtUI=0, u1B1RodtUI=0; - // Rx + U8 u1RxDQS0=0, u1RxDQS1=0; U8 u1RxDQM0=0, u1RxDQM1=0; U8 u1RxRK0B0DQ[8] = {70,70,70,70,70,70,70,70}; @@ -984,7 +984,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation vSetRank(p, u1RankIdx); #if 1 - //CBT + //DramcCmdUIDelaySetting(p, 0); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), P_Fld(40, SHU_R0_CA_CMD0_RG_ARPI_CMD) | @@ -993,7 +993,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation #endif #if 1 - //WL + if (p->rank == RANK_0) { u1WLB0_Dly = 34; @@ -1004,10 +1004,10 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation u1WLB0_Dly = 37; u1WLB1_Dly = 32; } - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u1WLB0_Dly, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u1WLB1_Dly, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); + - //Gating MCK/UI if (p->rank == RANK_0) { u1GatingMCKB0_Dly=0; u1GatingMCKB1_Dly=0; @@ -1066,7 +1066,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); #endif - //Gating PI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1GatingPIB0_Dly, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); @@ -1092,7 +1092,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation pRxB1DQ = u1RxRK1B1DQ; } - // set Rx dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), P_Fld((U32)u1RxDQS0, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), @@ -1104,7 +1104,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation P_Fld((U32)u1RxDQM1, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld((U32)0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); - // set Rx dq delay + U8 u1BitIdx; for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) { @@ -1148,7 +1148,7 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation TXSetDelayReg_DQM(p, 1, u1TXMCK_RK1, u1TXOENMCK_RK1, u1TXUI_RK1, u1TXOENUI_RK1, pTxDQPi); } - //Tx Perbits delay + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); @@ -1168,65 +1168,21 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation #endif void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p){ -// Enter body -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13206 - DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h09 (Mirror: 5'h00) - RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) - RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 - SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfeb (Mirror: 12'h000) - SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h015 (Mirror: 12'h000) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x09, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xfeb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x015, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13076 - DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h09 (Mirror: 5'h00) - DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h09 (Mirror: 5'h00) - DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h09 (Mirror: 5'h00) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x09, MISC_SHU_RDAT_DATLAT) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); #endif -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13012 - RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) - RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) - RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) - RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 - RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) - RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0 - RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13002 - RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h0 - RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 - RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) - RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h1 (Mirror: 4'h0) - RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h0 - RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h0 - RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h3 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKINCTL_STB)); @@ -1236,135 +1192,41 @@ vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANK P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_PHY)); #endif -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13229 - RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); #if !CODE_SIZE_REDUCE -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12823 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12827 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); -/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8022 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); -/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8036 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8029 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8040 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9429 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9443 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9436 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9447 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13022 - RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 - RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h1 (Mirror: 4'h0) - RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 - RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 - FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 - RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 - RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) - RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | @@ -1374,29 +1236,7 @@ vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODT #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x1, MISC_SHU_ODTCTRL_RODT_LAT); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8206 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -1406,29 +1246,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9613 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -1438,232 +1256,71 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @13176 - RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8044 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8051 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9451 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9458 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5628 - DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 - READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 - DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h0 - READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h0 - DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13192 - RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) - RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 - RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 - RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) - RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 - RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 - RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h1 (Mirror: 4'h0) - RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 - RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 - RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0 - RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12841 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12848 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @8000 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x09, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9407 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x09, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @8005 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9412 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8010 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9417 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8016 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9423 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: -// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10832 - RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 - RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 - RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 - RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00) - RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); @@ -1671,19 +1328,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_AR vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7980 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h19 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h19 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -1692,19 +1337,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x19, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x19, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9387 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h1f (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h1f (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -1713,19 +1346,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10842 - RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 - RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 - RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 - RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00) - RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); @@ -1734,19 +1355,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7990 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h13 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h13 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -1755,19 +1364,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0 vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9397 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h12 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h12 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -1776,82 +1373,25 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0 vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5331 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) - DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) - APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 - APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5683 - DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h0 - DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 - DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @5221 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h1 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @5226 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h1 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h1 (Mirror: 3'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5677 - TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h0 - TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h0 - TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5576 - TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 - TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 - TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h1 - TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h1 - TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 - TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); @@ -1861,20 +1401,7 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5587 - dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h1 - dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h1 - dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 - dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 - dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 - dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); @@ -1883,424 +1410,129 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @5041 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h1 - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h1 - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @5063 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h1 - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h1 - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @5085 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @5107 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @5052 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h1 - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h1 - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @5074 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h1 - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h1 - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @5096 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h7 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h7 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @5118 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h7 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h7 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @5129 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h019 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h01f (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x019, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @5139 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h019 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h01f (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x019, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @5177 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h019 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h01f (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x019, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @5134 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h013 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h012 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x012, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @5144 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h013 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h012 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x012, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @5182 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h013 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h012 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x012, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @5187 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h1f (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h19 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h1f (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h19 (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x19, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x19, SHURK_PI_RK0_ARPI_DQM_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @5194 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h12 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h13 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h12 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h13 (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x12, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x12, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B0)); #if !CODE_SIZE_REDUCE -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7826 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h3c (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h3c (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h3c (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h3c (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7840 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h3c (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h3c (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h3c (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h3c (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7868 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h3c (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x3c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9240 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9254 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9281 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: -// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: + #endif # if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE) -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5538 - ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 - TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h1 (Mirror: 3'h0) - TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h4 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | P_Fld(0x1, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x4, SHU_AC_DERATING0_TRCD_DERATE)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5544 - TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h3 (Mirror: 4'h0) - TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h2 (Mirror: 4'h0) - TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h00 - TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x3, SHU_AC_DERATING1_TRPAB_DERATE) | P_Fld(0x2, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRAS_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_AC_DERATING_05T_0 ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0 - @5551 - TRC_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[0:0]=1'h0 - TRCD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[6:6]=1'h0 - TRP_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[7:7]=1'h1 (Mirror: 1'h0) - TRPAB_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[8:8]=1'h1 (Mirror: 1'h0) - TRAS_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[9:9]=1'h1 (Mirror: 1'h0) - TRRD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[12:12]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRP_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRAS_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRRD_05T_DERATE)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5322 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5341 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5504 - TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 - TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 - TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 - TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 - TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 - TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) - TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 - TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) - TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 - TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 - TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) - TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 - TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 - TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 - TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 - TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) - TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0) - TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 - BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 - BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 - BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 - TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 - TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) - XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 - TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) - TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) - TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) - TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0) - TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 - TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0) - XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | @@ -2320,175 +1552,56 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5497 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h03 (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h3 (Mirror: 4'h1) - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h04 (Mirror: 5'h01) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x3, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x04, SHU_ACTIM_XRT_XRTW2W)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5443 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h04 (Mirror: 6'h01) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h07 (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2) - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h2 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x04, SHU_ACTIM0_TWTR) | P_Fld(0x07, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD) | P_Fld(0x2, SHU_ACTIM0_CKELCKCNT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5451 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha) - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h4 (Mirror: 4'h8) - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h2 - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) | P_Fld(0x4, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) | P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5459 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e) - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h0 - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h03 (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x0, SHU_ACTIM2_TRTP) | P_Fld(0x03, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5467 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h1a (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h40 (Mirror: 8'h00) - TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x1a, SHU_ACTIM3_TRFCPB) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0x40, SHU_ACTIM3_TRFC)); #endif vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x00, SHU_ACTIM3_TWTR_L)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5475 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h04e (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h07 (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h05 (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x04e, SHU_ACTIM4_TXREFCNT) | P_Fld(0x07, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) | P_Fld(0x10, SHU_ACTIM4_TZQCS)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5482 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h08 (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h09 (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h0b (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x08, SHU_ACTIM5_TR2PD) | P_Fld(0x09, SHU_ACTIM5_TWTPD) | P_Fld(0x0b, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5489 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h3 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h2 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h06 (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h09 (Mirror: 6'h13) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) | P_Fld(0x3, SHU_ACTIM6_TMRD) | P_Fld(0x2, SHU_ACTIM6_TMRW) | P_Fld(0x06, SHU_ACTIM6_TW2MRW) | P_Fld(0x09, SHU_ACTIM6_TR2MRW)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5567 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h1 (Mirror: 3'h2) - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x1, SHU_CKECTRL_TCKEPRD)); #endif vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5671 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8226 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | @@ -2500,26 +1613,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_P vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9633 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | @@ -2532,50 +1626,17 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_P vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8126 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9533 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7888 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -2584,77 +1645,27 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ P_Fld(0x64, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7902 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7916 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7930 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7944 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x64, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x64, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7954 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h0da (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h0da (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x0da, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x0da, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7895 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -2663,406 +1674,123 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld( P_Fld(0x63, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7909 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7923 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7937 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7949 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x63, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7959 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h0d9 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h0d9 (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0d9, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x0d9, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9295 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9309 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9323 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9337 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h64 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h64 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9351 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h64 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h64 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x64, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x64, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9361 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0da (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0da (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0da, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0da, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9302 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9316 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9330 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9344 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h63 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h63 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9356 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h63 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h63 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x63, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x63, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9366 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0d9 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0d9 (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0d9, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0d9, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7782 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9189 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7711 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h6e (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h6e (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h24 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h24 (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x6e, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x6e, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x24, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x24, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9118 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h6e (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h6e (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h24 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h24 (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x6e, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x6e, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x24, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x24, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7718 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9125 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT -// Exit body + } void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) { - // Enter body - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5271 - ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 - TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h1 (Mirror: 3'h0) - TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h2 (Mirror: 4'h0) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE) vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | P_Fld(0x1, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x2, SHU_AC_DERATING0_TRCD_DERATE)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5277 - TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h1 (Mirror: 4'h0) - TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h0 - TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h00 - TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x1, SHU_AC_DERATING1_TRPAB_DERATE) | P_Fld(0x0, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRAS_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5055 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5074 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h1e (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x1e, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5237 - TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 - TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 - TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 - TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 - TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 - TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0 - TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 - TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0 - TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 - TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 - TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h0 - TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 - TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 - TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 - TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 - TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0 - TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 - TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 - BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 - BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 - BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0) - TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 - TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0 - XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 - TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 - TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0 - TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 - TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 - TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 - TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 - XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) | @@ -3082,177 +1810,58 @@ void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5230 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h05 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0a (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h7 (Mirror: 4'h1) - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h0a (Mirror: 5'h01) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x05, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x7, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x0a, SHU_ACTIM_XRT_XRTW2W)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5176 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0b (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h2 - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) | P_Fld(0x0b, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x2, SHU_ACTIM0_TRCD)); #endif vIO32WriteFldAlign(DRAMC_REG_SHU_ACTIM0, 0x3, SHU_ACTIM0_CKELCKCNT); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5184 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h1 (Mirror: 4'ha) - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h7 (Mirror: 4'h8) - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h0 (Mirror: 4'h2) - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x1, SHU_ACTIM1_TRPAB) | P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x0, SHU_ACTIM1_TRP) | P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5192 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e) - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) | P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5200 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h07 (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h8 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h8 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h1a (Mirror: 8'h00) - TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h05 (Mirror: 6'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x07, SHU_ACTIM3_TRFCPB) | P_Fld(0x8, SHU_ACTIM3_TR2MRR) | P_Fld(0x1a, SHU_ACTIM3_TRFC)); #endif vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x8, SHU_ACTIM3_MANTMRR) | P_Fld(0x05, SHU_ACTIM3_TWTR_L)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5208 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h027 (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0e (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h07 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x027, SHU_ACTIM4_TXREFCNT) | P_Fld(0x0e, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | P_Fld(0x07, SHU_ACTIM4_TZQCS)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5215 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h10 (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h0f (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h0b (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x10, SHU_ACTIM5_TR2PD) | P_Fld(0x0f, SHU_ACTIM5_TWTPD) | P_Fld(0x0b, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5222 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h04 (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0d (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h11 (Mirror: 6'h13) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x04, SHU_ACTIM6_TZQLAT2) | P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x11, SHU_ACTIM6_TR2MRW)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5300 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h0 - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h3 (Mirror: 3'h1) - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h3 (Mirror: 3'h1) - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h2 - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) | P_Fld(0x3, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD)); #endif vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5404 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8224 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0018 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | @@ -3264,26 +1873,7 @@ void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0018, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9647 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0018 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0018, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)); @@ -3296,50 +1886,17 @@ void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8124 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h7 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x7, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9547 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h7 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x7, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7878 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h68 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h68 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h68 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h68 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -3347,77 +1904,27 @@ void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7892 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h68 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h68 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h68 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h68 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7906 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h68 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h68 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h68 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h68 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7920 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h68 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h68 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h68 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h68 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7934 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h68 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h68 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x68, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x68, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7944 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h14a (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h14a (Mirror: 9'h000) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x14a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x14a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7885 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'hc6 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'hc6 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'hc6 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'hc6 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -3425,154 +1932,54 @@ void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7899 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'hc6 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'hc6 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'hc6 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'hc6 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7913 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'hc6 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'hc6 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'hc6 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'hc6 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7927 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'hc6 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'hc6 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'hc6 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'hc6 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7939 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'hc6 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'hc6 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc6, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0xc6, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7949 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h1a1 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h1a1 (Mirror: 9'h000) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1a1, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x1a1, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9301 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h06 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h06 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h06 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h06 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9315 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h06 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h06 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h06 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h06 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9329 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h06 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h06 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h06 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h06 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9343 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h06 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h06 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h06 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h06 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9357 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h06 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h06 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x06, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x06, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9367 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9308 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h65 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h65 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h65 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h65 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); @@ -3580,236 +1987,78 @@ void sv_algorithm_assistance_LP4_400(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9322 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h65 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h65 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h65 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h65 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9336 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h65 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h65 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h65 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h65 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9350 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h65 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h65 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h65 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h65 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9362 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h65 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h65 (Mirror: 8'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x65, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x65, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9372 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h141 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h141 (Mirror: 9'h000) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x141, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x141, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7772 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9195 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7701 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h76 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h76 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h28 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h28 (Mirror: 6'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x76, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x76, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x28, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x28, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9124 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h14 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h14 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h06 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h06 (Mirror: 6'h00) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x14, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x14, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x06, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x06, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); - /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7708 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); -/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9131 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT -// Exit body + } void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) { - // Enter body - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13206 - DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0e (Mirror: 5'h00) - RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) - RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 - SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hff5 (Mirror: 12'h000) - SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h00b (Mirror: 12'h000) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0e, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xff5, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x00b, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13076 - DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0e (Mirror: 5'h00) - DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0e (Mirror: 5'h00) - DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0e (Mirror: 5'h00) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0e, MISC_SHU_RDAT_DATLAT) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); #endif - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13012 - RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) - RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) - RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h1 (Mirror: 2'h0) - RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 - RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) - RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0 - RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13002 - RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h3 (Mirror: 4'h0) - RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 - RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) - RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h4 (Mirror: 4'h0) - RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h4 (Mirror: 4'h0) - RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h4 (Mirror: 4'h0) - RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h6 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_STB)); @@ -3817,135 +2066,41 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_PHY)); #endif - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13229 - RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h4 (Mirror: 4'h0) - RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h4 (Mirror: 4'h0) - RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h4 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); #if !CODE_SIZE_REDUCE - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12823 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h6 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12827 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h6 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8022 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h6 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h8 (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x8, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8036 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8029 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h9 (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8040 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1f (Mirror: 7'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9429 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h6 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h8 (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x8, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9443 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9436 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h9 (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9447 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1f (Mirror: 7'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13022 - RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 - RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h4 (Mirror: 4'h0) - RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 - RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 - FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 - RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 - RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) - RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | @@ -3955,29 +2110,7 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x4, MISC_SHU_ODTCTRL_RODT_LAT); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8206 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -3987,29 +2120,7 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9613 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -4019,232 +2130,71 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @13176 - RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8044 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h1 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8051 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9451 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h1 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9458 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5628 - DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 - READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 - DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) - DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13192 - RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) - RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 - RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 - RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) - RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 - RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 - RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h5 (Mirror: 4'h0) - RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 - RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 - RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0 - RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h1 (Mirror: 4'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x5, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12841 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12848 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @8000 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x06, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9407 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x06, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @8005 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x07, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9412 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x07, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8010 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h08 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x06, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9417 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h06 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h08 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x06, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8016 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h09 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x07, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9423 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1f (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h07 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h09 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x07, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7980 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -4253,19 +2203,7 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9387 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -4274,19 +2212,7 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7990 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h18 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h18 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -4295,19 +2221,7 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x18, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9397 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h18 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h18 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -4316,82 +2230,25 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5331 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) - DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h6 (Mirror: 4'h0) - APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 - APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x5, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5683 - DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h0 - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) - DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 - DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @5221 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h0 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @5226 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h0 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5677 - TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0) - TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) - TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5576 - TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 - TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 - TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 - TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); @@ -4400,522 +2257,164 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @5041 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @5063 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @5085 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h2 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h2 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @5107 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h2 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h2 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @5052 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @5074 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @5096 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h1 - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h1 - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h2 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h2 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @5118 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h1 - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h1 - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h2 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h2 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @5129 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h018 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h018 (Mirror: 11'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @5139 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h018 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h018 (Mirror: 11'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @5177 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h018 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h018 (Mirror: 11'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @5134 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h018 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h018 (Mirror: 11'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @5144 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h018 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h018 (Mirror: 11'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @5182 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h018 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h018 (Mirror: 11'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @5187 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h18 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h18 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h18 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h18 (Mirror: 6'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @5194 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h18 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h18 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h18 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h18 (Mirror: 6'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B0)); #if !CODE_SIZE_REDUCE - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7826 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h30 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h30 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h30 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h30 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7840 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h30 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h30 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h30 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h30 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x30, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7868 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h30 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x30, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @9233 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h0c (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h0c (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h0c (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h0c (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @9247 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h0c (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h0c (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h0c (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h0c (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x0c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @9275 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h0c (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x0c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7833 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h10 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h10 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h10 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h10 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7847 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h10 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h10 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h10 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h10 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7874 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h10 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9240 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h20 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h20 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h20 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h20 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9254 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h20 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h20 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h20 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h20 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x20, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9281 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h20 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5651 - TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0) - TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0) - TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); #endif - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5538 - ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h1 (Mirror: 1'h0) - TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h2 (Mirror: 3'h0) - TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h4 (Mirror: 4'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE) vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x1, SHU_AC_DERATING0_ACDERATEEN) | P_Fld(0x2, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x4, SHU_AC_DERATING0_TRCD_DERATE)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5544 - TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h3 (Mirror: 4'h0) - TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h2 (Mirror: 4'h0) - TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h01 (Mirror: 6'h00) - TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x3, SHU_AC_DERATING1_TRPAB_DERATE) | P_Fld(0x2, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x01, SHU_AC_DERATING1_TRAS_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5322 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5341 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5497 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h05 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0a (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h6 (Mirror: 4'h1) - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h09 (Mirror: 5'h01) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x05, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x0a, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x09, SHU_ACTIM_XRT_XRTW2W)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5443 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0c (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2) - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) | P_Fld(0x0c, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5451 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha) - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h7 (Mirror: 4'h8) - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h2 - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h01 (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) | P_Fld(0x7, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) | P_Fld(0x01, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5459 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h07 (Mirror: 5'h0e) - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h0a (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | P_Fld(0x07, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) | P_Fld(0x0a, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5467 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h1a (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h8 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h8 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h40 (Mirror: 8'h00) - TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h25 (Mirror: 6'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x1a, SHU_ACTIM3_TRFCPB) | P_Fld(0x8, SHU_ACTIM3_TR2MRR) | P_Fld(0x40, SHU_ACTIM3_TRFC)); #endif @@ -4923,102 +2422,32 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) P_Fld(0x25, SHU_ACTIM3_TWTR_L)); #if !CODE_SIZE_REDUCE - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5475 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h04e (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x04e, SHU_ACTIM4_TXREFCNT) | P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | P_Fld(0x10, SHU_ACTIM4_TZQCS)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5482 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h10 (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h0f (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h15 (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x10, SHU_ACTIM5_TR2PD) | P_Fld(0x0f, SHU_ACTIM5_TWTPD) | P_Fld(0x15, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5489 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0d (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h11 (Mirror: 6'h13) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) | P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | P_Fld(0x0d, SHU_ACTIM6_TW2MRW) | P_Fld(0x11, SHU_ACTIM6_TR2MRW)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5567 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h0 - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h3 (Mirror: 3'h1) - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h3 (Mirror: 3'h1) - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h2 - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x3, SHU_CKECTRL_TPDE) | P_Fld(0x3, SHU_CKECTRL_TPDX) | P_Fld(0x2, SHU_CKECTRL_TCKEPRD)); #endif vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5671 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8226 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0031 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | @@ -5029,26 +2458,7 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) #endif vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0031, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9633 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0031 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0031, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)); @@ -5061,50 +2471,17 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8126 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h7 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x7, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9533 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h7 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x7, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7888 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -5112,77 +2489,27 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7902 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7916 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7930 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7944 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7954 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h17e (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h17e (Mirror: 9'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x17e, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x17e, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7895 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -5190,154 +2517,54 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7909 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7923 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7937 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7949 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x74, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7959 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h17d (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h17d (Mirror: 9'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17d, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x17d, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9295 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9309 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9323 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9337 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h75 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h75 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9351 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h75 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h75 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9361 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h17e (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h17e (Mirror: 9'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x17e, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x17e, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9302 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); @@ -5345,237 +2572,79 @@ void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9316 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9330 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9344 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h74 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h74 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9356 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h74 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h74 (Mirror: 8'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x74, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x74, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9366 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h17d (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h17d (Mirror: 9'h000) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17d, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x17d, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7782 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9189 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7711 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h03 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h03 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h35 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h35 (Mirror: 6'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x03, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x03, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x35, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x35, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9118 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h03 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h03 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h35 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h35 (Mirror: 6'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x03, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x03, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x35, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x35, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7718 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9125 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT - // Exit body + } void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) { - // Enter body - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13206 - DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0f (Mirror: 5'h00) - RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) - RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 - SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfd0 (Mirror: 12'h000) - SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h030 (Mirror: 12'h000) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0f, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xfd0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x030, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13076 - DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0f (Mirror: 5'h00) - DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0f (Mirror: 5'h00) - DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0f (Mirror: 5'h00) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0f, MISC_SHU_RDAT_DATLAT) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); #endif - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13012 - RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) - RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) - RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) - RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) - RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) - RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) - RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13002 - RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0) - RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 - RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) - RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h6 (Mirror: 4'h0) - RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0) - RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0) - RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB)); @@ -5584,135 +2653,41 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY)); #endif - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13229 - RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); #if !CODE_SIZE_REDUCE - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12823 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12827 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8022 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h0 - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h4 (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8036 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8029 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hb (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0xb, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8040 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1c (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1c, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9429 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h0 - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h4 (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9443 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9436 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h7 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hb (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0xb, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9447 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1c (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1c, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13022 - RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 - RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h7 (Mirror: 4'h0) - RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 - RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 - FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 - RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 - RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) - RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | @@ -5721,29 +2696,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x7, MISC_SHU_ODTCTRL_RODT_LAT); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8206 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -5753,29 +2706,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9613 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -5785,232 +2716,71 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @13176 - RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8044 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h3 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h3 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8051 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9451 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h3 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h3 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9458 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h2 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h2 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5628 - DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 - READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 - DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) - DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13192 - RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) - RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 - RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 - RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) - RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 - RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 - RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h6 (Mirror: 4'h0) - RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 - RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 - RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h2 (Mirror: 4'h0) - RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12841 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12848 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @8000 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x10, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9407 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x10, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @8005 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x17, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9412 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x17, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8010 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h14 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x14, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9417 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h10 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h14 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x14, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8016 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1b (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x17, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9423 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1c (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h17 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1b (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x17, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10832 - RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0 - RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0 - RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00 - RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00) - RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); @@ -6019,19 +2789,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7980 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h11 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h11 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -6040,19 +2798,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x11, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x11, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9387 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h12 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h12 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -6061,19 +2807,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x12, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10842 - RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0 - RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0 - RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00 - RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00) - RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA)); @@ -6082,19 +2816,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET),P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) | P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7990 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h16 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h16 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -6103,19 +2825,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x16, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9397 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h21 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h21 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -6124,82 +2834,25 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5331 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) - DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) - APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 - APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5683 - DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h2 (Mirror: 3'h0) - DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 - DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @5221 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @5226 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5677 - TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0) - TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) - TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5576 - TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 - TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 - TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 - TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); @@ -6209,20 +2862,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5587 - dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h1 - dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h1 - dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 - dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 - dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 - dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); @@ -6231,508 +2871,152 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @5041 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @5063 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @5085 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h2 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h2 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h7 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h7 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @5107 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h2 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h2 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h7 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h7 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @5052 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @5074 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @5096 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h3 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h3 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h0 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h0 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x0, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x0, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @5118 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h3 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h3 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h0 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h0 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x0, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x0, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @5129 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h011 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h012 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x011, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x012, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @5139 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h011 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h012 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x011, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x012, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @5177 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h011 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h012 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x011, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x012, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @5134 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h016 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h021 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @5144 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h016 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h021 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @5182 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h016 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h021 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x016, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @5187 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h12 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h11 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h12 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h11 (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x12, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x11, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x12, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x11, SHURK_PI_RK0_ARPI_DQM_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @5194 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h21 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h16 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h21 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h16 (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x16, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x16, SHURK_PI_RK0_ARPI_DQM_B0)); #if !CODE_SIZE_REDUCE - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7826 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7840 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7868 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @9233 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h04 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h04 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h04 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h04 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @9247 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h04 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h04 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h04 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h04 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @9275 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h04 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x04, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7833 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h34 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h34 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h34 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h34 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7847 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h34 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h34 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h34 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h34 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x34, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7874 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h34 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9240 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9254 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9281 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5651 - TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0) - TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0) - TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); #endif - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5538 - ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 - TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h5 (Mirror: 3'h0) - TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'h9 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE) vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | P_Fld(0x5, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0x9, SHU_AC_DERATING0_TRCD_DERATE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5544 - TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'h9 (Mirror: 4'h0) - TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h8 (Mirror: 4'h0) - TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h0c (Mirror: 6'h00) - TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0x9, SHU_AC_DERATING1_TRPAB_DERATE) | P_Fld(0x8, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x0c, SHU_AC_DERATING1_TRAS_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_DERATING_05T_0 ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0 - @5551 - TRC_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[0:0]=1'h0 - TRCD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[6:6]=1'h1 (Mirror: 1'h0) - TRP_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[7:7]=1'h0 - TRPAB_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[8:8]=1'h1 (Mirror: 1'h0) - TRAS_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[9:9]=1'h0 - TRRD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[12:12]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRP_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRAS_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRRD_05T_DERATE)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5322 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5341 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h75 (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x75, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5504 - TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 - TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 - TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0) - TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 - TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0) - TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0 - TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0) - TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0 - TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h1 (Mirror: 1'h0) - TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h1 (Mirror: 1'h0) - TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) - TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 - TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 - TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 - TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 - TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) - TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 - TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 - BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 - BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 - BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 - TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 - TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0 - XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 - TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) - TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0 - TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) - TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 - TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h1 (Mirror: 1'h0) - TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0) - XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | @@ -6754,72 +3038,23 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5497 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h1 - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5443 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h08 (Mirror: 6'h01) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0d (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h4 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h8 (Mirror: 4'h2) - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x08, SHU_ACTIM0_TWTR) | P_Fld(0x0d, SHU_ACTIM0_TWR) | P_Fld(0x4, SHU_ACTIM0_TRRD) | P_Fld(0x8, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5451 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h8 (Mirror: 4'ha) - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h7 (Mirror: 4'h2) - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0b (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x8, SHU_ACTIM1_TRPAB) | P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x7, SHU_ACTIM1_TRP) | P_Fld(0x0b, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5459 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0c (Mirror: 5'h0e) - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0) - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h0b (Mirror: 5'h05) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | P_Fld(0x0c, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) | P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x0b, SHU_ACTIM2_TFAW)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5467 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h4d (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'ha5 (Mirror: 8'h00) - TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4d, SHU_ACTIM3_TRFCPB) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0xa5, SHU_ACTIM3_TRFC)); #endif @@ -6827,102 +3062,32 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x00, SHU_ACTIM3_TWTR_L)); #if !CODE_SIZE_REDUCE - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5475 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h0b5 (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0d (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h28 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x0b5, SHU_ACTIM4_TXREFCNT) | P_Fld(0x0d, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) | P_Fld(0x28, SHU_ACTIM4_TZQCS)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5482 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0e (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h10 (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h23 (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0e, SHU_ACTIM5_TR2PD) | P_Fld(0x10, SHU_ACTIM5_TWTPD) | P_Fld(0x23, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5489 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h0e (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0a (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h10 (Mirror: 6'h13) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x0e, SHU_ACTIM6_TZQLAT2) | P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | P_Fld(0x0a, SHU_ACTIM6_TW2MRW) | P_Fld(0x10, SHU_ACTIM6_TR2MRW)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5567 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h3 (Mirror: 3'h2) - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD)); #endif vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5671 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8226 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h00e7 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | @@ -6934,26 +3099,7 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x00e7, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9633 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h00e7 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x00e7, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)); @@ -6966,50 +3112,17 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8126 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h4 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x4, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9533 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h4 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x4, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7888 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -7017,77 +3130,27 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7902 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7916 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7930 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7944 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x6d, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x6d, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7954 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h061 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h061 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x061, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x061, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7895 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -7096,77 +3159,27 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7909 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7923 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7937 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7949 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x6c, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7959 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h060 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h060 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x060, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x060, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9295 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); @@ -7174,77 +3187,27 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9309 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9323 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9337 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h6d (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h6d (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9351 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h6d (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h6d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x6d, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x6d, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9361 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h061 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h061 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x061, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x061, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9302 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); @@ -7253,237 +3216,79 @@ void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9316 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9330 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9344 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h6c (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h6c (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9356 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h6c (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h6c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6c, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x6c, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9366 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h060 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h060 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x060, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x060, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7782 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9189 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7711 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h2d (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h2d (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x2d, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x2d, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9118 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h2d (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h2d (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x2d, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x2d, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7718 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9125 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT - // Exit body + } void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) { - // Enter body - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @13241 - DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h10 (Mirror: 5'h00) - RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) - RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 - SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000) - SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @13111 - DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h10 (Mirror: 5'h00) - DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0f (Mirror: 5'h00) - DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0f (Mirror: 5'h00) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x10, MISC_SHU_RDAT_DATLAT) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0f, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); #endif - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @13047 - RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) - RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) - RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) - RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) - RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) - RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) - RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @13037 - RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0) - RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 - RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h1 (Mirror: 1'h0) - RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h6 (Mirror: 4'h0) - RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0) - RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0) - RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x1, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB)); @@ -7492,135 +3297,41 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY)); #endif - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @13264 - RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); #if !CODE_SIZE_REDUCE - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12858 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12862 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @8012 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @8026 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x01, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @8019 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @8030 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9435 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9449 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x01, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9442 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9453 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @13057 - RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 - RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h7 (Mirror: 4'h0) - RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 - RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 - FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 - RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 - RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) - RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | @@ -7630,29 +3341,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 0x7, MISC_SHU_ODTCTRL_RODT_LAT); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @8204 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -7662,29 +3351,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9627 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -7694,224 +3361,69 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @8034 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @8041 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9457 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9464 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5361 - DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 - READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 - DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) - DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @13227 - RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) - RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 - RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 - RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) - RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 - RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h0 - RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h6 (Mirror: 4'h0) - RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 - RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 - RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h2 (Mirror: 4'h0) - RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x6, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12876 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12883 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7990 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x01, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9413 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x01, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7995 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9418 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @8000 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x15, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9423 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x15, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @8006 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9429 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7970 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h13 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h13 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -7920,19 +3432,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x13, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @9393 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h16 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h16 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -7942,19 +3442,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) P_Fld(0x16, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7980 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h2b (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h2b (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h01 (Mirror: 6'h00) - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); @@ -7963,19 +3451,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2b, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x2b, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x01, SHU_R0_B0_DQ0_ARPI_PBYTE_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @9403 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h2b (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h2b (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h01 (Mirror: 6'h00) - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); @@ -7984,82 +3460,25 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2b, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x2b, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x01, SHU_R0_B1_DQ0_ARPI_PBYTE_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5064 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) - DPHY_CMD_CLKEN_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[10:8]=3'h3 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) - APHYPI_CKCGL_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h2 - APHYPI_CKCGH_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[23:20]=4'h4 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x3, SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | P_Fld(0x2, SHU_DCM_CTRL0_APHYPI_CKCGL_CNT) | P_Fld(0x4, SHU_DCM_CTRL0_APHYPI_CKCGH_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5416 - DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h3 (Mirror: 4'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) - DPHY_TX_DCM_EXTCNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[15:12]=4'h2 - DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4954 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h4 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4959 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h4 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5410 - TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0) - TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0) - TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5309 - TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 - TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 - TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 - TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); @@ -8069,20 +3488,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5320 - dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h5 (Mirror: 4'h1) - dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h5 (Mirror: 4'h1) - dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 - dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 - dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h2 (Mirror: 4'h1) - dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h2 (Mirror: 4'h1) - dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 - dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); @@ -8091,508 +3497,152 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0) | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4774 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4796 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4818 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h6 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h6 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h3 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h3 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4840 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h6 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h6 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h3 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h3 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4785 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4807 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4829 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h7 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h7 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h4 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h4 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4851 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h7 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h7 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h4 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h4 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4862 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h013 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h016 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x016, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4872 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h013 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h016 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x016, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4910 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h013 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h016 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x016, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4867 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h02b (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h02b (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x02b, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4877 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h02b (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h02b (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x02b, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4915 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h02b (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h02b (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02b, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x02b, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4920 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h16 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h13 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h16 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h13 (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x16, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x16, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4927 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h2b (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h2b (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h2b (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h2b (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x2b, SHURK_PI_RK0_ARPI_DQM_B0)); #if !CODE_SIZE_REDUCE - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7816 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h10 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h10 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h10 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7830 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h10 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h10 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h10 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7858 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h10 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @9239 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h04 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h04 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h04 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h04 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @9253 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h04 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h04 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h04 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h04 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x04, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @9281 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h04 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x04, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7823 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7837 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7864 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @9246 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @9260 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @9287 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5384 - TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0) - TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0) - TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); #endif - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_DERATING0_0 ral_reg_DRAMC_blk_SHU_AC_DERATING0_0 - @5271 - ACDERATEEN uvm_reg_field ... RW SHU_AC_DERATING0_0[0:0]=1'h0 - TRRD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[18:16]=3'h5 (Mirror: 3'h0) - TRCD_DERATE uvm_reg_field ... RW SHU_AC_DERATING0_0[27:24]=4'hb (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !(CODE_SIZE_REDUCE && AC_TIMING_DERATE_ENABLE) vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING0, P_Fld(0x0, SHU_AC_DERATING0_ACDERATEEN) | P_Fld(0x5, SHU_AC_DERATING0_TRRD_DERATE) | P_Fld(0xb, SHU_AC_DERATING0_TRCD_DERATE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_DERATING1_0 ral_reg_DRAMC_blk_SHU_AC_DERATING1_0 - @5277 - TRPAB_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[3:0]=4'hb (Mirror: 4'h0) - TRP_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[11:8]=4'h9 (Mirror: 4'h0) - TRAS_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[21:16]=6'h0f (Mirror: 6'h00) - TRC_DERATE uvm_reg_field ... RW SHU_AC_DERATING1_0[28:24]=5'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING1, P_Fld(0xb, SHU_AC_DERATING1_TRPAB_DERATE) | P_Fld(0x9, SHU_AC_DERATING1_TRP_DERATE) | P_Fld(0x0f, SHU_AC_DERATING1_TRAS_DERATE) | P_Fld(0x00, SHU_AC_DERATING1_TRC_DERATE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_DERATING_05T_0 ral_reg_DRAMC_blk_SHU_AC_DERATING_05T_0 - @5284 - TRC_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[0:0]=1'h0 - TRCD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[6:6]=1'h0 - TRP_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[7:7]=1'h1 (Mirror: 1'h0) - TRPAB_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[8:8]=1'h0 - TRAS_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[9:9]=1'h0 - TRRD_05T_DERATE uvm_reg_field ... RW SHU_AC_DERATING_05T_0[12:12]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(0x0, SHU_AC_DERATING_05T_TRC_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRCD_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRP_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRPAB_05T_DERATE) | P_Fld(0x0, SHU_AC_DERATING_05T_TRAS_05T_DERATE) | P_Fld(0x1, SHU_AC_DERATING_05T_TRRD_05T_DERATE)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5055 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5074 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5237 - TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 - TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h1 (Mirror: 1'h0) - TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 - TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 - TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 - TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) - TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 - TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) - TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 - TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 - TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h0 - TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 - TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 - TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 - TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h1 (Mirror: 1'h0) - TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0 - TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 - TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0) - BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 - BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 - BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0 - TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 - TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) - XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 - TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 - TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) - TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 - TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 - TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 - TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 - XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) | @@ -8612,72 +3662,23 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T)); - /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5230 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h1 - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5176 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[5:0]=6'h0a (Mirror: 6'h01) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h0f (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h3 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h3 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x0a, SHU_ACTIM0_TWTR) | P_Fld(0x0f, SHU_ACTIM0_TWR) | P_Fld(0x3, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5184 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'ha - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h8 (Mirror: 4'h2) - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h00 (Mirror: 5'h05) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xa, SHU_ACTIM1_TRPAB) | P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x8, SHU_ACTIM1_TRP) | P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5192 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h1 (Mirror: 4'h0) - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0e - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0) - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h08 (Mirror: 5'h05) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x1, SHU_ACTIM2_TXP) | P_Fld(0x0e, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) | P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x08, SHU_ACTIM2_TFAW)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5200 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h59 (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'hbf (Mirror: 8'h00) - TWTR_L uvm_reg_field ... RW SHU_ACTIM3_0[29:24]=6'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x59, SHU_ACTIM3_TRFCPB) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0xbf, SHU_ACTIM3_TRFC)); #endif @@ -8685,102 +3686,32 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) P_Fld(0x00, SHU_ACTIM3_TWTR_L)); #if !CODE_SIZE_REDUCE - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5208 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h0cf (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0b (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x0cf, SHU_ACTIM4_TXREFCNT) | P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0b, SHU_ACTIM4_TMRR2W) | P_Fld(0x2e, SHU_ACTIM4_TZQCS)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5215 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0f (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h12 (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h29 (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0f, SHU_ACTIM5_TR2PD) | P_Fld(0x12, SHU_ACTIM5_TWTPD) | P_Fld(0x29, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5222 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h8 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0b (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h12 (Mirror: 6'h13) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) | P_Fld(0x8, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | P_Fld(0x0b, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5300 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h3 (Mirror: 3'h2) - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD)); #endif vIO32WriteFldAlign(DRAMC_REG_SHU_CKECTRL, 0x3, SHU_CKECTRL_TCKESRX); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5404 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); #if !CODE_SIZE_REDUCE vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @8224 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) | @@ -8792,26 +3723,7 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9647 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | @@ -8823,50 +3735,17 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) #endif vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @8124 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9547 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7878 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h54 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h54 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h54 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h54 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -8874,77 +3753,27 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7892 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h54 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h54 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h54 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h54 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7906 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h54 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h54 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h54 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h54 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7920 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h54 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h54 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h54 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h54 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7934 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h54 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h54 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x54, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x54, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7944 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h04a (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h04a (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x04a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x04a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7885 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h46 (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h46 (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h46 (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h46 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); @@ -8952,77 +3781,27 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7899 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h46 (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h46 (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h46 (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h46 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7913 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h46 (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h46 (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h46 (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h46 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7927 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h46 (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h46 (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h46 (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h46 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7939 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h46 (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h46 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x46, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7949 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h038 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h038 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x038, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x038, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @9301 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'hcd (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'hcd (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'hcd (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'hcd (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); @@ -9030,77 +3809,27 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @9315 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'hcd (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'hcd (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'hcd (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'hcd (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @9329 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'hcd (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'hcd (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'hcd (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'hcd (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @9343 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'hcd (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'hcd (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'hcd (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'hcd (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @9357 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'hcd (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'hcd (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0xcd, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0xcd, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @9367 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0bd (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0bd (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @9308 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'hfe (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'hfe (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'hfe (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'hfe (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); @@ -9108,173 +3837,59 @@ void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @9322 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'hfe (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'hfe (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'hfe (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'hfe (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @9336 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'hfe (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'hfe (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'hfe (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'hfe (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @9350 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'hfe (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'hfe (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'hfe (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'hfe (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @9362 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'hfe (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'hfe (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if !CODE_SIZE_REDUCE vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xfe, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0xfe, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @9372 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0f4 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0f4 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0f4, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0f4, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7772 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @9195 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h0 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7701 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h5a (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h5a (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h14 (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h14 (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x5a, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x5a, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x14, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x14, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @9124 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h53 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h53 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h0d (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h0d (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x53, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x53, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x0d, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x0d, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7708 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x0e, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @9131 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h0e - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h0 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h0 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h0 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x0e, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT - // Exit body + } @@ -9306,7 +3921,7 @@ void TX_Path_Algorithm(DRAMC_CTX_T *p) u1DQS_OE_UI = u1DQS_OE_TotalUI - ((u1DQS_OE_TotalUI >> u1Small_ui_to_large) << u1Small_ui_to_large); u1DQS_OE_MCK = (u1DQS_OE_TotalUI >> u1Small_ui_to_large); - //u1DQ_UI = WL*DFS_TOP[0].CKR*2 - u1WDBI_EN*(DFS_TOP[0].DQ_P2S_RATIO) + (tDQSS+tDQS2DQ)*1000000/DFS_TOP[0].data_rate; + mcSHOW_DBG_MSG3(("[TX_path_calculate] data rate=%d, WL=%d, DQS_TotalUI=%d\n", DFS_TOP[0].data_rate, WL, u1DQS_TotalUI)); mcSHOW_DBG_MSG3(("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", u1DQS_MCK, u1DQS_UI, u1DQS_OE_MCK, u1DQS_OE_UI)); @@ -9328,318 +3943,90 @@ void TX_Path_Algorithm(DRAMC_CTX_T *p) void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) { - // Enter body - // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 - DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h09 (Mirror: 5'h00) - DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h07 (Mirror: 5'h00) - DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h09 (Mirror: 5'h00) - DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h07 (Mirror: 5'h00) - DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h09 (Mirror: 5'h00) - DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h07 (Mirror: 5'h00) - DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 - DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) | P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) | P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) | P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 - CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h09 (Mirror: 5'h00) - CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h07 (Mirror: 5'h00) - CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h09 (Mirror: 5'h00) - CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h07 (Mirror: 5'h00) - DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h09 (Mirror: 5'h00) - DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h07 (Mirror: 5'h00) - DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h1 (Mirror: 1'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0xF, SHU_MISC_DRVING2_CMDDRVN1) | P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0xF, SHU_MISC_DRVING2_CMDDRVN2) | P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) | P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 - DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) - DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) - DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) - DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) - DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) - DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 - CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) - CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) - CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) - CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) - DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) - DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 - IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h07 (Mirror: 6'h01) - DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 - DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 - IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h3 (Mirror: 3'h4) - IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 - IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 - IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 - IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) - IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x3, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 - DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0a (Mirror: 5'h00) - RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) - RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 - SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfeb (Mirror: 12'h000) - SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h015 (Mirror: 12'h000) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0a, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xfeb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x015, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 - DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0a (Mirror: 5'h00) - DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h09 (Mirror: 5'h00) - DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h09 (Mirror: 5'h00) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0a, MISC_SHU_RDAT_DATLAT) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x09, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 - RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) - RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) - RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) - RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0 - RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) - RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h0 - RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 - RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h0 - RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 - RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 - RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h2 (Mirror: 4'h0) - RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h0 - RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h0 - RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h3 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_PHY)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 - RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*0x80), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Name Type Size Value - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) - ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*0x80), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*0x80), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0 - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0 - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0 - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*0x80), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*0x80), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 - RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 - RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h1 (Mirror: 4'h0) - RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 - RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 - FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 - RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 - RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) - RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODT_LAT) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -9649,29 +4036,7 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -9681,289 +4046,87 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*0x80), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*0x80), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 - DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 - READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 - DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h0 - READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h0 - DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 - RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) - RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 - RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 - RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) - RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 - RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) - RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h3 (Mirror: 4'h0) - RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 - RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 - RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0) - RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x3, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*0x80), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x09, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x09, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x09, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h09 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0d (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x09, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*0x80), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h1d (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h1d (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h1d (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h1d (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x1d, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h0d (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h0d (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*0x80), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x0d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h13 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h13 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*0x80), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x13, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x13, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) - DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) - CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | @@ -9975,596 +4138,175 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 - DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h7 (Mirror: 4'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h0 - DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h1 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h1 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*0x200), P_Fld(0x1, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 - TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h0 - TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h0 - TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 - TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 - TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 - TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h1 - TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h1 - TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 - TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 - dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h1 - dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h1 - dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 - dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 - dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 - dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h1 - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h1 - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h1 - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h1 - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1 - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1 - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1 - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1 - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h6 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h6 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h1 - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h1 - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h1 - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h1 - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h7 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h7 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h7 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h7 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*0x200), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h01d (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h01d (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h01d (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h01d (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h01d (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h01d (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h00d (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h013 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x013, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h00d (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h013 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x013, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h00d (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h013 (Mirror: 11'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*0x200), P_Fld(0x00d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x013, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h1d (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h1d (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h1d (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h1d (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h13 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h0d (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h13 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h0d (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*0x200), P_Fld(0x13, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x0d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x13, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x0d, SHURK_PI_RK0_ARPI_DQM_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h10 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h10 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h10 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h10 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h10 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h10 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x10, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h10 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x10, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @8831 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h14 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h14 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h14 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h14 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @8845 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h14 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h14 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h14 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h14 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @8873 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h14 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x14, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h3c (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h3c (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h3c (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h3c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h3c (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h3c (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h3c (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h3c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x3c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h3c (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*0x80), P_Fld(0x3c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ9_0 ral_reg_DDRPHY_blk_SHU_B0_DQ9_0 - @7845 - RG_ARPI_RESERVE_B0 uvm_reg_field ... RW SHU_B0_DQ9_0[31:0]=32'hbf31f45b (Mirror: 32'hbf33f45b) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0xbf31f45b, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 - TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) - TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) - TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) - TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) - TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 - TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 - TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 - TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) - TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) - TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) - TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) - TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 - TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) - TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) - TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) - TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) - TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 - dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 - dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 - dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) - dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 - dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 - dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 - dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 - dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 - TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 - TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 - TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0 - TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 - TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0 - TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) - TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 - TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) - TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 - TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 - TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0) - TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0 - TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0 - TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 - TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0 - TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0) - TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0) - TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0 - BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 - BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 - BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0) - TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 - TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) - XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 - TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0 - TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) - TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0) - TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0) - TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 - TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 - XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) | @@ -10581,31 +4323,11 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h03 (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h3 (Mirror: 4'h1) - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h03 (Mirror: 5'h01) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x3, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x4, SHU_ACTIM_XRT_XRTW2W)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h4 (Mirror: 4'h1) - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h2 (Mirror: 3'h0) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h08 (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h1 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h4 (Mirror: 4'h2) - TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h7 (Mirror: 4'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x4, SHU_ACTIM0_TWTR) | P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x08, SHU_ACTIM0_TWR) | @@ -10616,138 +4338,39 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x08, SHU_ACTIM0_TWR) | P_Fld(0x1, SHU_ACTIM0_TRRD) | P_Fld(0x4, SHU_ACTIM0_TRCD)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h3 (Mirror: 4'ha) - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h4 (Mirror: 4'h8) - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h2 - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h00 (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h04 (Mirror: 5'h05) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x3, SHU_ACTIM1_TRPAB) | P_Fld(0x4, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x2, SHU_ACTIM1_TRP) | P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x04, SHU_ACTIM1_TRC)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h0 - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h05 (Mirror: 5'h0e) - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h1 (Mirror: 3'h0) - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h03 (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x0, SHU_ACTIM2_TXP) | P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) | P_Fld(0x03, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h10 (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h2c (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x10, SHU_ACTIM3_TRFCPB) | P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0x2c, SHU_ACTIM3_TRFC)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h03a (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h07 (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h05 (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h10 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x03a, SHU_ACTIM4_TXREFCNT) | P_Fld(0x07, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) | P_Fld(0x10, SHU_ACTIM4_TZQCS)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h08 (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h09 (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h12 (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x08, SHU_ACTIM5_TR2PD) | P_Fld(0x09, SHU_ACTIM5_TWTPD) | P_Fld(0x12, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h06 (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h3 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h2 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h06 (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h07 (Mirror: 6'h13) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x06, SHU_ACTIM6_TZQLAT2) | P_Fld(0x3, SHU_ACTIM6_TMRD) | P_Fld(0x2, SHU_ACTIM6_TMRW) | P_Fld(0x06, SHU_ACTIM6_TW2MRW) | P_Fld(0x07, SHU_ACTIM6_TR2MRW)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h1 (Mirror: 3'h2) - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x1, SHU_CKECTRL_TCKEPRD) | P_Fld(0x3, SHU_CKECTRL_TCKESRX)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | @@ -10756,26 +4379,7 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0063 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | @@ -10784,500 +4388,153 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x20, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); //RX_ARDQ_VREF_SEL_B0 is useless - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h5 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x20, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); //RX_ARDQ_VREF_SEL_B0 is useless - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x9f, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x9f, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x0e5, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x0e5, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*0x80), P_Fld(0x9e, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x9e, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h0e4 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h0e4 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*0x80), P_Fld(0x0e4, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x0e4, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h9f (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h9f (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h9f (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h9f (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x9f, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x9f, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h0e5 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h0e5 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0e5, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h9e (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h9e (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h9e (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h9e (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*0x80), P_Fld(0x9e, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x9e, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h0e4 (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h0e4 (Mirror: 9'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*0x80), P_Fld(0x0e4, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x0e4, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h29 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h29 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h1f (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h1f (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x29, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x29, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x1f, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x1f, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h29 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h29 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h1f (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h1f (Mirror: 6'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x29, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x29, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x1f, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x1f, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT - // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 - FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0) - FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 - FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0 - DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0) - DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0 - LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h0 - LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h0 - CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 - BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 - BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) - LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 - BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 - LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h0 - SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | @@ -11286,31 +4543,11 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) | P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 - SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) - TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 - REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 - TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 - DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 - CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | @@ -11322,62 +4559,17 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 - DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) - ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 - ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) - PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) - REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) - REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 - MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) - NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023 - DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 - TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 - TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 - DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 - TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 - DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 - OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 - DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 - WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) - DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 - DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 - ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 - TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 - DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 - DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 - RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 - DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | @@ -11387,26 +4579,7 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | P_Fld(0x0, TX_SET0_DRAMOEN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 - DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 - DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 - TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 - TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h5 (Mirror: 3'h0) - WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 - DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 - WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 - TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 - WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h0 - TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 - TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 - OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) - DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e - TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | @@ -11426,40 +4599,12 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 - DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 - DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 - r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 - STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) - STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) - DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 - DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h0 - PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) - DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) - DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) - DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h1 - DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 - DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 - STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) - STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) - DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 - DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 - DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) | P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | @@ -11467,191 +4612,63 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 - RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) - RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 - RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 - RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 - RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 - RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) - RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 - RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 - DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0) - RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0) - RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter - // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_HWSET_MR13_0 ral_reg_DRAMC_blk_SHU_HWSET_MR13_0 - @5127 - HWSET_MR13_MRSMA uvm_reg_field ... RW SHU_HWSET_MR13_0[12:0]=13'h000d - HWSET_MR13_OP uvm_reg_field ... RW SHU_HWSET_MR13_0[23:16]=8'h08 (Mirror: 8'hc8) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13, P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) | P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_HWSET_VRCG_0 ral_reg_DRAMC_blk_SHU_HWSET_VRCG_0 - @5132 - HWSET_VRCG_MRSMA uvm_reg_field ... RW SHU_HWSET_VRCG_0[12:0]=13'h000d - HWSET_VRCG_OP uvm_reg_field ... RW SHU_HWSET_VRCG_0[23:16]=8'h00 (Mirror: 8'hc0) - VRCGDIS_PRDCNT uvm_reg_field ... RW SHU_HWSET_VRCG_0[31:24]=8'h00 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) | P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 - tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) - tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h2b (Mirror: 8'h00) - tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h18 (Mirror: 8'h00) - tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | P_Fld(0x2b, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x18, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit - // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 - r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h1 (Mirror: 1'h0) - r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 - r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) - r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); mcDELAY_US(1); - /*TINFO=---===BROADCAST OFF!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); mcDELAY_US(1); - /*TINFO=---===BROADCAST ON!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 - DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h08 (Mirror: 8'h00) - DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 - DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 - DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x08, SHU_DQSOSCR_DQSOSCRCNT) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 - DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 - DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h011 (Mirror: 10'h00f) - DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | P_Fld(0x011, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 - DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h0866 (Mirror: 16'h0000) - DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h0866 (Mirror: 16'h0000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0866, SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(0x0866, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 - DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0399 (Mirror: 16'h0000) - DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0399 (Mirror: 16'h0000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*0x200), P_Fld(0x0399, SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(0x0399, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 - DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h0ac (Mirror: 12'h001) - DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h072 (Mirror: 12'h001) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x0ac, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | P_Fld(0x072, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 - DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h01f (Mirror: 12'h001) - DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h015 (Mirror: 12'h001) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*0x200), P_Fld(0x01f, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | P_Fld(0x015, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 - DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 - DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 - TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 - TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h5 - WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 - DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 - WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 - TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 - WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h0 - TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 - TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 - OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 - DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h08 (Mirror: 6'h0e) - TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | @@ -11671,46 +4688,13 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x08, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); #endif - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 - ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) - TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1b - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h32 - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x32, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0063 - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0063, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | @@ -11719,26 +4703,7 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0063 - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0063, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | @@ -11747,29 +4712,7 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'hd (Mirror: 4'h0) - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0xd, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -11779,29 +4722,7 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'hd (Mirror: 4'h0) - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0xd, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -11811,60 +4732,27 @@ void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p) P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794 - RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0 - RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0 - RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0 - RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0 - RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0 - RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0 - RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0 - RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0 - RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h2 - RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); - /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - Name Type Size Value - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197 - RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0 - RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0 - RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0 - RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0 - RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0 - RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0 - RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0 - RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0 - RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h2 - RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0 - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - */ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); - // Exit body + } #if 0 void CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DRAMC_CTX_T *p) { -// Enter body -// ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Enter: + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) | P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) | P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) | @@ -11888,13 +4776,13 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld( P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Exit: + mcDELAY_US(1); mcDELAY_US(1); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) | @@ -12114,8 +5002,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, S P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) | @@ -12335,13 +5222,13 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit + mcDELAY_US(1); mcDELAY_US(1); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) | @@ -12354,7 +5241,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld( P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX_MODE_SET related setting Enter + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) | @@ -12373,7 +5260,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Enter: + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xff0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x010, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); @@ -12474,8 +5361,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+ P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Exit: -// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Enter: + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x17, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x17, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | @@ -12602,8 +5488,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRP P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Exit: -// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Enter: + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | @@ -12627,8 +5512,7 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Enter: + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4b, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | @@ -12667,10 +5551,7 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_MISC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_M vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) | P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Enter. -// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Exit. -// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | @@ -12759,8 +5640,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRP P_Fld(0xe4, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x189, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x189, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set EXIT -// ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Enter + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_COMMON0_FREQDIV4) | P_Fld(0x1, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | @@ -12812,37 +5692,32 @@ vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fl P_Fld(0x2, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Enter -// ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Enter + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) | P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP)); vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) | P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Enter + vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | P_Fld(0x2b, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Exit -// ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Enter + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); mcDELAY_US(1); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Enter + mcDELAY_US(1); mcDELAY_US(1); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); -// ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Exit + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0c, SHU_DQSOSCR_DQSOSCRCNT) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); @@ -12918,324 +5793,96 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); -// Exit body + } #endif void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p) { -// Enter body -// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter: -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634 - DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00) - DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00) - DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00) - DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00) - DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00) - DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00) - DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0 - DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) | P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) | P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) | P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) | P_Fld(0x1, SHU_MISC_DRVING1_DIS_IMPCAL_HW)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645 - CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00) - CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00) - CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00) - CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00) - DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00) - DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00) - DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) | P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) | P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) | P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655 - DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00) - DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00) - DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00) - DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00) - DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00) - DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664 - CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00) - CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00) - CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00) - CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00) - DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00) - DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682 - IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h0a (Mirror: 6'h01) - DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00 - DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x0a, SHU_MISC_DRVING6_IMP_TXDLY_CMD) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625 - IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h7 (Mirror: 3'h4) - IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00 - IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00 - IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4 - IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00) - IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x7, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) | P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit: -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter: -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734 - DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h10 (Mirror: 5'h00) - RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0) - RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0 - SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000) - SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x10, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) | P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) | P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604 - DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h10 (Mirror: 5'h00) - DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h10 (Mirror: 5'h00) - DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h10 (Mirror: 5'h00) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x10, MISC_SHU_RDAT_DATLAT) | P_Fld(0x10, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x10, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540 - RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0) - RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0) - RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0) - RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0) - RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0) - RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) - RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x3, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530 - RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h5 (Mirror: 4'h0) - RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1 - RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0 - RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h8 (Mirror: 4'h0) - RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h6 (Mirror: 4'h0) - RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h6 (Mirror: 4'h0) - RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h9 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) | P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL_PHY)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757 - RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0) - RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h8 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x8, MISC_SHU_RK_DQSCTL_DQSINCTL); -/*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Name Type Size Value ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356 - DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h8 (Mirror: 4'h0) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x8, MISC_SHU_RK_DQSCTL_DQSINCTL); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x01, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631 - DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642 - DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'h1 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h5 (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h1 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h01 (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x01, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034 - DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h9 (Mirror: 4'h0) - DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'hd (Mirror: 4'h0) - DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h1 (Mirror: 4'h0) - DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x9, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045 - DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h08 (Mirror: 7'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x08, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550 - RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0 - RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h8 (Mirror: 4'h0) - RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0 - RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0 - FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0 - RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1 - RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0) - RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x8, MISC_SHU_ODTCTRL_RODT_LAT) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) | P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -13245,29 +5892,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0) - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0) - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -13277,297 +5902,89 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @12704 - RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653 - RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | P_Fld(0x4, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0 - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056 - RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h4 (Mirror: 3'h0) - RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h4 (Mirror: 3'h0) - RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0) - RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | P_Fld(0x4, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323 - DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0 - READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0 - DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0) - DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0) - READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720 - RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0) - RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0 - RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0 - RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0) - RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0 - RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0) - RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h9 (Mirror: 4'h0) - RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0 - RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0 - RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0) - RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x9, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377 - DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00) - DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0) - DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00) - DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x01, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x01, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607 - CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) | P_Fld(0x19, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010 - CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) | P_Fld(0x19, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x15, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h01 (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h11 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h15 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x01, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x15, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618 - NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) - NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) | P_Fld(0x19, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x1d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021 - NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h08 (Mirror: 7'h00) - NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h19 (Mirror: 8'h00) - NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h1d (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) | P_Fld(0x19, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x1d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit: -// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter: -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h15 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h15 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x15, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h15 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h15 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592 - RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h24 (Mirror: 6'h00) - SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h24 (Mirror: 6'h00) - ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x24, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) | P_Fld(0x24, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995 - RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0 - RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0 - SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h22 (Mirror: 6'h00) - SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h22 (Mirror: 6'h00) - ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00 - DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0 - DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) | P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0) - DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0) - CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0 - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | @@ -13579,652 +5996,191 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_ P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377 - DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h7 (Mirror: 4'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931 - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h4 (Mirror: 3'h0) - DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) | P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371 - TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0) - TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0) - TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) | P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271 - TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1) - TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1) - TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1 - TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1 - TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1 - TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282 - dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h5 (Mirror: 4'h1) - dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h5 (Mirror: 4'h1) - dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1 - dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1 - dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h2 (Mirror: 4'h1) - dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h2 (Mirror: 4'h1) - dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1 - dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0) | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0) | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h6 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h6 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h3 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h3 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h6 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h6 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h3 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h3 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757 - TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1 - TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1 - TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1 - TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ0) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779 - TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h3 (Mirror: 3'h1) - TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h3 (Mirror: 3'h1) - TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1 - TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1 - TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1) - TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1 - TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM0) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801 - dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h7 (Mirror: 4'h1) - dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h7 (Mirror: 4'h1) - dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1 - dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1 - dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h4 (Mirror: 4'h1) - dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h4 (Mirror: 4'h1) - dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1 - dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ0) | P_Fld(0x4, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823 - dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h7 (Mirror: 4'h1) - dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h7 (Mirror: 4'h1) - dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1 - dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1 - dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h4 (Mirror: 4'h1) - dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h4 (Mirror: 4'h1) - dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1 - dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM0) | P_Fld(0x4, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h015 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h015 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h015 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h015 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h015 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h015 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839 - BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h024 (Mirror: 11'h000) - BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h022 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) | P_Fld(0x022, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849 - BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h024 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h022 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) | P_Fld(0x022, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887 - BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h024 (Mirror: 11'h000) - BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h022 (Mirror: 11'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x024, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) | P_Fld(0x022, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h15 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h15 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h15 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h15 (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899 - RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h22 (Mirror: 6'h00) - RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h24 (Mirror: 6'h00) - RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h22 (Mirror: 6'h00) - RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h24 (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x22, SHURK_PI_RK0_ARPI_DQ_B1) | P_Fld(0x24, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x22, SHURK_PI_RK0_ARPI_DQM_B1) | P_Fld(0x24, SHURK_PI_RK0_ARPI_DQM_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x08, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x08, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @8831 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h08 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @8845 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h08 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h08 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h08 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @8873 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h08 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435 - TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h20 (Mirror: 8'h00) - TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h20 (Mirror: 8'h00) - TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h20 (Mirror: 8'h00) - TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h20 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449 - TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h20 (Mirror: 8'h00) - TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h20 (Mirror: 8'h00) - TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h20 (Mirror: 8'h00) - TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h20 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) | P_Fld(0x20, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476 - TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h20 (Mirror: 8'h00) - TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x20, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838 - TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h28 (Mirror: 8'h00) - TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h28 (Mirror: 8'h00) - TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h28 (Mirror: 8'h00) - TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h28 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852 - TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h28 (Mirror: 8'h00) - TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h28 (Mirror: 8'h00) - TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h28 (Mirror: 8'h00) - TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h28 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) | P_Fld(0x28, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879 - TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h28 (Mirror: 8'h00) - TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00 - TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x28, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345 - TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0) - TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0) - TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) | P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ9_0 ral_reg_DDRPHY_blk_SHU_B0_DQ9_0 - @7845 - RG_ARPI_RESERVE_B0 uvm_reg_field ... RW SHU_B0_DQ9_0[31:0]=32'h31105ab1 (Mirror: 32'h31165ab1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0x31105ab1, SHU_B0_DQ9_RG_ARPI_RESERVE_B0); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ9_0 ral_reg_DDRPHY_blk_SHU_B1_DQ9_0 - @9248 - RG_ARPI_RESERVE_B1 uvm_reg_field ... RW SHU_B1_DQ9_0[31:0]=32'hd5713d50 (Mirror: 32'hd5733d50) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xd5713d50, SHU_B1_DQ9_RG_ARPI_RESERVE_B1); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit: -// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter: -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041 - TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1) - TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1) - TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1) - TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1) - TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052 - TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01 - TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) | P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060 - TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1) - TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1) - TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1) - TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1) - TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071 - TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1) - TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1) - TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1) - TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1) - TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1) - TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1) - TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1) - TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082 - dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1 - dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1 - dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1) - dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1 - dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1 - dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1 - dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1 - dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter: -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018 - CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3 - SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) | P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00) - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199 - TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0 - TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0 - TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0) - TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0 - TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0) - TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h1 (Mirror: 1'h0) - TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0 - TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0) - TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0 - TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0 - TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h0 - TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h1 (Mirror: 1'h0) - TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h1 (Mirror: 1'h0) - TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0 - TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h1 (Mirror: 1'h0) - TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0 - TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0 - TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0) - BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0 - BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0 - BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0) - TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0 - TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0) - XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0 - TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0) - TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h1 (Mirror: 1'h0) - TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0 - TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0 - TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0 - TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0 - XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) | @@ -14241,31 +6197,11 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192 - XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h03 (Mirror: 5'h01) - XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h08 (Mirror: 6'h01) - XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h1 - XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h05 (Mirror: 5'h01) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x03, SHU_ACTIM_XRT_XRTR2R) | P_Fld(0x08, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x1, SHU_ACTIM_XRT_XRTW2R) | P_Fld(0x05, SHU_ACTIM_XRT_XRTW2W)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138 - TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'ha (Mirror: 4'h1) - CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0) - TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h10 (Mirror: 8'h06) - TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h4 (Mirror: 3'h0) - TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2) - TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'hc (Mirror: 4'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0xa, SHU_ACTIM0_TWTR) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x10, SHU_ACTIM0_TWR) | @@ -14276,152 +6212,43 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0xa, SHU_ACTIM0_TWTR) | P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x10, SHU_ACTIM0_TWR) | P_Fld(0x4, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147 - TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'ha - TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8 - TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h8 (Mirror: 4'h2) - TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04) - TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h19 (Mirror: 5'h05) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xa, SHU_ACTIM1_TRPAB) | P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x8, SHU_ACTIM1_TRP) | P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x19, SHU_ACTIM1_TRC)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155 - TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h2 (Mirror: 4'h0) - TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0e - TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0) - TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h09 (Mirror: 6'h00) - TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h0d (Mirror: 5'h05) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x2, SHU_ACTIM2_TXP) | P_Fld(0x0e, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) | P_Fld(0x09, SHU_ACTIM2_TR2W) | P_Fld(0x0d, SHU_ACTIM2_TFAW)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163 - TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h3f (Mirror: 8'h00) - MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0) - TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0) - TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h89 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x3f, SHU_ACTIM3_TRFCPB) | P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) | P_Fld(0x89, SHU_ACTIM3_TRFC)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170 - TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h09a (Mirror: 10'h028) - TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00) - TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0b (Mirror: 6'h00) - TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x09a, SHU_ACTIM4_TXREFCNT) | P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0b, SHU_ACTIM4_TMRR2W) | P_Fld(0x2e, SHU_ACTIM4_TZQCS)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177 - TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0f (Mirror: 7'h00) - TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h12 (Mirror: 7'h00) - TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h30 (Mirror: 8'h00) - TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0f, SHU_ACTIM5_TR2PD) | P_Fld(0x12, SHU_ACTIM5_TWTPD) | P_Fld(0x30, SHU_ACTIM5_TPBR2PBR) | P_Fld(0x0, SHU_ACTIM5_TPBR2ACT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184 - TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f) - TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0) - TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0) - TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0b (Mirror: 6'h00) - TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h12 (Mirror: 6'h13) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) | P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) | P_Fld(0x0b, SHU_ACTIM6_TW2MRW) | P_Fld(0x12, SHU_ACTIM6_TR2MRW)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262 - TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0) - TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0 - TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1 - TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1 - TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2) - TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) | P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) | P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) | P_Fld(0x3, SHU_CKECTRL_TCKESRX)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365 - REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2 - DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4) - DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) | P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MISC_TX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_TX_PIPE_CTRL_0 - @12708 - CMD_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0) - CK_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[1:1]=1'h1 (Mirror: 1'h0) - TX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[2:2]=1'h0 - CS_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[3:3]=1'h1 (Mirror: 1'h0) - SKIP_TXPIPE_BYPASS uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[8:8]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL, P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) | P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) | P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter. -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit. -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | @@ -14430,26 +6257,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000) - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0 - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0) - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | @@ -14458,498 +6266,151 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728 - RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) | P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131 - RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e - RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0 - RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00 - RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0 - RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0 - RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0) - RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) | P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x6f, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x6f, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h02f (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h02f (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x02f, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x02f, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497 - RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511 - RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525 - RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539 - RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551 - RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0x6e, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561 - RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h02e (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h02e (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x02e, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) | P_Fld(0x02e, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h6f (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h6f (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h6f (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h6f (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x6f, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x6f, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h02f (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h02f (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x02f, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x02f, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900 - RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914 - RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928 - RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942 - RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h6e (Mirror: 8'h00) - RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h6e (Mirror: 8'h00) - RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954 - RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h6e (Mirror: 8'h00) - RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h6e (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x6e, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0x6e, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964 - RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h02e (Mirror: 9'h000) - RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h02e (Mirror: 9'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x02e, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) | P_Fld(0x02e, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384 - RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) | P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) | P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787 - RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1 - RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0 - R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1 - R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0 - R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00 - R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0 - R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0 - R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0 - R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) | P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) | P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313 - RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h2f (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h2f (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) | P_Fld(0x75, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x2f, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) | P_Fld(0x2f, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716 - RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h75 (Mirror: 7'h00) - RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h2f (Mirror: 6'h00) - RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h2f (Mirror: 6'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) | P_Fld(0x75, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x2f, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) | P_Fld(0x2f, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320 - RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10 - RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1 - RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1 - RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1 - RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723 - RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10 - RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1 - RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1 - RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0 - RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1 - RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT -// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001 - FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0) - FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0 - FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0 - DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0) - DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0 - LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h0 - LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h0 - CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0 - BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0 - BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0) - LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0 - BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1 - LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h0 - SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) | P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) | @@ -14958,31 +6419,11 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) | P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) | P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) | P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255 - SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a) - TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0 - REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000 - TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) | P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) | P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027 - DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 - DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4 - DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 - CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0 - FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0) - FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) | @@ -14994,62 +6435,17 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_ P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356 - DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08) - ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0 - ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0) - PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0) - REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0) - REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) | P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) | P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) | P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996 - MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0) - NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) | P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023 - DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899 - TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0 - TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0 - DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0 - TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1 - DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0 - OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0 - DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0 - WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0) - DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0 - DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0 - ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0 - TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0 - DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0 - DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0 - RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0 - DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) | P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) | @@ -15059,26 +6455,7 @@ vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) | P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) | P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) | P_Fld(0x0, TX_SET0_DRAMOEN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 - DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 - DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 - TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 - TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0) - WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 - DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0 - WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 - TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 - WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0) - TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 - TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 - OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0) - DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e - TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | @@ -15098,40 +6475,12 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514 - DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0 - DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0 - r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0 - STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0) - STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0) - DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) | P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) | P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) | P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499 - DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0) - PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0) - DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0) - DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0) - DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h1 - DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1 - DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0 - STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0) - STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0) - DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0 - DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0 - DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) | P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) | @@ -15139,62 +6488,16 @@ vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBL P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562 - RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0) - RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0 - RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0 - RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0) - RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1 - RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0 - RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0) - RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0 - RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751 - DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0) - RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0) - RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -15204,29 +6507,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0) - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0) - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0 - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0 - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0 - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -15236,26 +6517,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 - DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 - DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 - TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 - TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 - WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 - DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0) - WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 - TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 - WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 - TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 - TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 - OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 - DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e - TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | @@ -15275,147 +6537,50 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); #endif -// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122 - HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002 - HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h3f (Mirror: 8'h12) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) | P_Fld(0x3f, SHU_HWSET_MR2_HWSET_MR2_OP)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384 - tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00) - tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h72 (Mirror: 8'h00) - tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h09 (Mirror: 8'h00) - tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) | P_Fld(0x72, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x09, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit -// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523 - r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0 - r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0 - r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46) - r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) | P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit + mcDELAY_US(1); mcDELAY_US(1); -/*TINFO=---===BROADCAST OFF!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter + mcDELAY_US(1); mcDELAY_US(1); -/*TINFO=---===BROADCAST ON!===---*/ + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); -// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338 - DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h15 (Mirror: 8'h00) - DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0 - DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0 - DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x15, SHU_DQSOSCR_DQSOSCRCNT) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) | P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332 - DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1 - DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h012 (Mirror: 10'h00f) - DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) | P_Fld(0x012, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906 - DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h0326 (Mirror: 16'h0000) - DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h0326 (Mirror: 16'h0000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0326, SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(0x0326, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911 - DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0159 (Mirror: 16'h0000) - DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0159 (Mirror: 16'h0000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916 - DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h018 (Mirror: 12'h001) - DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h010 (Mirror: 12'h001) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x018, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | P_Fld(0x010, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921 - DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h004 (Mirror: 12'h001) - DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h002 (Mirror: 12'h001) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x004, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) | P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306 - DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0 - DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0 - TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0 - TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 - WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0 - DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 - WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0 - TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0 - WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 - TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3 - TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1 - OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 - DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h17 (Mirror: 6'h0e) - TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) | @@ -15435,56 +6600,16 @@ vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) | P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) | P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN)); #endif -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 - ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0000 - TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1d (Mirror: 5'h1b) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) | P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351 - ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000) - TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1d ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) | P_Fld(0x1d, SHU_ZQ_SET0_TZQLAT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036 - FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 - REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) | P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828 - R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 - R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 - R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 - R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) | @@ -15493,26 +6618,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231 - R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 - R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0) - R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0 - R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0 - R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 - R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0 - R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0 - R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 - R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0 - R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0 - R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0 - R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0 - R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0 - R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) | @@ -15521,29 +6627,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808 - R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 - R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 - R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'hb (Mirror: 4'h0) - R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h1 (Mirror: 1'h0) - R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h1 (Mirror: 1'h0) - R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 - R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 - R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 - R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 - R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) | P_Fld(0xb, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | @@ -15553,29 +6637,7 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0 P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211 - R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0 - R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 - R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 - R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'hb (Mirror: 4'h0) - R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0 - R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h1 (Mirror: 1'h0) - R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h1 (Mirror: 1'h0) - R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 - R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0 - R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0 - R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0 - R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0 - R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0 - R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 - R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 - R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 - R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) | P_Fld(0xb, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | @@ -15585,53 +6647,21 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1 P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794 - RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0 - RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0 - RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0 - RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0 - RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0 - RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0 - RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0 - RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0 - RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h2 - RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) | P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0)); -/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Name Type Size Value ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197 - RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0 - RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0 - RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0 - RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0 - RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0 - RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0 - RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0 - RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0) - RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0 - RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h2 - RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -*/ + vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) | P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) | P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1)); -// Exit body + } diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c index 0b51b4b7fb..7341ae3c0d 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c @@ -67,7 +67,7 @@ DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T *p, DRAM_DFS_SR return &pFreqTbl[u1ShuffleIdx]; } -#if 0 //@Darren, debug codes +#if 0 void DramcWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data) { U32 ii, u4tmp, u4Offset=0; @@ -97,14 +97,14 @@ void FullRGDump(DRAMC_CTX_T *p, U8 step, U32 u4ShuOffset) U8 u1RankIdx=0; mcSHOW_DBG_MSG(("[FullRGDump] STEP%d\n", step)); - //Darren-DumpAoNonShuReg(); + for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); mcSHOW_DBG_MSG(("[FullRGDump] RANK%d\n", u1RankIdx)); DumpAoShuReg(u4ShuOffset, u4ShuOffset); } - //Darren-DumpNaoReg(); + } U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg) @@ -124,17 +124,17 @@ U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg) #endif }; - //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1 + //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; - u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg));// SHU1 + u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg)); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; mcSHOW_DBG_MSG(("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value)); @@ -161,16 +161,16 @@ void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data #endif }; - //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); // SHU8 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; - vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1 + vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; mcSHOW_DBG_MSG(("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data)); @@ -182,7 +182,7 @@ void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) { U32 ii, u4tmp, u4Offset=0; - DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1 + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) { @@ -201,7 +201,7 @@ void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr) { U32 ii, u4tmp, u4Offset=0; - DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; // SHU1 need use p->ShuRGAccessIdx=DRAM_DFS_REG_SHU1 for RK1 + DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx; for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4) { @@ -230,31 +230,31 @@ void CmdBusTrainingLP4YWA(DRAMC_CTX_T *p, U8 u1OnOff) { U8 u1MR51 = 0; - if ((p->frequency > 800) && (p->dram_fsp==FSP_0)) // skip DDR1600 up + if ((p->frequency > 800) && (p->dram_fsp==FSP_0)) return; - if (p->dram_fsp==FSP_1) //for HIGH speed in FSP1, FSP0 SE setting will be mismatch + if (p->dram_fsp==FSP_1) { if (u1OnOff==DISABLE) { p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; - //CLK to Diff end + ClkSingleEndRGEnable ( p, u1OnOff); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; } } - else //for LOW speed under DDR1600 + else { if (u1OnOff == DISABLE) - u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3); // disable CLK SE mode + u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3); else - u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3); // enable CLK SE mode + u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3); DramcModeRegWriteByRank(p, p->rank, 51, u1MR51Value[p->dram_fsp]); - //CLK to Diff end + ClkSingleEndRGEnable ( p, u1OnOff); } } @@ -276,10 +276,10 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset_BeforeK] FSP%d\n", p->dram_fsp)); #endif -#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 1) //Set SE before Calibration +#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 1) if (p->frequency <=800) { - u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; // CLK[3]=1, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y + u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; } else { @@ -287,7 +287,7 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) } #endif - //! save shux mr1/mr2/mr3/mr11 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4), P_Fld(u1MR01Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0) | P_Fld(u1MR02Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1) | @@ -296,7 +296,7 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp])); #endif - //! save shux mr22/mr51 + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4), P_Fld(u1MR21Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5) | P_Fld(u1MR22Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6) | @@ -310,10 +310,10 @@ void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level) #if CHANNEL_NUM > 2 if (channel_num_auxadc > 2) { if (u1ChIdx >= CHANNEL_C) - u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); // for 4ch others DPM + u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); } #endif - //! save shux mr12/mr14 + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4), P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) | P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) | @@ -349,10 +349,10 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0x7F) | (p->DBI_W_onoff[p->dram_fsp] << 7)); #endif -#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0) //Set SE after Calibration +#if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0) if (p->frequency <=800) { - u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; // CLK[3]=1, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y + u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe; } else { @@ -360,13 +360,13 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) } #endif - //! save shux mr1/mr2/mr3/mr11 + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4), u1MR03_Value, LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2); #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03_Value, u1MR11Value[p->dram_fsp])); #endif - //! save shux mr22/mr51 + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4), u1MR51_Value, LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7); #if ENABLE_RTMRW_DEBUG_LOG @@ -378,10 +378,10 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) #if CHANNEL_NUM > 2 if (channel_num_auxadc > 2) { if (u1ChIdx >= CHANNEL_C) - u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); // for 4ch others DPM + u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); } #endif - //! save shux mr12/mr14 + vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4), P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) | P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) | @@ -403,15 +403,15 @@ void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level) static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1MR1, U8 u1MR2, U8 u1MR3, U8 u1MR11, U8 u1MR12, U8 u1MR13, U8 u1MR14, U8 u1MR21, U8 u1MR22, U8 u1MR51) { U8 rt_response_ack = 1, rt_ack = 0; - U8 u1MRW_1ST_Num = 0x5; // MR13, MR1, MR2, MR3, MR11, MR12 - U8 u1MRW_2ND_Num = 0x2; // MR14, 22, 51 + U8 u1MRW_1ST_Num = 0x5; + U8 u1MRW_2ND_Num = 0x2; #if ENABLE_LP4Y_DFS - u1MRW_2ND_Num++; // for LP4Y MR21 + u1MRW_2ND_Num++; #endif #if 1 - //! MR13, MR1, MR2, MR3, MR11, MR12 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) | P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) | @@ -423,28 +423,28 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) | P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT)); - //! MA = 13, 1, 2, 3 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), P_Fld(13, RTMRW_CTRL1_RTMRW0_MA) | P_Fld(1, RTMRW_CTRL1_RTMRW1_MA) | P_Fld(2, RTMRW_CTRL1_RTMRW2_MA) | P_Fld(3, RTMRW_CTRL1_RTMRW3_MA)); - //! OP13, OP1, OP2, OP3 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), P_Fld(u1MR13, RTMRW_CTRL2_RTMRW0_OP) | P_Fld(u1MR1, RTMRW_CTRL2_RTMRW1_OP) | P_Fld(u1MR2, RTMRW_CTRL2_RTMRW2_OP) | P_Fld(u1MR3, RTMRW_CTRL2_RTMRW3_OP)); - //! MR11/MR12 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3), P_Fld(11, RTMRW_CTRL3_RTMRW4_MA) | P_Fld(12, RTMRW_CTRL3_RTMRW5_MA) | P_Fld(u1MR11, RTMRW_CTRL3_RTMRW4_OP) | P_Fld(u1MR12, RTMRW_CTRL3_RTMRW5_OP)); - //!runtime MRW trigger + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN); do { @@ -455,7 +455,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M #endif #if 1 - //! MR14/22/51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0), P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) | P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) | @@ -467,7 +467,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) | P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT)); - //! MA = 14, 22, 51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1), P_Fld(14, RTMRW_CTRL1_RTMRW0_MA) | #if ENABLE_LP4Y_DFS @@ -476,7 +476,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(22, RTMRW_CTRL1_RTMRW1_MA) | P_Fld(51, RTMRW_CTRL1_RTMRW2_MA)); - //! OP14, OP22, OP51 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2), P_Fld(u1MR14, RTMRW_CTRL2_RTMRW0_OP) | #if ENABLE_LP4Y_DFS @@ -485,7 +485,7 @@ static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1M P_Fld(u1MR22, RTMRW_CTRL2_RTMRW1_OP) | P_Fld(u1MR51, RTMRW_CTRL2_RTMRW2_OP)); - //!runtime MRW trigger + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN); do { @@ -505,9 +505,9 @@ static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_s mcSHOW_DBG_MSG(("[DFSRTMRW_HwsetWA] \n")); #endif - p->ShuRGAccessIdx = cur_shu_mux_index; // Currect + p->ShuRGAccessIdx = cur_shu_mux_index; u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP); - p->ShuRGAccessIdx = pingpong_shu_level; // Next + p->ShuRGAccessIdx = pingpong_shu_level; u1VRCG_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), SHU_HWSET_VRCG_HWSET_VRCG_OP); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; @@ -515,26 +515,26 @@ static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_s { if (cur_shu_mux_index == PHYPLL_MODE) { - u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL - u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1MR13_OP &= 0x3F; + u1VRCG_OP &= 0x3F; } else { - u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL - u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + u1MR13_OP |= 0xC0; + u1VRCG_OP |= 0xC0; } } else { if (cur_shu_mux_index == PHYPLL_MODE) { - u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL - u1VRCG_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + u1MR13_OP |= 0xC0; + u1VRCG_OP |= 0xC0; } else { - u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL - u1VRCG_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1MR13_OP &= 0x3F; + u1VRCG_OP &= 0x3F; } } @@ -548,10 +548,10 @@ static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_s bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - p->ShuRGAccessIdx = cur_shu_mux_index; // Currect - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current - p->ShuRGAccessIdx = pingpong_shu_level; // Next - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP); // Next + p->ShuRGAccessIdx = cur_shu_mux_index; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); + p->ShuRGAccessIdx = pingpong_shu_level; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; if (CH_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); @@ -573,14 +573,12 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); ch_bak = vGetPHY2ChannelMapping(p); - //! get mr13 - //rtmr13 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0, LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0); - //! get shux mr1/mr2/mr3/mr11 + rtmr1 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0); rtmr2 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1); rtmr3 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2); rtmr11 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3); - //! get shux mr21/mr22/mr51 + rtmr21 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5); rtmr22 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6); rtmr51 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7); @@ -589,16 +587,16 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev if (p->boot_fsp== FSP_1) { if(cur_shu_mux_index == PHYPLL_MODE) - rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL + rtmr13 |= (0x1 << 7); else - rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL + rtmr13 |= (0x1 << 6); } else { if(cur_shu_mux_index == PHYPLL_MODE) - rtmr13 |= (0x1 << 6); //! MR13 OP7 = 0, OP6 = 1, from CLRPLL to PHYPLL + rtmr13 |= (0x1 << 6); else - rtmr13 |= (0x1 << 7); //! MR13 OP7 = 1, OP6 = 0, from PHYPLL to CLRPLL + rtmr13 |= (0x1 << 7); } #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("[DFSRuntimeMRWEn]\n")); @@ -613,7 +611,7 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev #if (CHANNEL_NUM > 2) if (channel_num_auxadc > 2) { if (u1ChIdx >= CHANNEL_C) - DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);//SHIFT_TO_CHB_ADDR; + DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM); else } #endif @@ -621,7 +619,7 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { - //! get shux mr12/mr14/ + rtmr12 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4), Fld(8, u1RankIdx*8)); rtmr14 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4), Fld(8, (u1RankIdx*8)+16)); #if ENABLE_RTMRW_DEBUG_LOG @@ -648,13 +646,13 @@ static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U #if ENABLE_RTMRW_DEBUG_LOG mcSHOW_DBG_MSG(("[DFSHwSetWA] \n")); #endif - p->ShuRGAccessIdx = cur_shu_mux_index; // NOTE: Currect shuffle + p->ShuRGAccessIdx = cur_shu_mux_index; u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP); - if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1)) // for term shuffle level - u1MR13_OP |= 0xC0; //! MR13 OP7 = 1, OP6 = 1, from CLRPLL to PHYPLL + if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1)) + u1MR13_OP |= 0xC0; else - u1MR13_OP &= 0x3F; //! MR13 OP7 = 0, OP6 = 0, from PHYPLL to CLRPLL + u1MR13_OP &= 0x3F; if (CH_num > CHANNEL_SINGLE) { @@ -666,7 +664,7 @@ static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U mcSHOW_DBG_MSG(("HWSET_MR13_OP = 0x%x\n", u1MR13_OP)); #endif - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); // Current + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP); if (CH_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); @@ -700,7 +698,7 @@ void ConfigMCK4To1MUX(DRAMC_CTX_T *p, CLK_MUX_T eClkMux) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, P_Fld(0x3, MISC_CG_CTRL0_CLK_MEM_SEL) | P_Fld(0x1, MISC_CG_CTRL0_W_CHG_MEM)); - mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + mcDELAY_XNS(100); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_W_CHG_MEM); } @@ -772,19 +770,19 @@ static void ChkDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) { WaitDFSDebugSM(p, 0x1e); - // HW shuffle will switch clock to 208MHz and continue DFS + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); - mcDELAY_US(1); // Wait 1T 26MHz + mcDELAY_US(1); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); WaitDFSDebugSM(p, 0x1f); - // HW shuffle will switch clock to MCK and continue DFS + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); - mcDELAY_US(1); // Wait 1T 26MHz + mcDELAY_US(1); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL) | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE)); @@ -814,10 +812,8 @@ static void EntryDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode) { vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN) | P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN)); - // for DPM RG mode + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); - // for PHY RG mode (no support) - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); } else { @@ -836,13 +832,11 @@ U32 u4PERFCTL0_backup=0; void EnableDFSNoQueueFlush(DRAMC_CTX_T *p) { vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_HWSET_WLRL) - | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP) // sync MP settings + | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP) | P_Fld(1, DVFS_CTRL0_DVFS_NOQUEFLUSH_EN) | P_Fld(0, DVFS_CTRL0_R_DMDVFSMRW_EN)); vIO32WriteFldMulti_All(DRAMC_REG_SHUCTRL1, P_Fld(0, SHUCTRL1_FC_PRDCNT) #if ENABLE_LP4Y_WA - //@Berson, LP4Y tCKFSPE/X_SE violation at shuffle as DVFS noqueflush enable - // LP4Y tCKFSPE/X_SE violation at shuffle from 7.5ns to 15ns | P_Fld(5, SHUCTRL1_CKFSPE_PRDCNT) | P_Fld(5, SHUCTRL1_VRCGEN_PRDCNT) #else @@ -850,27 +844,27 @@ void EnableDFSNoQueueFlush(DRAMC_CTX_T *p) | P_Fld(0, SHUCTRL1_VRCGEN_PRDCNT) #endif | P_Fld(0, SHUCTRL1_CKFSPX_PRDCNT)); - vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT); // sync MP settings + vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT); -#if ENABLE_DFS_RUNTIME_MRW // for Skip HW MR2 - vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP) // OP CHG & VRCG High - | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP) // VRCG Low - | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP)); // MR2 RL/WL (reduce 50ns) +#if ENABLE_DFS_RUNTIME_MRW + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP) + | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP) + | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP)); #endif #if ENABLE_DFS_NOQUEUE_FLUSH_DBG - // for debug mode only (skip HW MRW) + vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE) | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE) | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE)); #endif - //Fix wdle cnt fail issue + vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_GROUP_A_REV); } #if 0 static void WaitNoQueueFlushComplete(DRAMC_CTX_T *p) { - // for debug mode only + U8 u1tCKFSPe_OK[CHANNEL_NUM] = {0}; U8 u1tVRCGDis_OK[CHANNEL_NUM] = {0}; U8 u1ChIdx = 0; @@ -928,7 +922,7 @@ static void TimingTxsrWA(DRAMC_CTX_T *p, U32 next_shu_level) { U32 onoff=0, bc_bak=0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); @@ -961,23 +955,23 @@ void TxReadBaseODTWA(DRAMC_CTX_T *p, U8 next_shu_level) { U32 termen_dis, bc_bak=0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1)) // for DDR4266/DDR3200 - termen_dis = DISABLE; //term + if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1)) + termen_dis = DISABLE; else - termen_dis = ENABLE; // un-term + termen_dis = ENABLE; //mcSHOW_DBG_MSG(("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis)); vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, termen_dis, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0); vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, termen_dis, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1); vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, termen_dis, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS); - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); } #endif @@ -987,7 +981,7 @@ static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level) { U32 bc_bak=0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); @@ -1005,7 +999,7 @@ static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level) | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) ); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; - if (p->support_channel_num > CHANNEL_SINGLE) //for dual single + if (p->support_channel_num > CHANNEL_SINGLE) DramcBroadcastOnOff(bc_bak); } #endif @@ -1018,13 +1012,13 @@ static void DDR800_SOPEN_DSC_WA(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff) if (p->DRAMPinmux != PINMUX_DSC) return; - if (p->support_channel_num> CHANNEL_SINGLE) //for dual single + if (p->support_channel_num> CHANNEL_SINGLE) { bc_bak = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); } - if ((next_shu_level == SRAM_SHU6) && (u1OnOff==DISABLE))// for DDR800 + if ((next_shu_level == SRAM_SHU6) && (u1OnOff==DISABLE)) { MPDIV_CG = DISABLE; vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG); @@ -1042,15 +1036,15 @@ static void DDR800_SOPEN_DSC_WA(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff) void EnableDFSHwModeClk(DRAMC_CTX_T *p) { - //Shuffle HW mode for MCK/208M switch + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, - P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) | // dvfs source clock selection when ddrphy shuffle - P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)); // dvfs destination clock selection when ddrphy shuffle + P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) | + P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, - P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) | //M_CK clock mux selection update enable by shuffle - P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) | // by shuffle - P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) | // HW mode by shuffle - P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL)); // 4-to-1 mux for PLLCK + P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) | + P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) | + P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) | + P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL)); } #if 0 static void DFSEnlargeTimingSettings(DRAMC_CTX_T *p) @@ -1072,33 +1066,30 @@ static void DFSEnlargeTimingSettings(DRAMC_CTX_T *p) #endif void DVFSSettings(DRAMC_CTX_T *p) { - U8 u1DVFS_52M_104M_SEL = 1; // DVFS_SM freq: 0: 52Mhz 1:104Mhz - U8 u1Master_DLL_Idle = 0x2b; // Master from MCK - U8 u1Slave_DLL_Idle = 0x43; // Slave from MCK -#if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only - U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0; // 1=ignore + U8 u1DVFS_52M_104M_SEL = 1; + U8 u1Master_DLL_Idle = 0x2b; + U8 u1Slave_DLL_Idle = 0x43; +#if (fcFOR_CHIP_ID == fcA60868) + U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0; #endif U32 backup_broadcast = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); if (vGet_Div_Mode(p) == DIV16_MODE) { - u1Master_DLL_Idle = 0x37; // Master from MCK - u1Slave_DLL_Idle = 0x4D; // Slave from MCK + u1Master_DLL_Idle = 0x37; + u1Slave_DLL_Idle = 0x4D; } - //DVFS debug enable - MRR_STATUS2_DVFS_STATE - //@Lynx, A60868 HW always enable shuffle debug. remove RG: DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE - //vIO32WriteFldAlign_All(DRAMC_REG_DVFSDLL, 1, DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL); //Set DVFS_SM's clk + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL); #if ENABLE_DFS_208M_CLOCK - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL); //Set DVFS_SM's clk to 208M + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL); #endif vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(u1Master_DLL_Idle, MISC_SHU_DVFSDLL_R_DLL_IDLE) | P_Fld(u1Slave_DLL_Idle, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)); - // @Darren, set current SRAM SHU index for SPM mode DFS latch/restore vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, vGet_Current_SRAMIdx(p), MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM); //mcSHOW_DBG_MSG(("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_SRAMIdx(p))); @@ -1108,9 +1099,9 @@ void DVFSSettings(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(u1ChClkIgnore[1], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB) | P_Fld(u1ChClkIgnore[0], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA)); #endif - // DFS trigger by DDRPHY RG - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); // DFS RG mode for calibration - //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS); // DFS RG mode for disable tx tracking + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_RG_MRW_AFTER_DFS); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) @@ -1120,10 +1111,10 @@ void DVFSSettings(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_OPT, P_Fld(1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN) | P_Fld(1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)); #if ENABLE_DFS_HW_SAVE_MASK - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY); // 0x1 = disable dfs hw save + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY); #endif -#if 0 // @Darren, reserved from Mengru Dsim +#if 0 U8 u1MarginNew = (u1DVFS_52M_104M_SEL == 1) ? 0x3 : 0x1; vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_OPT, 0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW) @@ -1144,14 +1135,14 @@ void DVFSSettings(DRAMC_CTX_T *p) | P_Fld(1, MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT)); #endif -#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION // @Mazar +#if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 1, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE) | P_Fld(3, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN) | P_Fld(3, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW)); #endif -#if (fcFOR_CHIP_ID == fc8195) // @Darren, for Mar_gaux New setting for ddrphy shuffle (sync mode) +#if (fcFOR_CHIP_ID == fc8195) vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL); vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHB_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL); #if CHANNEL_NUM > 2 @@ -1162,8 +1153,7 @@ void DVFSSettings(DRAMC_CTX_T *p) #endif #endif - //DLL_SHUFFLE should be set enable before switch frequency - // @Darren, func is empty after IPM via @Mazar + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_RG_DLL_SHUFFLE); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0, MISC_DVFSCTL2_R_DVFS_OPTION) @@ -1180,7 +1170,7 @@ void DVFSSettings(DRAMC_CTX_T *p) DFSEnlargeTimingSettings(p); #endif - //EnableDFSHwModeClk(p); // @Darren, for DFS shuffle change + //EnableDFSHwModeClk(p); DramcBroadcastOnOff(backup_broadcast); } @@ -1231,9 +1221,9 @@ static void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff) if ((cur_shu_level == 0x0) || (cur_shu_level == 0x8) || (cur_shu_level == 0x9) || (cur_shu_level == 0x6) || (cur_shu_level == 0x5)) { if (!(p->u1PLLMode == PHYPLL_MODE)) - vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN); // CLRPLL SSC + vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN); else - vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN); // PHYPLL SSC + vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN); } } #endif @@ -1242,28 +1232,23 @@ static void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff) #if DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM || ENABLE_DFS_SSC_WA void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p) { - /*TINFO="DRAM : SPM DVS DMY RD ENTR"*/ - /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 1"*/ vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 1, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 1"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_intv_sel = 1"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_en = 1"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_EN); mcDELAY_US(1); @@ -1271,33 +1256,28 @@ void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p) void DVS_DMY_RD_EXIT(DRAMC_CTX_T *p) { - /*TINFO="DRAM : SPM DVS DMY RD EXIT"*/ - /*TINFO="DRAM : set sc_dmyrd_en = 0"*/ - //! diff with WE vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_EN); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_intv_sel = 0"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_dmyrd_en_mod_sel = 0"*/ - //! diff with WE + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL); mcDELAY_US(1); - /*TINFO="DRAM : set sc_ddrphy_fb_ck_en = 0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); mcDELAY_US(1); - /*TINFO="DRAM : SPM DVS DMY RD EXIT end "*/ + } #endif @@ -1309,11 +1289,11 @@ static void EnableDramcTrackingByShuffle(DRAMC_CTX_T *p, U8 u1EnDPMCh, U8 u1OnOf { #if ENABLE_RX_TRACKING vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN); - //RX delay cell use Vmddr in all freq, so rx tracking is not needed. + #endif #if ENABLE_TX_TRACKING vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS); - //The LPDDR4 DRAM cannot be placed in power-down state during "Start DQS Interval Oscillator" operation. + #endif } else if (u1OnOff == DISABLE) @@ -1338,19 +1318,19 @@ static void EnableDramcTrackingBySPMControl(DRAMC_CTX_T *p) static void TransferToRegControl(void) { - /* Chen-Hsiang@20160323: After leave preloader and low power scenario, conf is controller by RG*/ + } -static void TransferToSPMControl(DRAMC_CTX_T *p)//Open all APHY controls from SPM path except PWR_ON && ISO (related to low power and DVFS) +static void TransferToSPMControl(DRAMC_CTX_T *p) { -#if ENABLE_TX_TRACKING //HW mode - vIO32WriteFldAlign_All(DRAMC_REG_TX_TRACKING_SET0, 0x0, TX_TRACKING_SET0_TX_TRACKING_OPT);//Set TX_TRACKING_OPT = 0 to let spm side band control HW TX tracking +#if ENABLE_TX_TRACKING + vIO32WriteFldAlign_All(DRAMC_REG_TX_TRACKING_SET0, 0x0, TX_TRACKING_SET0_TX_TRACKING_OPT); #endif -#if 0 // Low power features remove to others RG: B0_LP_CTRL0/B1_LP_CTRL/CA_LP_CTRL/MISC_LP_CTRL +#if 0 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xfbffefff, MISC_SPM_CTRL0_PHY_SPM_CTL0); vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0xffffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2); - vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2 + SHIFT_TO_CHB_ADDR, 0x7fffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2);//Lewis@20170627: Set CHB CA DLL type to slave mode + vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2 + SHIFT_TO_CHB_ADDR, 0x7fffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2); #endif return; @@ -1376,18 +1356,18 @@ void DPMInit(DRAMC_CTX_T *p) u1SetVal = (p->support_channel_num > 1) ? 0x3 : 0x1; - // pre-setting DPM to dramc low power interface setting + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) | // both channel phy pll en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) | // both channel dpy pll en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) | // both channel dpy 2nd pll en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) | // both channel dpy dll ck en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN)); // both channel dpy vref en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN)); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) | // both channel mck8x en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) | // both channel midpi en - P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN)); // both channel dpy pi resetb en + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) | + P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN)); if (p->u1PLLMode == PHYPLL_MODE) { @@ -1408,17 +1388,17 @@ void DPMInit(DRAMC_CTX_T *p) P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN) | P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW)); - // all by lpif fw mode + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, - /* TBA set control mux in DV initial */ - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | // 0: DPM, 1: SPM - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | // 0: DPM, 1: SPM - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | // 0: DPM, 1: SPM - P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) | // 0: DPM, 1: SPM - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) | // 0: DPM SCU, 1: DPM CFG - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) | // 0: DPM SCU, 1: DPM CFG - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) | // 0: DPM SCU, 1: DPM CFG - P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND)); // 0: DPM SCU, 1: DPM CFG + + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) | + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) | + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) | + P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) | + P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND)); vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0, P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) | @@ -1426,7 +1406,7 @@ void DPMInit(DRAMC_CTX_T *p) P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) | P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) | P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) | - P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | // @Darren, fix dfs phypll init + P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) | P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW)); u1ShuSramVal = u1CurrShuLevel; @@ -1434,18 +1414,18 @@ void DPMInit(DRAMC_CTX_T *p) if (p->support_channel_num > 1) u1ShuSramVal |= u1CurrShuLevel << 4; - // NOTE: DPM PST mode shuffle level = (LPIF_CTRL_CTRL1_LPIF_DRAMC_DR_SHU_LEVEL_SRAM | LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL) + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ShuSramVal, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL); #if __ETT__ vIO32WriteFldAlign_All(DDRPHY_MD32_REG_SSPM_CFGREG_GPR0, 0xE7700E77, SSPM_CFGREG_GPR0_GPR0); #endif - // for DFS + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN); vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN); - // enable DFD + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 , 0x1, LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN); } #endif @@ -1499,11 +1479,11 @@ void DFSBypassMR13HwSet(DRAMC_CTX_T *p) mcSHOW_ERR_MSG(("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx)); break; } - BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //0x1 (Bypass), 0x0 (Not bypass) + BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //mcSHOW_DBG_MSG(("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP)); vIO32WriteFldAlign_All(TransferReg.u4Addr, BFSP, TransferReg.u4Fld); } - vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); // 1: shuffle level = 10, 0: shuffle level =4 + vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CDC_CTRL, 0x0, MISC_CDC_CTRL_REG_CDC_BYPASS_DBG); vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0x1, BYPASS_FSPOP_BPFSP_OPT); #endif @@ -1557,7 +1537,7 @@ void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T srcRG, DRAM_DFS_S } vSetPHY2ChannelMapping(p, eOriChannel); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //MP setting:should disable WR MDOE + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE); } void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_REG_SHU_T dstRG) @@ -1574,8 +1554,8 @@ void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_ vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE); //diff with DramcSaveToShuffleSRAM - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE); // diff with DramcSaveToShuffleSRAM + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM); @@ -1613,7 +1593,7 @@ static U8 WaitChShuEnAck(DRAMC_CTX_T *p, U32 u4Addr, U32 u4Fld, U8 u1Status) } vSetPHY2ChannelMapping(p, eOriChannel); - return u1AckDone; // shu end + return u1AckDone; } void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) @@ -1638,7 +1618,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le u1ShuAck |= (0x1 << i); } - /* cc: Fix RG mode Hang. Since ACK is read from DPM and a DPM can only support up to 2 dram channels */ + u1SramAck = u1ShuAck; u1ShuAck &= 0x3; @@ -1651,10 +1631,10 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le mcSHOW_DBG_MSG4(("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); - // sram latch + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH); mcDELAY_US(1); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH); @@ -1675,14 +1655,14 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le } mcDELAY_US(1); -#if 1 //Darren- +#if 1 //vIO32WriteFldMulti((DDRPHY_MISC_SPM_CTRL3), P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH1) // | P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH0)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM); - //wait sram load ack. + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD); - //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK)); // wait SRAM PLL load ack + //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK)); while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, u1ChkComplete) != u1SramAck) //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK)) { @@ -1694,15 +1674,15 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le if (p->u1PLLMode == PHYPLL_MODE) { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); } else { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); } - #if 0//ENABLE_DFS_DEBUG_MODE + #if 0 EntryDFSDebugMode(p, CHG_CLK_MODE); #endif @@ -1711,9 +1691,9 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le #endif #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_US(20); #else - mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_XUS(20); #endif #if 0 @@ -1728,22 +1708,21 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_le //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN); mcSHOW_DBG_MSG4(("SHUFFLE Start\n")); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from SHU_EN=1 to ACK, DV spec < 5.1us + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); #if DFS_NOQUEUE_FLUSH_ENABLE && ENABLE_DFS_NOQUEUE_FLUSH_DBG - WaitNoQueueFlushComplete(p); // for debug mode MRW skip + WaitNoQueueFlushComplete(p); #endif - // Fixed DV sim spec for DFS shu_en=1 < 5.1us and shu_en=0 < 120ns -#if 1//Darren-for test chip(FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) + +#if 1 //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n")); //mcDELAY_US(5); - #if 0//ENABLE_DFS_DEBUG_MODE + #if 0 ChkDFSDebugMode(p, CHG_CLK_MODE); #endif - //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END - //@tg Fix RG mode can not recevie shuffle end ack. + if (channel_num_auxadc <= 2) { while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck) { @@ -1759,10 +1738,10 @@ else { } #else - while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); // SHUFFLE_END + while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); #endif - #if 0//ENABLE_DFS_DEBUG_MODE + #if 0 ExitDFSDebugMode(p, CHG_CLK_MODE); #endif @@ -1775,7 +1754,7 @@ else { #endif //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from ACK to SHU_EN=0, DV spec < 120ns + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); mcSHOW_DBG_MSG4(("SHUFFLE End\n")); #if ENABLE_DDR800_SOPEN_DSC_WA @@ -1790,19 +1769,16 @@ else { if (p->u1PLLMode == PHYPLL_MODE) { - /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); } else { - /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); } -#if 1 //Darren- - //wait sram restore ack. +#if 1 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE); while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, u1ChkComplete) != u1SramAck) //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK)) @@ -1811,7 +1787,7 @@ else { } vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE); - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); #endif @@ -1849,7 +1825,7 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) u1ShuAck |= (0x1 << i); } - /* cc: Fix RGmode Hang. Since ACK is read from DPM and a DPM can only support up to 2 dram channels */ + u1ShuAck &= 0x3; if (p->u1PLLMode == PHYPLL_MODE) @@ -1861,13 +1837,13 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) mcSHOW_DBG_MSG4(("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); if (shu_level == DRAM_DFS_REG_SHU0) - u1shu_level = shu_level; // Darren: shuffle to shu0 status (original calib flow.) + u1shu_level = shu_level; else - u1shu_level = 1; // Darren: Using shu1 for backup/restore, it diff with SPM mode + u1shu_level = 1; if (p->u1PLLMode == PHYPLL_MODE) { @@ -1888,18 +1864,18 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) if (p->u1PLLMode == PHYPLL_MODE) { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN); } else { //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN); } #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - mcDELAY_US(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_US(20); #else - mcDELAY_XUS(20); // for SRAM shuffle DV sim spec > 20us + mcDELAY_XUS(20); #endif #if 0 @@ -1919,8 +1895,8 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level) //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n")); //mcDELAY_US(5); - //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END - //@tg Fix RG mode can not recevie shuffle end ack. + //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) + if (channel_num_auxadc <= 2) { while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck) { @@ -1949,18 +1925,18 @@ else { if (p->u1PLLMode == PHYPLL_MODE) { - /*TINFO="DRAM : set sc_phypll_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); // Disable PHYPLL - vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN); } else { - /*TINFO="DRAM : set sc_phypll2_mode_sw=0"*/ - //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); // Disable CLRPLL - vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); // Darren NOTE: Don't use PHYPLLx_MODE_SW and it will lock RCLRPLL_EN and RPHYPLL_EN control + + //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW); + vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN); } - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); mcSHOW_DBG_MSG4(("Shuffle flow complete\n")); @@ -1974,7 +1950,7 @@ void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) U8 u1ShuAck = 0, u1EnDPMCh = 0; U8 u1ChIdx = 0; U8 u1ChNum_dpm = (p->support_channel_num==CHANNEL_SINGLE)?0x1:0x2; - U8 pingpong_shu_level = 0; // for shu0/1 + U8 pingpong_shu_level = 0; U8 u1PingPong = 0; U16 u2SramLevel = 0; @@ -1993,16 +1969,15 @@ void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); // HJ Huang - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH); mcDELAY_US(1); vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH); - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB - pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); // read shuffle level for dramc conf0/1 + + pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); mcSHOW_DBG_MSG4(("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1))); for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++) { @@ -2031,7 +2006,7 @@ void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level) DFSRuntimeMRWEn(p, p->u1PLLMode, shu_level); #endif -#if 0 //Darren test+ +#if 0 vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, 0, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL); vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, shu_level, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL); #else @@ -2089,10 +2064,10 @@ else { mcDELAY_US(20); - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); //func_imp_tracking_value_backup(); @@ -2101,8 +2076,8 @@ else { #if ENABLE_DFS_SSC_WA DVS_DMY_RD_EXIT(p); - //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); // for waveform measure - //mcDELAY_US(10); // for waveform measure + //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE); + //mcDELAY_US(10); #endif #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION @@ -2119,7 +2094,7 @@ else { #if ENABLE_DFS_DEBUG_MODE ChkDFSDebugMode(p, CHG_CLK_MODE); - // Add WA at here + ExitDFSDebugMode(p, CHG_CLK_MODE); #endif @@ -2139,8 +2114,8 @@ else { } } #if DFS_NOQUEUE_FLUSH_LATENCY_CNT - U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); // show chx max cnt - // cnt * 8 * 4.8ns (208M) + U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); + mcSHOW_DBG_MSG2(("\tMAX CNT = %d\n", MaxCnt)); #endif @@ -2156,9 +2131,9 @@ else { mcSHOW_DBG_MSG4(("SHUFFLE End\n")); if (p->u1PLLMode == PHYPLL_MODE) - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); else - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION DDR800semiPowerSavingOn(p, shu_level, ENABLE); @@ -2177,7 +2152,7 @@ else { #endif //func_imp_tracking_on(); -#if 1 //Darren test+ +#if 1 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE); if (channel_num_auxadc <= 2) { @@ -2198,13 +2173,10 @@ else { vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE); #endif - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); EnableDramcTrackingByShuffle(p, u1EnDPMCh, ENABLE); - //----------------------------------- - // TRIGGER DRAM GATING ERROR - //----------------------------------- //func_dram_dummy_read_on(); //mcDELAY_US(2); //func_dram_dummy_read_off(); @@ -2239,8 +2211,7 @@ void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_leve mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode_forK to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck)); } - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA - //LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB + mcSHOW_DBG_MSG4(("Direct jump to CONF%d\n", shu_level)); for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++) { @@ -2270,10 +2241,10 @@ void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_leve mcDELAY_US(20); - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); - /*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/ + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); @@ -2299,11 +2270,11 @@ else { mcSHOW_DBG_MSG4(("SHUFFLE End\n")); if (p->u1PLLMode == PHYPLL_MODE) - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); else - vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // CLRPLL off + vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); + - /*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/ vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); p->u1PLLMode = !p->u1PLLMode; @@ -2316,19 +2287,19 @@ else { void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level) { #if (DRAMC_DFS_MODE == 2) - gDVFSCtrlSel = 2; // SRAM RG mode + gDVFSCtrlSel = 2; #elif (DRAMC_DFS_MODE == 1) - gDVFSCtrlSel = 1; // DPM mode + gDVFSCtrlSel = 1; #elif (DRAMC_DFS_MODE == 0) - gDVFSCtrlSel = 0; // Legacy mode + gDVFSCtrlSel = 0; #endif if (gDVFSCtrlSel == 0) { - if (shu_level == SRAM_SHU0) // DDR4266 - DramcDFSDirectJump_RGMode(p, 0); // Legacy mode for CONF0 + if (shu_level == SRAM_SHU0) + DramcDFSDirectJump_RGMode(p, 0); else - DramcDFSDirectJump_RGMode(p, 1); // Legacy mode for CONF1 + DramcDFSDirectJump_RGMode(p, 1); } else if (gDVFSCtrlSel == 1) { @@ -2342,9 +2313,9 @@ void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level) #if 0 static void No_Parking_On_CLRPLL(DRAMC_CTX_T *p) { - if (p->u1PLLMode == PHYPLL_MODE) return; /* already parking on PHYPLL */ + if (p->u1PLLMode == PHYPLL_MODE) return; - DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0); /* parking on PHYPLL */ + DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0); } #endif void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p) @@ -2352,8 +2323,7 @@ void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p) U8 operating_fsp = p->dram_fsp; U8 u1RankIdx, backup_rank= u1GetRank(p); - // Support single rank and dual ranks - // Double confirm from CLRPLL to PHYPLL + if (operating_fsp == FSP_1) { cbt_dfs_mr13_global(p, CBT_HIGH_FREQ); diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c index 97800f4f21..1137db81de 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c @@ -11,13 +11,10 @@ //----------------------------------------------------------------------------- U8 gDRSEnableSelfWakeup = 0; -//---------------------------------------- -// Auto Gen Code -- START -//---------------------------------------- #if (CHECK_GOLDEN_SETTING == TRUE) typedef struct _GOLDEN_FIELD_T { - char fieldName[64]; //field name + char fieldName[64]; U32 group; U32 field; U32 u4ChaValue; @@ -25,7 +22,7 @@ typedef struct _GOLDEN_FIELD_T GOLDEN_FIELD_T *golden_setting_anwer; #if APPLY_LOWPOWER_GOLDEN_SETTINGS -// DCM On + GOLDEN_FIELD_T shuf_golden_setting_anwer[] = { {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0}, @@ -169,7 +166,7 @@ GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] = }; #else -// DCM Off + GOLDEN_FIELD_T shuf_golden_setting_anwer[] = { {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x1}, @@ -336,7 +333,7 @@ static void EnableCommonDCMNonShuffle(DRAMC_CTX_T *p) P_Fld(0x0, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE) | P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG) | P_Fld(0x5, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT)); - // RG group needs to be toggled!! + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); vIO32WriteFldAlign_All(DDRPHY_REG_CA_DLL_ARPI1, 0x0, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT); @@ -395,7 +392,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; U8 MPDIV_CG = 1; - // Special case + EnableCommonDCMNonShuffle(p); if(bEn) @@ -407,7 +404,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2, P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) | P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN)); - // RG group needs to be toggled!! + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, @@ -475,7 +472,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4, #if (RX_PICG_NEW_MODE || TX_PICG_NEW_MODE) P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_MCK) | - P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) | //WA for DDR800 DSC DRAM, Need to check in Sim + P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) | #endif #if RX_PICG_NEW_MODE P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQSIEN) | @@ -501,7 +498,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2, P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) | P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN)); - // RG group needs to be toggled!! + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG); vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, @@ -582,7 +579,7 @@ void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn) void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - // Special case + // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND3: Special case // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND2: Special case // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND1: Special case @@ -662,9 +659,7 @@ void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn) return; } -//---------------------------------------- -// Auto Gen Code -- END -//---------------------------------------- + void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn) { @@ -672,7 +667,7 @@ void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn) DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); EnableDramcPhyDCMNonShuffle(p, bEn); - EnableDramcPhyDCMShuffle(p, bEn);//only need to set SHU0 RG while init, SHU0 will copy to others + EnableDramcPhyDCMShuffle(p, bEn); #if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0)) DRAM_STATUS_T stResult = CheckGoldenSetting(p); @@ -726,7 +721,7 @@ DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p) u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN); mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value)); - for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); @@ -774,15 +769,15 @@ static DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_set U16 u2Idx = 0; for(u2Idx = 0; u2Idx < array_cnt; u2Idx++) { - for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)//comapre CHA && CHB + for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) { vSetPHY2ChannelMapping(p, channel_idx); u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field); //mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value)); - u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);//golden_setting_anwer only has CHA value + u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue); - if(u4Answer != 0xffffffff)//0xffffffff: no need to compare + if(u4Answer != 0xffffffff) { if(u4Answer == u4Value) { @@ -823,11 +818,11 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p) else { mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2)); - u1SramShuffleIdx = u1BkShuffleIdx; //Restore to original freq && check conf SHU0 + u1SramShuffleIdx = u1BkShuffleIdx; } //mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n", sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0]))); - DramcDFSDirectJump(p, u1SramShuffleIdx); //fill conf SHU0 && SHU1 from SRAM SHU(0~9) while DVFS twice + DramcDFSDirectJump(p, u1SramShuffleIdx); DramcDFSDirectJump(p, u1SramShuffleIdx); eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer)); @@ -846,7 +841,7 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p) } #endif -//#ifdef HW_SAVE_FOR_SR + void HwSaveForSR(DRAMC_CTX_T *p) { vIO32WriteFldMulti_All(DRAMC_REG_SREF_DPD_CTRL, P_Fld(0, SREF_DPD_CTRL_GT_SYNC_MASK) @@ -854,15 +849,13 @@ void HwSaveForSR(DRAMC_CTX_T *p) | P_Fld(1, SREF_DPD_CTRL_SREF2_OPTION) | P_Fld(0, SREF_DPD_CTRL_SREF3_OPTION)); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY);//PIC: Robert + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY); } //#endif //#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL -//If dramc enter SREF and power down, all configure need to sync 2T again after exit SREF. -//If Psel is 1, clock will be free run at the periof of 2T to let conf be applied. -//If Psel is 0, Clock will be gated + void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p) { vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, P_Fld(0, TX_CG_SET0_PSEL_OPT1) @@ -887,26 +880,26 @@ void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff) U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP); U8 u1IsDdr800Semi = u4IO32ReadFldAlign(DDRPHY_REG_SHU_PLL1 + (SHU_GRP_DDRPHY_OFFSET * u1ShuLevel), SHU_PLL1_RG_RPHYPLL_DDR400_EN); - if (u1IsDdr800Semi != 1) // close mode will return + if (u1IsDdr800Semi != 1) return; if ((next_shu_level != SRAM_SHU9) && (u1OnOff == DISABLE)) { - // for NORMAL_CLOSE_LOOP + EnableDllCg(p, DISABLE); } else if ((next_shu_level == SRAM_SHU9) && (u1OnOff == ENABLE)) { - // for DDR800_SEMI_LOOP power saving, clock gating + EnableDllCg(p, ENABLE); } #endif } #endif -#if 0 //Comment out unused code +#if 0 void DramcDRS(DRAMC_CTX_T *p, U8 bEnable) { - //R_DMDRS_CNTX[6:0](DVT set 0, HQA set 4 or 5) + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DRSCTRL), P_Fld(0, DRSCTRL_DRSPB2AB_OPT) | P_Fld(0, DRSCTRL_DRSMON_CLR) | P_Fld(8, DRSCTRL_DRSDLY) @@ -919,7 +912,7 @@ void DramcDRS(DRAMC_CTX_T *p, U8 bEnable) } #endif -#if 0 //Comment out unused code +#if 0 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op) { @@ -931,11 +924,9 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op) mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit"))); - if (op == 1) // enter self refresh + if (op == 1) { - // ONLY work for LP4, not LP3 - // MISCA_SRFPD_DIS =1, self-refresh - // MISCA_SRFPD_DIS =0, self-refresh power down + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SRFPD_DIS); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SELFREF); @@ -949,7 +940,7 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op) u4TimeCnt --; } } - else // exit self refresh + else { vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 0, SREFCTRL_SELFREF); @@ -974,26 +965,26 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op) } } #endif -#endif //Comment out unused code +#endif //#if ENABLE_RX_DCM_DPHY void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq) { U8 u1PRECAL_CG_EN = 0; - //open loop mode and semi-open do not enable tracking + if (u1IsPhaseMode(p) == TRUE) u1PRECAL_CG_EN = 1; else u1PRECAL_CG_EN = 0; - //power gain + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT) | P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) | P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT) | P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN) | - P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) | // if Rx gating Auto K, set 0, Runtime set 1 + P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) | P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) | P_Fld(u1PRECAL_CG_EN, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN) | P_Fld(0x2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) | @@ -1002,7 +993,7 @@ void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq) #if RDSEL_TRACKING_EN if(u2Freq >= RDSEL_TRACKING_TH) { - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN); // if K, set 1, at runtime if enable, set 0, else 1 + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN); } else #endif @@ -1022,7 +1013,7 @@ void EnableCmdPicgEffImprove(DRAMC_CTX_T *p) { u2Clk_Dyn_Gating_Sel = 0x6; } - else //DIV8_MODE, DIV16_MODE + else { u2Clk_Dyn_Gating_Sel = 0x5; } diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c index 3badd6ebb3..c64af885dc 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c @@ -26,37 +26,36 @@ U8 u1PrintModeRegWrite = 0; #if ENABLE_RODT_TRACKING_SAVE_MCK -// global variables for RODT tracking & ROEN -U8 u1ODT_ON; // infor of p->odt_onoff -U8 u1WDQS_ON = 0; // infor of WDQS on(ROEN=1) -U8 u1RODT_TRACK = 0; // infor of rodt tracking enable -U8 u1ROEN, u1ModeSel;//status of ROEN, MODESEL setting + +U8 u1ODT_ON; +U8 u1WDQS_ON = 0; +U8 u1RODT_TRACK = 0; +U8 u1ROEN, u1ModeSel; #endif -//MRR DRAM->DRAMC + const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = { { - // for EMCP - //CH-A + { 0, 1, 2, 3, 5, 7, 6, 4, 9, 8, 13, 15, 10, 14, 11, 12 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 5, 4, 3, 7, 6, 2, 9, 8, 13, 14, 10, 15, 11, 12 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 5, 7, 6, 4, 9, 8, 13, 15, 10, 14, 11, 12 }, - //CH-D + { 0, 1, 5, 4, 3, 7, 6, 2, 9, 8, 13, 14, 10, 15, 11, 12 @@ -64,26 +63,25 @@ const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = #endif }, { - // for DSC_2CH, HFID RESERVED - //CH-A + { 0, 1, 4, 3, 2, 5, 7, 6, 9, 8, 10, 11, 14, 13, 15, 12 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 2, 4, 5, 3, 7, 6, 8, 9, 10, 11, 15, 14, 13, 12 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, - //CH-D + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 @@ -91,26 +89,25 @@ const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = #endif }, { - // for MCP - //CH-A + { 0, 1, 3, 6, 4, 7, 2, 5, 8, 9, 10, 13, 11, 12, 15, 14 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 4, 7, 3, 5, 6, 2, 9, 8, 10, 12, 11, 14, 13, 15 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 14, 11, 15, 13, 12 }, - //CH-D + { 0, 1, 4, 7, 3, 5, 6, 2, 9, 8, 10, 12, 11, 14, 13, 15 @@ -118,26 +115,25 @@ const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = #endif }, { - // for DSC_180 - //CH-A + { 9, 8, 11, 10, 14, 15, 13, 12, 0, 1, 7, 6, 4, 5, 2, 3 }, #if (CHANNEL_NUM>1) - //CH-B + { 8, 9, 11, 10, 12, 14, 13, 15, 1, 0, 5, 6, 3, 2, 7, 4 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12 }, - //CH-D + { 1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15 @@ -147,28 +143,28 @@ const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = }; -//MRR DRAM->DRAMC + U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] = { - //CH-A + { 0, 1, 2, 3, 7, 4, 6, 5, 9, 8, 12, 14, 15, 10, 13, 11 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 7, 4, 3, 2, 6, 5, 9, 8, 12, 14, 15, 10, 11, 13 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 7, 4, 6, 5, 9, 8, 12, 14, 15, 10, 13, 11 }, - //CH-D + { 0, 1, 7, 4, 3, 2, 6, 5, 9, 8, 12, 14, 15, 10, 11, 13 @@ -203,20 +199,20 @@ static void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p) U32 backup_broadcast; DRAM_CHANNEL_T chIdx = CHANNEL_A; - //Backup channel & broadcast + backup_channel = vGetPHY2ChannelMapping(p); backup_broadcast = GetDramcBroadcast(); - DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //Disable broadcast + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + - //LP4: Set each channel's pinmux individually, LP3: Only has 1 channel (support_channel_num == 1) for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++) { vSetPHY2ChannelMapping(p, chIdx); uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR4_MRR_Mapping_POP[chIdx]; - //Set MRR pin mux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_MRR_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_MRR_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) | P_Fld(uiLPDDR_MRR_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_MRR_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_MRR_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_MRR_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) | @@ -227,7 +223,7 @@ static void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p) P_Fld(uiLPDDR_MRR_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_MRR_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL)); } - //Recover channel & broadcast + vSetPHY2ChannelMapping(p, backup_channel); DramcBroadcastOnOff(backup_broadcast); } @@ -240,20 +236,20 @@ static void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p) U32 backup_broadcast; DRAM_CHANNEL_T chIdx = CHANNEL_A; - //Backup channel & broadcast + backup_channel = vGetPHY2ChannelMapping(p); backup_broadcast = GetDramcBroadcast(); - DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); //Disable broadcast + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); + - //LP4: Set each channel's pinmux individually, LP3: Only has 1 channel (support_channel_num == 1) for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++) { vSetPHY2ChannelMapping(p, chIdx); uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[chIdx]; - //Set MRR pin mux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0), P_Fld(uiLPDDR_DQO1_Mapping[0], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0) | P_Fld(uiLPDDR_DQO1_Mapping[1], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1) | P_Fld(uiLPDDR_DQO1_Mapping[2], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2) @@ -272,7 +268,7 @@ static void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p) | P_Fld(uiLPDDR_DQO1_Mapping[15], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15)); } - //Recover channel & broadcast + vSetPHY2ChannelMapping(p, backup_channel); DramcBroadcastOnOff(backup_broadcast); } @@ -286,7 +282,7 @@ static void SetRankInfoToConf(DRAMC_CTX_T *p) emi_set = &g_default_emi_setting; - u4value = ((emi_set->EMI_CONA_VAL >> 17) & 0x1)? 0: 1;//CONA 17th bit 0: Disable dual rank mode 1: Enable dual rank mode + u4value = ((emi_set->EMI_CONA_VAL >> 17) & 0x1)? 0: 1; vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, u4value, SA_RESERVE_SINGLE_RANK); @@ -314,7 +310,7 @@ static void UpdateHighestFreqInDFSTbl(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T new_fr DRAM_PLL_FREQ_SEL_T cur_freq_sel = 0; U8 u1ShuffleIdx = 0; - // lookup table to find highest freq + cur_freq_sel = GetSelByFreq(p, u2HighestFreq); if (cur_freq_sel == new_freq_sel) return; @@ -323,13 +319,13 @@ static void UpdateHighestFreqInDFSTbl(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T new_fr if (gFreqTbl[u1ShuffleIdx].freq_sel == cur_freq_sel) break; - gFreqTbl[u1ShuffleIdx].freq_sel = new_freq_sel; // update + gFreqTbl[u1ShuffleIdx].freq_sel = new_freq_sel; gUpdateHighestFreq = TRUE; - u2HighestFreq = u2DFSGetHighestFreq(p); // @Darren, Update u2FreqMax variables + u2HighestFreq = u2DFSGetHighestFreq(p); #if __ETT__ - UpdateEttDFVSTblHighest(p, cur_freq_sel, new_freq_sel); //@Darren, Update for ETT DVFS stress + UpdateEttDFVSTblHighest(p, cur_freq_sel, new_freq_sel); #endif mcSHOW_DBG_MSG2(("[UpdateHighestFreqInDFSTbl] Get Highest Freq is %d\n", u2HighestFreq)); #endif @@ -387,13 +383,7 @@ static void vInitDeviationVariable(void) { gSetSpecificedVref_Enable[0] = ENABLE; - /* - CH_BA : (0: ch A + rank 0) - CH_BA : (1: ch A + rank 1) - CH_BA : (2: ch B + rank 0) - CH_BA : (3: ch B + rank 1) - CH_BA : (4: All Channel and All Rank) - */ + if (deviation_info_ptr->ca_channel_bank == 4) { gSetSpecificedVref_All_ChRk[0] = ENABLE; @@ -494,11 +484,7 @@ void Global_Option_Init(DRAMC_CTX_T *p) #endif } -/* RxDQSIsiPulseCG() - API for "RX DQS ISI pulse CG function" 0: disable, 1: enable - * 1. RG_*_RPRE_TOG_EN (16nm APHY): B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1 - * 2. RG_RX_*RDQS*_DQSSTB_CG_EN*(10nm APHY): B0_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B0, B1_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B1 - * Supports setting current channel only, add function to set "all channels" in the future - */ + #if 0 static void RxDQSIsiPulseCG(DRAMC_CTX_T *p, U8 u1OnOff) { @@ -506,11 +492,7 @@ static void RxDQSIsiPulseCG(DRAMC_CTX_T *p, U8 u1OnOff) mcSHOW_DBG_MSG4(("CH%u RX DQS ISI pulse CG: %u (0:disable, 1:enable)\n", u1OnOff)); - /* LP4: Disable(set to 0) "RX DQS ISI pulse CG function" during the below senarios (must enable(set to 1) when done) - * 1. Gating window calibration - * 2. Duty related calibration (Justin: prevents DQSI from being kept high after READ burst) - * LP3: should always be set to 1 - */ + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1); @@ -528,7 +510,7 @@ static void OpenLoopModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eDDR800Mode) { #if __A60868_TO_BE_PORTING__ - //Enable SHU option for MCK8X_EN and PHDET_EN + if (eDDR800Mode == DDR800_OPEN_LOOP) { vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL6, P_Fld(0x1, MISC_CG_CTRL6_RG_M_CK_OPENLOOP_MODE_EN) @@ -585,7 +567,7 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 DDR800Mode.pll0_ada_mck8x_chb_en = 1; DDR800Mode.pll0_ada_mck8x_cha_en = 1; - if (p->frequency <= 400) //DDR800 1:4 mode + if (p->frequency <= 400) { *uDLL1 = 1; *uMode = 0; @@ -593,27 +575,27 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 } else if (p->frequency <= 800) { - if (vGet_Div_Mode(p) == DIV8_MODE) // DDR1600 1:8 mode + if (vGet_Div_Mode(p) == DIV8_MODE) { *uDLL1 = 0; *uMode = 0; *uDLL0 = 2; } - else // DDR1600 1:4 mode + else { *uDLL1 = 0; *uMode = 1; *uDLL0 = 0; } } - else // 1:8 mode + else { *uDLL1 = 0; *uMode = 0; *uDLL0 = 2; } } - else if (eMode == DDR800_OPEN_LOOP) // For DDR800 + else if (eMode == DDR800_OPEN_LOOP) { DDR800Mode.phypll_ddr400_en = 1; DDR800Mode.ddr400_en_b0 = 1; @@ -625,12 +607,12 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 DDR800Mode.dll_phdet_en_ca_chb = 0; DDR800Mode.phypll_ada_mck8x_en = 0; #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - DDR800Mode.ddr400_dqs_ps_b0 = 0; // 2'b00-0 degree, 2'b01-45 degree, 2'b10-90 degree + DDR800Mode.ddr400_dqs_ps_b0 = 0; DDR800Mode.ddr400_dqs_ps_b1 = 0; DDR800Mode.ddr400_dq_ps_b0 = 0; DDR800Mode.ddr400_dq_ps_b1 = 0; - DDR800Mode.ddr400_dqs_ps_ca = 0; // clk - DDR800Mode.ddr400_dq_ps_ca = 0; // ca + DDR800Mode.ddr400_dqs_ps_ca = 0; + DDR800Mode.ddr400_dq_ps_ca = 0; #else DDR800Mode.ddr400_dqs_ps_b0 = 1; DDR800Mode.ddr400_dqs_ps_b1 = 1; @@ -649,7 +631,7 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 *uMode = 1; *uDLL0 = 0; } - else if (eMode == DDR800_SEMI_LOOP) // For DDR800 + else if (eMode == DDR800_SEMI_LOOP) { DDR800Mode.phypll_ddr400_en = 1; DDR800Mode.ddr400_en_b0 = 1; @@ -661,12 +643,12 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 DDR800Mode.dll_phdet_en_ca_chb = 0; DDR800Mode.phypll_ada_mck8x_en = 1; #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) - DDR800Mode.ddr400_dqs_ps_b0 = 0; // 2'b00-0 degree, 2'b01-45 degree, 2'b10-90 degree + DDR800Mode.ddr400_dqs_ps_b0 = 0; DDR800Mode.ddr400_dqs_ps_b1 = 0; DDR800Mode.ddr400_dq_ps_b0 = 0; DDR800Mode.ddr400_dq_ps_b1 = 0; - DDR800Mode.ddr400_dqs_ps_ca = 0; // clk - DDR800Mode.ddr400_dq_ps_ca = 0; // ca + DDR800Mode.ddr400_dqs_ps_ca = 0; + DDR800Mode.ddr400_dq_ps_ca = 0; #else DDR800Mode.ddr400_dqs_ps_b0 = 1; DDR800Mode.ddr400_dqs_ps_b1 = 1; @@ -685,7 +667,7 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 *uMode = 1; *uDLL0 = 2; } - else // Others + else { mcSHOW_ERR_MSG(("[FAIL] APhy mode incorrect !!!\n")); #if __ETT__ @@ -693,14 +675,14 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 #endif } - // Enable DDR800 RG - vIO32WriteFldAlign(DDRPHY_SHU_PLL1, DDR800Mode.phypll_ddr400_en, SHU_PLL1_RG_RPHYPLL_DDR400_EN); // CHA only + + vIO32WriteFldAlign(DDRPHY_SHU_PLL1, DDR800Mode.phypll_ddr400_en, SHU_PLL1_RG_RPHYPLL_DDR400_EN); //vIO32WriteFldAlign_All(DDRPHY_PLL4, DDR800Mode.phypll_ada_mck8x_en, PLL4_RG_RPHYPLL_ADA_MCK8X_EN); vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, DDR800Mode.ddr400_en_b0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0); vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, DDR800Mode.ddr400_en_b1, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1); vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, DDR800Mode.ddr400_en_ca, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA); - // DLL & Clock + vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, DDR800Mode.dll_phdet_en_b0, SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU); vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, DDR800Mode.dll_phdet_en_b1, SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU); vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, DDR800Mode.dll_phdet_en_ca_cha, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); @@ -709,7 +691,7 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.pll0_ada_mck8x_chb_en, SHU_PLL0_ADA_MCK8X_CHB_EN); vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.pll0_ada_mck8x_cha_en, SHU_PLL0_ADA_MCK8X_CHA_EN); - // CA/DQS/DQ position + vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_dqs_ps_b0, SHU_B0_DQ9_RG_DDR400_DQS_PS_B0); vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_dqs_ps_b1, SHU_B1_DQ9_RG_DDR400_DQS_PS_B1); vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_dq_ps_b0, SHU_B0_DQ9_RG_DDR400_DQ_PS_B0); @@ -717,7 +699,7 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_dqs_ps_ca, SHU_CA_CMD9_RG_DDR400_DQS_PS_CA); vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_dq_ps_ca, SHU_CA_CMD9_RG_DDR400_DQ_PS_CA); - // Semi Open Enable + vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_semi_en_b0, SHU_B0_DQ9_RG_DDR400_SEMI_EN_B0); vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_semi_en_b1, SHU_B1_DQ9_RG_DDR400_SEMI_EN_B1); vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_semi_en_ca, SHU_CA_CMD9_RG_DDR400_SEMI_EN_CA); @@ -728,7 +710,7 @@ static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 static void DDRDllModeSetting(DRAMC_CTX_T * p) { #if __A60868_TO_BE_PORTING__ - U8 uDLL1 = 0, uMode = 0, uDLL0 = 2; // 1:8 mode for bring-up + U8 uDLL1 = 0, uMode = 0, uDLL0 = 2; APhyModeSetting(p, vGet_DDR800_Mode(p), &uDLL1, &uMode, &uDLL0); @@ -767,7 +749,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) U8 u1Gain_Ca_ChA = 0, u1Gain_Ca_ChB = 0; U8 u1CurrShuLevel = 0; - u1VTH_SEL = 0x2; /* RG_*RPI_MIDPI_VTH_SEL[1:0] is 2 for all freqs */ + u1VTH_SEL = 0x2; #if (fcFOR_CHIP_ID == fcLafite) if (p->frequency <= 400) @@ -798,12 +780,12 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) { u1CAP_SEL = 0x2; } - else//4266 + else { u1CAP_SEL = 0x1; } - if (p->frequency <= 933) //Lewis@20161129: Fix DDR1600 S-idle Vcore power is too big problem. + if (p->frequency <= 933) { u1MIDPICAP_SEL = 0x2; } @@ -823,14 +805,14 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) { u1MIDPICAP_SEL = 0x1; } - else//4266 + else { u1MIDPICAP_SEL = 0x0; } #if EMI_LPBK_USE_DDR_800 if (p->frequency == 800) { - u1CAP_SEL = 0xf; //Ying-Yu suggest setting for FT pattern + u1CAP_SEL = 0xf; } #endif #endif @@ -862,7 +844,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) } #endif - if (u1CA_DLL_Mode[CHANNEL_A] == DLL_SLAVE)//All slave mode + if (u1CA_DLL_Mode[CHANNEL_A] == DLL_SLAVE) { vIO32WriteFldAlign_All(DRAMC_REG_SHU_DVFSCTL, 1, SHU_DVFSCTL_R_BYPASS_1ST_DLL); } @@ -884,7 +866,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA)); vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA)); - vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 1, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA); // RG_*RPI_RESERVE_CA[1] 1'b1 tracking leaf(slave) + vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 1, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA); } else { @@ -897,12 +879,12 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDIV_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA)); vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA)); - vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 0, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA); // RG_*RPI_RESERVE_CA[1] 1'b1 tracking leaf(slave) + vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 0, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA); } } #endif -#if (fcFOR_CHIP_ID == fcLafite) // @Darren, enhance DLL Gain for 4S corner DDR2400/DDR1600 0.6125V DVS fail +#if (fcFOR_CHIP_ID == fcLafite) u1CurrShuLevel = vGet_Current_SRAMIdx(p); if ((u1CurrShuLevel == SRAM_SHU4) || (u1CurrShuLevel == SRAM_SHU6)) { @@ -944,33 +926,24 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_CA_CMD7, P_Fld(0x1, CA_CMD7_RG_TX_ARCMD_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCS_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCLK_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCLKB_PULL_DN)); - // DMSUS replaced by CA_CMD2_RG_TX_ARCMD_OE_DIS, CMD_OE_DIS(1) will prevent illegal command ouput - // And DRAM 1st reset_n pulse will disappear if use CA_CMD2_RG_TX_ARCMD_OE_DIS + vIO32WriteFldAlign_All(DDRPHY_CA_CMD2, 1, CA_CMD2_RG_TX_ARCMD_OE_DIS); #endif } - //26M + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_CLK_MEM_SEL); #ifdef USE_CLK26M vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_RG_DA_RREF_CK_SEL); #endif - //PLL close sequence: - //DLL_PHDET_EN_* = 0 - //==> CG = 1 - //==> MIDPI_EN = 0(async) - //==> RG_ARPI_RESETB_* = 0 - //==> MCK8X_EN(source of clk gating) = 0 - //==> PLL_EN = 0 PIC: Ying-Yu - //DLL vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1); - //CG + vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0) | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0) | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0) @@ -999,7 +972,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN) | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA)); - //MIDPI_EN + vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)); vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1) @@ -1007,26 +980,25 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA)); - //RESETB + vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); mcDELAY_US(1); - //MCK8X_EN + vIO32WriteFldMulti_All(DDRPHY_PLL4, P_Fld(0x0, PLL4_RG_RPHYPLL_ADA_MCK8X_EN) | P_Fld(0x0, PLL4_RG_RPHYPLL_RESETB)); - //PLL + vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x0, PLL1_RG_RPHYPLL_EN); vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN); - ///TODO: PLL/MIDPI Settings - //Ref clock should be 20M~30M, if MPLL=52M, Pre-divider should be set to 1 + #ifdef USE_CLK26M vIO32WriteFldMulti_All(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_PREDIV)); vIO32WriteFldMulti_All(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_PREDIV)); - #else //MPLL 52M + #else vIO32WriteFldMulti_All(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x1, SHU_PLL8_RG_RPHYPLL_PREDIV)); vIO32WriteFldMulti_All(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x1, SHU_PLL10_RG_RCLRPLL_PREDIV)); #endif @@ -1036,9 +1008,9 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) u2SDM_PCW = 0xa400; } else if (p->frequency == 1866) - { // 2722/26=143(0x8f) + { #if ENABLE_FIX_SHORT_PLUSE - u2SDM_PCW = 0x7b00; // DDR3200 + u2SDM_PCW = 0x7b00; #else u2SDM_PCW = 0x8f00; #endif @@ -1047,21 +1019,21 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) { #if ENABLE_FIX_SHORT_PLUSE if (p->frequency == 1600) - u2SDM_PCW = 0x6c00; //DDR2800 + u2SDM_PCW = 0x6c00; #else if (p->frequency == 1600) - u2SDM_PCW = 0x7700; //DDR3200(3094) + u2SDM_PCW = 0x7700; else if (p->frequency == 800) - u2SDM_PCW = 0x7600; //DDR1600(1534) + u2SDM_PCW = 0x7600; #endif else if ((p->frequency == 400) && (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP)) - u2SDM_PCW = 0x3c00; //DDR800 Open Loop Mode + u2SDM_PCW = 0x3c00; else if (p->frequency == 400) - u2SDM_PCW = 0x7e00; //DDR826 for avoid GPS de-sense + u2SDM_PCW = 0x7e00; else - u2SDM_PCW = 0x7b00; //DDR1600 + u2SDM_PCW = 0x7b00; -#if EMI_LPBK_USE_DDR_800 // For Ei_ger DDR800 no need +#if EMI_LPBK_USE_DDR_800 if (p->frequency == 800) { vIO32WriteFldAlign_All(DDRPHY_SHU_PLL8, 0x1, SHU_PLL8_RG_RPHYPLL_POSDIV); @@ -1076,7 +1048,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) else if (p->frequency == 1200) { #if ENABLE_FIX_SHORT_PLUSE - u2SDM_PCW = 0x5100; //DDR2100 + u2SDM_PCW = 0x5100; #else u2SDM_PCW = 0x5c00; #endif @@ -1085,7 +1057,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) { u2SDM_PCW = 0x5700; } - //LP3 + else if (p->frequency == 933) { u2SDM_PCW = 0x8f00; @@ -1099,15 +1071,13 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) u2SDM_PCW = 0x4700; } - /* SDM_PCW: Feedback divide ratio (8-bit integer + 8-bit fraction) - * PLL_SDM_FRA_EN: SDMPLL fractional mode enable (0:Integer mode, 1:Fractional mode) - */ + vIO32WriteFldMulti_All(DDRPHY_SHU_PLL5, P_Fld(u2SDM_PCW, SHU_PLL5_RG_RPHYPLL_SDM_PCW) - | P_Fld(0x0, SHU_PLL5_RG_RPHYPLL_SDM_FRA_EN)); // Disable fractional mode + | P_Fld(0x0, SHU_PLL5_RG_RPHYPLL_SDM_FRA_EN)); vIO32WriteFldMulti_All(DDRPHY_SHU_PLL7, P_Fld(u2SDM_PCW, SHU_PLL7_RG_RCLRPLL_SDM_PCW) - | P_Fld(0x0, SHU_PLL7_RG_RCLRPLL_SDM_FRA_EN)); // Disable fractional mode + | P_Fld(0x0, SHU_PLL7_RG_RCLRPLL_SDM_FRA_EN)); -#if (fcFOR_CHIP_ID == fcLafite) // YH for LPDDR4 1:4 mode and 1:8 mode, Darren confirm with YH Cho +#if (fcFOR_CHIP_ID == fcLafite) DDRDllModeSetting(p); #endif @@ -1129,23 +1099,12 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(u1CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) | P_Fld(u1MIDPICAP_SEL, SHU_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA)); - //PLL open sequence - //PLL_EN = 1 - //==> some of MIDPI*_EN = 1(async) - //==> RG_ARPI_RESETB_* = 1(async, open first) - //==> MCK8X_EN(source of clk gating) = 1 - //==> CG = 0 - //==> DLL_PHDET_EN_* = 1 PIC: Ying-Yu - //PLL vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_EN); vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_EN); mcDELAY_US(100); - ///TODO: MIDPI Init 2 - /* MIDPI Settings (Olymp_us): DA_*RPI_MIDPI_EN, DA_*RPI_MIDPI_CKDIV4_EN - * Justin suggests use frequency > 933 as boundary - */ + if (p->frequency > 933) { vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0) @@ -1157,7 +1116,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) } else { - if ((p->frequency == 400) && (vGet_DDR800_Mode(p) != DDR800_CLOSE_LOOP)) // For *DDR800_OPEN_LOOP + if ((p->frequency == 400) && (vGet_DDR800_Mode(p) != DDR800_CLOSE_LOOP)) { vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)); @@ -1165,20 +1124,20 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1)); if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP) { - // DDR800_SEMI_LOOP from YY comment to DVT (1/0, CHA CA/other) + vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, 0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA); vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD6, 0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA); vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD6 + SHIFT_TO_CHB_ADDR, 0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA); } else - { //DDR800_OPEN_LOOP + { vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA)); } } else { - //MIDPI_EN + vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0) | P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)); vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1) @@ -1189,14 +1148,13 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) } mcDELAY_US(1); - //RESETB + vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); mcDELAY_US(1); - ///TODO: MIDPI Init 1 - //MCK8X_EN + vIO32WriteFldMulti_All(DDRPHY_PLL4, P_Fld(0x1, PLL4_RG_RPHYPLL_ADA_MCK8X_EN) | P_Fld(0x1, PLL4_RG_RPHYPLL_RESETB)); mcDELAY_US(1); @@ -1207,7 +1165,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CLK_EN) | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CMD_EN)); - vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI3 + SHIFT_TO_CHB_ADDR, P_Fld(u1BRPI_MCTL_EN_CA, CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA) //CH_B CA slave + vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI3 + SHIFT_TO_CHB_ADDR, P_Fld(u1BRPI_MCTL_EN_CA, CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA) | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CLK_EN) @@ -1223,7 +1181,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1)); - //CG + vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA) | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA) | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA) @@ -1259,22 +1217,22 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_CLK_MEM_SEL); mcDELAY_US(1); -#if ENABLE_APHY_DLL_IDLE_MODE_OPTION //Should before the PHDET_EN = 1 +#if ENABLE_APHY_DLL_IDLE_MODE_OPTION vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI5, 0x0, CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA); vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI5 + SHIFT_TO_CHB_ADDR, 0x1, CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x1, B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x1, B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1); - vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x3, B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0);//Zone1: 48ps Zone2: 96ps if(8ps/delay cell) - vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x3, B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1);//Intrinsic 2 delay cell, setting: x - vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0x3, CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA);//Zone1 = 2 + 2x; Zone2 = 2 * Zone1 + vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x3, B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0); + vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x3, B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1); + vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0x3, CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0xC, B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0xC, B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1); vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0xC, CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA); #endif - //DLL + vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA); mcDELAY_US(1); vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA); @@ -1293,8 +1251,7 @@ static void DDRPhyPLLSetting(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xffffffff, MISC_SPM_CTRL0_PHY_SPM_CTL0); vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL2, 0xffffffff, MISC_SPM_CTRL2_PHY_SPM_CTL2); #else - // DMSUS replaced by CA_CMD2_RG_TX_ARCMD_OE_DIS, CMD_OE_DIS(1) will prevent illegal command ouput - // And DRAM 1st reset_n pulse will disappear if use CA_CMD2_RG_TX_ARCMD_OE_DIS + vIO32WriteFldAlign_All(DDRPHY_CA_CMD2, 0, CA_CMD2_RG_TX_ARCMD_OE_DIS); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); #endif @@ -1323,12 +1280,11 @@ void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value) P_Fld(value, SHU_SELPH_CA7_DLY_RA5) | P_Fld(value, SHU_SELPH_CA7_DLY_RA6)); - // Note: CKE UI must sync CA UI (CA and CKE delay circuit are same) @Lin-Yi - // To avoid tXP timing margin issue + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), value, SHU_SELPH_CA5_DLY_CKE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), value, SHU_SELPH_CA6_DLY_CKE1); - ///TODO: Yirong : new calibration flow : change CS UI to 0 + // vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); } #endif @@ -1349,7 +1305,7 @@ void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq) DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE); } - else // CBT_HIGH_FREQ + else { DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE); @@ -1361,7 +1317,7 @@ void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq) void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq) { -#if (FOR_DV_SIMULATION_USED == TRUE) // @Darren+ for DV sim +#if (FOR_DV_SIMULATION_USED == TRUE) return; #endif @@ -1372,11 +1328,11 @@ void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq) static U8 _CurFreq = CBT_UNKNOWN_FREQ; if (_CurFreq == freq) { - return; // Do nothing no meter the frequency is. + return; } _CurFreq = freq; - /* @chengchun + Dynamic MIOCK to avoid CK stop state violation during DFS */ + ch_bak = p->channel; for (ch = CHANNEL_A; ch < p->support_channel_num; ch++) { vSetPHY2ChannelMapping(p, ch); @@ -1391,11 +1347,11 @@ void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq) if (freq == CBT_LOW_FREQ) { #if REPLACE_DFS_RG_MODE - DramcDFSDirectJump_SPMMode_forK(p, DRAM_DFS_REG_SHU1); //only use in Calibration (SCSM mode) - //DramcDFSDirectJump_SPMMode(p, SRAM_SHU3);// Darren NOTE: Dramc shu1 for MRW (DramcModeRegInit_LP4 and CBT) - //We use SRAM3(DDR1866-DIFF) instead of SRAM4(DDR1600-SE) because MRW is blocked and will cause SOC(SE) and DRAM(DIFF) mismatch. + DramcDFSDirectJump_SPMMode_forK(p, DRAM_DFS_REG_SHU1); + //DramcDFSDirectJump_SPMMode(p, SRAM_SHU3); + #else - DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU1); // Darren NOTE: Dramc shu1 for MRW (DramcModeRegInit_LP4 and CBT) + DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU1); #endif } else @@ -1433,7 +1389,7 @@ void DramcPowerOnSequence(DRAMC_CTX_T *p) #endif #ifdef DUMP_INIT_RG_LOG_TO_DE - //CKE high + CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); return; #endif @@ -1442,34 +1398,34 @@ void DramcPowerOnSequence(DRAMC_CTX_T *p) //static U8 u1PowerOn=0; //if(u1PowerOn ==0) { - //reset dram = low + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x0, MISC_CTRL1_R_DMDA_RRESETB_I); //vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_CKE2RANK_OPT2); - //CKE low + CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL); - // delay tINIT1=200us(min) & tINIT2=10ns(min) + mcDELAY_US(200); - //reset dram = low + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMDA_RRESETB_I); - // Disable HW MIOCK control to make CLK always on + DramCLKAlwaysOnOff(p, ON, TO_ALL_CHANNEL); - //tINIT3=2ms(min) + mcDELAY_MS(2); - //CKE high + CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); - // tINIT5=2us(min) + mcDELAY_US(2); //u1PowerOn=1; - //// Enable HW MIOCK control to make CLK dynamic + DramCLKAlwaysOnOff(p, OFF, TO_ALL_CHANNEL); mcSHOW_DBG_MSG5(("APPLY_LP4_POWER_INIT_SEQUENCE\n")); } @@ -1503,39 +1459,39 @@ DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround) vSetRank(p, u1RankIdx); mcSHOW_DBG_MSG2(("[DramcModeRegInit_CATerm] CH%u RK%u bWorkAround=%d\n", u1ChannelIdx, u1RankIdx, bWorkAround)); - /* FSP_1: 1. For term freqs 2. Assumes "data rate >= DDR2667" are terminated */ + #if MRW_CHECK_ONLY mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); #endif - DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR); //@Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal) + DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR); DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR); - //MR12 use previous value + if (p->dram_type == TYPE_LPDDR4P) { - u1MR11_Value = 0x0; //ODT disable + u1MR11_Value = 0x0; } else { #if ENABLE_SAMSUNG_NT_ODT - if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) // 1ynm process for NT-ODT + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) { - u1MR11_Value = 0x2; //@Darren, DQ ODT:120ohm -> parallel to 60ohm - u1MR11_Value |= (0x1 << 3); //@Darren, MR11[3]=1 to enable NT-ODT for B707 + u1MR11_Value = 0x2; + u1MR11_Value |= (0x1 << 3); } else #endif - u1MR11_Value = 0x3; //DQ ODT:80ohm + u1MR11_Value = 0x3; #if FSP1_CLKCA_TERM if (p->dram_cbt_mode[u1RankIdx] == CBT_NORMAL_MODE) { - u1MR11_Value |= 0x40; //CA ODT:60ohm for byte mode + u1MR11_Value |= 0x40; } else { - u1MR11_Value |= 0x20; //CA ODT:120ohm for byte mode + u1MR11_Value |= 0x20; } #endif } @@ -1544,15 +1500,15 @@ DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround) u1MR11_Value = gDramcDqOdtRZQAdjust; #endif u1MR11Value[p->dram_fsp] = u1MR11_Value; - DramcModeRegWriteByRank(p, u1RankIdx, 11, u1MR11Value[p->dram_fsp]); //ODT + DramcModeRegWriteByRank(p, u1RankIdx, 11, u1MR11Value[p->dram_fsp]); if (p->dram_type == TYPE_LPDDR4) { - u1MR22_Value = 0x24; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + u1MR22_Value = 0x24; } - else //TYPE_LPDDR4x, LP4P + else { - u1MR22_Value = 0x3c; //Disable CA-CS-CLK ODT, SOC ODT=RZQ/4 + u1MR22_Value = 0x3c; #if FSP1_CLKCA_TERM if (bWorkAround) { @@ -1562,11 +1518,11 @@ DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround) { if (u1RankIdx == RANK_0) { - u1MR22_Value = 0x4; //Enable CA-CS-CLK ODT, SOC ODT=RZQ/4 + u1MR22_Value = 0x4; } else { - u1MR22_Value = 0x2c; //Enable CS ODT, SOC ODT=RZQ/4 + u1MR22_Value = 0x2c; } } #endif @@ -1620,31 +1576,28 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) vPrintCalibrationBasicInfo_ForJV(p); #endif - /* Fix nWR value to 30 (MR01[6:4] = 101B) for DDR3200 - * Fix nWR value to 34 (MR01[6:4] = 110B) for DDR3733 - * Other vendors: Use default MR01 for each FSP (Set in vInitGlobalVariablesByCondition() ) - */ + { - /* Clear MR01 OP[6:4] */ + u1MR01Value[FSP_0] &= 0x8F; u1MR01Value[FSP_1] &= 0x8F; if (u2FreqMax == 2133) { - /* Set MR01 OP[6:4] to 111B = 7 */ + u1MR01Value[FSP_0] |= (0x7 << 4); u1MR01Value[FSP_1] |= (0x7 << 4); u1nWR = 40; } else if (u2FreqMax == 1866) { - /* Set MR01 OP[6:4] to 110B = 6 */ + u1MR01Value[FSP_0] |= (0x6 << 4); u1MR01Value[FSP_1] |= (0x6 << 4); u1nWR = 34; } - else // Freq <= 1600 + else { - /* Set MR01 OP[6:4] to 101B = 5 */ + u1MR01Value[FSP_0] |= (0x5 << 4); u1MR01Value[FSP_1] |= (0x5 << 4); u1nWR = 30; @@ -1657,8 +1610,7 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) #ifndef DUMP_INIT_RG_LOG_TO_DE if(p->dram_fsp == FSP_1) { - // @Darren, VDDQ = 600mv + CaVref default is 301mV (no impact) - // Fix high freq keep FSP0 for CA term workaround (PPR abnormal) + CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL); cbt_switch_freq(p, CBT_LOW_FREQ); CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ALL_CHANNEL); @@ -1684,11 +1636,10 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u4RankIdx, MRS_MRSRK); - // Note : MR37 for LP4P should be set before any Mode register. - // MR37 is not shadow register, just need to set by channel and rank. No need to set by FSP + if(p->dram_type == TYPE_LPDDR4P) { - //temp solution, need remove later + #ifndef MT6779_FPGA #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) #if __Petrus_TO_BE_PORTING__ @@ -1699,7 +1650,7 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) DramcModeRegWriteByRank(p, u4RankIdx, 37, 0x1); - //temp solution, need remove later + #ifndef MT6779_FPGA #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) #if __Petrus_TO_BE_PORTING__ @@ -1712,7 +1663,7 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) // if(p->frequency<=1200) { - /* FSP_0: 1. For un-term freqs 2. Assumes "data rate < DDR2667" are un-term */ + u1MRFsp = FSP_0; mcSHOW_DBG_MSG2(("\tFsp%d\n", u1MRFsp)); #if VENDER_JV_LOG @@ -1724,44 +1675,44 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) P_Fld(1, MR13_VRCG), TO_MR); - //MR12 use previous value + DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]); - //MR2 set Read/Write Latency + u1MR2_RLWL = LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency << 1); - u1MR02Value[p->dram_fsp] = u1MR2_RLWL | (u1MR2_RLWL << 3); //@tg update 1:4 mode DDR400/800 WL/RL according to spec. + u1MR02Value[p->dram_fsp] = u1MR2_RLWL | (u1MR2_RLWL << 3); #if 0 - if (p->freqGroup <= 400) // DDR800, DDR400 + if (p->freqGroup <= 400) { - u1MR02Value[u1MRFsp] = 0x12; // the minimum of WL is 8, and the minimum of RL is 14 (Jouling and HJ) + u1MR02Value[u1MRFsp] = 0x12; } - else if ((p->freqGroup == 800) || (p->freqGroup == 600)) // DDR1600, DDR1200 + else if ((p->freqGroup == 800) || (p->freqGroup == 600)) { u1MR02Value[u1MRFsp] = 0x12; } - else if (p->freqGroup == 933) // DDR1866 + else if (p->freqGroup == 933) { - u1MR02Value[u1MRFsp] = 0x1b; //RL=20, WL=10 + u1MR02Value[u1MRFsp] = 0x1b; } - else if (p->freqGroup == 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1) + else if (p->freqGroup == 1200) { u1MR02Value[u1MRFsp] = 0x24; } #endif DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]); - //if(p->odt_onoff) + u1MR11Value[u1MRFsp] = 0x0; - DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); //ODT disable + DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); #if ENABLE_LP4Y_DFS - // For LPDDR4Y <= DDR1600 un-term + if (p->freqGroup <= 800) { - u1MR21Value[u1MRFsp] |= (0x1 << 5); // Low Speed CA buffer for LP4Y + u1MR21Value[u1MRFsp] |= (0x1 << 5); #if LP4Y_BACKUP_SOLUTION - u1MR51Value[u1MRFsp] |= (0x3 << 1); // CLK[3]=0, WDQS[2]=1 and RDQS[1]=1 Single-End mode for LP4Y + u1MR51Value[u1MRFsp] |= (0x3 << 1); #endif } else if ((p->freqGroup == 1200) || (p->freqGroup == 933)) @@ -1775,11 +1726,11 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) if(p->dram_type == TYPE_LPDDR4) { - u1MR22_Value = 0x20; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + u1MR22_Value = 0x20; } - else //TYPE_LPDDR4x, LP4P + else { - u1MR22_Value = 0x38; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + u1MR22_Value = 0x38; } #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0) @@ -1790,15 +1741,15 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) u1MR22Value[u1MRFsp] = u1MR22_Value; DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]); - //MR14 use previous value - DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ + + DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); #if CALIBRATION_SPEED_UP_DEBUG mcSHOW_DBG_MSG2(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); mcSHOW_DBG_MSG2(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp,u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); #endif - //MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K) + u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F); if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P) @@ -1811,14 +1762,14 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3); } #endif - // @Darren, Follow samsung PPR recommend flow + DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]); DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); } //else { - /* FSP_1: 1. For term freqs 2. Assumes "data rate >= DDR2667" are terminated */ + u1MRFsp = FSP_1; mcSHOW_DBG_MSG2(("\tFsp%d\n", u1MRFsp)); #if VENDER_JV_LOG @@ -1827,16 +1778,16 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR); - //MR12 use previous value + #if CBT_FSP1_MATCH_FSP0_UNTERM_WA if (p->dram_fsp == FSP_0) - DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][FSP_0]); //MR12 VREF-CA + DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][FSP_0]); else #endif - DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR12 VREF-CA + DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]); #if 0 - //MR2 set Read/Write Latency + if (p->freqGroup == 2133) { u1MR02Value[u1MRFsp] = 0x3f; @@ -1857,18 +1808,18 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]); if(p->dram_type == TYPE_LPDDR4P) - u1MR11_Value = 0x0; //ODT disable + u1MR11_Value = 0x0; else { #if ENABLE_SAMSUNG_NT_ODT - if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) // 1ynm process for NT-ODT + if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7)) { - u1MR11_Value = 0x2; //@Darren, DQ ODT:120ohm -> parallel to 60ohm - u1MR11_Value |= (0x1 << 3); //@Darren, MR11[3]=1 to enable NT-ODT for B707 + u1MR11_Value = 0x2; + u1MR11_Value |= (0x1 << 3); } else #endif - u1MR11_Value = 0x3; //DQ ODT:80ohm + u1MR11_Value = 0x3; #if FSP1_CLKCA_TERM #if CBT_FSP1_MATCH_FSP0_UNTERM_WA @@ -1877,11 +1828,11 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) { if(p->dram_cbt_mode[u4RankIdx]==CBT_NORMAL_MODE) { - u1MR11_Value |= 0x40; //CA ODT:60ohm for normal mode die + u1MR11_Value |= 0x40; } else { - u1MR11_Value |= 0x20; //CA ODT:120ohm for byte mode die + u1MR11_Value |= 0x20; } } #endif @@ -1894,7 +1845,7 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) } #endif u1MR11Value[u1MRFsp] = u1MR11_Value; - DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); //ODT + DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]); u1MR21Value[u1MRFsp] = 0; u1MR51Value[u1MRFsp] = 0; @@ -1903,11 +1854,11 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) if(p->dram_type == TYPE_LPDDR4) { - u1MR22_Value = 0x24; //SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA + u1MR22_Value = 0x24; } - else //TYPE_LPDDR4x, LP4P + else { - u1MR22_Value = 0x3c; //Disable CA-CS-CLK ODT, SOC ODT=RZQ/4 + u1MR22_Value = 0x3c; #if FSP1_CLKCA_TERM #if CBT_FSP1_MATCH_FSP0_UNTERM_WA if (p->dram_fsp == FSP_1) @@ -1915,11 +1866,11 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) { if(u4RankIdx==RANK_0) { - u1MR22_Value = 0x4; //Enable CA-CS-CLK ODT, SOC ODT=RZQ/4 + u1MR22_Value = 0x4; } else { - u1MR22_Value = 0x2c; //Enable CS ODT, SOC ODT=RZQ/4 + u1MR22_Value = 0x2c; } } #endif @@ -1933,15 +1884,15 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) u1MR22Value[u1MRFsp] = u1MR22_Value; DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]); - //MR14 use previous value - DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ + + DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); #if CALIBRATION_SPEED_UP_DEBUG mcSHOW_DBG_MSG2(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); mcSHOW_DBG_MSG2(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f))); #endif - //MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K) + u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F); if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P) @@ -1954,17 +1905,17 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3); } #endif - // @Darren, Follow samsung PPR recommend flow + DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]); DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]); } #if ENABLE_LP4_ZQ_CAL - DramcZQCalibration(p, u4RankIdx); //ZQ calobration should be done before CBT calibration by switching to low frequency + DramcZQCalibration(p, u4RankIdx); #endif - /* freq < 1333 is assumed to be odt_off -> uses FSP_0 */ + //if (p->frequency < MRFSP_TERM_FREQ) if(operating_fsp == FSP_0) { @@ -1986,7 +1937,7 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) } #else - /* MRS two ranks simutaniously */ + if (p->support_rank_num == RANK_DUAL) u1set_mrsrk = 0x3; else @@ -1994,26 +1945,22 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p) DramcModeRegWriteByRank(p, u1set_mrsrk, 13, u1MR13Value[RANK_0]); #endif - /* Auto-MRW related register write (Used during HW DVFS frequency switch flow) - * VRCG seems to be enabled/disabled even when switching to same FSP(but different freq) to simplify HW DVFS flow - */ - // 1. MR13 OP[3] = 1 : Enable "high current mode" to reduce the settling time when changing FSP(freq) during operation + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_MR13_HWSET_MR13_OP) | P_Fld(13, SHU_HWSET_MR13_HWSET_MR13_MRSMA)); - // 2. MR13 OP[3] = 1 : Enable "high current mode" after FSP(freq) switch operation for calibration + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(13, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA)); - // 3. MR2 : Set RL/WL after FSP(freq) switch + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2), P_Fld(u1MR02Value[operating_fsp], SHU_HWSET_MR2_HWSET_MR2_OP) | P_Fld(2, SHU_HWSET_MR2_HWSET_MR2_MRSMA)); } #ifndef DUMP_INIT_RG_LOG_TO_DE - //switch to high freq + if(p->dram_fsp == FSP_1) { - // @Darren, no effect via DDR1600 (purpose to keep @FSP0) - // Fix high freq keep FSP0 for CA term workaround (PPR abnormal) + CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL); cbt_switch_freq(p, CBT_HIGH_FREQ); CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ALL_CHANNEL); @@ -2045,40 +1992,40 @@ void MPLLInit(void) #if (FOR_DV_SIMULATION_USED == 0) unsigned int tmp; - DRV_WriteReg32(AP_PLL_CON0, 0x11); // CLKSQ Enable + DRV_WriteReg32(AP_PLL_CON0, 0x11); mcDELAY_US(100); - DRV_WriteReg32(AP_PLL_CON0, 0x13); // CLKSQ LPF Enable + DRV_WriteReg32(AP_PLL_CON0, 0x13); mcDELAY_MS(1); - DRV_WriteReg32(MPLL_PWR_CON0, 0x3); // power on MPLL + DRV_WriteReg32(MPLL_PWR_CON0, 0x3); mcDELAY_US(30); - DRV_WriteReg32(MPLL_PWR_CON0, 0x1); // turn off ISO of MPLL + DRV_WriteReg32(MPLL_PWR_CON0, 0x1); mcDELAY_US(1); tmp = DRV_Reg32(MPLL_CON1); - DRV_WriteReg32(MPLL_CON1, tmp | 0x80000000); // Config MPLL freq - DRV_WriteReg32(MPLL_CON0, 0x181); // enable MPLL + DRV_WriteReg32(MPLL_CON1, tmp | 0x80000000); + DRV_WriteReg32(MPLL_CON0, 0x181); mcDELAY_US(20); #endif #else unsigned int tmp; tmp = DRV_Reg32(MPLL_CON4); - DRV_WriteReg32(MPLL_CON4, tmp | 0x1); // turn off ISO of MPLL + DRV_WriteReg32(MPLL_CON4, tmp | 0x1); tmp = DRV_Reg32(MPLL_CON4); - DRV_WriteReg32(MPLL_CON4, tmp & 0xfffffffd); // turn off ISO of MPLL + DRV_WriteReg32(MPLL_CON4, tmp & 0xfffffffd); tmp = DRV_Reg32(MPLL_CON0); - DRV_WriteReg32(MPLL_CON0, tmp & 0xffffefff); // turn off ISO of MPLL + DRV_WriteReg32(MPLL_CON0, tmp & 0xffffefff); tmp = DRV_Reg32(MPLL_CON2); - DRV_WriteReg32(MPLL_CON2, 0x84200000); // turn off ISO of MPLL + DRV_WriteReg32(MPLL_CON2, 0x84200000); tmp = DRV_Reg32(MPLL_CON0); - DRV_WriteReg32(MPLL_CON0, tmp | 0x200); // turn off ISO of MPLL + DRV_WriteReg32(MPLL_CON0, tmp | 0x200); #endif #endif @@ -2100,16 +2047,16 @@ void XRTRTR_SHU_Setting(DRAMC_CTX_T * p) //U8 u1RankIdx = 0; //U8 u1Rank_backup = u1GetRank(p); - if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) // DDR800semi + if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) u1RkSelMCKMinus = 1; - else if (p->frequency >= 1600) //DDR3200 up + else if (p->frequency >= 1600) u1RkSelUIMinus = 2; - // DV codes is included + /*vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ6, u1ShuRkMode, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ6, u1ShuRkMode, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);*/ - //DRAMC setting - @Darren, DV no set (double confirm) + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(u1RkSelMCKMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS) | P_Fld(u1RkSelUIMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) @@ -2117,10 +2064,10 @@ void XRTRTR_SHU_Setting(DRAMC_CTX_T * p) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) - | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) // @HJ, no use + | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN)); - //Darren-vIO32WriteFldAlign_All(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSIEN_RX_SELPH_OPT); //@HJ, internal wire assign to 1'b1 + //Darren-vIO32WriteFldAlign_All(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSIEN_RX_SELPH_OPT); /*for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { @@ -2136,15 +2083,15 @@ void XRTRTR_SHU_Setting(DRAMC_CTX_T * p) #if 0 static void ENABLE_XRTRTR_Setting(DRAMC_CTX_T * p) { -#if 0 // @Darren, DV codes is included +#if 0 U8 u1ByteIdx = 0; U32 u4ByteOffset = 0; - // DV codes is included + for(u1ByteIdx=0; u1ByteIdx<DQS_NUMBER_LP4; u1ByteIdx++) { u4ByteOffset = u1ByteIdx*DDRPHY_AO_B0_B1_OFFSET; - // PHY setting for B0/B1 + vIO32WriteFldAlign_All(DDRPHY_REG_B0_DLL_ARPI1 + u4ByteOffset, 0x1, B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL_ARPI3 + u4ByteOffset, 0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0); @@ -2158,22 +2105,21 @@ static void ENABLE_XRTRTR_Setting(DRAMC_CTX_T * p) vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13 + u4ByteOffset, 0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0); } - // DV codes is included + vIO32WriteFldMulti_All(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0)); vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1)); - //Darren-vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD9, P_Fld(0, CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT)); + //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD9, P_Fld(0, CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT)); + - // DV codes is included vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ10, 0x1, B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0); vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ10, 0x1, B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1); - // DV codes is included + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2, P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN) | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST)); - //Extend 1T timing of FIFO mode rank switch - // DV codes is included + vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 0x2, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0); vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 0x2, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1); vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 0x1, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0); @@ -2194,8 +2140,8 @@ void XRTWTW_SHU_Setting(DRAMC_CTX_T * p) { vSetRank(p, u1RankIdx); - u2TxDly_OEN_RK[u1RankIdx][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); //Byte0 - u2TxDly_OEN_RK[u1RankIdx][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); //Byte1 + u2TxDly_OEN_RK[u1RankIdx][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + u2TxDly_OEN_RK[u1RankIdx][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); } vSetRank(p, u1Rank_bak); @@ -2203,9 +2149,9 @@ void XRTWTW_SHU_Setting(DRAMC_CTX_T * p) { u2TxDly_OEN_RK_max = (u2TxDly_OEN_RK[0][u1ByteIdx] > u2TxDly_OEN_RK[1][u1ByteIdx])? u2TxDly_OEN_RK[0][u1ByteIdx]: u2TxDly_OEN_RK[1][u1ByteIdx]; if (p->frequency >= 1200) - u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 2)? (u2TxDly_OEN_RK_max - 2): 0; //Byte0 + u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 2)? (u2TxDly_OEN_RK_max - 2): 0; else - u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 1)? (u2TxDly_OEN_RK_max - 1): 0; //Byte0 + u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 1)? (u2TxDly_OEN_RK_max - 1): 0; } u2TxPI_UPD_max = (u2TxPI_UPD[0] > u2TxPI_UPD[1])? u2TxPI_UPD[0]: u2TxPI_UPD[1]; @@ -2222,18 +2168,18 @@ void XRTWTW_SHU_Setting(DRAMC_CTX_T * p) #if 0 static void ENABLE_XRTWTW_Setting(DRAMC_CTX_T * p) { -#if 0 // @Darren, DV codes is included - // DV codes is included +#if 0 + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2, P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0)); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13, 0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0); - // DV codes is included + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2, P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1)); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13, 0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1); - // @Darren, CA don't care for xrank w2w + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2, P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA)); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 0x1, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA); @@ -2273,21 +2219,7 @@ static void UpdateTxOEN(DRAMC_CTX_T *p) U8 u1ByteIdx, backup_rank, ii; U8 u1DQ_OE_CNT; - // For LP4 - // 1. R_DMDQOE_OPT (dramc_conf 0x8C0[11]) - // set 1'b1: adjust DQSOE/DQOE length with R_DMDQOE_CNT - // 2. R_DMDQOE_CNT (dramc_conf 0x8C0[10:8]) - // set 3'h3 - // 3. Initial TX setting OE/DATA - // OE = DATA - 4 UI - - // For LP3 - // 1. R_DMDQOE_OPT (dramc_conf 0x8C0[11]) - // set 1'b1: adjust DQSOE/DQOE length with R_DMDQOE_CNT - // 2. R_DMDQOE_CNT (dramc_conf 0x8C0[10:8]) - // set 3'h2 - // 3. Initial TX setting OE/DATA - // OE = DATA - 2 UI + u1DQ_OE_CNT = 3; @@ -2318,19 +2250,19 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 1, SHU_ODTCTRL_ROEN); vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1); - vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN) // OE Suspend EN - | P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN)); //ODT Suspend EN + vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN) + | P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN)); } else { vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 0, SHU_ODTCTRL_ROEN); vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_R_DMRODTEN_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_R_DMRODTEN_B1); - vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN) // OE Suspend EN - | P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN)); //ODT Suspend EN + vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN) + | P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN)); } - //close RX DQ/DQS tracking to save power + vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS2, P_Fld(0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0) | P_Fld(0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0) | P_Fld(0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0)); @@ -2343,11 +2275,11 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS2, P_Fld(0x0, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1) | P_Fld(0x0, R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1) | P_Fld(0x0, R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1)); - //wei-jen: RX rank_sel for CA is not used(), set it's dly to 0 to save power - vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD7, 0, SHU_CA_CMD7_R_DMRANKRXDVS_CA); //Move to DCM off setting + + vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD7, 0, SHU_CA_CMD7_R_DMRANKRXDVS_CA); + - //DDRPhyTxRxInitialSettings_LP4 vIO32WriteFldAlign(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN); vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x1, CA_CMD10_RG_RX_ARCLK_DQSIENMODE); @@ -2370,7 +2302,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vIO32WriteFldAlign(DDRPHY_B1_DQ5, 0x1, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1); vIO32WriteFldAlign(DDRPHY_CA_CMD5, 0x1, CA_CMD5_RG_RX_ARCLK_DVS_EN); - //LP4 no need, follow LP3 first. + //vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, P_Fld(0x1, MISC_VREF_CTRL_RG_RVREF_DDR3_SEL) // | P_Fld(0x0, MISC_VREF_CTRL_RG_RVREF_DDR4_SEL)); @@ -2408,7 +2340,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) { if (p->odt_onoff == ODT_ON) { - u2RXVrefDefault = 0x17; // 0.6*VDDQ, 0x12=0.5*VDDQ + u2RXVrefDefault = 0x17; } else { @@ -2419,7 +2351,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) { if (p->odt_onoff == ODT_ON) { - u2RXVrefDefault = 0x17; // 0.6*VDDQ, 0x12=0.5*VDDQ + u2RXVrefDefault = 0x17; } else { @@ -2453,35 +2385,34 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) if ((p->dram_type == TYPE_LPDDR4X) || (p->dram_type == TYPE_LPDDR4P)) { - // LP4x eye fine-tune - // APHY Review by YY Hsu + vIO32WriteFldAlign(DDRPHY_B0_DQ8, 0x1, B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ8, 0x1, B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1); vIO32WriteFldAlign(DDRPHY_CA_CMD9, 0x1, CA_CMD9_RG_TX_ARCMD_EN_LP4P); } - /* Set initial default mode to "new burst mode (7UI or new 8UI)" */ + DramcGatingMode(p, 1); vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x1, CA_CMD8_RG_TX_RRESETB_DDR3_SEL); - vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL); //TODO: Remove if register default value is 0 - //End of DDRPhyTxRxInitialSettings_LP4 + vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL); + + - //DFS workaround vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT); - //should set 0x2a, otherwise AC-timing violation from Berson + vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG, P_Fld(0x2a, SHU_DQSG_SCINTV) | P_Fld(0x1, SHU_DQSG_DQSINCTL_PRE_SEL)); - //Update setting for + vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x0, SHU_B0_DQ5_RG_ARPI_FB_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x0, SHU_B1_DQ5_RG_ARPI_FB_B1); vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x0, SHU_CA_CMD5_RG_ARPI_FB_CA); - //Reserved bits usage, check with PHY owners + DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0); vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1); @@ -2489,20 +2420,18 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA)); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - //IMP Tracking Init Settings - //Write (DRAMC _BASE+ 0x219) [31:0] = 32'h80080020//DDR3200 default - //SHU_IMPCAL1_IMPCAL_CHKCYCLE should > 12.5/MCK, 1:4 mode will disable imp tracking -> don't care + vIO32WriteFldMulti(DRAMC_REG_SHU_IMPCAL1, P_Fld(8, SHU_IMPCAL1_IMPCAL_CALICNT) | P_Fld(0x10, SHU_IMPCAL1_IMPCALCNT) | P_Fld(4, SHU_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(1, SHU_IMPCAL1_IMPCALCNT_OPT) | P_Fld((p->frequency * 25 / 8000) + 1, SHU_IMPCAL1_IMPCAL_CHKCYCLE)); - //for _K_ + vIO32WriteFldMulti(DRAMC_REG_SREFCTRL, P_Fld(0x1, SREFCTRL_SCSM_CGAR) | P_Fld(0x1, SREFCTRL_SCARB_SM_CGAR) | P_Fld(0x1, SREFCTRL_RDDQSOSC_CGAR) | P_Fld(0x1, SREFCTRL_HMRRSEL_CGAR)); vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TXUIPI_CAL_CGAR); - /* DVFS related, PREA interval counter (After DVFS DVT, set to 0xf (originally was 0x1f)) */ + vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0xf, SHU_MISC_PREA_INTV); vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ8, P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) @@ -2541,7 +2470,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) | P_Fld(0x0, SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA) | P_Fld(0x7fff, SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA)); vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG); - /* HW design issue: run-time PBYTE (B0, B1) flags will lose it's function and become per-bit -> set to 0 */ + vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0)); @@ -2551,7 +2480,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_CLKAR, P_Fld(0x1, CLKAR_SELPH_CMD_CG_DIS) | P_Fld(0x7FFF, CLKAR_REQQUE_PACG_DIS)); - vIO32WriteFldAlign(DRAMC_REG_SHU_DQSG_RETRY, 0x0, SHU_DQSG_RETRY_R_RETRY_PA_DSIABLE); //SH: Set to 0 -> save power + vIO32WriteFldAlign(DRAMC_REG_SHU_DQSG_RETRY, 0x0, SHU_DQSG_RETRY_R_RETRY_PA_DSIABLE); vIO32WriteFldAlign(DRAMC_REG_WRITE_LEV, 0x0, WRITE_LEV_DDRPHY_COMB_CG_SEL); vIO32WriteFldAlign(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT); vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x0, STBCAL2_STB_UIDLYCG_IG) @@ -2562,20 +2491,20 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) //vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) // | P_Fld(0x1, SHU_ODTCTRL_RODTEN_SELPH_CG_IG)); - vIO32WriteFldAlign(DDRPHY_SHU_B0_DLL0, 0x1, SHU_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU);//Move to DCM off setting - vIO32WriteFldAlign(DDRPHY_SHU_B1_DLL0, 0x1, SHU_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU);//Move to DCM off setting - //vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU); move to DramcSetting_Olympus_LP4_ByteMode() + vIO32WriteFldAlign(DDRPHY_SHU_B0_DLL0, 0x1, SHU_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU); + vIO32WriteFldAlign(DDRPHY_SHU_B1_DLL0, 0x1, SHU_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU); + //vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU); vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA); - //end _K_ - //DE_UPDATE + + #if (fcFOR_CHIP_ID == fcLafite) - // Must check with EMI owners -> Asynchronous EMI: Can't turn on RWSPLIT, Synchronous EMI: Can enable RWSPLIT (DE: JL Wu) + vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_WRFIFO_OPT) - | P_Fld(0x0, PERFCTL0_REORDEREN) // from Unique review (it will remove) - | P_Fld(0x1, PERFCTL0_RWSPLIT)); //synchronous EMI -> can turn on RWSPLIT + | P_Fld(0x0, PERFCTL0_REORDEREN) + | P_Fld(0x1, PERFCTL0_RWSPLIT)); #endif vIO32WriteFldAlign(DRAMC_REG_SREFCTRL, 0x1, SREFCTRL_SREF2_OPTION); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x1a, SHUCTRL1_FC_PRDCNT); @@ -2605,12 +2534,10 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_BIAS_EN)); #endif - //end DE UPDATE - //Disable RODT tracking //vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0, SHU_RODTENSTB_RODTENSTB_TRACK_EN); - //Rx Gating tracking settings + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSG), \ P_Fld(9, SHU_DQSG_STB_UPDMASKCYC) | \ P_Fld(1, SHU_DQSG_STB_UPDMASK_EN)); @@ -2623,7 +2550,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x4, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x4, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1); #else - //Modify for corner IC failed at HQA test XTLV + vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x7, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x7, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1); #endif @@ -2642,7 +2569,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) #if ENABLE_TX_WDQS mcSHOW_DBG_MSG2(("Enable WDQS\n")); - //Check reserved bits with PHY integrator + vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(1, SHU_B0_DLL1_RG_READ_BASE_DQS_EN_B0) | P_Fld(1, SHU_B0_DLL1_RG_READ_BASE_DQSB_EN_B0) | P_Fld(!p->odt_onoff, SHU_B0_DLL1_RG_ODT_DISABLE_B0)); vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(1, SHU_B1_DLL1_RG_READ_BASE_DQS_EN_B1) | P_Fld(1, SHU_B1_DLL1_RG_READ_BASE_DQSB_EN_B1) @@ -2657,8 +2584,8 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) SetTxWDQSStatusOnOff(1); #endif - #else //WDQS and reak pull are disable - //Check reserved bits with PHY integrator + #else + vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(0, SHU_B0_DLL1_RG_READ_BASE_DQS_EN_B0) | P_Fld(0, SHU_B0_DLL1_RG_READ_BASE_DQSB_EN_B0) | P_Fld(0, SHU_B0_DLL1_RG_ODT_DISABLE_B0)); vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(0, SHU_B1_DLL1_RG_READ_BASE_DQS_EN_B1) | P_Fld(0, SHU_B1_DLL1_RG_READ_BASE_DQSB_EN_B1) @@ -2666,31 +2593,26 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) #endif - //DE review WhitneyE2 + vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS); vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFNA_OPT); - vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x1, ZQCS_ZQCS_MASK_SEL_CGAR);//Move to DCM off setting - vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x0, DUMMY_RD_DMYRD_HPRI_DIS)); //La_fite MP setting = 0 + vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x1, ZQCS_ZQCS_MASK_SEL_CGAR); + vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x0, DUMMY_RD_DMYRD_HPRI_DIS)); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2, 0x1, SHUCTRL2_R_DVFS_SREF_OPT); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL3, 0xb, SHUCTRL3_VRCGDIS_PRDCNT); vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG); - //End - //DE review - /* ARPISM_MCK_SEL_B0, B1 set to 1 (Joe): "Due to TX_PICG modify register is set to 1, - * ARPISM_MCK_SEL_Bx should be 1 to fulfill APHY TX OE spec for low freq (Ex: DDR1600)" - */ vIO32WriteFldMulti(DDRPHY_B0_DLL_ARPI1, P_Fld(0x1, B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT) | P_Fld(0x1, B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0)); vIO32WriteFldMulti(DDRPHY_B1_DLL_ARPI1, P_Fld(0x1, B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT) | P_Fld(0x1, B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1)); - vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);//Move to DCM off setting - vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF);//Move to DCM off setting + vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT); + vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF); vIO32WriteFldAlign(DDRPHY_MISC_RXDVS2, 1, MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG); vIO32WriteFldAlign(DRAMC_REG_CLKCTRL, 0x1, CLKCTRL_SEQCLKRUN3); vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 1, REFCTRL1_SREF_CG_OPT); - vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x0, SHUCTRL_DVFS_CG_OPT) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3));//Move to DCM off setting(SHUCTRL_DVFS_CG_OPT) + vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x0, SHUCTRL_DVFS_CG_OPT) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3)); //vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3)); vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x1, SHUCTRL2_SHORTQ_OPT) | P_Fld(0x3, SHUCTRL2_R_DVFS_PICG_MARGIN)); vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x0, STBCAL2_STB_DBG_EN); @@ -2700,7 +2622,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) if (u2DFSGetHighestFreq(p) >= 1866) #endif { - //if product supports 3733, CLKAR_SELPH_4LCG_DIS always 1 else o, but if 1, comsume more power + vIO32WriteFldAlign(DRAMC_REG_CLKAR, 1, CLKAR_SELPH_4LCG_DIS); } @@ -2712,35 +2634,34 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_CA_TX_MCK, P_Fld(0x1, CA_TX_MCK_R_DMRESET_FRPHY_OPT) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY)); - //Syl_via MP setting should set CKECTRL_CKELCKFIX as 0 to rollback to M17 - //Ei_ger review by CF Chang + vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x0, CKECTRL_CKELCKFIX); - //Gating error problem happened in M17 has been solved by setting this RG as 0 (when RODT tracking on (), TX DLY of byte2,3 must not be zero) + vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x0, SHU_RODTENSTB_RODTENSTB_4BYTE_EN); - #if (fcFOR_CHIP_ID == fcLafite) //RODT old mode - // RODT old mode (it must set SHU_RODTENSTB_RODTENSTB_TRACK_EN=1) from HJ review + #if (fcFOR_CHIP_ID == fcLafite) + vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 0x1, SHU_ODTCTRL_RODTEN_OPT); vIO32WriteFldMulti(DRAMC_REG_SHU_RODTENSTB, P_Fld(0, SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(1, SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(1, SHU_RODTENSTB_RODTENSTB_SELPH_MODE)); vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x0, SHU_STBCAL_DQSIEN_PICG_MODE); - #if ENABLE_RODT_TRACKING // The SHU_RODTENSTB_RODTENSTB_TRACK_EN will depend on SHU_ODTCTRL_ROEN setting + #if ENABLE_RODT_TRACKING if (vGet_Div_Mode(p) == DIV4_MODE) vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x21, SHU_RODTENSTB_RODTENSTB_OFFSET); else vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x11, SHU_RODTENSTB_RODTENSTB_OFFSET); #endif - //Enable RODT tracking at Init, because RODT position should be changed with Gating position simultaneously + U8 u1ReadROEN; u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \ P_Fld(u1ReadROEN, SHU_RODTENSTB_RODTENSTB_TRACK_EN)); #endif - #if (fcFOR_CHIP_ID == fcLafite) //DDRPHY settings review from YH Cho + #if (fcFOR_CHIP_ID == fcLafite) vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ3, 0x0, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ3, 0x0, SHU_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1); #endif @@ -2750,7 +2671,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) #endif #if ENABLE_TMRRI_NEW_MODE - //[DVT](1)dram auto refersh rate by hardware mr4 for rank0 and rank1; (2)After suspend resume, HW MR4 will be fire autoly (Berson) + vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, (p->support_rank_num == RANK_DUAL)? (1): (0), SPCMDCTRL_HMR4_TOG_OPT); #else vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_HMR4_TOG_OPT); @@ -2760,65 +2681,63 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) RXPICGSetting(p); #endif - //[DVT]RX FIFO debug feature, MP setting should enable debug function + vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1); - // E2 - new -start ========================================================================= - //Design Review Meeting dramc_stbcal_cross rank read to read for new APHY spec - HJ Huang + vIO32WriteFldMulti(DDRPHY_B0_DQ9, P_Fld(4, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0)); vIO32WriteFldMulti(DDRPHY_B1_DQ9, P_Fld(4, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1)); vIO32WriteFldMulti(DDRPHY_CA_CMD10, P_Fld(0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD10_R_DMRXDVS_R_F_DLY_RK_OPT)); vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x0, MISC_CTRL3_ARPI_CG_RK1_SRC_SEL); vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x1, SHU_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK); - vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x0, SHU_RANK_SEL_STB_RANK_SEL_STB_SERMODE); // for old rank mode settings - HJ Huang + vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x0, SHU_RANK_SEL_STB_RANK_SEL_STB_SERMODE); + - // Update VREF1/VREF2 per bit select - Ying-Yu Hsu - // Note: The RG (SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1) need update when using VREF2 per bit select vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ3, P_Fld(0, SHU_B0_DQ3_RG_TX_ARDQS0_PDB_B0) | P_Fld(0, SHU_B0_DQ3_RG_TX_ARDQ_PDB_B0)); vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ3, P_Fld(0, SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1) | P_Fld(0, SHU_B1_DQ3_RG_TX_ARDQ_PDB_B1)); - // DQSI DLY 3B in FIFO for adjustmen by YingMin + vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x4, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x4, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1); #if ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION - vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_8X_MUX); // @Mazar: MCK8X uncertainty remove - vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_DDR400_MUX); // @Mazar: open loop mode setting(found connection problem in CHB in DSIM) + vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_8X_MUX); + vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_DDR400_MUX); #endif #if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION - vIO32WriteFldAlign(DDRPHY_DVFS_EMI_CLK, 1, DVFS_EMI_CLK_R_DDRPHY_SHUFFLE_MUX_ENABLE); // @Lynx - vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 1, DVFSDLL2_R_SHUFFLE_PI_RESET_ENABLE); // @Lynx - vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_MCK8X_MARGIN); // @Lynx + vIO32WriteFldAlign(DDRPHY_DVFS_EMI_CLK, 1, DVFS_EMI_CLK_R_DDRPHY_SHUFFLE_MUX_ENABLE); + vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 1, DVFSDLL2_R_SHUFFLE_PI_RESET_ENABLE); + vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_MCK8X_MARGIN); - vIO32WriteFldAlign(DDRPHY_B0_DLL_ARPI0, 1, B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0); // @YY - vIO32WriteFldAlign(DDRPHY_B1_DLL_ARPI0, 1, B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1); // @YY - vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI0, 1, CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA); // @YY + vIO32WriteFldAlign(DDRPHY_B0_DLL_ARPI0, 1, B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0); + vIO32WriteFldAlign(DDRPHY_B1_DLL_ARPI0, 1, B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1); + vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI0, 1, CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA); - vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_PICG_MARGIN4_NEW); // @Lynx + vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_PICG_MARGIN4_NEW); #endif - vIO32WriteFldAlign(DDRPHY_SHU_MISC1, 0x00000020, SHU_MISC1_DR_EMI_RESERVE); // @TK, For EMI slice timing + vIO32WriteFldAlign(DDRPHY_SHU_MISC1, 0x00000020, SHU_MISC1_DR_EMI_RESERVE); + - //@Ton, DQS retry off vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE) | P_Fld(0x0, SHU_DQSG_RETRY_R_RDY_SEL_DLE) | P_Fld(0x0, SHU_DQSG_RETRY_R_DQSIENLAT) | P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_ROUND_NUM) | P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_ONCE)); - vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TX_TRACKING_OPT); //@Jouling + vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TX_TRACKING_OPT); + + + vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SPDR_MR4_OPT); - //@Berson, NOTE: Please set to 1 when DVT is verified. SPMFW must updated by DVT owner. - vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SPDR_MR4_OPT); //S0 from suspend to resume trigger HW MR4 - //@YY, APHY init settings review vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1); vIO32WriteFldAlign(DDRPHY_CA_CMD5, 0x29, CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL); vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x4, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY); - // E2 - new -end ========================================================================= + #if CMD_CKE_WORKAROUND_FIX CMD_CKE_Modified_txp_Setting(p); @@ -2839,10 +2758,10 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) u1CaUI = 0; u1CaPI = 24; } - // CA delay shift u1CaUI*UI + DramcCmdUIDelaySetting(p, u1CaUI); - // Rank0/1 u1CaPI*PI CA delay + u1RankIdxBak = u1GetRank(p); @@ -2856,7 +2775,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) vSetRank(p, u1RankIdxBak); #endif - //Reset XRTRTR related setting + #if XRTRTR_NEW_CROSS_RK_MODE vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1); @@ -2864,14 +2783,14 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) #endif - //Update MP setting - vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRSCLR_RK0_EN); //Jouling + + vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRSCLR_RK0_EN); vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x7, STBCAL2_STBCAL_UI_UPD_MASK_OPT) - |P_Fld(0x1, STBCAL2_STBCAL_UI_UPD_MASK_EN)); //HJ, Gating tracking + |P_Fld(0x1, STBCAL2_STBCAL_UI_UPD_MASK_EN)); #if XRTRTR_NEW_CROSS_RK_MODE vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |P_Fld(0x2, SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) - |P_Fld(0x1, SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN)); //HJ, R2R + |P_Fld(0x1, SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN)); #endif #endif// #if __A60868_TO_BE_PORTING__ @@ -2880,9 +2799,7 @@ static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p) #endif #if __A60868_TO_BE_PORTING__ #if LEGACY_DELAY_CELL -/* Legacy CA, TX DQ, TX DQM delay cell initial settings - * RK#_TX_ARCA#_DLY (RK0~2, CA0~5), RK#_TX_ARDQ#_DLY_B# (RK0~2, DQ0~8, B0~1), RK#_TX_ARDQM0_DLY_B# (RK0~2, B0~1) - */ + static void LegacyDlyCellInitLP4_DDR2667(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0) @@ -2951,11 +2868,7 @@ static void LegacyDlyCellInitLP4_DDR3200(DRAMC_CTX_T *p) #endif #if LEGACY_TX_TRACK -/* Legacy tx tracking related initial settings (actual correct values are set during calibration steps) - * BOOT_ORIG_UI_RK#_DQ#, BOOT_TARG_UI_RK#_DQ#, BOOT_TARG_UI_RK#_DQM#, BOOT_TARG_UI_RK#_OEN_DQ#, BOOT_TARG_UI_RK#_OEN_DQM# - * DQSOSCTHRD_DEC, DQSOSCTHRD_INC, DQSOSC_PRDCNT - * DQSOSC_BASE_RK#, DQSOSCR_RK#_BYTE_MODE, DQSOSCR_DQSOSCRCNT - */ + static void LegacyTxTrackLP4_DDR2667(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0) @@ -3162,9 +3075,7 @@ static void LegacyTxTrackLP4_DDR3200(DRAMC_CTX_T *p) #endif #if LEGACY_TDQSCK_PRECAL -/* Legacy tDQSCK precal related initial settings (actual correct values are set during calibration) - * Ex: TDQSCK_JUMP_RATIO, TDQSCK_UIFREQ#, TDQSCK_PIFREQ# - */ + static void LegacyPreCalLP4_DDR2667(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x1a, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0) @@ -3329,10 +3240,7 @@ static void LegacyPreCalLP4_DDR3200(DRAMC_CTX_T *p) #endif #if LEGACY_GATING_DLY -/* Legacy initial settings (actual correct values are set during gating calibration) - * Ex: TX_DLY_DQS#_GATED, TX_DLY_DQS#_GATED_P1, REG_DLY_DQS#_GATED, REG_DLY_DQS#_GATED_P1 - * TXDLY_B#_RODTEN, TXDLY_B#_RODTEN_P1, DLY_B#_RODTEN, DLY_B#_RODTEN_P1 - */ + static void LegacyGatingDlyLP3(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1) @@ -3447,15 +3355,14 @@ static void LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T *p) if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { - // Byte mode don't use. need fine-tune for DV sim for DDR800 - //RK0 + ucR0GatingMCK = 0x2; ucR0GatingP1MCK = 0x2; ucR0GatingB0UI = 0x2; ucR0GatingB1UI = 0x2; ucR0GatingB0P1UI = 0x6; ucR0GatingB1P1UI = 0x6; - //RK1 + ucR1GatingMCK = 0x2; ucR1GatingP1MCK = 0x3; ucR1GatingB0UI = 0x5; @@ -3465,14 +3372,14 @@ static void LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T *p) } else { - //RK0 + ucR0GatingMCK = 0x1; ucR0GatingP1MCK = 0x1; ucR0GatingB0UI = 0x4; ucR0GatingB1UI = 0x4; ucR0GatingB0P1UI = 0x6; ucR0GatingB1P1UI = 0x6; - //RK1 + ucR1GatingMCK = 0x1; ucR1GatingP1MCK = 0x1; ucR1GatingB0UI = 0x5; @@ -3481,7 +3388,7 @@ static void LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T *p) ucR1GatingB1P1UI = 0x7; } - //Gating PI + if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP) { ucR0GatingB0PI = 0xc; @@ -3491,39 +3398,39 @@ static void LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T *p) } else { - // DDR800_SEMI_LOOP and DDR800_OPEN_LOOP + ucR0GatingB0PI = 0x0; ucR0GatingB1PI = 0x0; ucR1GatingB0PI = 0x0; ucR1GatingB1PI = 0x0; } - //Gating RK0 MCK + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1) | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED) | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1) | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED)); - //Gating RK0 UI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1) | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED) | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1) | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED)); - //Gating RK1 MCK + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1) | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED) | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1) | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED)); - //Gating RK1 UI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1) | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED) | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1) | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED)); - //Gating RK0 PI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN) | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN)); - //Gating RK1 PI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN) | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN)); } @@ -3542,17 +3449,17 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { - // DV sim mix mode = RK0_BYTE and RK1_NORMAL - if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) // DV sim mixed mode + + if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) { - //RK0 + ucR0GatingMCK = 0x2; ucR0GatingP1MCK = 0x2; ucR0GatingB0UI = 0x0; ucR0GatingB1UI = 0x0; ucR0GatingB0P1UI = 0x4; ucR0GatingB1P1UI = 0x4; - //RK1 + ucR1GatingMCK = 0x2; ucR1GatingP1MCK = 0x2; ucR1GatingB0UI = 0x3; @@ -3562,14 +3469,14 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) } else { - //RK0 + ucR0GatingMCK = 0x2; ucR0GatingP1MCK = 0x2; ucR0GatingB0UI = 0x0; ucR0GatingB1UI = 0x1; ucR0GatingB0P1UI = 0x4; ucR0GatingB1P1UI = 0x5; - //RK1 + ucR1GatingMCK = 0x1; ucR1GatingP1MCK = 0x2; ucR1GatingB0UI = 0x7; @@ -3580,20 +3487,17 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) } else { - // Normal mode DRAM - //Normal mode dram, B0/1 tDQSCK = 1.5ns - //Byte/Mix mode dram, B0 tDQSCK = 1.5ns, B1 tDQSCK = 1.95ns - //RK1, tDQSCK=3.5ns + if (vGet_Div_Mode(p) == DIV4_MODE) { - //RK0 + ucR0GatingMCK = 0x1; ucR0GatingP1MCK = 0x1; ucR0GatingB0UI = 0x4; ucR0GatingB1UI = 0x4; ucR0GatingB0P1UI = 0x6; ucR0GatingB1P1UI = 0x6; - //RK1 + ucR1GatingMCK = 0x1; ucR1GatingP1MCK = 0x2; ucR1GatingB0UI = 0x7; @@ -3603,14 +3507,14 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) } else { - //RK0 + ucR0GatingMCK = 0x2; ucR0GatingP1MCK = 0x3; ucR0GatingB0UI = 0x4; ucR0GatingB1UI = 0x4; ucR0GatingB0P1UI = 0x0; ucR0GatingB1P1UI = 0x0; - //RK1 + ucR1GatingMCK = 0x2; ucR1GatingP1MCK = 0x3; ucR1GatingB0UI = 0x7; @@ -3620,7 +3524,7 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) } } - //Gating PI + if (vGet_Div_Mode(p) == DIV4_MODE) { ucR0GatingB0PI = 0xb; @@ -3630,24 +3534,24 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) } else { - // for DDR1600 1:8 mode + if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { - if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1)) // RK1 gating for byte mode + if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1)) { ucR0GatingB0PI = 0xa; ucR0GatingB1PI = 0x0; ucR1GatingB0PI = 0xc; ucR1GatingB1PI = 0x16; } - else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) // DV sim mixed mode + else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) { ucR0GatingB0PI = 0xa; ucR0GatingB1PI = 0x1e; ucR1GatingB0PI = 0xc; ucR1GatingB1PI = 0xc; } - else //RK0: normal and RK1: byte + else { ucR0GatingB0PI = 0xa; ucR0GatingB1PI = 0x0; @@ -3665,32 +3569,32 @@ static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p) } } - //Gating RK0 MCK + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1) | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED) | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1) | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED)); - //Gating RK0 UI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1) | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED) | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1) | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED)); - //Gating RK1 MCK + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1) | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED) | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1) | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED)); - //Gating RK1 UI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1) | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED) | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1) | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED)); - //Gating RK0 PI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN) | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN)); - //Gating RK1 PI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN) | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN)); } @@ -3972,8 +3876,7 @@ static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p) if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { - // Byte mode don't use. need fine-tune for DV sim - //RK0 + ucR0GatingMCK = 0x3; ucR0GatingP1MCK = 0x3; ucR0GatingB0UI = 0x3; @@ -3982,7 +3885,7 @@ static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p) ucR0GatingB1P1UI = 0x7; ucR0GatingB0PI = 0x14; ucR0GatingB1PI = 0x14; - //RK1 + ucR1GatingMCK = 0x4; ucR1GatingP1MCK = 0x4; ucR1GatingB0UI = 0x4; @@ -3994,9 +3897,7 @@ static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p) } else { - //RK0 - //Normal mode dram, B0/1 tDQSCK = 1.5ns - //Byte/Mix mode dram, B0 tDQSCK = 1.5ns, B1 tDQSCK = 1.95ns + ucR0GatingMCK = 0x2; ucR0GatingP1MCK = 0x2; ucR0GatingB0UI = 0x3; @@ -4005,7 +3906,7 @@ static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p) ucR0GatingB1P1UI = 0x7; ucR0GatingB0PI = 0x11; ucR0GatingB1PI = 0x11; - //RK1, tDQSCK=3.5ns + ucR1GatingMCK = 0x3; ucR1GatingP1MCK = 0x3; ucR1GatingB0UI = 0x2; @@ -4023,50 +3924,45 @@ static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p) ucR1GatingP1MCK++; #endif - //Gating RK0 MCK + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1) | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED) | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1) | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED)); - //Gating RK0 UI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1) | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED) | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1) | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED)); - //Gating RK1 MCK + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1) | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED) | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1) | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED)); - //Gating RK1 UI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1) | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED) | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1) | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED)); - //Gating RK0 PI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x0, SHURK0_DQSIEN_R0DQS3IEN) | P_Fld(0x0, SHURK0_DQSIEN_R0DQS2IEN) | P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN) | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN)); - //Gating RK1 PI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN) | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN) | P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN) | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN)); } -#endif //LEGACY_GATING_DLY +#endif #if LEGACY_RX_DLY -/* Legacy RX related delay initial settings: - * RK#_RX_ARDQ#_F_DLY_B#, RK#_RX_ARDQ#_R_DLY_B# (DQ Rx per bit falling/rising edge delay line control) - * RK#_RX_ARDQS#_F_DLY_B#, RK#_RX_ARDQS#_R_DLY_B# (DQS RX per bit falling/rising edge delay line control) - * RK#_RX_ARDQM#_F_DLY_B#, RK#_RX_ARDQM#_R_DLY_B# (DQM RX per bit falling/rising edge delay line control) - * TODO: Channel B's PHY, seems to be all used for LP3's DQ, DQS, DQM -> LP3's Channel B RX CA, CKE etc.. delay should be regarded as RX_DLY? - */ + static void LegacyRxDly_LP4_DDR2667(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0) @@ -4117,7 +4013,7 @@ static void LegacyRxDly_LP4_DDR800(DRAMC_CTX_T *p) U8 u1Dqm = 0x0; U8 u1Dqs = 0x26; - //RK0_B0 + vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0) | P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0) @@ -4128,7 +4024,7 @@ static void LegacyRxDly_LP4_DDR800(DRAMC_CTX_T *p) | P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) | P_Fld(u1Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0)); - //RK0_B1 + vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1) | P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1) @@ -4139,7 +4035,7 @@ static void LegacyRxDly_LP4_DDR800(DRAMC_CTX_T *p) | P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1) | P_Fld(u1Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1)); - //RK1_B0 + vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0) | P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0) @@ -4150,7 +4046,7 @@ static void LegacyRxDly_LP4_DDR800(DRAMC_CTX_T *p) | P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0) | P_Fld(u1Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0)); - //RK1_B1 + vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1) | P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1) @@ -4193,7 +4089,7 @@ static void LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T *p) u1Rk1_Dqs = 0x16; } - //RK0_B0 + vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0) | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0) @@ -4204,7 +4100,7 @@ static void LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T *p) | P_Fld(u1Rk0_Dq5_6, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Rk0_Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) | P_Fld(u1Rk0_Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0)); - //RK0_B1 + vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1) | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1) @@ -4215,7 +4111,7 @@ static void LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T *p) | P_Fld(u1Rk0_Dq5_6, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Rk0_Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1) | P_Fld(u1Rk0_Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1)); - //RK1_B0 + vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0) | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0) @@ -4226,7 +4122,7 @@ static void LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T *p) | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Rk1_Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0) | P_Fld(u1Rk1_Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0)); - //RK1_B1 + vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1) | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1) @@ -4289,7 +4185,7 @@ static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p) U8 u1Dqm = 0xf; U8 u1Dqs = 0x0; - //RK0_B0 + vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0) | P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0) @@ -4300,7 +4196,7 @@ static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p) | P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) | P_Fld(u1Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0)); - //RK1_B0 + vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0) | P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0) @@ -4311,7 +4207,7 @@ static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p) | P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0) | P_Fld(u1Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0)); - //RK0_B1 + vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1) | P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1) @@ -4322,7 +4218,7 @@ static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p) | P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1) | P_Fld(u1Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1)); - //RK1_B1 + vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1) | P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1)); vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1) @@ -4335,29 +4231,29 @@ static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p) | P_Fld(u1Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1)); } -#endif //LEGACY_RX_DLY +#endif #if LEGACY_DAT_LAT static void LegacyDatlatLP4_DDR3733(DRAMC_CTX_T *p) { - // set by DramcRxdqsGatingPostProcess + #if 0 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x7, SHU_RANKCTL_RANKINCTL_PHY) | P_Fld(0x5, SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x5, SHU_RANKCTL_RANKINCTL)); #endif - // DATLAT init by AcTiming Table + /*vIO32WriteFldMulti(DRAMC_REG_SHU_CONF1, P_Fld(0x11, SHU_CONF1_DATLAT) | P_Fld(0xf, SHU_CONF1_DATLAT_DSEL) | P_Fld(0xf, SHU_CONF1_DATLAT_DSEL_PHY));*/ - //DATLAT 1:8 mode DDR3733 + vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT) | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT)); - //RDATA PIPE from Ton + vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1) | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_PIPE_READ_START_EXTEND2) @@ -4378,8 +4274,8 @@ static void DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T *p, DRAM_RANK_T eRank) { if (vGet_Div_Mode(p) == DIV4_MODE) { - ucR0TxdlyOendq = 0x3; // don't use - ucR0Txdlydq = 0x4; // don't use + ucR0TxdlyOendq = 0x3; + ucR0Txdlydq = 0x4; } else { @@ -4427,12 +4323,12 @@ static void DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T *p, DRAM_RANK_T eRank) } if (vGet_Div_Mode(p) == DIV4_MODE) { - ucR0TxdlyOendq = 0x2; //don't use - ucR0Txdlydq = 0x1; //don't use + ucR0TxdlyOendq = 0x2; + ucR0Txdlydq = 0x1; } else { - ucR0TxdlyOendq = 0x7; // TX OE -3UI + ucR0TxdlyOendq = 0x7; ucR0Txdlydq = 0x2; } vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ3) @@ -4452,12 +4348,12 @@ static void DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T *p, DRAM_RANK_T eRank) | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM1) | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM0)); } - else //RANK_1 + else { if (vGet_Div_Mode(p) == DIV4_MODE) { - ucR1TxdlyOendq = 0x3; //don't use - ucR1Txdlydq = 0x4; //don't use + ucR1TxdlyOendq = 0x3; + ucR1Txdlydq = 0x4; } else { @@ -4504,8 +4400,8 @@ static void DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T *p, DRAM_RANK_T eRank) } if (vGet_Div_Mode(p) == DIV4_MODE) { - ucR1TxdlyOendq = 0x3; //don't use - ucR1Txdlydq = 0x2; //don't use + ucR1TxdlyOendq = 0x3; + ucR1Txdlydq = 0x2; } else { @@ -4553,9 +4449,9 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR4266(DRAMC_CTX_T *p) static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p) { - DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_0); // TX DQ/DQM MCK/UI - DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_1); // TX DQ/DQM MCK/UI - // TX DQ/DQM PI + DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_0); + DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_1); + vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0xe, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0) | P_Fld(0x13, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0xe, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1) @@ -4565,7 +4461,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x19, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1) | P_Fld(0x22, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1)); - //TX DQS MCK by WriteLeveling + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) @@ -4574,7 +4470,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0)); - //TX DQS UI by WriteLeveling + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS3) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1) @@ -4601,7 +4497,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p) #endif -#if LEGACY_DAT_LAT // TODO: Darren +#if LEGACY_DAT_LAT LegacyDatlatLP4_DDR3733(p); #endif } @@ -4609,7 +4505,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p) static void DramcSetting_Olympus_LP4_ByteMode_DDR2667(DRAMC_CTX_T *p) { - ////DRAMC0-SHU2 + #if LEGACY_TDQSCK_PRECAL LegacyPreCalLP4_DDR2667(p); #endif @@ -4780,7 +4676,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR2667(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x4, SHU_DQSG_RETRY_R_DQSIENLAT) | P_Fld(0x1, SHU_DQSG_RETRY_R_DDR1866_PLUS)); - ////DDRPHY0-SHU2 + vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0); //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0) // | P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)); @@ -4933,7 +4829,7 @@ static void DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T *p, DRAM_RANK_T eRank) | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM1) | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM0)); } - else //RANK_1 + else { if (vGet_Div_Mode(p) == DIV4_MODE) { @@ -5031,13 +4927,13 @@ static void DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T *p, DRAM_RANK_T eRank) { if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { - // Byte mode For RK0 Tx PI + u1R0B0Pi = 0x1e; u1R0B1Pi = 0x1e; } else { - // For RK0 Tx PI + u1R0B0Pi = 0x1a; u1R0B1Pi = 0x1a; } @@ -5048,10 +4944,10 @@ static void DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T *p, DRAM_RANK_T eRank) } else { - // For RK1 Tx PI + if (vGet_Div_Mode(p) == DIV4_MODE) { - // for DDR1600 1:4 mode + u1R1B0Pi = 0x1b; u1R1B1Pi = 0x1b; } @@ -5059,13 +4955,13 @@ static void DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T *p, DRAM_RANK_T eRank) { if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { - // Byte mode for DDR1600 1:8 mode + u1R1B0Pi = 0x13; u1R1B1Pi = 0x12; } else { - // for DDR1600 1:8 mode + u1R1B0Pi = 0x26; u1R1B1Pi = 0x26; } @@ -5123,7 +5019,7 @@ static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank) if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP) { - // TX OE -3*UI + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ3) | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ1) @@ -5141,9 +5037,9 @@ static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank) | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM0)); } - else //if (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP) + else { - // DDR800_OPEN_LOOP and DDR800_SEMI_LOOP + vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ3) | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ2) | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ1) @@ -5205,7 +5101,7 @@ static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank) if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP) { - // TX OE -3*UI + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3) | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2) | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1) @@ -5223,9 +5119,9 @@ static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank) | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM1) | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM0)); } - else //if (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP) + else { - // DDR800_OPEN_LOOP and DDR800_SEMI_LOOP + vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3) | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2) | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1) @@ -5247,7 +5143,7 @@ static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank) if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP) { - // DDR800 1:4 mode TX PI + vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0) | P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1) @@ -5259,8 +5155,7 @@ static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank) } else { - // DDR800_SEMI_LOOP and DDR800_OPEN_LOOP - // DDR800 1:4 mode TX PI + vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x0, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0) | P_Fld(0x0, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0)); vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x0, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1) @@ -5277,7 +5172,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) U8 ucMCKTxdlyOendqs = 0, ucMCKTxdlydqs = 0; U8 ucUITxdlyOendqs = 0, ucUITxdlydqs = 0; - ////DRAMC0-SHU3 + #if LEGACY_TDQSCK_PRECAL LegacyPreCalLP4_DDR1600(p); #endif @@ -5314,7 +5209,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) ucUITxdlydqs = 0x1; } - //MCK by Wleveling + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS3) | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) @@ -5323,7 +5218,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS2) | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS0)); - //UI by Wleveling + vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS3) | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS2) | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS1) @@ -5339,18 +5234,18 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B0) | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B1) | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B0)); - //Rank0/1 TX Delay + if (p->freqGroup == 400) { DramcSetting_LP4_TX_Delay_DDR800(p, RANK_0); DramcSetting_LP4_TX_Delay_DDR800(p, RANK_1); } - else // for DDR1200 and DDR1600 + else { DramcSetting_LP4_TX_Delay_DDR1600(p, RANK_0); DramcSetting_LP4_TX_Delay_DDR1600(p, RANK_1); } - // Tx tracking + vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQM_B1) | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQM_B0) | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQ_B1) @@ -5358,16 +5253,16 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) #if LEGACY_GATING_DLY if (p->freqGroup == 400) - LegacyGatingDlyLP4_DDR800(p); // for 1:4 mode settings + LegacyGatingDlyLP4_DDR800(p); else - LegacyGatingDlyLP4_DDR1600(p); // for 1:8 and 1:4 mode settings for DDR1200 and DDR1600 + LegacyGatingDlyLP4_DDR1600(p); #endif vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x3, SHU_DQSG_RETRY_R_DQSIENLAT) | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS)); - ////DDRPHY0-SHU3 - vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0); // for Rx guard + + vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0); //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ6, P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0) // | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)); if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) @@ -5382,7 +5277,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) | P_Fld(0x1, SHU_B0_DQ7_MIDPI_DIV4_ENABLE) | P_Fld(0x0, SHU_B0_DQ7_MIDPI_ENABLE)); } - vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1); // for Rx guard + vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1); //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ6, P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1) // | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)); if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) @@ -5394,7 +5289,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) } #if LEGACY_RX_DLY - if (p->freqGroup == 400) // for DDR800 1:4 mode + if (p->freqGroup == 400) LegacyRxDly_LP4_DDR800(p); else LegacyRxDly_LP4_DDR1600(p); @@ -5406,26 +5301,26 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) if (vGet_Div_Mode(p) == DIV4_MODE) { #if 0 - if (p->freqGroup == 400) // for DDR800 1:4 mode + if (p->freqGroup == 400) { vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY) | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x4, SHU_RANKCTL_RANKINCTL)); } - else // for DDR1600 1:4 mode + else { vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY) | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x4, SHU_RANKCTL_RANKINCTL)); } #endif - // 1:4 mode + vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x0, SHU_CONF0_DM64BITEN) | P_Fld(0x1, SHU_CONF0_FDIV2) | P_Fld(0x0, SHU_CONF0_FREQDIV4) | P_Fld(0x0, SHU_CONF0_DUALSCHEN) | P_Fld(0x1, SHU_CONF0_WDATRGO)); -#if 0 // 1:8 mode +#if 0 vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x1, SHU_CONF0_DM64BITEN) | P_Fld(0x0, SHU_CONF0_FDIV2) | P_Fld(0x1, SHU_CONF0_FREQDIV4) @@ -5438,11 +5333,11 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA1, 0x1, SHU_SELPH_CA1_TXDLY_CKE); vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA2, 0x1, SHU_SELPH_CA2_TXDLY_CKE1); #endif - //DATLAT 1:4 mode from Ton + vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT) | P_Fld(0x1, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT)); - //RDATA PIPE from Ton + vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1) | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1) | P_Fld(0x1, SHU_PIPE_READ_START_EXTEND2) @@ -5453,7 +5348,7 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) #if 0 else { - // for DDR1600 1:8 mode + vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x2, SHU_RANKCTL_RANKINCTL_PHY) | P_Fld(0x0, SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x0, SHU_RANKCTL_RANKINCTL)); @@ -5461,53 +5356,46 @@ static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p) #endif } -/* -CANNOT use DRAMC_WBR : -DDRPHY_CA_DLL_ARPI0 -> DDRPHY_SHU_CA_DLL1 -DDRPHY_CA_DLL_ARPI3 -DDRPHY_CA_DLL_ARPI5 -> DDRPHY_SHU_CA_DLL0 -DDRPHY_SHU_CA_CMD6 -*/ + void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) { U8 u1CAP_SEL; U8 u1MIDPICAP_SEL; - //U16 u2SDM_PCW = 0; // SDM_PCW are set in DDRPhyPLLSetting() + //U16 u2SDM_PCW = 0; U8 u1TXDLY_CMD; U8 u1TAIL_LAT; AutoRefreshCKEOff(p); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); - //before switch clock from 26M to PHY, need to init PHY clock first - vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX) //move CKMUX_SEL_R_PHYCTRLMUX to here (it was originally between MISC_CG_CTRL0_CLK_MEM_SEL and MISC_CTRL0_R_DMRDSEL_DIV2_OPT) - | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); // PHYCTRLDCM 1: follow DDRPHY_conf DCM settings, 0: follow infra DCM settings + + vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX) + | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - //chg_mem_en = 1 + vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_W_CHG_MEM); - //26M + vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_CLK_MEM_SEL); vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT) | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT)); - // 0 ===LP4_3200_intial_setting_shu1 begin=== + #if APOLLO_SPECIFIC vIO32WriteFldAlign(DRAMC_REG_RKCFG, 1, RKCFG_CS1FORCE0); #endif - //Francis : pin mux issue, need to set CHD - // TODO: ARDMSUS_10 already set to 0 in SwimpedanceCal(), may be removed here? + vIO32WriteFldMulti(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA)); vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0x0, MISC_SPM_CTRL2_PHY_SPM_CTL2); vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL0, 0x0, MISC_SPM_CTRL0_PHY_SPM_CTL0); - vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL2, 0x6003bf, MISC_CG_CTRL2_RG_MEM_DCM_CTL);//Move to DCM off setting - vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL4, 0x333f3f00, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL);//Move to DCM off setting + vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL2, 0x6003bf, MISC_CG_CTRL2_RG_MEM_DCM_CTL); + vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL4, 0x333f3f00, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL); vIO32WriteFldMulti(DDRPHY_SHU_PLL1, P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) | P_Fld(0x7, SHU_PLL1_SHU1_PLL1_RFU)); vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE) @@ -5532,7 +5420,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x0, B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1) | P_Fld(0x0, B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1) | P_Fld(0x0, B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1)); - #if 0 //Correct settings are set in UpdateInitialSettings_LP4() + #if 0 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x0, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x7, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1); vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA); @@ -5631,7 +5519,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR4_SEL) | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL) | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN)); - /* ARCMD_DRVP, DRVN , ARCLK_DRVP, DRVN not used anymore + /* vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD1, P_Fld(0x1, SHU_CA_CMD1_RG_TX_ARCMD_DRVN) | P_Fld(0x1, SHU_CA_CMD1_RG_TX_ARCMD_DRVP)); vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD2, P_Fld(0x1, SHU_CA_CMD2_RG_TX_ARCLK_DRVN) @@ -5642,14 +5530,14 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD2, P_Fld(0x1, SHU2_CA_CMD2_RG_TX_ARCLK_DRVN) // | P_Fld(0x1, SHU2_CA_CMD2_RG_TX_ARCLK_DRVP)); vIO32WriteFldMulti(DDRPHY_PLL3, P_Fld(0x0, PLL3_RG_RPHYPLL_TSTOP_EN) | P_Fld(0x0, PLL3_RG_RPHYPLL_TST_EN)); - vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x0, MISC_VREF_CTRL_RG_RVREF_VREF_EN); //LP3 VREF + vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x0, MISC_VREF_CTRL_RG_RVREF_VREF_EN); vIO32WriteFldAlign(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1); mcDELAY_US(1); - //Ref clock should be 20M~30M, if MPLL=52M, Pre-divider should be set to 1 + vIO32WriteFldMulti(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x1, SHU_PLL8_RG_RPHYPLL_PREDIV)); //vIO32WriteFldAlign(DDRPHY_SHU2_PLL8, 0x0, SHU2_PLL8_RG_RPHYPLL_POSDIV); //vIO32WriteFldAlign(DDRPHY_SHU3_PLL8, 0x0, SHU3_PLL8_RG_RPHYPLL_POSDIV); @@ -5668,7 +5556,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) mcDELAY_US(1); - //Ref clock should be 20M~30M, if MPLL=52M, Pre-divider should be set to 1 + vIO32WriteFldMulti(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x1, SHU_PLL10_RG_RCLRPLL_PREDIV)); //vIO32WriteFldAlign(DDRPHY_SHU2_PLL10, 0x0, SHU2_PLL10_RG_RCLRPLL_POSDIV); //vIO32WriteFldAlign(DDRPHY_SHU3_PLL10, 0x0, SHU3_PLL10_RG_RCLRPLL_POSDIV); @@ -5677,7 +5565,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) mcDELAY_US(1); - ///TODO: MIDPI Init 1 + vIO32WriteFldMulti(DDRPHY_PLL4, P_Fld(0x0, PLL4_RG_RPHYPLL_AD_MCK8X_EN) | P_Fld(0x1, PLL4_PLL4_RFU) | P_Fld(0x1, PLL4_RG_RPHYPLL_MCK8X_SEL)); @@ -5685,7 +5573,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) mcDELAY_US(1); - //@Darren-vIO32WriteFldAlign(DDRPHY_SHU_PLL0, 0x3, SHU_PLL0_RG_RPHYPLL_TOP_REV); // debug1111, org:3 -> mdf:0 + vIO32WriteFldMulti(DDRPHY_SHU_PLL0, P_Fld(0x1, SHU_PLL0_ADA_MCK8X_CHB_EN) | P_Fld(0x1, SHU_PLL0_ADA_MCK8X_CHA_EN)); //@Darren+ //vIO32WriteFldAlign(DDRPHY_SHU2_PLL0, 0x3, SHU2_PLL0_RG_RPHYPLL_TOP_REV); @@ -5707,8 +5595,8 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) #if (fcFOR_CHIP_ID == fcLafite) DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); - vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);//Move to DCM off setting - vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);//Move to DCM off setting + vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU); + vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); #endif @@ -5763,7 +5651,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x00, SHU_B1_DQ7_RG_ARDQ_REV_B1) // | P_Fld(0x0, SHU_B1_DQ7_DQ_REV_B1_BIT_05)); - //lynx added + //vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_RG_ARDQ_REV_B0); //vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_RG_ARDQ_REV_B1); // @@ -5799,7 +5687,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1, P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA)); vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) - | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));//CH_B CA slave mode + | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA)); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); #endif vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0)); @@ -5818,29 +5706,29 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) DDRPhyPLLSetting(p); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - //rollback tMRRI design change + #if ENABLE_TMRRI_NEW_MODE - //fix rank at 0 to trigger new TMRRI setting + vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANK); vIO32WriteFldAlign(DRAMC_REG_RKCFG, 1, RKCFG_TXRANKFIX); - vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x0, DRSCTRL_RK_SCINPUT_OPT);// new mode, HW_MRR: R_DMMRRRK, SW_MRR: R_DMMRSRK + vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x0, DRSCTRL_RK_SCINPUT_OPT); vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_MRRIOPT) | P_Fld(0x0, DRAMCTRL_TMRRIBYRK_DIS) | P_Fld(0x1, DRAMCTRL_TMRRICHKDIS)); vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SC_PG_UPD_OPT); vIO32WriteFldMulti(DRAMC_REG_SPCMDCTRL, P_Fld(0x0, SPCMDCTRL_SC_PG_MPRW_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_STCMD_AREF_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_OPT2_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_MAN_DIS)); vIO32WriteFldMulti(DRAMC_REG_MPC_OPTION, P_Fld(0x1, MPC_OPTION_ZQ_BLOCKALE_OPT) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT2) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT1) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT)); - //fix rank at 0 to trigger new TMRRI setting + vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANK); vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANKFIX); #else - vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_RK_SCINPUT_OPT);// old mode, HW/SW MRR: R_DMMRRRK + vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_RK_SCINPUT_OPT); vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x1, DRAMCTRL_MRRIOPT) | P_Fld(0x1, DRAMCTRL_TMRRIBYRK_DIS) | P_Fld(0x0, DRAMCTRL_TMRRICHKDIS)); vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_SC_PG_UPD_OPT); vIO32WriteFldMulti(DRAMC_REG_SPCMDCTRL, P_Fld(0x1, SPCMDCTRL_SC_PG_MPRW_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_STCMD_AREF_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_OPT2_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_MAN_DIS)); #endif - vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x1, CKECTRL_RUNTIMEMRRCKEFIX);//Set Run time MRR CKE fix to 1 in tMRRI old mode to avoid no ACK from precharge all + vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x1, CKECTRL_RUNTIMEMRRCKEFIX); vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x0, CKECTRL_RUNTIMEMRRMIODIS); vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0); @@ -5851,9 +5739,9 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0xf, SHURK1_DQSIEN_R1DQS0IEN)); vIO32WriteFldMulti(DRAMC_REG_STBCAL1, P_Fld(0x0, STBCAL1_DLLFRZ_MON_PBREF_OPT) | P_Fld(0x1, STBCAL1_STB_FLAGCLR) - | P_Fld(0x1, STBCAL1_STBCNT_SHU_RST_EN) // from HJ review bring-up setting + | P_Fld(0x1, STBCAL1_STBCNT_SHU_RST_EN) | P_Fld(0x1, STBCAL1_STBCNT_MODESEL)); - /* Darren- + /* vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x1, SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE) | P_Fld(0x1, SHU_DQSG_RETRY_R_RDY_SEL_DLE) | P_Fld(0x6, SHU_DQSG_RETRY_R_DQSIENLAT) @@ -5950,7 +5838,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x1, MISC_CTRL0_R_DMSTBEN_OUTSEL) | P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); } - //vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDA_RRESETB_E) //Already set in vDramcInit_PreSettings() + //vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDA_RRESETB_E) vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDQSIENCG_EN) | P_Fld(0x1, MISC_CTRL1_R_DM_TX_ARCMD_OE) #if ENABLE_PINMUX_FOR_RANK_SWAP @@ -5962,13 +5850,12 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldAlign(DDRPHY_CA_RXDVS0, 0, CA_RXDVS0_R_HWSAVE_MODE_ENA_CA); vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCMD_PULL_DN); - vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCS_PULL_DN); // Added by Lingyun.Wu, 11-15 + vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCS_PULL_DN); vIO32WriteFldAlign(DDRPHY_B0_DQ7, 0x0, B0_DQ7_RG_TX_ARDQ_PULL_DN_B0); vIO32WriteFldAlign(DDRPHY_B1_DQ7, 0x0, B1_DQ7_RG_TX_ARDQ_PULL_DN_B1); - //vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN); //Already set in vDramcInit_PreSettings() + //vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN); + - //For 1:8 mode start================= - // 1:8 mode vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x1, SHU_CONF0_DM64BITEN) | P_Fld(0x0, SHU_CONF0_FDIV2) | P_Fld(0x1, SHU_CONF0_FREQDIV4) @@ -5990,26 +5877,26 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) u1TAIL_LAT = 1; } else - //DIV8_MODE + { u1TAIL_LAT = 0; } - //PICG old mode + vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P0) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P1) | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT)); - //PICG_DQSIEN old/new project have same settings - vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT) //TAIL should be set as same value by old/new mode, no matter it is old or new mode - | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT) //TAIL should be set as same value by old/new mode, no matter it is old or new mode + + vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT) + | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT) | P_Fld(u1TAIL_LAT, SHU_STBCAL_DQSIEN_RX_SELPH_OPT)); - //RX_IN_GATE_EN old mode + vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD)); #endif - //For 1:8 mode end================= + vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE) | P_Fld(0x1, SHU_ODTCTRL_RODTE2) @@ -6166,23 +6053,23 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x1, CKECTRL_CKEON) | P_Fld(0x1, CKECTRL_CKETIMER_SEL)); vIO32WriteFldMulti(DRAMC_REG_RKCFG, P_Fld(0x1, RKCFG_CKE2RANK) - | P_Fld(0x1, RKCFG_CKE2RANK_OPT2)); // Darren for CKE dependent + | P_Fld(0x1, RKCFG_CKE2RANK_OPT2)); if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { vIO32WriteFldMulti(DRAMC_REG_SHU_CONF2, P_Fld(0x1, SHU_CONF2_WPRE2T) | P_Fld(0x7, SHU_CONF2_DCMDLYREF)); - //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT)); //ACTiming related -> set in UpdateACTiming_Reg() + //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT)); vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_CLR_EN); - //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV); (Set in UpdateACTimingReg()) + //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x40, SHUCTRL1_FC_PRDCNT); } else { vIO32WriteFldMulti(DRAMC_REG_SHU_CONF2, P_Fld(0x1, SHU_CONF2_WPRE2T) | P_Fld(0x7, SHU_CONF2_DCMDLYREF)); - //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT)); //ACTiming related -> set in UpdateACTiming_Reg() + //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT)); vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_CLR_EN); - //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV); (Set in UpdateACTimingReg()) + //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x40, SHUCTRL1_FC_PRDCNT); } vIO32WriteFldAlign(DRAMC_REG_SHUCTRL, 0x1, SHUCTRL_LPSM_BYPASS_B); @@ -6196,11 +6083,11 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) #endif vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CLKWITRFC); vIO32WriteFldMulti(DRAMC_REG_MISCTL0, P_Fld(0x1, MISCTL0_REFP_ARB_EN2) - | P_Fld(0x1, MISCTL0_PRE_DLE_VLD_OPT) // MISCTL0_PRE_DLE_VLD_OPT from Chris review + | P_Fld(0x1, MISCTL0_PRE_DLE_VLD_OPT) | P_Fld(0x1, MISCTL0_PBC_ARB_EN) | P_Fld(0x1, MISCTL0_REFA_ARB_EN2)); vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_MWHPRIEN) - //| P_Fld(0x1, PERFCTL0_RWSPLIT) //Set in UpdateInitialSettings_LP4() + //| P_Fld(0x1, PERFCTL0_RWSPLIT) | P_Fld(0x1, PERFCTL0_WFLUSHEN) | P_Fld(0x1, PERFCTL0_EMILLATEN) | P_Fld(0x1, PERFCTL0_RWAGEEN) @@ -6213,10 +6100,10 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x1, PADCTRL_DQIENQKEND)); vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMREF_OPT); vIO32WriteFldMulti(DRAMC_REG_CLKCTRL, P_Fld(0x1, CLKCTRL_CLK_EN_1) - | P_Fld(0x1, CLKCTRL_CLK_EN_0)); // CLK_EN_0 from Jouling review + | P_Fld(0x1, CLKCTRL_CLK_EN_0)); vIO32WriteFldMulti(DRAMC_REG_REFCTRL0, P_Fld(0x4, REFCTRL0_DISBYREFNUM) | P_Fld(0x1, REFCTRL0_DLLFRZ)); -#if 0 //CATRAIN_INTV, CATRAINLAT: Correct values are set in UpdateACTimingReg( ) +#if 0 vIO32WriteFldMulti(DRAMC_REG_CATRAINING1, P_Fld(0xff, CATRAINING1_CATRAIN_INTV) | P_Fld(0x0, CATRAINING1_CATRAINLAT)); #endif @@ -6246,8 +6133,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS1IEN) | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS0IEN)); } - // 41536 === over_write_setting_begin === - // 41536 === over_write_setting_end === + vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x1, DRAMCTRL_PREALL_OPTION); vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x56, ZQCS_ZQCSOP); @@ -6258,16 +6144,15 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFFRERUN); vIO32WriteFldAlign(DRAMC_REG_SREFCTRL, 0x1, SREFCTRL_SREF_HW_EN); vIO32WriteFldAlign(DRAMC_REG_MPC_OPTION, 0x1, MPC_OPTION_MPCRKEN); - vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN);//Move to DCM off setting - vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMEN);//Move to DCM off setting + vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN); + vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMEN); vIO32WriteFldMulti(DRAMC_REG_EYESCAN, P_Fld(0x0, EYESCAN_RX_DQ_EYE_SEL) | P_Fld(0x0, EYESCAN_RG_RX_EYE_SCAN_EN)); vIO32WriteFldMulti(DRAMC_REG_STBCAL1, P_Fld(0x1, STBCAL1_STBCNT_LATCH_EN) | P_Fld(0x1, STBCAL1_STBENCMPEN)); vIO32WriteFldAlign(DRAMC_REG_TEST2_1, 0x10000, TEST2_1_TEST2_BASE); #if (FOR_DV_SIMULATION_USED == 1 || SW_CHANGE_FOR_SIMULATION == 1) - //because cmd_len=1 has bug with byte mode, so need to set cmd_len=0, then it will cost more time to do a pattern test - //workaround: reduce TEST2_OFF to make less test agent cmd. make lpddr4-1600 can finish in 60us (Mengru) + vIO32WriteFldAlign(DRAMC_REG_TEST2_2, 0x20, TEST2_2_TEST2_OFF); #else vIO32WriteFldAlign(DRAMC_REG_TEST2_2, 0x400, TEST2_2_TEST2_OFF); @@ -6281,7 +6166,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_HW_MRR_FUN, P_Fld(0x0, HW_MRR_FUN_TRPMRR_EN) | P_Fld(0x0, HW_MRR_FUN_TRCDMRR_EN) | P_Fld(0x0, HW_MRR_FUN_TMRR_ENA) - | P_Fld(0x0, HW_MRR_FUN_MANTMRR_EN)); // from YH Tsai review for samsung MRR/Read cmd issue + | P_Fld(0x0, HW_MRR_FUN_MANTMRR_EN)); if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { vIO32WriteFldAlign(DRAMC_REG_PERFCTL0, 0x1, PERFCTL0_WRFIO_MODE2); @@ -6334,8 +6219,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0x0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT); vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSG_MODE); vIO32WriteFldAlign(DRAMC_REG_STBCAL, 0x1, STBCAL_SREF_DQSGUPD); - //M17_Remap:vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x0, MISC_CTRL1_R_DMDQMDBI); - /* RX Tracking DQM SM enable (actual values are set in DramcRxInputDelayTrackingHW()) */ + #if ENABLE_RX_TRACKING vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, p->DBI_R_onoff[p->dram_fsp], SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, p->DBI_R_onoff[p->dram_fsp], SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1); @@ -6343,7 +6227,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0); vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1); #endif -//Sylv_ia MP setting should set SHU_STBCAL_DMSTBLAT as 0x2 (review by HJ Huang) + vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(0x1, SHU_STBCAL_PICGLAT) | P_Fld(0x2, SHU_STBCAL_DMSTBLAT)); vIO32WriteFldMulti(DRAMC_REG_REFCTRL1, P_Fld(0x1, REFCTRL1_REF_QUE_AUTOSAVE_EN) @@ -6362,11 +6246,11 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) mcDELAY_US(12); - ///TODO: DDR3200 + //if(p->frequency==1600) { #if 0 - // 60826 ===dramc_shu1_lp4_3200 begin=== + if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x5, SHU_RANKCTL_RANKINCTL_PHY) @@ -6384,9 +6268,9 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) #endif #if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK - vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, p->dram_fsp, SHU_WODT_WPST1P5T); //Set write post-amble by FSP with MR3 + vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, p->dram_fsp, SHU_WODT_WPST1P5T); #else - vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, 0x0, SHU_WODT_WPST1P5T); //Set write post-amble by FSP with MR3 + vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, 0x0, SHU_WODT_WPST1P5T); #endif //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR2, 0x2d, SHU_HWSET_MR2_HWSET_MR2_OP); @@ -6427,14 +6311,14 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1) | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)); vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x0, SHU_DQSG_RETRY_R_XSR_RETRY_SPM_MODE) - | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS)); //La_fite MP setting = 0 + | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS)); #if LEGACY_TDQSCK_PRECAL LegacyPreCalLP4_DDR3200(p); #endif - // 61832 ===dramc_shu1_lp4_3200 end=== - // 66870 ===ddrphy_shu1_lp4_3200_CHA begin=== + + if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) { vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0); @@ -6446,16 +6330,13 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)); vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)); -//francis remove : it will make CLRPLL frequency wrong! -//francis remove vIO32WriteFldMulti(DDRPHY_SHU_PLL7, P_Fld(0x3d00, SHU_PLL7_RG_RCLRPLL_SDM_PCW) -//francis remove | P_Fld(0x1, SHU_PLL7_RG_RCLRPLL_SDM_PCW_CHG)); + } - // 67761 ===ddrphy_shu1_lp4_3200_CHA end=== - //NOT included in parsing tool + vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x0, SHU_DQS2DQ_TX_OE2DQ_OFFSET); } - ///TODO: DDR3733 + if (p->freqGroup == 2133) { DramcSetting_Olympus_LP4_ByteMode_DDR4266(p); @@ -6464,8 +6345,8 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) { DramcSetting_Olympus_LP4_ByteMode_DDR3733(p); } - ///TODO: DDR2667 - else if (p->freqGroup == 1333 || p->freqGroup == 1200) // TODO: Initial settings for DDR2400? + + else if (p->freqGroup == 1333 || p->freqGroup == 1200) { DramcSetting_Olympus_LP4_ByteMode_DDR2667(p); } @@ -6476,7 +6357,7 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) UpdateInitialSettings_LP4(p); -#if SIMULATION_SW_IMPED // Darren: Need porting by E2 IMP Calib DVT owner +#if SIMULATION_SW_IMPED #if FSP1_CLKCA_TERM U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ; #else @@ -6516,9 +6397,9 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x1, SHUCTRL2_MR13_SHU_EN) | P_Fld(0x1, SHUCTRL2_HWSET_WLRL)); vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS); - //vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_REFRDIS);//Lewis@20160613: Fix refresh rate is wrong while diable MR4 + //vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_REFRDIS); vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x1, DRAMCTRL_REQQUE_THD_EN); - //| P_Fld(0x1, DRAMCTRL_DPDRK_OPT)); //DPDRK_OPT doesn't exit for Sylv_ia + //| P_Fld(0x1, DRAMCTRL_DPDRK_OPT)); vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM) | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT6) @@ -6527,9 +6408,9 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) | P_Fld(0x1, DUMMY_RD_DUMMY_RD_SW)); vIO32WriteFldAlign(DRAMC_REG_TEST2_4, 0x4, TEST2_4_TESTAGENTRKSEL); vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CTOREQ_HPRI_OPT); - // 60759 === DE initial sequence done === -///TODO: DVFS_Enable + + mcDELAY_US(1); @@ -6538,13 +6419,13 @@ void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p) mcDELAY_US(1); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); - //CH-A + vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x1, SHUCTRL_R_DRAMC_CHA) | P_Fld(0x0, SHUCTRL_SHU_PHYRST_SEL)); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2, 0x1, SHUCTRL2_R_DVFS_DLL_CHA); - //CH-B + vIO32WriteFldMulti(DRAMC_REG_SHUCTRL + SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHUCTRL_R_DRAMC_CHA) | P_Fld(0x1, SHUCTRL_SHU_PHYRST_SEL)); vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2 + SHIFT_TO_CHB_ADDR, 0x0, SHUCTRL2_R_DVFS_DLL_CHA); - // 60826 ===LP4_3200_intial_setting_shu1 end=== + #ifndef LOOPBACK_TEST DDRPhyFMeter_Init(p); @@ -6565,18 +6446,12 @@ void vApplyConfigAfterCalibration(DRAMC_CTX_T *p) U8 u1RankIdx; #endif -/*================================ - PHY RX Settings -==================================*/ + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL4, 0x11400000, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL); vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x0, REFCTRL1_SREF_CG_OPT); - vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL, 0x0, SHUCTRL_DVFS_CG_OPT);//Move to DCM off setting + vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL, 0x0, SHUCTRL_DVFS_CG_OPT); + - /* Burst mode settings are removed from here due to - * 1. Set in UpdateInitialSettings_LP4 - * 2. DQS Gating ensures new burst mode is switched when to done - * (or doesn't switch gatingMode at all, depending on "LP4_GATING_OLD_BURST_MODE") - */ vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN); #if 0 @@ -6593,10 +6468,10 @@ void vApplyConfigAfterCalibration(DRAMC_CTX_T *p) EnableDRAMModeRegReadDBIAfterCalibration(p); #endif - // Set VRCG{MR13[3]} to 0 both to DRAM and DVFS + SetMr13VrcgToNormalOperation(p); - //DA mode + vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1); vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_BIAS_PS); @@ -6605,60 +6480,44 @@ void vApplyConfigAfterCalibration(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1); vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN); -/*================================ - IMPCAL Settings -==================================*/ - vIO32WriteFldMulti_All(DRAMC_REG_IMPCAL, P_Fld(0, IMPCAL_IMPCAL_IMPPDP) | P_Fld(0, IMPCAL_IMPCAL_IMPPDN)); //RG_RIMP_BIAS_EN and RG_RIMP_VREF_EN move to IMPPDP and IMPPDN + + vIO32WriteFldMulti_All(DRAMC_REG_IMPCAL, P_Fld(0, IMPCAL_IMPCAL_IMPPDP) | P_Fld(0, IMPCAL_IMPCAL_IMPPDN)); vIO32WriteFldAlign_All(DDRPHY_MISC_IMP_CTRL0, 0, MISC_IMP_CTRL0_RG_IMP_EN); -/*================================ - MR1 -==================================*/ - //MR1 op[7]=0 already be setted at end of gating calibration, no need to set here again -/* - u1MR01Value[p->dram_fsp] &= 0x7f; - DramcModeRegWrite(p, 1, u1MR01Value[p->dram_fsp]); -*/ - //Prevent M_CK OFF because of hardware auto-sync vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, Fld(4, 0, AC_MSKB0)); - //DFS- fix Gating Tracking settings + vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_STBENCMP_DIV4CK_EN); vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT); - ///TODO: Disable MR4 MR18/MR19, TxHWTracking, Dummy RD - for DFS workaround - vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS); //MR4 Disable - //vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); //MR18, MR19 Disable - //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++) - //vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS); - //vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1, SHU_SCINTV_DQSOSCENDIS); - //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_SCINTV, 0x1, SHU2_SCINTV_DQSOSCENDIS); - //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_SCINTV, 0x1, SHU3_SCINTV_DQSOSCENDIS); + + vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS); + vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)); #if APPLY_LP4_POWER_INIT_SEQUENCE - //CKE dynamic + #if ENABLE_TMRRI_NEW_MODE CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL); #else CKEFixOnOff(p, RANK_0, CKE_DYNAMIC, TO_ALL_CHANNEL); #endif - //// Enable HW MIOCK control to make CLK dynamic + DramCLKAlwaysOnOff(p, OFF); #endif - //close eyescan to save power + vIO32WriteFldMulti_All(DRAMC_REG_EYESCAN, P_Fld(0x0, EYESCAN_EYESCAN_DQS_SYNC_EN) | P_Fld(0x0, EYESCAN_EYESCAN_NEW_DQ_SYNC_EN) | P_Fld(0x0, EYESCAN_EYESCAN_DQ_SYNC_EN)); - /* TESTAGENT2 */ - vIO32WriteFldAlign_All(DRAMC_REG_TEST2_4, 4, TEST2_4_TESTAGENTRKSEL); // Rank selection is controlled by Test Agent + + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_4, 4, TEST2_4_TESTAGENTRKSEL); #endif } #endif @@ -6669,7 +6528,7 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) backup_rank = p->rank; - //Disable RX Tracking + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), P_Fld(0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), P_Fld(0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0), P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0) @@ -6693,15 +6552,14 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 0, SWCMD_CTRL1_WRFIFO_MODE2); - //Bringup setting review + { U32 backup_broadcast = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); U8 u1DQ_HYST_SEL=0x1, u1CA_HYST_SEL=0x1; U8 u1DQ_CAP_SEL=0x1b, u1CA_CAP_SEL=0x1b; - //Critical - //APHY + if(p->frequency<=933) { u1DQ_HYST_SEL = 0x1; @@ -6746,29 +6604,29 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6, P_Fld(u1CA_HYST_SEL, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(u1CA_CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA)); - //Jeremy + vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2,P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) - | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) //Sync MP setting WL - | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0)); //Sync MP setting WL + | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) + | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0)); vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2,P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) - | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) //Sync MP setting WL - | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1)); //Sync MP setting WL + | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) + | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1)); vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2,P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) - | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) //Sync MP setting WL - | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA)); //Sync MP setting WL + | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) + | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA)); + - //disable RX PIPE for RX timing pass vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x0, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN); - //Disable DPM IRQ + vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL1, 0x0); vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL4, 0x0); vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL7, 0x0); - //Disable NEW RX DCM mode + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY) | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) @@ -6820,10 +6678,10 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL2, 0x1, SHU_B0_DLL2_RG_ARDQ_REV_B0); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL2, 0x1, SHU_B1_DLL2_RG_ARDQ_REV_B1); - vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL2, 0x1, SHU_CA_DLL2_RG_ARCMD_REV); //Jeremy + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL2, 0x1, SHU_CA_DLL2_RG_ARCMD_REV); #if 1 - //Follow DE - DRAMC + //vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 1, DDRCOMMON0_DISSTOP26M); //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A3, 1, TEST2_A3_TEST_AID_EN); //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 0, TEST2_A4_TESTAGENTRKSEL); @@ -6842,7 +6700,7 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DRAMC_REG_DVFS_TIMING_CTRL1, 1, DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT); vIO32WriteFldMulti_All(DRAMC_REG_HMR4, P_Fld(1, HMR4_REFRCNT_OPT) | P_Fld(0, HMR4_REFR_PERIOD_OPT) - | P_Fld(1, HMR4_SPDR_MR4_OPT)//Resume from S0, trigger HW MR4 + | P_Fld(1, HMR4_SPDR_MR4_OPT) | P_Fld(0, HMR4_HMR4_TOG_OPT)); vIO32WriteFldAlign_All(DRAMC_REG_RX_SET0, 0, RX_SET0_SMRR_UPD_OLD); vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 1, DRAMCTRL_SHORTQ_OPT); @@ -6854,7 +6712,7 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(0, REFCTRL0_PBREF_BK_REFA_NUM)); vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA); vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPB2AB_IGZQCS); - vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPENDINGINT_OPT1); // @Darren, sync MP settings from Derping + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPENDINGINT_OPT1); vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE1,5, REF_BOUNCE1_REFRATE_DEBOUNCE_TH); vIO32WriteFldAlign_All(DRAMC_REG_REFPEND2, 8, REFPEND2_MPENDREFCNT_TH8); vIO32WriteFldAlign_All(DRAMC_REG_SCSMCTRL, 0, SCSMCTRL_SC_PG_MAN_DIS); @@ -6866,22 +6724,22 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x1ff, SHU_HMR4_DVFS_CTRL0_REFRCNT) | P_Fld(0, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT)); vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, 11, SHU_HWSET_VRCG_VRCGDIS_PRDCNT); vIO32WriteFldAlign_All(DRAMC_REG_SHU_MISC, 2, SHU_MISC_REQQUE_MAXCNT); - vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0, SREF_DPD_CTRL_DSM_HW_EN);//DSM only for LP5 + vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0, SREF_DPD_CTRL_DSM_HW_EN); + - //Follow DE - DDRPHY vIO32WriteFldMulti_All(DDRPHY_REG_B0_DLL_ARPI4, P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0) | P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0)); vIO32WriteFldMulti_All(DDRPHY_REG_B1_DLL_ARPI4, P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1) | P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1)); vIO32WriteFldMulti_All(DDRPHY_REG_CA_DLL_ARPI4, P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA) | P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA)); vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD11, P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVN) | P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVP)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0x1f, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL); - vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQSIEN_CFG, 1, SHU_B0_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B0);//checked with WL - vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQSIEN_CFG, 1, SHU_B1_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B1);//checked with WL - vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DQSIEN_CFG, 1, SHU_CA_DQSIEN_CFG_RG_RX_ARCLK_DQSIEN_GLITCH_FREE_EN_C0);//checked with WL + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQSIEN_CFG, 1, SHU_B0_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B0); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQSIEN_CFG, 1, SHU_B1_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B1); + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DQSIEN_CFG, 1, SHU_CA_DQSIEN_CFG_RG_RX_ARCLK_DQSIEN_GLITCH_FREE_EN_C0); -#if (ENABLE_DDR400_OPEN_LOOP_MODE_OPTION == 0) // Darren- for DDR400 open loop mode disable +#if (ENABLE_DDR400_OPEN_LOOP_MODE_OPTION == 0) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL9, P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF) | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF) | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN) @@ -6893,9 +6751,9 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN) | P_Fld(0, MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN)); #endif - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL, 1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE); + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL, 1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE) - | P_Fld(0, MISC_DVFSCTL2_RG_DLL_SHUFFLE)); // Darren- + | P_Fld(0, MISC_DVFSCTL2_RG_DLL_SHUFFLE)); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, P_Fld(0x10, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK) | P_Fld(1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE) @@ -6903,7 +6761,7 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK) | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK)); - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); + //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DDR_RESERVE, 0xf, MISC_DDR_RESERVE_WDT_CONF_ISO_CNT); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMP_CTRL1, P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT) | P_Fld(1, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR)); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV) @@ -6914,7 +6772,7 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DUTYSCAN1, P_Fld(1, MISC_DUTYSCAN1_EYESCAN_DQS_OPT) | P_Fld(1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY); - // @Darren, MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT is empty after IPM from Mao + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL0, P_Fld(0, MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT) | P_Fld(1, MISC_CTRL0_IMPCAL_CDC_ECO_OPT) | P_Fld(1, MISC_CTRL0_IMPCAL_LP_ECO_OPT)); @@ -6944,9 +6802,9 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, 1, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, 1, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1); - vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA); //sync MP settings by @WL review + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA); + - // @Darren, sync MP settings by @WL review { U8 u1DQ_BW_SEL_B0=0, u1DQ_BW_SEL_B1=0, u1CA_BW_SEL_CA=0; @@ -6963,7 +6821,7 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) } //vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD1, P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA) | P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA)); - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); + //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, 0, SHU_CA_CMD12_RG_RIMP_REV); @@ -6975,11 +6833,11 @@ static void vReplaceDVInit(DRAMC_CTX_T *p) | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS) | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS)); - //Darren-vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(67, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE) | P_Fld(43, MISC_SHU_DVFSDLL_R_DLL_IDLE)); + //vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(67, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE) | P_Fld(43, MISC_SHU_DVFSDLL_R_DLL_IDLE)); - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_IMPCAL1, 0, SHU_MISC_IMPCAL1_IMPCALCNT); - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, 0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN); - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING6, 7, SHU_MISC_DRVING6_IMP_TXDLY_CMD); + //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_IMPCAL1, 0, SHU_MISC_IMPCAL1_IMPCALCNT); + //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, 0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN); + //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING6, 7, SHU_MISC_DRVING6_IMP_TXDLY_CMD); vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY) | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) @@ -6999,77 +6857,70 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p) U8 u1RankIdx, u1RankIdxBak; u1RankIdxBak = u1GetRank(p); - //Clk free run {Move to Init_DRAM() and only call once} + #if (SW_CHANGE_FOR_SIMULATION == 0) EnableDramcPhyDCM(p, 0); #endif - //Set LP3/LP4 Rank0/1 CA/TX delay chain to 0 + #if (FOR_DV_SIMULATION_USED == 0) - //CA0~9 per bit delay line -> CHA_CA0 CHA_CA3 CHA_B0_DQ6 CHA_B0_DQ7 CHA_B0_DQ2 CHA_B0_DQ5 CHA_B0_DQ4 CHA_B0_DQ1 CHA_B0_DQ0 CHA_B0_DQ3 + vResetDelayChainBeforeCalibration(p); #endif - //MR4 refresh cnt set to 0x1ff (2ms update) + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_REFRCNT); - //The counter for Read MR4 cannot be reset after SREF if DRAMC no power down. + vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 1, SPCMDCTRL_SRFMR4_CNTKEEP_B); - //---- ZQ CS init -------- - vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1B, SHU_SCINTV_TZQLAT); //ZQ Calibration Time, unit: 38.46ns, tZQCAL min is 1 us. need to set larger than 0x1b + + vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1B, SHU_SCINTV_TZQLAT); //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++) - //vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3 + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 - vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 - //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 - //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 - vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 0, DRAMCTRL_ZQCALL); // HW send ZQ command for both rank, disable it due to some dram only have 1 ZQ pin for two rank. + //vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3 + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1ff, SHU_CONF3_ZQCSCNT); + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); + //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); + //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT); + vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 0, DRAMCTRL_ZQCALL); + - //Dual channel ZQCS interlace, 0: disable, 1: enable if (p->support_channel_num == CHANNEL_SINGLE) { - //single channel, ZQCSDUAL=0, ZQCSMASK=0 + vIO32WriteFldMulti(DRAMC_REG_ZQCS, P_Fld(0, ZQCS_ZQCSDUAL) | P_Fld(0x0, ZQCS_ZQCSMASK)); } else if (p->support_channel_num == CHANNEL_DUAL) { - // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin. + #ifdef ZQCS_ENABLE_LP4 - // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1 + vIO32WriteFldMulti_All(DRAMC_REG_ZQCS, P_Fld(1, ZQCS_ZQCSDUAL) | \ P_Fld(0, ZQCS_ZQCSMASK_OPT) | \ P_Fld(0, ZQCS_ZQMASK_CGAR) | \ P_Fld(0, ZQCS_ZQCS_MASK_SEL_CGAR)); - //Move to DCM off setting - //vIO32WriteFldMulti_All(DRAMC_REG_ZQCS, P_Fld(1, ZQCS_ZQCSDUAL) | - // P_Fld(0, ZQCS_ZQCSMASK_OPT) | - // P_Fld(0, ZQCS_ZQMASK_CGAR)); - - // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0. - // ZQCSMASK setting: (Ch A, Ch B) = (1,0) or (0,1) - // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + vIO32WriteFldAlign(DRAMC_REG_ZQCS + (CHANNEL_A << POS_BANK_NUM), 1, ZQCS_ZQCSMASK); vIO32WriteFldAlign(DRAMC_REG_ZQCS + SHIFT_TO_CHB_ADDR, 0, ZQCS_ZQCSMASK); - // DRAMC CHA(CHN0):ZQCS_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQCS_ZQCS_MASK_SEL=0. + vIO32WriteFldAlign_All(DRAMC_REG_ZQCS, 0, ZQCS_ZQCS_MASK_SEL); #endif } - // Disable LP3 HW ZQ - vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCSDISB); //LP3 ZQCSDISB=0 - // Disable LP4 HW ZQ - vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCALDISB); //LP4 ZQCALDISB=0 - // ---- End of ZQ CS init ----- - //Disable write-DBI of DRAMC (Avoids pre-defined data pattern being modified) + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCSDISB); + + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCALDISB); + + + DramcWriteDBIOnOff(p, DBI_OFF); - //Disable read-DBI of DRAMC (Avoids pre-defined data pattern being modified) + DramcReadDBIOnOff(p, DBI_OFF); - //disable MR4 read, REFRDIS=1 + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 1, SPCMDCTRL_REFRDIS); - vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x1, DQSOSCR_DQSOSCRDIS); //MR18, MR19 Disable + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x1, DQSOSCR_DQSOSCRDIS); //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++) //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV), 0x1, SHU_SCINTV_DQSOSCENDIS); @@ -7080,38 +6931,38 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p) | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)); - // Disable HW gating tracking first, 0x1c0[31], need to disable both UI and PI tracking or the gating delay reg won't be valid. + DramcHWGatingOnOff(p, 0); - // Disable gating debug + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_STBCAL2), 0, STBCAL2_STB_GERRSTOP); for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++) { vSetRank(p, u1RankIdx); - // Disable RX delay tracking + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1); - //RX delay mux, delay vlaue from reg. + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_CA_RXDVS2), 0x0, R0_CA_RXDVS2_R_RK0_DVS_MODE_CA); } vSetRank(p, u1RankIdxBak); - // Set to all-bank refresh + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_PBREFEN); - // set MRSRK to 0, MPCRKEN always set 1 (Derping) + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MRS), 0, MRS_MRSRK); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN); - //RG mode + vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1); vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_BIAS_PS); @@ -7122,9 +6973,9 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p) #ifdef LOOPBACK_TEST #ifdef LPBK_INTERNAL_EN - DramcLoopbackTest_settings(p, 0); //0: internal loopback test 1: external loopback test + DramcLoopbackTest_settings(p, 0); #else - DramcLoopbackTest_settings(p, 1); //0: internal loopback test 1: external loopback test + DramcLoopbackTest_settings(p, 1); #endif #endif @@ -7139,8 +6990,7 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DRAMC_REG_DRSCTRL, 1, DRSCTRL_DRSDIS); #ifdef IMPEDANCE_TRACKING_ENABLE - // set correct setting to control IMPCAL HW Tracking in shuffle RG - // if p->freq >= 1333, enable IMP HW tracking(SHU_DRVING1_DIS_IMPCAL_HW=0), else SHU_DRVING1_DIS_IMPCAL_HW = 1 + U8 u1DisImpHw; U32 u4TermFreq; @@ -7155,31 +7005,30 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p) #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && RX_DELAY_PRE_CAL - s2RxDelayPreCal = PASS_RANGE_NA; // reset variable for fast k test + s2RxDelayPreCal = PASS_RANGE_NA; #endif #endif } -/* vDramcInit_PreSettings(): Initial register settings(which are required to be set before all calibration flow) */ + #if 0 static void vDramcInit_PreSettings(DRAMC_CTX_T *p) { #if __A60868_TO_BE_PORTING__ - /* PAD_RRESETB control sequence */ - //remove twice dram reset pin pulse before dram power on sequence flow + vIO32WriteFldMulti(DDRPHY_CA_CMD8, P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_PULL_UP) | P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN) | P_Fld(0x1, CA_CMD8_RG_TX_RRESETB_DDR3_SEL) | P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL) | P_Fld(0xa, CA_CMD8_RG_RRESETB_DRVP) | P_Fld(0xa, CA_CMD8_RG_RRESETB_DRVN)); - vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMRRESETB_I_OPT); //Change to glitch-free path - //replace DDRCONF0_GDDR3RST with MISC_CTRL1_R_DMDA_RRESETB_I + vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMRRESETB_I_OPT); + vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x0, MISC_CTRL1_R_DMDA_RRESETB_I); vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMDA_RRESETB_E); #if __ETT__ if (GetDramcBroadcast() == DRAMC_BROADCAST_OFF) - { // In this function, broadcast is assumed to be ON(LP4) -> Show error if broadcast is OFF + { mcSHOW_ERR_MSG(("Err! Broadcast is OFF!\n")); } #endif @@ -7218,22 +7067,22 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p) if(!is_lp5_family(p)) { - if(p->frequency>=2133) //Term + if(p->frequency>=2133) { mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_4266 \n")); sv_algorithm_assistance_LP4_4266(p); } - else if(p->frequency>=1333) //Term + else if(p->frequency>=1333) { mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_3733 \n")); sv_algorithm_assistance_LP4_3733(p); } - else if(p->frequency>400) //Unterm + else if(p->frequency>400) { mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_1600 \n")); sv_algorithm_assistance_LP4_1600(p); } - else if(p->frequency==400) //DDR800 Semi-Open + else if(p->frequency==400) { //mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP4_1600 \n")); //CInit_golden_mini_freq_related_vseq_LP4_1600(p); @@ -7241,7 +7090,7 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p) mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_800 \n")); sv_algorithm_assistance_LP4_800(p); } - else //DDR400 Open Loop + else { mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_400 \n")); sv_algorithm_assistance_LP4_400(p); @@ -7251,7 +7100,7 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p) RESETB_PULL_DN(p); ANA_init(p); DIG_STATIC_SETTING(p); - DIG_CONFIG_SHUF(p,0,0); //temp ch0 group 0 + DIG_CONFIG_SHUF(p,0,0); { LP4_UpdateInitialSettings(p); @@ -7278,10 +7127,10 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) //CInit_ConfigFromTBA(); mcSHOW_DBG_MSG(("MEM_TYPE=%d, freq_sel=%d\n", MEM_TYPE, p->freq_sel)); - SV_BroadcastOn_DramcInit(p); // @Darren, Broadcast Off after SV_BroadcastOn_DramcInit done + SV_BroadcastOn_DramcInit(p); #if PRINT_CALIBRATION_SUMMARY - //default set DRAM status = NO K + memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag)); memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag)); #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK @@ -7290,7 +7139,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) #endif #endif - EnableDramcPhyDCM(p, DCM_OFF); //Let CLK always free-run + EnableDramcPhyDCM(p, DCM_OFF); vResetDelayChainBeforeCalibration(p); DVFSSettings(p); @@ -7307,7 +7156,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) vSetRank(p, RANK_0); - // 8PhaseCal need executed before DutyCal + #ifdef DDR_INIT_TIME_PROFILING U32 CPU_Cycle; TimeProfileBegin(); @@ -7348,9 +7197,9 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) #if 0//__A60868_TO_BE_PORTING__ - U32 save_ch, dram_t; //Darren + U32 save_ch, dram_t; #if (!__ETT__ && !FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0) - EMI_SETTINGS *emi_set; //Darren + EMI_SETTINGS *emi_set; #endif U8 dram_cbt_mode; @@ -7358,7 +7207,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) vSetPHY2ChannelMapping(p, CHANNEL_A); - //default set DRAM status = NO K + memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag)); memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag)); @@ -7370,17 +7219,16 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) //DdrUpdateACTiming(p); -#if 0 //update refresh rate - // for free-run clk 26MHz, 0x62 * (1/26) = 3.8ns +#if 0 + vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0x62, DRAMC_PD_CTRL_REFCNT_FR_CLK); - // for non-fre-run clk, reg = 3.8 ns * f / 4 / 16; + u4RefreshRate = 38 * p->frequency / 640; vIO32WriteFldAlign_All(DRAMC_REG_CONF2, u4RefreshRate, CONF2_REFCNT); #endif #if (fcFOR_CHIP_ID == fcLafite) - // For kernel api for check LPDDR3/4/4X (Darren), only for fcOlympus and fcElbrus. - // For Other chip, please confirm the register is free for SW use. + save_ch = vGetPHY2ChannelMapping(p); vSetPHY2ChannelMapping(p, CHANNEL_A); @@ -7402,7 +7250,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) } vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), dram_t, ARBCTL_RSV_DRAM_TYPE); - // For DRAM normal, byte and mixed mode + if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE)) dram_cbt_mode = CBT_R0_R1_NORMAL; else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1)) @@ -7416,7 +7264,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RSTMASK), dram_cbt_mode, RSTMASK_RSV_DRAM_CBT_MIXED); - // Sagy: Keep original setting till OS kernel ready, if ready, remove it + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), (p->dram_cbt_mode[RANK_0] | p->dram_cbt_mode[RANK_1]), ARBCTL_RSV_DRAM_CBT); vSetPHY2ChannelMapping(p, save_ch); @@ -7432,13 +7280,13 @@ static void Switch26MHzDisableDummyReadRefreshAllBank(DRAMC_CTX_T *p) { #if __A60868_TO_BE_PORTING__ - vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_CLK_MEM_SEL);//Switch clk to 26MHz + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_CLK_MEM_SEL); vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM); vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM); - vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0, REFCTRL0_PBREFEN);//Switch to all bank refresh + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0, REFCTRL0_PBREFEN); - vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DQSG_DMYWR_EN)//Disable Dummy Read + vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DQSG_DMYWR_EN) | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG) | P_Fld(0x0, DUMMY_RD_DMY_WR_DBG)); @@ -7451,10 +7299,10 @@ static void Switch26MHzDisableDummyReadRefreshAllBank(DRAMC_CTX_T *p) #if ENABLE_TMRRI_NEW_MODE void SetCKE2RankIndependent(DRAMC_CTX_T *p) { - #if ENABLE_TMRRI_NEW_MODE//Newly added CKE control mode API + #if ENABLE_TMRRI_NEW_MODE mcSHOW_DBG_MSG2(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON\n")); vCKERankCtrl(p, CKE_RANK_INDEPENDENT); - #else //Legacy individual CKE control register settings + #else mcSHOW_DBG_MSG2(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: OFF\n")); vCKERankCtrl(p, CKE_RANK_DEPENDENT); #endif @@ -7515,7 +7363,7 @@ void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p) } } - //[Ei_ger] DVT item RD2MRR & MRR2RD + vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0x1, HW_MRR_FUN_TR2MRR_ENA) | P_Fld(0x1, HW_MRR_FUN_R2MRRHPRICTL) | P_Fld(0x1, HW_MRR_FUN_MANTMRR_EN)); @@ -7526,7 +7374,7 @@ void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p) #endif -static void SetMr13VrcgToNormalOperationShuffle(DRAMC_CTX_T *p)//Only set DRAM_DFS_SHUFFLE_1 +static void SetMr13VrcgToNormalOperationShuffle(DRAMC_CTX_T *p) { U32 u4Value = 0; @@ -7604,7 +7452,7 @@ void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p) for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++) { vSetPHY2ChannelMapping(p, u1ChIdx); - //To DRAM: MR13[3] = 0 + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); @@ -7625,12 +7473,12 @@ static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p) ShuRGAccessIdxBak = p->ShuRGAccessIdx; mcSHOW_DBG_MSG2(("\n==[DramcShuTrackingDcmEnBySRAM]==\n")); - for (u1ShuffleIdx = 0; u1ShuffleIdx <= 1; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX) + for (u1ShuffleIdx = 0; u1ShuffleIdx <= 1; u1ShuffleIdx++) { - //Aceess DMA SRAM by APB bus use debug mode by conf SHU3 + p->ShuRGAccessIdx = u1ShuffleIdx; #ifdef HW_GATING - //DramcHWGatingOnOff(p, 1, u4DramcShuOffset); // Enable HW gating tracking + //DramcHWGatingOnOff(p, 1, u4DramcShuOffset); #endif #if ENABLE_TX_TRACKING @@ -7642,12 +7490,12 @@ static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p) #endif #ifdef HW_GATING - Enable_Gating_Tracking(p); // Enable HW gating tracking + Enable_Gating_Tracking(p); #endif } p->ShuRGAccessIdx = ShuRGAccessIdxBak; #else - DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; // from dramc conf shu0 + DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable; U8 u1ShuffleIdx; U16 u2Freq = 0; @@ -7665,41 +7513,40 @@ static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p) #endif }; - //Backup regs + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE) Enable_and_Trigger_TX_Retry(p); #endif - //Aceess DMA SRAM by APB bus use debug mode by conf SHU3 - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS); - for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX) + for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) { if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX) { - //for SHU0 restore to SRAM - vSetDFSTable(p, pFreqTable);//Restore DFS table + + vSetDFSTable(p, pFreqTable); u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel); - //Restore regs, or SHU0 RG cannot be set + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;//Since access conf SHU0 + p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0; } else { - //Aceess DMA SRAM by APB bus use debug mode by conf SHU1 - vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx));//Update DFS table + + vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx)); u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel); - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);//before setting + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL); - //APB bus use debug mode by conf SHU1 - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);//Trigger DEBUG MODE + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL); p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1; } - // add your function - // For example: EnableDramcPhyDCMShuffle(p, enable_dcm, u4DramcShuOffset, u4DDRPhyShuOffset, u1ShuffleIdx); + #if ENABLE_TX_TRACKING Enable_TX_Tracking(p); #endif @@ -7707,7 +7554,7 @@ static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p) Enable_RDSEL_Tracking(p, u2Freq); #endif #ifdef HW_GATING - Enable_Gating_Tracking(p); // Enable HW gating tracking + Enable_Gating_Tracking(p); #endif #if ENABLE_PER_BANK_REFRESH && (!IMP_TRACKING_PB_TO_AB_REFRESH_WA) @@ -7716,8 +7563,8 @@ static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p) EnableRxDcmDPhy(p, u2Freq); EnableCmdPicgEffImprove(p); - Enable_ClkTxRxLatchEn(p); // for new xrank mode -#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration + Enable_ClkTxRxLatchEn(p); +#if ENABLE_TX_WDQS Enable_TxWDQS(p); #endif @@ -7746,17 +7593,17 @@ void DramcSetPerBankRefreshMode(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(2, REFCTRL0_PBREF_BK_REFA_NUM)); #if PER_BANK_REFRESH_USE_MODE==0 - vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Original mode + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Original Mode\n")); #endif #if PER_BANK_REFRESH_USE_MODE==1 - vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(1, REFCTRL0_KEEP_PBREF_OPT)); //Hybrid mode + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(1, REFCTRL0_KEEP_PBREF_OPT)); mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Hybrid Mode\n")); #endif #if PER_BANK_REFRESH_USE_MODE==2 - vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Always per-bank mode + vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Always Per-Bank Mode\n")); #endif @@ -7778,17 +7625,16 @@ void DramcHMR4_Presetting(DRAMC_CTX_T *p) // vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual, REFCTRL1_REFRATE_MANUAL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFR_PERIOD_OPT); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_REFRCNT_OPT); // 0: 3.9us * cnt, 1: 15.6us * cnt + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_REFRCNT_OPT); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HMR4_DVFS_CTRL0), 0x80, SHU_HMR4_DVFS_CTRL0_REFRCNT); - // Support byte mode, default disable - // Support byte/normal mode + if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_HMR4_BYTEMODE_EN); else vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_HMR4_BYTEMODE_EN); - // Toggle to clear record + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 1, REFCTRL1_REFRATE_MON_CLR); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR); @@ -7807,15 +7653,15 @@ static void SwitchHMR4(DRAMC_CTX_T *p, bool en) vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 5, REFCTRL2_MR4INT_TH); } - // TOG_OPT, 0: Read rank0 only, 1: read both rank0 and rank1 + if (en && p->support_rank_num == RANK_DUAL) - vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 1, HMR4_HMR4_TOG_OPT); // Read both rank0 and rank1 + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 1, HMR4_HMR4_TOG_OPT); else - vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_HMR4_TOG_OPT); // Read rank0 only (need for manual/SW MRR) + vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_HMR4_TOG_OPT); vIO32WriteFldAlign_All(DRAMC_REG_HMR4, !en, HMR4_REFRDIS); -#if 0 // Reading HMR4 repeatedly for debugging +#if 0 while(1) { mcSHOW_DBG_MSG(("@@ --------------------\n")); @@ -7825,7 +7671,7 @@ static void SwitchHMR4(DRAMC_CTX_T *p, bool en) u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MIN_MON), u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MAX_MON))); - // if HMR4_HMR4_TOG_OPT == 1 + { mcSHOW_DBG_MSG(("@@ MIN MAX\n")); mcSHOW_DBG_MSG(("@@ RK0_B0: %d %d\n", @@ -7851,10 +7697,10 @@ static void SwitchHMR4(DRAMC_CTX_T *p, bool en) #if ENABLE_REFRESH_RATE_DEBOUNCE static void DramcRefreshRateDeBounceEnable(DRAMC_CTX_T *p) { - vIO32WriteFldMulti_All(DRAMC_REG_REF_BOUNCE1, P_Fld(0x4 , REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT) | // when De-bounce counter >= this count, then dramc apply new dram's MR4 value - P_Fld(5 , REF_BOUNCE1_REFRATE_DEBOUNCE_TH) | // MR4 value >= 0.5X refresh rate, then de-bounce count active + vIO32WriteFldMulti_All(DRAMC_REG_REF_BOUNCE1, P_Fld(0x4 , REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT) | + P_Fld(5 , REF_BOUNCE1_REFRATE_DEBOUNCE_TH) | P_Fld(0 , REF_BOUNCE1_REFRATE_DEBOUNCE_OPT) | - P_Fld(0xff1f , REF_BOUNCE1_REFRATE_DEBOUNCE_DIS) ); //all bits set 1 to disable debounce function + P_Fld(0xff1f , REF_BOUNCE1_REFRATE_DEBOUNCE_DIS) ); } #endif @@ -7912,10 +7758,10 @@ static void ToggleOpenLoopModeClk(DRAMC_CTX_T *p) mcDELAY_US(1); vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN); mcDELAY_US(1); - #else //PHY_RG_MODE + #else mcSHOW_DBG_MSG(("[WARNING] DDR400 out (PHY RG MODE) Toggle CLK WA\n")); - //set SPM project code and enable clock enable + vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(1, POWERON_CONFIG_EN_BCLK_CG_EN)); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); @@ -7931,16 +7777,16 @@ static void ToggleOpenLoopModeClk(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN); mcDELAY_US(1); - //Other WA + //DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU7); //DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU7); #endif } #endif -//1.Some RG setting will need to be DCM on, since not consider S0 2.ENABLE_RX_DCM_DPHY should be 1 + #if 0 -static void S0_DCMOffWA(DRAMC_CTX_T *p)//For S0 + DCM off +static void S0_DCMOffWA(DRAMC_CTX_T *p) { vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) | @@ -7964,14 +7810,14 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) SetDramInfoToConf(p); -#if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0) && (REPLACE_DFS_RG_MODE==0)// for DPM RG/PST mode +#if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0) && (REPLACE_DFS_RG_MODE==0) DPMInit(p); mcSHOW_DBG_MSG(("DPM_CONTROL_AFTERK: ON\n")); #endif #if ENABLE_PER_BANK_REFRESH #if IMP_TRACKING_PB_TO_AB_REFRESH_WA - // enable pb-ref for current shu + vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0x1, SHU_CONF0_PBREFEN); #endif mcSHOW_DBG_MSG(("PER_BANK_REFRESH: ON\n")); @@ -7979,13 +7825,13 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("PER_BANK_REFRESH: OFF\n")); #endif -///TODO:KIWI + #if __A60868_TO_BE_PORTING__ #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP) { - EnableDllCg(p, ENABLE); //open CG to save power + EnableDllCg(p, ENABLE); } #endif @@ -8001,7 +7847,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #if XRTWTW_NEW_CROSS_RK_MODE if (p->support_rank_num == RANK_DUAL) { - //ENABLE_XRTWTW_Setting(p); // @Darren, DV codes is included + //ENABLE_XRTWTW_Setting(p); mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: ON\n")); } #else @@ -8011,7 +7857,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #if XRTRTR_NEW_CROSS_RK_MODE if (p->support_rank_num == RANK_DUAL) { - //ENABLE_XRTRTR_Setting(p); // @Darren, DV codes is included + //ENABLE_XRTRTR_Setting(p); mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: ON\n")); } #else @@ -8032,7 +7878,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #if TDQSCK_PRECALCULATION_FOR_DVFS mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: ")); - /* Maoauo: Enable DQS precalculation for LP4, disable for LP3(same as Kibo) */ + DramcDQSPrecalculation_enable(p); mcSHOW_DBG_MSG(("ON\n")); #else @@ -8052,7 +7898,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) DramcRxDlyTrackDebug(p); #endif -/* HW gating - Disabled by default(in preloader) to save power (DE: HJ Huang) */ + #if (defined(HW_GATING)) mcSHOW_DBG_MSG(("HW_GATING DBG: ON\n")); DramcHWGatingDebugOnOff(p, ENABLE); @@ -8062,7 +7908,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #endif #ifdef ZQCS_ENABLE_LP4 - // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + #if (fcFOR_CHIP_ID == fcPetrus) vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB); vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB); @@ -8082,14 +7928,14 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #endif mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: ON\n")); #else - vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 0, ZQ_SET1_ZQCALDISB);// LP3 and LP4 are different, be careful. + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 0, ZQ_SET1_ZQCALDISB); mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: OFF\n")); - #if (!__ETT__) && ENABLE_LP4Y_DFS // for preloader + #if (!__ETT__) && ENABLE_LP4Y_DFS #error RTMRW DFS must support the SWZQ at DPM!!! #endif #endif -///TODO:JEREMY + #if 0 #ifdef DUMMY_READ_FOR_DQS_GATING_RETRY DummyReadForDqsGatingRetryNonShuffle(p, 1); @@ -8129,7 +7975,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) if(enable_dcm == 0) { - //S0_DCMOffWA(p);//For S0 + DCM off + //S0_DCMOffWA(p); } #else @@ -8137,7 +7983,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) EnableDramcPhyDCMNonShuffle(p, 0); mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n")); - //S0_DCMOffWA(p);//For S0 + DCM off + //S0_DCMOffWA(p); #endif #endif @@ -8150,7 +7996,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #endif -//Dummy read should NOT be enabled before gating tracking + #ifdef DUMMY_READ_FOR_TRACKING DramcDummyReadForTrackingEnable(p); #else @@ -8167,8 +8013,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("!!! SPM could not control APHY\n")); #endif -// when time profiling multi times, SW impedance tracking will fail when trakcing enable. -// ignor SW impedance tracking when doing time profling + #ifndef DDR_INIT_TIME_PROFILING #ifdef IMPEDANCE_TRACKING_ENABLE if (p->dram_type == TYPE_LPDDR4 || p->dram_type == TYPE_LPDDR4X) @@ -8185,7 +8030,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #endif #endif - //0x1c0[31] + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSCAL0), 0, DQSCAL0_STBCALEN); #ifdef TEMP_SENSOR_ENABLE @@ -8229,7 +8074,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #if DFS_NOQUEUE_FLUSH_LATENCY_CNT vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_FSM_CFG, 1, LPIF_FSM_CFG_DBG_LATENCY_CNT_EN); - // DPM clock is 208M + vIO32WriteFldMulti_All(DDRPHY_MD32_REG_SSPM_MCLK_DIV, P_Fld(0, SSPM_MCLK_DIV_MCLK_SRC) | P_Fld(0, SSPM_MCLK_DIV_MCLK_DIV)); mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: ON\n")); @@ -8247,7 +8092,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) #endif //CheckRxPICGNewModeSetting(p); - vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x0, REFCTRL0_REFDIS); //After k, auto refresh should be enable + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x0, REFCTRL0_REFDIS); #if DDR_RESERVE_NEW_MODE mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: ON\n")); @@ -8274,7 +8119,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("=========================\n")); } -#if 0 //no use? +#if 0 void DramcTest_DualSch_stress(DRAMC_CTX_T *p) { U32 count = 0; @@ -8304,13 +8149,13 @@ void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff) { static U8 gIsddr800TxRetry = 0; - // MCK still available for DRAMC RG access from Joe comment + if (shu_level == SRAM_SHU6) { gIsddr800TxRetry = 1; } - //Need to do tx retry when DDR800 -> DDr1200 + if ((gIsddr800TxRetry == 1) && (shu_level != SRAM_SHU6) #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION && (shu_level != SRAM_SHU7)) @@ -8325,27 +8170,27 @@ void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff) mcDELAY_US(1); #if TX_RETRY_CONTROL_BY_SPM vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN); - #else //control by DRAMC + #else vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_EN); #endif } - else //DISABLE + else { mcSHOW_DBG_MSG2(("TX track retry: DISABLE! (DDR800 to DDR1200)\n")); #if TX_RETRY_CONTROL_BY_SPM vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN); - #else //control by DRAMC + #else vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_EN); #endif - mcDELAY_US(1); //add 1us delay to wait emi and tx retry be done (because PPR_CTRL_TX_RETRY_SHU_RESP_OPT=1) - vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); //enable block emi to let tx retry be finish + mcDELAY_US(1); + vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK); gIsddr800TxRetry = 0; } } } #if SW_TX_RETRY_ENABLE -#define SW_TX_RETRY_ENABLE_WA 1 //To recieve response by disable CG +#define SW_TX_RETRY_ENABLE_WA 1 void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p) { U8 u4Response; @@ -8367,7 +8212,7 @@ void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p) do { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TX_RETRY_DONE_RESPONSE); - mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("still wait tx retry be done\n", u4Response)); }while (u4Response == 0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN); @@ -8381,7 +8226,7 @@ void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p) #endif #endif -// The "ENABLE_RANK_NUMBER_AUTO_DETECTION" use this API + void DFSInitForCalibration(DRAMC_CTX_T *p) { #ifdef DDR_INIT_TIME_PROFILING @@ -8443,12 +8288,12 @@ void DFSInitForCalibration(DRAMC_CTX_T *p) #endif } -#if 0 /* cc mark to use DV initial setting */ +#if 0 void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) { #ifdef HW_GATING #if DramcHWDQSGatingTracking_FIFO_MODE - //REFUICHG=0, STB_SHIFT_DTCOUT_IG=0, DQSG_MODE=1, NARROW_IG=0 + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) | P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) | @@ -8462,7 +8307,7 @@ void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) | - //cc mark P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) | + //P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) | P_Fld(1, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG)); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0), @@ -8470,7 +8315,7 @@ void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) P_Fld(0, MISC_CTRL0_R_DMVALID_DLY) | P_Fld(0, MISC_CTRL0_R_DMVALID_DLY_OPT) | P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG)); - //cc mark P_Fld(0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); + //P_Fld(0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 0, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0); @@ -8480,7 +8325,7 @@ void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) 0, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL); #else - //REFUICHG=0, STB_SHIFT_DTCOUT_IG=0, DQSG_MODE=1, NARROW_IG=0 + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) | P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) | @@ -8494,7 +8339,7 @@ void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) | - //cc mark P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) | + //P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) | P_Fld(0, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG)); @@ -8503,7 +8348,7 @@ void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p) P_Fld(3, MISC_CTRL0_R_DMVALID_DLY) | P_Fld(1, MISC_CTRL0_R_DMVALID_DLY_OPT) | P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG)); - //cc mark P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); + //P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT)); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0); @@ -8533,13 +8378,12 @@ void GetTXPICGSetting(DRAMC_CTX_T * p) for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++) { vSetPHY2ChannelMapping(p, u1CHIdx); - //Set TX DQS PICG - //DQS0 - u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);//m - u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);//n - //DQS1 - u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m - u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n + + u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0); + u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0); + + u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1); + u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1); mcSHOW_DBG_MSG(("CH%d\n", u1CHIdx)); mcSHOW_DBG_MSG(("DQS0 m=%d n=%d \n", u2DQS_OEN_2T[0], u2DQS_OEN_05T[0])); @@ -8555,18 +8399,18 @@ void GetTXPICGSetting(DRAMC_CTX_T * p) mcSHOW_DBG_MSG(("TX_DQS_SEL_P1 %d \n", u2COMB_TX_SEL[1])); mcSHOW_DBG_MSG(("COMB_TX_PICG_CNT %d \n", u2COMB_TX_PICG_CNT)); - //Set TX RK0 and RK1 DQ PICG + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { mcSHOW_DBG_MSG(("Rank%d\n", u1RankIdx)); vSetRank(p, u1RankIdx); - //DQ0 - u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);//p - u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0);//q - //DQ1 - u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);//p - u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);//q + + u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0); + + u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); + u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1); mcSHOW_DBG_MSG(("DQ0 p=%d q=%d \n", u2DQ_OEN_2T[0], u2DQ_OEN_05T[0])); mcSHOW_DBG_MSG(("DQ1 p=%d q=%d \n", u2DQ_OEN_2T[1], u2DQ_OEN_05T[1])); @@ -8583,7 +8427,7 @@ void GetTXPICGSetting(DRAMC_CTX_T * p) } #endif -#define ADD_1UI_TO_APHY 1 //After A60-868/Pe-trus +#define ADD_1UI_TO_APHY 1 void TXPICGSetting(DRAMC_CTX_T * p) { U32 u4DQS_OEN_final, u4DQ_OEN_final; @@ -8595,38 +8439,37 @@ void TXPICGSetting(DRAMC_CTX_T * p) U16 u2COMB_TX_PICG_CNT; U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio; - u2COMB_TX_PICG_CNT = 3;//After Pe-trus, could detect HW OE=1 -> 0 automatically, and prolong TX picg + u2COMB_TX_PICG_CNT = 3; if (vGet_Div_Mode(p) == DIV8_MODE) { - u2Shift_DQS_Div[0] = 10;//phase 0 - u2Shift_DQS_Div[1] = 6;//phase 1 - u2Shift_DQ_Div[0] = 8;//phase 0 - u2Shift_DQ_Div[1] = 4;//phase 1 + u2Shift_DQS_Div[0] = 10; + u2Shift_DQS_Div[1] = 6; + u2Shift_DQ_Div[0] = 8; + u2Shift_DQ_Div[1] = 4; u1Div_ratio = 3; } - else //DIV4_MODE + else { - u2Shift_DQS_Div[0] = 2;//phase 0 - u2Shift_DQS_Div[1] = 0;//phase 1, no use - u2Shift_DQ_Div[0] = 0;//phase 0 - u2Shift_DQ_Div[1] = 0;//phase 1, no use + u2Shift_DQS_Div[0] = 2; + u2Shift_DQS_Div[1] = 0; + u2Shift_DQ_Div[0] = 0; + u2Shift_DQ_Div[1] = 0; u1Div_ratio = 2; } for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++) { vSetPHY2ChannelMapping(p, u1CHIdx); - //Set TX DQS PICG - //DQS0 - u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);//m - u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);//n + + u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0); + u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0); u2DQS_OEN_Delay[0] = (u2DQS_OEN_2T[0] << u1Div_ratio) + u2DQS_OEN_05T[0]; - //DQS1 - u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m - u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n + + u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1); + u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1); u2DQS_OEN_Delay[1] = (u2DQS_OEN_2T[1] << u1Div_ratio) + u2DQS_OEN_05T[1]; - u4DQS_OEN_final = (u2DQS_OEN_Delay[0] > u2DQS_OEN_Delay[1])? u2DQS_OEN_Delay[1]: u2DQS_OEN_Delay[0]; //choose minimum value + u4DQS_OEN_final = (u2DQS_OEN_Delay[0] > u2DQS_OEN_Delay[1])? u2DQS_OEN_Delay[1]: u2DQS_OEN_Delay[0]; u4DQS_OEN_final += ADD_1UI_TO_APHY; @@ -8640,21 +8483,21 @@ void TXPICGSetting(DRAMC_CTX_T * p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) | P_Fld(u2COMB_TX_SEL[1], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(u2COMB_TX_PICG_CNT, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT)); - //Set TX RK0 and RK1 DQ PICG + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); - //DQ0 + u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0); u2DQ_OEN_Delay[0] = (u2DQ_OEN_2T[0] << u1Div_ratio) + u2DQ_OEN_05T[0]; - //DQ1 + u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1); u2DQ_OEN_Delay[1] = (u2DQ_OEN_2T[1] << u1Div_ratio) + u2DQ_OEN_05T[1]; - u4DQ_OEN_final = (u2DQ_OEN_Delay[0] > u2DQ_OEN_Delay[1])? u2DQ_OEN_Delay[1]: u2DQ_OEN_Delay[0]; //choose minimum value + u4DQ_OEN_final = (u2DQ_OEN_Delay[0] > u2DQ_OEN_Delay[1])? u2DQ_OEN_Delay[1]: u2DQ_OEN_Delay[0]; u4DQ_OEN_final += ADD_1UI_TO_APHY; u2COMB_TX_SEL[0] = (u4DQ_OEN_final > u2Shift_DQ_Div[0])? ((u4DQ_OEN_final - u2Shift_DQ_Div[0]) >> u1Div_ratio): 0; @@ -8683,23 +8526,21 @@ static void RXPICGSetting(DRAMC_CTX_T * p) vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STBCALEN); vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STB_SELPHCALEN); - //PI_CG_DQSIEN new mode + vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL1, 1, MISC_STBCAL1_STBCNT_SHU_RST_EN); vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE); - //APHY control new mode + vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, 1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT); vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, 1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT); - //Dummy code (based on DVT document Verification plan of RX PICG efficiency improvment.docx) - //No need to set since HW setting or setting in other place - //Pls. don't remove for the integrity + { U8 u1TAIL_LAT = (vGet_Div_Mode(p) == DIV4_MODE) ? 1: 0; vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0, MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN); - for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank + for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL, P_Fld(u1TAIL_LAT, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT) @@ -8736,12 +8577,12 @@ static void RXPICGSetting(DRAMC_CTX_T * p) void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p) { #if !__ETT__ - //set for SPM DRAM self refresh + vIO32WriteFldAlign(SPM_POWERON_CONFIG_EN, 1, POWERON_CONFIG_EN_BCLK_CG_EN); vIO32WriteFldAlign(SPM_DRAMC_DPY_CLK_SW_CON_2, 1, SPM_DRAMC_DPY_CLK_SW_CON_2_SW_PHYPLL_MODE_SW); vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_PHYPLL_MODE_SW); #endif - //Preloader exit with legacy mode for CTP load used + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL); vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN); vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN); @@ -8751,7 +8592,7 @@ void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p) #if TX_PICG_NEW_MODE void TXPICGNewModeEnable(DRAMC_CTX_T * p) { - //Switch TX PICG to new mode + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, P_Fld(0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT) | P_Fld(0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT) | P_Fld(0, MISC_CTRL3_ARPI_CG_DQS_OPT) @@ -8770,12 +8611,6 @@ void ApplyWriteDBIProtect(DRAMC_CTX_T *p, U8 onoff) uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel]; - // Write DMI/DBI Protect Function - // Byte0 can not have bit swap between Group1(DQ0/1) and Group2(DQ02~DQ07). - // Byte1 can not have bit swap between Group1(DQ8/9) and Group2(DQ10~DQ15). - // DBIWR_IMP_EN=1 and DBIWR_PINMUX_EN=1 - // set DBIWR_OPTB0[7:0] meet with Byte0 pin MUX table. - // set DBIWR_OPTB1[7:0] meet with Byte1 pin MUX table. for (DQ_index = 0; DQ_index < 16; DQ_index++) { @@ -8796,41 +8631,13 @@ void ApplyWriteDBIProtect(DRAMC_CTX_T *p, U8 onoff) void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff) { - // set DBIWR_IMP_EN = 1 - // DBIWR_OPTB0[1:0]=0, DBIWR_OPT_B0[7]=0 - // DBIWR_OPTB1[1:0]=0, DBIWR_OPT_B1[7]=0 + vIO32WriteFldMulti_All(DRAMC_REG_DBIWR_PROTECT, P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B1) | P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B0) | P_Fld(0, DBIWR_PROTECT_DBIWR_PINMUX_EN) | P_Fld(onoff, DBIWR_PROTECT_DBIWR_IMP_EN)); } -/* DDR800 mode struct declaration (declared here due Fld_wid for each register type) */ -/* -typedef struct _DDR800Mode_T -{ - U8 dll_phdet_en_b0: Fld_wid(SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU); - U8 dll_phdet_en_b1: Fld_wid(SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU); - U8 dll_phdet_en_ca_cha: Fld_wid(SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); - U8 dll_phdet_en_ca_chb: Fld_wid(SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); - U8 phypll_ada_mck8x_en: Fld_wid(SHU_PLL22_RG_RPHYPLL_ADA_MCK8X_EN_SHU); - U8 ddr400_en_b0: Fld_wid(SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0); - U8 ddr400_en_b1: Fld_wid(SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1); - U8 ddr400_en_ca: Fld_wid(SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA); - U8 phypll_ddr400_en: Fld_wid(SHU_PLL1_RG_RPHYPLL_DDR400_EN); - U8 ddr400_dqs_ps_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_DQS_PS_B0); - U8 ddr400_dqs_ps_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_DQS_PS_B1); - U8 ddr400_dq_ps_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_DQ_PS_B0); - U8 ddr400_dq_ps_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_DQ_PS_B1); - U8 ddr400_dqs_ps_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_DQS_PS_CA); - U8 ddr400_dq_ps_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_DQ_PS_CA); - U8 ddr400_semi_en_b0: Fld_wid(SHU_B0_DQ9_RG_DDR400_SEMI_EN_B0); - U8 ddr400_semi_en_b1: Fld_wid(SHU_B1_DQ9_RG_DDR400_SEMI_EN_B1); - U8 ddr400_semi_en_ca: Fld_wid(SHU_CA_CMD9_RG_DDR400_SEMI_EN_CA); - U8 ddr400_semi_open_en: Fld_wid(SHU_PLL0_RG_DDR400_SEMI_OPEN_EN); - U8 pll0_ada_mck8x_chb_en: Fld_wid(SHU_PLL0_ADA_MCK8X_CHB_EN); - U8 pll0_ada_mck8x_cha_en: Fld_wid(SHU_PLL0_ADA_MCK8X_CHA_EN); -} DDR800Mode_T; -*/ + #endif @@ -8840,12 +8647,12 @@ static void RODTSettings(DRAMC_CTX_T *p) U8 u1RankIdx, u1RankIdxBak; BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - //VREF_EN + vIO32WriteFldAlign(DDRPHY_REG_B0_DQ5, 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); vIO32WriteFldAlign(DDRPHY_REG_B1_DQ5, !isLP4_DSC, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); vIO32WriteFldAlign(DDRPHY_REG_CA_CMD5, isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN); - //Update related setting of APHY RX and ODT + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, !(p->odt_onoff), SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); if (!isLP4_DSC) vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, !(p->odt_onoff), SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); @@ -8854,11 +8661,11 @@ static void RODTSettings(DRAMC_CTX_T *p) if(p->odt_onoff==ODT_ON) { - u1VrefSel = 0x2c;//term LP4 + u1VrefSel = 0x2c; } else { - u1VrefSel = 0x37;//unterm LP4 + u1VrefSel = 0x37; } u1RankIdxBak = u1GetRank(p); @@ -8901,20 +8708,18 @@ static void RODTSettings(DRAMC_CTX_T *p) #endif #if ENABLE_RODT_TRACKING - //RODT tracking + vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) | P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME)); #endif - //Darren-vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, !(p->odt_onoff), B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0); - //Darren-vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, !(p->odt_onoff), B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1); - //Darren-vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, !(p->odt_onoff), CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS); + vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ13, !(p->odt_onoff), SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0); vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ13, !(p->odt_onoff), SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1); vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD13, !(p->odt_onoff), SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA); - //APHY CG disable + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13, P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0)); vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ14, 0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0); @@ -8933,11 +8738,7 @@ static void RODTSettings(DRAMC_CTX_T *p) } } -/* LP4 use 7UI mode (1) - * LP5 lower than 4266 use 7UI mode (1) - * LP5 higher than 4266 use 11UI mode (2) - * LP5 higher than 4266 with better SI use 11/24UI mode (3) - */ + static void DQSSTBSettings(DRAMC_CTX_T *p) { unsigned int dqsien_mode = 1; @@ -8976,21 +8777,20 @@ static void SetMck8xLowPwrOption(DRAMC_CTX_T *p) void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) { U8 u1RankIdx, u1RankIdxBak; - ///TODO: - //BRINGUP-TEST + vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL3, 0, MISC_CTRL3_ARPI_CG_CLK_OPT); vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, 0, MISC_CTRL4_R_OPT2_CG_CLK); //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA)); //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLKB_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLKB_OE_TIE_SEL_CA)); - //Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux + //Set_MRR_Pinmux_Mapping(p); vReplaceDVInit(p); - //Let CA and CS be independent - vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //@Jimmy, confirm with WL set EMCP/DSC = 0, from mt6833 - //Disable perbyte option + vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); + + vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0)); @@ -9002,7 +8802,7 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) RXPICGSetting(p); #endif -#if SIMULATION_SW_IMPED // Darren: Need porting by E2 IMP Calib DVT owner +#if SIMULATION_SW_IMPED #if FSP1_CLKCA_TERM U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ; #else @@ -9018,7 +8818,7 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) RODTSettings(p); - //WDBI-OFF + vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR); #if CBT_MOVE_CA_INSTEAD_OF_CLK @@ -9027,11 +8827,11 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) u1CaUI = 1; u1CaPI = 0; - // CA delay shift u1CaUI*UI + DramcCmdUIDelaySetting(p, u1CaUI); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1)); - // Rank0/1 u1CaPI*PI CA delay + u1RankIdxBak = u1GetRank(p); @@ -9046,19 +8846,19 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) #endif #if ENABLE_TPBR2PBR_REFRESH_TIMING - vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA); //@Derping - vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA); //@Unique - vIO32WriteFldAlign(DRAMC_REG_SCHEDULER_COM, 0x1, SCHEDULER_COM_PBR2PBR_OPT); //@YH + vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA); + vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA); + vIO32WriteFldAlign(DRAMC_REG_SCHEDULER_COM, 0x1, SCHEDULER_COM_PBR2PBR_OPT); #endif #if RDSEL_TRACKING_EN - vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1 + vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); #endif #if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK - vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, p->dram_fsp, SHU_TX_SET0_WPST1P5T); //Set write post-amble by FSP with MR3 + vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, p->dram_fsp, SHU_TX_SET0_WPST1P5T); #else - vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_WPST1P5T); //Set write post-amble by FSP with MR3 + vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_WPST1P5T); #endif #if (!XRTRTR_NEW_CROSS_RK_MODE) @@ -9069,42 +8869,31 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) if(p->support_rank_num== RANK_SINGLE) vIO32WriteFldAlign(DRAMC_REG_CMD_DEC_CTRL0, 1, CMD_DEC_CTRL0_CS1FIXOFF); - //vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_EMI_CTRL, 0x26, SHU_MISC_EMI_CTRL_DR_EMI_RESERVE);//Alex-CH checked + //vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_EMI_CTRL, 0x26, SHU_MISC_EMI_CTRL_DR_EMI_RESERVE); #endif - //MP Setting + vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x1, DUMMY_RD_SREF_DMYRD_EN)); - // @Unique, sync MP settings + vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN) | P_Fld(0x1, DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN) | P_Fld(0x1, DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN)); vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSGCNT_BYP_REF); - //@Darren- enable bit11 via FMeter, vIO32WriteFldAlign(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN); - //1:8 --> data rate<=1600 set 0, data rate<=3200 set 1, else 2 - //1:4 --> data rate<= 800 set 0, data rate<=1600 set 1, else 2 - // @Darren, confirm w/ Chau-Wei Wang (Jason) sync MP settings if(p->frequency<=800) vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD); else if(p->frequency<=1200) vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD); - else // for DDR4266/DDR3200 + else vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD); - // @Darren, Fix DQ/DQM duty PI not work. + vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW); - // @Darren, sync MP from Mao + vIO32WriteFldMulti(DDRPHY_REG_CA_TX_MCK, P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY)); - // @Darren, Fix GE for new RANK_SEL design from HJ/WL Lee (B16/8 + APHY design skew = 3*MCK) - /* - DQSI_DIV latency: - 100ps + 200ps + 234ps*3 + 200ps = 1202ps - (INB) (gate dly) (3UI@4266) (LVSH+wire) - LEAD/LAG latency: (after retime with DQSI_DIV_INV) 200ps (LVSH+wire) - */ vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) | P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA)); @@ -9113,27 +8902,16 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p) #define CKGEN_FMETER 0x0 #define ABIST_FMETER 0x1 -/* -1. Select meter clock input: CLK_DBG_CFG[1:0] = 0x0 -2. Select clock source from below table: CLK_DBG_CFG[21:16] = 0x39 -3. Setup meter div: CLK_MISC_CFG_0[31:24] = 0x0 -4. Enable frequency meter: CLK26CALI_0[12] = 0x1 -5. Trigger frequency meter: CLK26CALI_0[4] = 0x1 -6. Wait until CLK26CALI_0[4] = 0x0 -7. Read meter count: CLK26CALI_1[15:0] -8. Calculate measured frequency: freq. = (26 * cal_cnt) / 1024 - -DE: Mas Lin -*/ + static unsigned int FMeter(unsigned char u1CLKMeterSel, unsigned char u1CLKMuxSel) { #if (FOR_DV_SIMULATION_USED==0) unsigned int tmp, u4CalCnt; - // enable fmeter + DRV_WriteReg32(CLK26CALI_0, (0x1 << 7)); - // select meter + tmp = DRV_Reg32(CLK_DBG_CFG); tmp &= ~0x3; @@ -9142,7 +8920,7 @@ static unsigned int FMeter(unsigned char u1CLKMeterSel, unsigned char u1CLKMuxSe DRV_WriteReg32(CLK_DBG_CFG, tmp); - // select fmeter's input clock + tmp = DRV_Reg32(CLK_DBG_CFG); if (u1CLKMeterSel == CKGEN_FMETER) { @@ -9155,31 +8933,31 @@ static unsigned int FMeter(unsigned char u1CLKMeterSel, unsigned char u1CLKMuxSe DRV_WriteReg32(CLK_DBG_CFG, tmp); - // setup fmeter div + tmp = DRV_Reg32(CLK_MISC_CFG_0); tmp &= ~(0xFF << 24); DRV_WriteReg32(CLK_MISC_CFG_0, tmp); - // set load_cnt to 0x3FF (1024 - 1) + tmp = DRV_Reg32(CLK26CALI_1); tmp &= ~(0x3FF << 16); tmp |= 0x3FF << 16; DRV_WriteReg32(CLK26CALI_1, tmp); - // trigger fmeter + tmp = DRV_Reg32(CLK26CALI_0); tmp |= (0x1 << 4); DRV_WriteReg32(CLK26CALI_0, tmp); - // wait + while (DRV_Reg32(CLK26CALI_0) & (0x1 << 4)) { mcDELAY_US(1); } - // read + u4CalCnt = DRV_Reg32(CLK26CALI_1) & 0xFFFF; - // disable fmeter + tmp = DRV_Reg32(CLK26CALI_0); tmp &= ~(0x1 << 7); DRV_WriteReg32(CLK26CALI_0, tmp); @@ -9193,15 +8971,15 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) #if (FOR_DV_SIMULATION_USED == 0) - unsigned int reg0=0;//reg1=0 + unsigned int reg0=0; unsigned int backup_phypll = 0, backup_clrpll = 0; unsigned int before_value=0, after_value=0; unsigned int frq_result=0; unsigned int meter_value=0; U16 frqValue = 0; -#if 1//def HJ_SIM - /*TINFO="\n[PhyFreqMeter]"*/ +#if 1 + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; backup_phypll = reg0; @@ -9211,48 +8989,48 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 | (1 << 16)); mcDELAY_US(1); - // abist_clk22: AD_CLKSQ_FS26M_CK + frq_result = FMeter(ABIST_FMETER, 22); mcSHOW_DBG_MSG4(("AD_CLKSQ_FS26M_CK=%d MHz\n", frq_result)); - // abist_clk30: AD_MPLL_CK + frq_result = FMeter(ABIST_FMETER, 30); mcSHOW_DBG_MSG4(("AD_MPLL_CK=%d MHz\n", frq_result)); - /*TINFO="AD_MPLL_CK FREQ=%d\n", frq_result*/ + #if 1 if((DRV_Reg32(Channel_A_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0) { - // abist_clk119: AD_RCLRPLL_DIV4_CK_ch01 + //frq_result = FMeter(ABIST_FMETER, 119); //mcSHOW_DBG_MSG4(("AD_RCLRPLL_DIV4_CK_ch01 FREQ=%d MHz\n", frq_result)); - /*TINFO="AD_RCLRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result*/ + } else { - // abist_clk120: AD_RPHYRPLL_DIV4_CK_ch01 + //frq_result = FMeter(ABIST_FMETER, 120); //mcSHOW_DBG_MSG4(("AD_RPHYRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result)); - /*TINFO="AD_RPHYRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result*/ + } #endif - //! ch0 + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ; DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); - // abistgen_clk118: fmem_ck_bfe_dcm_ch0 (DRAMC CHA's clock before idle mask) + before_value = FMeter(ABIST_FMETER, 118); mcSHOW_DBG_MSG4(("fmem_ck_bfe_dcm_ch0 FREQ=%d MHz\n", before_value)); - /*TINFO="fmem_ck_bfe_dcm_ch0 FREQ=%d\n", before_value*/ - // abistgen_clk117: fmem_ck_aft_dcm_ch0 (DRAMC CHA's clock after idle mask) + + after_value = FMeter(ABIST_FMETER, 117); mcSHOW_DBG_MSG4(("fmem_ck_aft_dcm_ch0 FREQ=%d MHz\n", after_value)); - /*TINFO="fmem_ck_aft_dcm_ch0 FREQ=%d\n", after_value*/ + //gddrphyfmeter_value = after_value << 2; - #if 0 // @ tg change for Open loop mode(0x70C need fix 1) + #if 0 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 & ~(1 << 16)); reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ; @@ -9272,17 +9050,17 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) #if 1 if((DRV_Reg32(Channel_C_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0) { - // abist_clk116: AD_RCLRPLL_DIV4_CK_ch23 + //frq_result = FMeter(ABIST_FMETER, 116); //mcSHOW_DBG_MSG4(("AD_RCLRPLL_DIV4_CK_ch23 FREQ=%d MHz\n", frq_result)); - /*TINFO="AD_RCLRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result*/ + } else { - // abist_clk115: AD_RPHYRPLL_DIV4_CK_ch23 + //frq_result = FMeter(ABIST_FMETER, 115); //mcSHOW_DBG_MSG4(("AD_RPHYRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result)); - /*TINFO="AD_RPHYRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result*/ + } #endif @@ -9291,15 +9069,15 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ; DRV_WriteReg32 (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); - // abistgen_clk114: fmem_ck_bfe_dcm_ch2 (DRAMC CHC's clock after idle mask) + before_value = FMeter(ABIST_FMETER, 114); mcSHOW_DBG_MSG4(("fmem_ck_bfe_dcm_ch2 FREQ=%d MHz\n", before_value)); - /*TINFO="fmem_ck_bfe_dcm_ch2 FREQ=%d\n", after_value*/ - // abistgen_clk113: fmem_ck_aft_dcm_ch2 (DRAMC CHC's clock after idle mask) + + after_value = FMeter(ABIST_FMETER, 113); mcSHOW_DBG_MSG4(("fmem_ck_aft_dcm_ch2 FREQ=%d MHz\n", after_value)); - /*TINFO="fmem_ck_aft_dcm_ch2 FREQ=%d\n", after_value*/ + reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ; DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 & ~(1 << 16)); @@ -9311,22 +9089,22 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) meter_value = (before_value<<16 | after_value); #else mcSHOW_DBG_MSG3(("\n[PhyFreqMeter]\n")); - // abist_clk29: AD_MPLL_CK + mcSHOW_DBG_MSG(("AD_MPLL_CK FREQ=%d\n", FMeter(ABIST_FMETER, 29))); - // abist_clk31: AD_RCLRPLL_DIV4_CK_ch02 + mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", FMeter(ABIST_FMETER, 31))); - // abist_clk32: AD_RCLRPLL_DIV4_CK_ch13 + mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", FMeter(ABIST_FMETER, 32))); - // abist_clk33: AD_RPHYRPLL_DIV4_CK_ch02 + mcSHOW_DBG_MSG(("AD_RPHYRPLL_DIV4_CK_ch02 FREQ=%d\n", FMeter(ABIST_FMETER, 33))); - // abist_clk34: AD_RPHYRPLL_DIV4_CK_ch13 + mcSHOW_DBG_MSG(("AD_RPHYRPLL_DIV4_CK_ch13 FREQ=%d\n", FMeter(ABIST_FMETER, 34))); - // enable ck_bfe_dcm_en for freqmeter measure ddrphy clock, not needed for normal use + reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ; DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); @@ -9339,19 +9117,19 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ; DRV_WriteReg32 (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11)); - // abistgen_clk44: fmem_ck_bfe_dcm_ch0 (DRAMC CHA's clock before idle mask) + before_value = FMeter(ABIST_FMETER, 44); mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch0 FREQ=%d\n", FMeter(ABIST_FMETER, 44))); - // abistgen_clk45: fmem_ck_bfe_dcm_ch1 (DRAMC CHB's clock before idle mask) + before_value = FMeter(ABIST_FMETER, 45); mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch1 FREQ=%d\n", FMeter(ABIST_FMETER, 45))); - // abistgen_clk46: fmem_ck_bfe_dcm_ch2 (DRAMC CHC's clock before idle mask) + before_value = FMeter(ABIST_FMETER, 46); mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch2 FREQ=%d\n", FMeter(ABIST_FMETER, 46))); - // abistgen_clk47: fmem_ck_bfe_dcm_ch3 (DRAMC CHC's clock before idle mask) + before_value = FMeter(ABIST_FMETER, 47); mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch3 FREQ=%d\n", FMeter(ABIST_FMETER, 47))); @@ -9363,7 +9141,7 @@ unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p) return ((before_value<<16) | after_value); #endif -#endif //! end DSIM +#endif if(vGet_Div_Mode(p) == DIV8_MODE) { diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index e73e6e5358..ff9fbdd7ec 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -17,7 +17,7 @@ #define PASS_RANGE_NA 0x7fff -#define DIE_NUM_MAX 1 //LP4 only +#define DIE_NUM_MAX 1 static U8 fgwrlevel_done = 0; #if __ETT__ @@ -134,18 +134,18 @@ U32 u4DQ_PI_RK1_backup[2]; U8 u1DVS_increase[RANK_MAX][DQS_BYTE_NUMBER]; #endif -//static U8 gu1DieNum[RANK_MAX]; // 2 rank may have different die number +//static U8 gu1DieNum[RANK_MAX]; static S32 CATrain_CmdDelay[CHANNEL_NUM][RANK_MAX]; static U32 CATrain_CsDelay[CHANNEL_NUM][RANK_MAX]; //static S8 iFirstCAPass[RANK_MAX][DIE_NUM_MAX][CATRAINING_NUM]; //static S8 iLastCAPass[RANK_MAX][DIE_NUM_MAX][CATRAINING_NUM]; -static S32 wrlevel_dqs_final_delay[RANK_MAX][DQS_BYTE_NUMBER]; // 3 is channel number +static S32 wrlevel_dqs_final_delay[RANK_MAX][DQS_BYTE_NUMBER]; //static U16 u2rx_window_sum; -U8 gFinalRXVrefDQForSpeedUp[CHANNEL_NUM][RANK_MAX][2/*ODT_onoff*/][2/*2bytes*/] = {0}; -U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX] = {{0,0,0,0},{0,0,0,0},{0,0,0,0}};//ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN +U8 gFinalRXVrefDQForSpeedUp[CHANNEL_NUM][RANK_MAX][2][2] = {0}; +U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX] = {{0,0,0,0},{0,0,0,0},{0,0,0,0}}; S16 gu2RX_DQS_Duty_Offset[DQS_BYTE_NUMBER][2]; @@ -179,25 +179,25 @@ static void vSetCalibrationResult(DRAMC_CTX_T *p, U8 ucCalType, U8 ucResult) Pointer_CalResult = &p->aru4CalResultFlag[p->channel][p->rank]; } - if (ucResult == DRAM_FAIL) // Calibration FAIL + if (ucResult == DRAM_FAIL) { - *Pointer_CalExecute |= (1<<ucCalType); // ececution done - *Pointer_CalResult |= (1<<ucCalType); // no result found + *Pointer_CalExecute |= (1<<ucCalType); + *Pointer_CalResult |= (1<<ucCalType); } - else if(ucResult == DRAM_OK) // Calibration OK + else if(ucResult == DRAM_OK) { - *Pointer_CalExecute |= (1<<ucCalType); // ececution done - *Pointer_CalResult &= (~(1<<ucCalType)); // result found + *Pointer_CalExecute |= (1<<ucCalType); + *Pointer_CalResult &= (~(1<<ucCalType)); } - else if(ucResult == DRAM_FAST_K) // FAST K + else if(ucResult == DRAM_FAST_K) { - *Pointer_CalExecute &= (~(1<<ucCalType)); // no ececution - *Pointer_CalResult &= (~(1<<ucCalType)); // result found + *Pointer_CalExecute &= (~(1<<ucCalType)); + *Pointer_CalResult &= (~(1<<ucCalType)); } - else // NO K + else { - *Pointer_CalExecute &= (~(1<<ucCalType)); // no ececution - *Pointer_CalResult |= (1<<ucCalType); // no result found + *Pointer_CalExecute &= (~(1<<ucCalType)); + *Pointer_CalResult |= (1<<ucCalType); } } @@ -230,7 +230,7 @@ void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType) { DramcEngine2Init(p, 0x55000000, 0xaa000000 |0x23, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT); - //Gating Counter Reset + DramPhyReset(p); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, MISC_STBCAL2_DQSG_CNT_RST); @@ -255,14 +255,14 @@ void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType) if ((FastK_Check_flag==1)&&(CheckResult==0)) { //mcSHOW_DBG_MSG((" [FAST K CHECK]->PASS\n")) - *Pointer_FastKResult &= (~(1<<ucCalType)); // result PASS - *Pointer_FastKExecute |= (1<<ucCalType);; // Excuted + *Pointer_FastKResult &= (~(1<<ucCalType)); + *Pointer_FastKExecute |= (1<<ucCalType);; } else if ((FastK_Check_flag==1)&&(CheckResult !=0)) { //mcSHOW_DBG_MSG((" [FAST K CHECK]->FAIL\n")) - *Pointer_FastKResult |= (1<<ucCalType); // result FAIL - *Pointer_FastKExecute |= (1<<ucCalType);; // Excuted + *Pointer_FastKResult |= (1<<ucCalType); + *Pointer_FastKExecute |= (1<<ucCalType);; } } #endif @@ -310,8 +310,8 @@ void vPrintCalibrationResult(DRAMC_CTX_T *p) { if(ucCalIdx==0) { - ucCalExecute = (U8)p->SWImpCalExecute; //for SW Impedence - ucCalResult = (U8)p->SWImpCalResult; //for SW Impedence + ucCalExecute = (U8)p->SWImpCalExecute; + ucCalResult = (U8)p->SWImpCalResult; } else { @@ -321,7 +321,7 @@ void vPrintCalibrationResult(DRAMC_CTX_T *p) #if PRINT_CALIBRATION_SUMMARY_DETAIL mcSHOW_DBG_MSG(("%s: ", szCalibStatusName[ucCalIdx])) - if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail + if(ucCalExecute==1 && ucCalResult ==1) { u1CalibrationFail =1; mcSHOW_DBG_MSG(("%s\n", "@_@FAIL@_@")) @@ -330,21 +330,21 @@ void vPrintCalibrationResult(DRAMC_CTX_T *p) while (1); #endif } - else if (ucCalExecute==1 && ucCalResult ==0) // DRAM_OK + else if (ucCalExecute==1 && ucCalResult ==0) { mcSHOW_DBG_MSG(("%s\n", "PASS")) } - else if (ucCalExecute==0 && ucCalResult ==0) // DRAM_FAST K + else if (ucCalExecute==0 && ucCalResult ==0) { mcSHOW_DBG_MSG(("%s\n", "FAST K")) } - else //DRAM_NO K + else { mcSHOW_DBG_MSG(("%s\n", "NO K")) } #else - if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail + if(ucCalExecute==1 && ucCalResult ==1) { u1CalibrationFail =1; mcSHOW_DBG_MSG(("%s: %s\n", szCalibStatusName[ucCalIdx],"@_@FAIL@_@")) @@ -431,7 +431,7 @@ void SetDeviationVref(DRAMC_CTX_T *p) for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); - //CBT + if (gSetSpecificedVref_Enable[Deviation_CA]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_CA] && p->rank==gSetSpecificedVref_Rank[Deviation_CA]) || gSetSpecificedVref_All_ChRk[Deviation_CA]==ENABLE)) { deviation_Vref = u1MR12Value[p->channel][p->rank][p->dram_fsp]& 0x3f; @@ -442,7 +442,7 @@ void SetDeviationVref(DRAMC_CTX_T *p) u1MR12Value[p->channel][p->rank][p->dram_fsp]=temp_Vref; mcSHOW_DBG_MSG2(("CBT Channel%d, Rank%d, u1MR12Value = 0x%x\n", p->channel, p->rank, u1MR12Value[p->channel][p->rank][p->dram_fsp])); } - //TX + if (gSetSpecificedVref_Enable[Deviation_TX]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_TX] && p->rank==gSetSpecificedVref_Rank[Deviation_TX]) || gSetSpecificedVref_All_ChRk[Deviation_TX]==ENABLE)) { deviation_Vref = u1MR14Value[p->channel][p->rank][p->dram_fsp]& 0x3f; @@ -454,10 +454,10 @@ void SetDeviationVref(DRAMC_CTX_T *p) mcSHOW_DBG_MSG2(("TX Channel%d, Rank%d, u1MR14Value = 0x%x\n", p->channel, p->rank, u1MR14Value[p->channel][p->rank][p->dram_fsp])); } - //RX + if (gSetSpecificedVref_Enable[Deviation_RX]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_RX] && p->rank==gSetSpecificedVref_Rank[Deviation_RX]) || gSetSpecificedVref_All_ChRk[Deviation_RX]==ENABLE)) { - //BYTE_0 + deviation_Vref = gFinalRXVrefDQ[p->channel][p->rank][BYTE_0]; DeviationAddVrefOffset(Deviation_RX, NULL, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_RX]); gFinalRXVrefDQ[p->channel][p->rank][BYTE_0] = deviation_Vref; @@ -466,7 +466,7 @@ void SetDeviationVref(DRAMC_CTX_T *p) P_Fld(deviation_Vref, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); mcSHOW_DBG_MSG2(("RX Channel%d, Rank%d, RX Vref B0 = 0x%x\n", p->channel, p->rank, gFinalRXVrefDQ[p->channel][p->rank][BYTE_0])); - //BYTE_1 + deviation_Vref = gFinalRXVrefDQ[p->channel][p->rank][BYTE_1]; DeviationAddVrefOffset(Deviation_RX, NULL, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_RX]); gFinalRXVrefDQ[p->channel][p->rank][BYTE_1] = deviation_Vref; @@ -489,20 +489,20 @@ void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p) u1MR01Value[FSP_0] = 0x26; u1MR01Value[FSP_1] = 0x56; - u1MR03Value[FSP_0] = 0x31; //Set write post-amble as 0.5 tck - u1MR03Value[FSP_1] = 0x31; //Set write post-amble as 0.5 tck + u1MR03Value[FSP_0] = 0x31; + u1MR03Value[FSP_1] = 0x31; #ifndef ENABLE_POST_PACKAGE_REPAIR - u1MR03Value[FSP_0] |= 0x4; //MR3 OP[2]=1 for PPR protection enabled - u1MR03Value[FSP_1] |= 0x4; //MR3 OP[2]=1 for PPR protection enabled + u1MR03Value[FSP_0] |= 0x4; + u1MR03Value[FSP_1] |= 0x4; #endif #if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK - u1MR03Value[FSP_1] |= 0x2; //MR3 OP[1]=1 for Set write post-amble as 1.5 tck, support after Eig_er E2 + u1MR03Value[FSP_1] |= 0x2; #endif - // @Darren, Follow samsung PPR recommend flow + u1MR04Value[RANK_0] = 0x3; u1MR04Value[RANK_1] = 0x3; - // @Darren, for LP4Y single-end mode + u1MR21Value[FSP_0] = 0x0; u1MR21Value[FSP_1] = 0x0; u1MR51Value[FSP_0] = 0x0; @@ -517,8 +517,8 @@ void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p) for (u1RankIdx = 0; u1RankIdx < RANK_MAX; u1RankIdx++) for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) { - // MR14 default value, LP4 default 0x4d, LP4X 0x5d - u1MR14Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x18; //0x18: customize for Eig_er + + u1MR14Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x18; #if FSP1_CLKCA_TERM u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x1b; #else @@ -536,96 +536,92 @@ void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p) const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6] = { { - // for EMCP - //CH-A + { 3, 1, 0, 5, 7, 4 }, #if (CHANNEL_NUM>1) - //CH-B + { 3, 2, 4, 0, 5, 1 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 3, 1, 0, 5, 7, 4 }, - //CH-D + { 3, 2, 4, 0, 5, 1 }, #endif }, { - // for DSC_2CH, HFID RESERVED - //CH-A + { 5, 2, 1, 3, 4, 0 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 2, 1, 3, 4, 5 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 4, 5 }, - //CH-D + { 0, 1, 2, 3, 4, 5 }, #endif }, { - // for MCP - //CH-A + { 5, 4, 3, 2, 1, 0 }, #if (CHANNEL_NUM>1) - //CH-B + { 4, 5, 2, 0, 3, 1 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 5, 4, 0, 2, 1, 3 }, - //CH-D + { 3, 5, 2, 4, 0, 1 }, #endif }, { - // for DSC_2CH, HFID RESERVED - //CH-A + { 3, 0, 2, 4, 1, 5 }, #if (CHANNEL_NUM>1) - //CH-B + { 4, 1, 0, 2, 3, 5 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 5, 0, 4, 3, 1, 2 }, - //CH-D + { 2, 5, 3, 0, 4, 1 }, @@ -633,30 +629,29 @@ const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6] = }, }; -//O1 DRAM->APHY + const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = { { - // for EMCP - //CH-A + { 0, 1, 2, 3, 5, 7, 6, 4, 9, 8, 13, 15, 10, 14, 11, 12 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 5, 4, 3, 7, 6, 2, 9, 8, 13, 14, 10, 15, 11, 12 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 5, 7, 6, 4, 9, 8, 13, 15, 10, 14, 11, 12 }, - //CH-D + { 0, 1, 5, 4, 3, 7, 6, 2, 9, 8, 13, 14, 10, 15, 11, 12 @@ -664,26 +659,25 @@ const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = #endif }, { - // for DSC_2CH, HFID RESERVED - //CH-A + { 0, 1, 4, 3, 2, 5, 7, 6, 9, 8, 10, 11, 14, 13, 15, 12 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 2, 4, 5, 3, 7, 6, 8, 9, 10, 11, 15, 14, 13, 12 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, - //CH-D + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 @@ -691,26 +685,25 @@ const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = #endif }, { - // for MCP - //CH-A + { 0, 1, 3, 6, 4, 7, 2, 5, 8, 9, 10, 13, 11, 12, 15, 14 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 4, 7, 3, 5, 6, 2, 9, 8, 10, 12, 11, 14, 13, 15 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 14, 11, 15, 13, 12 }, - //CH-D + { 0, 1, 4, 7, 3, 5, 6, 2, 9, 8, 10, 12, 11, 14, 13, 15 @@ -718,26 +711,25 @@ const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = #endif }, { - // for DSC_180 - //CH-A + { 9, 8, 11, 10, 14, 15, 13, 12, 0, 1, 7, 6, 4, 5, 2, 3 }, #if (CHANNEL_NUM>1) - //CH-B + { 8, 9, 11, 10, 12, 14, 13, 15, 1, 0, 5, 6, 3, 2, 7, 4 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12 }, - //CH-D + { 1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15 @@ -746,28 +738,28 @@ const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = }, }; -//CA DRAM->APHY + #if (CA_PER_BIT_DELAY_CELL || PINMUX_AUTO_TEST_PER_BIT_CA) U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] = { - //CH-A + { 2, 1, 0, 5, 3, 4 }, #if (CHANNEL_NUM>1) - //CH-B + { 3, 5, 1, 0, 2, 4 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 2, 1, 0, 5, 3, 4 }, - //CH-D + { 3, 5, 1, 0, 2, 4 }, @@ -775,28 +767,28 @@ U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] = }; #endif -//O1 DRAM->APHY + U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16] = { - //CH-A + { 0, 1, 2, 3, 5, 7, 6, 4, 9, 8, 13, 15, 10, 14, 11, 12 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 5, 4, 3, 7, 6, 2, 9, 8, 13, 14, 10, 15, 11, 12 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 5, 7, 6, 4, 9, 8, 13, 15, 10, 14, 11, 12 }, - //CH-D + { 0, 1, 5, 4, 3, 7, 6, 2, 9, 8, 13, 14, 10, 15, 11, 12 @@ -824,7 +816,7 @@ static void ImpedanceTracking_DisImpHw_Setting(DRAMC_CTX_T *p, U8 u1DisImpHw) | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS)); #if (fcFOR_CHIP_ID == fc8195) - //WCK_ODTN_UPD_DIS is used as the swith of mux for B1/CA swap here. + if (p->DRAMPinmux == PINMUX_DSC){ vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, 1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS); }else{ @@ -850,20 +842,19 @@ void vBeforeCalibration(DRAMC_CTX_T *p) DramcRxInputDelayTrackingInit_byFreq(p); #endif - DramcHWGatingOnOff(p, 0); //disable gating tracking + DramcHWGatingOnOff(p, 0); - CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); //Let CLK always on during calibration + CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); #if ENABLE_TMRRI_NEW_MODE - SetCKE2RankIndependent(p); //CKE should be controlled independently + SetCKE2RankIndependent(p); #endif - //WDBI-OFF + vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR); #ifdef IMPEDANCE_TRACKING_ENABLE - // set correct setting to control IMPCAL HW Tracking in shuffle RG - // if p->freq >= 1333, enable IMP HW tracking(SHU_DRVING1_DIS_IMPCAL_HW=0), else SHU_DRVING1_DIS_IMPCAL_HW = 1 + U8 u1DisImpHw; U32 u4TermFreq, u4WbrBackup; @@ -883,41 +874,39 @@ void vBeforeCalibration(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_SHU_ZQ_SET0, - P_Fld(0x1ff, SHU_ZQ_SET0_ZQCSCNT) | //Every refresh number to issue ZQCS commands, only for DDR3/LPDDR2/LPDDR3/LPDDR4 + P_Fld(0x1ff, SHU_ZQ_SET0_ZQCSCNT) | P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); if (p->support_channel_num == CHANNEL_SINGLE) { - //single channel, ZQCSDUAL=0, ZQCSMASK=0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0), P_Fld(0, ZQ_SET0_ZQCSDUAL) | P_Fld(0x0, ZQ_SET0_ZQCSMASK)); } else if (p->support_channel_num == CHANNEL_DUAL) { - // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin. + #ifdef ZQCS_ENABLE_LP4 - // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1 + vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) | P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) | P_Fld(0, ZQ_SET0_ZQMASK_CGAR) | P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR)); - // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0. - // ZQCSMASK setting: (Ch A, Ch B) = (1,0) or (0,1) - // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + SHIFT_TO_CHB_ADDR, 0, ZQ_SET0_ZQCSMASK); - // DRAMC CHA(CHN0):ZQ_SET0_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQ_SET0_ZQCS_MASK_SEL=0. + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL); #endif } #if (CHANNEL_NUM > 2) else if (p->support_channel_num == CHANNEL_FOURTH) { - // HW ZQ command is channel interleaving since 2 channel share the same ZQ pin. + #ifdef ZQCS_ENABLE_LP4 - // dual channel, ZQCSDUAL =1, and CHA ZQCSMASK=0, CHB ZQCSMASK=1 + vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) | P_Fld(0, ZQ_SET0_ZQCALL) | @@ -926,9 +915,7 @@ void vBeforeCalibration(DRAMC_CTX_T *p) P_Fld(0, ZQ_SET0_ZQMASK_CGAR) | P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR)); - // DRAMC CHA(CHN0):ZQCSMASK=1, DRAMC CHB(CHN1):ZQCSMASK=0. - // ZQCSMASK setting: (Ch A, Ch C) = (1,0) or (0,1), (Ch B, Ch D) = (1,0) or (0,1) - // if CHA.ZQCSMASK=1, and then set CHA.ZQCALDISB=1 first, else set CHB.ZQCALDISB=1 first + #if fcFOR_CHIP_ID == fcPetrus vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_B << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); @@ -941,13 +928,13 @@ void vBeforeCalibration(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_D << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); #endif - // DRAMC CHA(CHN0):ZQ_SET0_ZQCS_MASK_SEL=0, DRAMC CHB(CHN1):ZQ_SET0_ZQCS_MASK_SEL=0. + vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL); #endif } #endif - // Set 0 to be able to adjust TX DQS/DQ/DQM PI during calibration, for new cross rank mode. + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 0, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0); if (!isLP4_DSC) vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1); @@ -957,15 +944,14 @@ void vBeforeCalibration(DRAMC_CTX_T *p) #if ENABLE_PA_IMPRO_FOR_TX_AUTOK vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0x0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK); #endif - // ARPI_DQ SW mode mux, TX DQ use 1: PHY Reg 0: DRAMC Reg + #if ENABLE_PA_IMPRO_FOR_TX_TRACKING vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING); #endif - //Darren-vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW); @Darren, remove to LP4_UpdateInitialSettings - //Disable HW MR18/19 to prevent fail case when doing SW MR18/19 in DQSOSCAuto + vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); - vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS); //disable refresh + vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS); vIO32WriteFldAlign_All(DRAMC_REG_SHU_MATYPE, u1MaType, SHU_MATYPE_MATYPE); @@ -983,10 +969,10 @@ void vAfterCalibration(DRAMC_CTX_T *p) EnableDRAMModeRegWriteDBIAfterCalibration(p); #endif - SetMr13VrcgToNormalOperation(p);// Set VRCG{MR13[3]} to 0 + SetMr13VrcgToNormalOperation(p); - CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL); //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) + CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL); vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, p->support_rank_num, DUMMY_RD_RANK_NUM); @@ -1002,24 +988,24 @@ void vAfterCalibration(DRAMC_CTX_T *p) } #endif - //@Darren, KaiHsin sync MP setting + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN); - /* TESTAGENT2 for @Chris sync MP settings*/ - vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL); // Rank selection is controlled by Test Agent - vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A2, 0x20, TEST2_A2_TEST2_OFF); //@Chris, MP setting for runtime TA2 Length - //@Darren, CW sync MP setting + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL); + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A2, 0x20, TEST2_A2_TEST2_OFF); + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); - //@Darren, HJ sync MP setting + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT); } static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - #if 0//O1_SETTING_RESTORE + #if 0 const U32 u4O1RegBackupAddress[] = { (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), @@ -1035,16 +1021,14 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) if (u1OnOff == ON) { - // These RG will be restored when leaving each calibration flow - // ------------------------------------------------------- - // VREF_UNTERM_EN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF), 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); if (!isLP4_DSC) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF), 1, SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA); - u1VrefSel = 0x37;//unterm LP4 + u1VrefSel = 0x37; vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | @@ -1063,9 +1047,7 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) } } - // DQ_O1 enable/release - // ------------------------------------------------------- - // Actually this RG naming is O1_EN in APHY + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0); if (!isLP4_DSC) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1); @@ -1073,7 +1055,7 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), u1OnOff, CA_CMD6_RG_RX_ARCMD_O1_SEL); - // DQ_IN_BUFF_EN + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) | P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0)); @@ -1090,14 +1072,14 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) P_Fld(u1OnOff, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN)); } - // DQ_BUFF_EN_SEL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), u1OnOff, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0); if (!isLP4_DSC) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), u1OnOff, B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1); else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), u1OnOff, CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA); - // Gating always ON + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL),(u1OnOff << 1) | u1OnOff, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); mcDELAY_US(1); @@ -1127,15 +1109,7 @@ static u8 get_autok_sweep_max_cnt(u8 lenpi, u8 respi) return lenpi > max? max: lenpi; } -/* - * cbt_wlev_train_autok -- ca/cs/dqs autok - * @mode: ca or cs select, 0 for ca, 1 for cs - * @initpi: init pi select - * @lenpi: sweep how many pi step, 0 ~ 63 - * @respi: sweep pi resolution, 00 for 1 pi, 01 for 2 pi, 10 for 4 pi, 11 for 8 pi - * - * autok result store to @cmp0 and @cmp1. - */ + static int cbt_wlev_train_autok(DRAMC_CTX_T *p, ATUOK_MODE_T autok_mode, u8 initpi, u8 lenpi, u8 respi, @@ -1146,10 +1120,7 @@ static int cbt_wlev_train_autok(DRAMC_CTX_T *p, ATUOK_MODE_T autok_mode, u8 sweep_max_cnt, i; u32 cnt, ready; - /* - * it's takes 3.6us for one step. - * max times is 64, about 3.6 * 64 = 231us - */ + cnt = TIME_OUT_CNT * 3; switch (autok_mode){ @@ -1292,11 +1263,7 @@ static int cbt_wlev_train_autok(DRAMC_CTX_T *p, ATUOK_MODE_T autok_mode, return 0; } #endif -/* - * set_cbt_intv -- set interval related rg according to speed. - * - * TODO, move these to ACTimingTable ????!!! - */ + struct cbt_intv { DRAM_PLL_FREQ_SEL_T freq_sel; @@ -1342,94 +1309,94 @@ static void set_cbt_wlev_intv_lp4(DRAMC_CTX_T *p) { LP4_DDR4266, DIV8_MODE, - 17, /*tcmdo1lat*/ - 14, /* catrain_intv */ - 19, /* new_cbt_pat_intv */ - 19, /* wlev_dqspat_lat */ + 17, + 14, + 19, + 19, }, { LP4_DDR3733, DIV8_MODE, - 16, /*tcmdo1lat*/ - 13, /* catrain_intv */ - 18, /* new_cbt_pat_intv */ - 18, /* wlev_dqspat_lat */ + 16, + 13, + 18, + 18, }, { LP4_DDR3200, DIV8_MODE, - 14, /*tcmdo1lat*/ - 11, /* catrain_intv */ - 16, /* new_cbt_pat_intv */ - 16, /* wlev_dqspat_lat */ + 14, + 11, + 16, + 16, }, { LP4_DDR2667, DIV8_MODE, - 13, /*tcmdo1lat*/ - 10, /* catrain_intv */ - 15, /* new_cbt_pat_intv */ - 15, /* wlev_dqspat_lat */ + 13, + 10, + 15, + 15, }, { LP4_DDR2400, DIV8_MODE, - 12, /*tcmdo1lat*/ - 9, /* catrain_intv */ - 14, /* new_cbt_pat_intv */ - 14, /* wlev_dqspat_lat */ + 12, + 9, + 14, + 14, }, { LP4_DDR1866, DIV8_MODE, - 11, /*tcmdo1lat*/ - 9, /* catrain_intv */ - 13, /* new_cbt_pat_intv */ - 13, /* wlev_dqspat_lat */ + 11, + 9, + 13, + 13, }, { LP4_DDR1600, DIV8_MODE, - 10, /*tcmdo1lat*/ - 8, /* catrain_intv */ - 12, /* new_cbt_pat_intv */ - 12, /* wlev_dqspat_lat */ + 10, + 8, + 12, + 12, }, { LP4_DDR1200, DIV8_MODE, - 9, /*tcmdo1lat*/ - 8, /* catrain_intv */ - 11, /* new_cbt_pat_intv */ - 11, /* wlev_dqspat_lat */ + 9, + 8, + 11, + 11, }, { LP4_DDR800, DIV8_MODE, - 8, /*tcmdo1lat*/ - 8, /* catrain_intv */ - 10, /* new_cbt_pat_intv */ - 10, /* wlev_dqspat_lat */ + 8, + 8, + 10, + 10, }, { LP4_DDR1600, DIV4_MODE, - 16, /*tcmdo1lat*/ - 13, /* catrain_intv */ - 16, /* new_cbt_pat_intv */ - 16, /* wlev_dqspat_lat */ + 16, + 13, + 16, + 16, }, { LP4_DDR1200, DIV4_MODE, - 14, /*tcmdo1lat*/ - 13, /* catrain_intv */ - 14, /* new_cbt_pat_intv */ - 14, /* wlev_dqspat_lat */ + 14, + 13, + 14, + 14, }, { LP4_DDR800, DIV4_MODE, - 12, /*tcmdo1lat*/ - 13, /* catrain_intv */ - 12, /* new_cbt_pat_intv */ - 12, /* wlev_dqspat_lat */ + 12, + 13, + 12, + 12, }, { LP4_DDR400, DIV4_MODE, - 12, /*tcmdo1lat*/ - 13, /* catrain_intv */ - 12, /* new_cbt_pat_intv */ - 12, /* wlev_dqspat_lat */ + 12, + 13, + 12, + 12, }, }; @@ -1451,21 +1418,21 @@ static void set_cbt_wlev_intv(DRAMC_CTX_T *p) } #if SIMUILATION_CBT == 1 -/* To process LPDDR5 Pinmux */ + struct cbt_pinmux { - u8 dram_dq_b0; /* EMI_B0 is mapped to which DRAMC byte ?? */ + u8 dram_dq_b0; u8 dram_dq_b1; - u8 dram_dmi_b0; /* EMI_DMI0 is mapped to which DRAMC DMI ?? */ + u8 dram_dmi_b0; u8 dram_dmi_b1; - u8 dram_dq7_b0; /* EMI_DQ7 is mapped to which DRAMC DQ ?? */ - u8 dram_dq7_b1; /* EMI_DQ15 is mapped to which DRAMC DQ ?? */ + u8 dram_dq7_b0; + u8 dram_dq7_b1; }; -/* Per-project definition */ + static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { { - /* CHA */ + .dram_dq_b0 = 0, .dram_dq_b1 = 1, @@ -1474,7 +1441,7 @@ static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { }, #if (CHANNEL_NUM>1) { - /* CHB */ + .dram_dq_b0 = 0, .dram_dq_b1 = 1, @@ -1484,7 +1451,7 @@ static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { #endif #if (CHANNEL_NUM>2) { - /* CHC */ + .dram_dq_b0 = 0, .dram_dq_b1 = 1, @@ -1492,7 +1459,7 @@ static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { .dram_dmi_b1 = 1, }, { - /* CHD */ + .dram_dq_b0 = 0, .dram_dq_b1 = 1, @@ -1504,7 +1471,7 @@ static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { #if 0 static struct cbt_pinmux lp5_cp[CHANNEL_NUM] = { { - /* CHA */ + .dram_dq_b0 = 1, .dram_dq_b1 = 0, @@ -1516,7 +1483,7 @@ static struct cbt_pinmux lp5_cp[CHANNEL_NUM] = { }, #if (CHANNEL_NUM > 1) { - /* CHB */ + .dram_dq_b0 = 1, .dram_dq_b1 = 0, @@ -1538,7 +1505,7 @@ static void vSetDramMRCBTOnOff(DRAMC_CTX_T *p, U8 u1OnOff, U8 operating_fsp) { if (u1OnOff) { - // op[7] = !(p->dram_fsp), dram will switch to another FSP_OP automatically + if (operating_fsp) { MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | @@ -1557,15 +1524,14 @@ static void vSetDramMRCBTOnOff(DRAMC_CTX_T *p, U8 u1OnOff, U8 operating_fsp) if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) | - P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1 + P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); } } else { if (operating_fsp) { - // !! Remain MR13_FSP_OP = 0, because of system is at low frequency now. - // @Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal) + MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | P_Fld(1, MR13_FSP_WR) | P_Fld(0, MR13_CBT), @@ -1596,20 +1562,19 @@ static void CBTEntryLP4(DRAMC_CTX_T *p, U8 operating_fsp, U16 operation_frequenc CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); - // yr: CA train old mode and CS traing need to check MRSRK at this point + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); - //Step 0: MRW MR13 OP[0]=1 to enable CBT + vSetDramMRCBTOnOff(p, ENABLE, operating_fsp); - //Step 0.1: before CKE low, Let DQS=0 by R_DMwrite_level_en=1, spec: DQS_t has to retain a low level during tDQSCKE period + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) { vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); - //TODO, pinmux - //force byte0 tx + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0x1, CBT_WLEV_CTRL0_DQSOEAOEN); @@ -1619,34 +1584,33 @@ static void CBTEntryLP4(DRAMC_CTX_T *p, U8 operating_fsp, U16 operation_frequenc mcDELAY_US(1); - //Step 1.0: let CKE go low + CKEFixOnOff(p, p->rank, CKE_FIXOFF, TO_ONE_CHANNEL); - // Adjust u1MR13Value + (operating_fsp == FSP_1)? DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE): DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); - // Step 1.1 : let IO to O1 path valid + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) { - // Let R_DMFIXDQIEN1=1 (byte1), 0xd8[13] ==> Note: Do not enable again. - //Currently set in O1PathOnOff + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0x3, PADCTRL_FIXDQIEN); - // Let DDRPHY RG_RX_ARDQ_SMT_EN_B1=1 (byte1) + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); O1PathOnOff(p, ON); } if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) { - // let IO to O1 path valid by DDRPHY RG_RX_ARDQ_SMT_EN_B0=1 + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); O1PathOnOff(p, ON); } - // Wait tCAENT + mcDELAY_US(1); } @@ -1656,61 +1620,48 @@ static void CBTExitLP4(DRAMC_CTX_T *p, U8 operating_fsp, U8 operation_frequency) if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) { - //Step 1: CKE go high (Release R_DMCKEFIXOFF, R_DMCKEFIXON=1) + CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); - //Step 2:wait tCATX, wait tFC + mcDELAY_US(1); - //Step 3: MRW to command bus training exit (MR13 OP[0]=0 to disable CBT) + vSetDramMRCBTOnOff(p, DISABLE, operating_fsp); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); } - //Step 4: - //Disable O1 path output + if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) { - //Let DDRPHY RG_RX_ARDQ_SMT_EN_B1=0 + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 0, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); O1PathOnOff(p, OFF); - //Let FIXDQIEN1=0 ==> Note: Do not enable again. - //Moved into O1PathOnOff + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0, PADCTRL_FIXDQIEN); } if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) { - //Let DDRPHY RG_RX_ARDQ_SMT_EN_B0=0 + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 0, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); O1PathOnOff(p, OFF); - //Disable Byte mode CBT enable bit + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) | - P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1 + P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); } - // Wait tCAENT + mcDELAY_US(1); } -/* - * get_mck_ck_ratio -- get ratio of mck:ck - * - * TODO, remove later, get the ratio from dram ctx dfs table!!!! - * - * - * return 1 means 1:1 - * return 0 means 1:2 - */ + static u8 get_mck_ck_ratio(DRAMC_CTX_T *p) { - /* - * as per DE's comments, LP5 mck:ck has only 1:1 and 1:2. - * read SHU_LP5_CMD.LP5_CMD1TO2EN to decide which one. - */ + u32 ratio; //u32 ui_max; @@ -1726,17 +1677,7 @@ static u8 get_cbtui_adjustable_maxvalue(DRAMC_CTX_T *p) { u8 ratio; - /* - * MCK:CK=1:1, - * ther are only 0~1 for ui adjust, if ui value is larger than 1, adjust MCK. - * - * MCK:CK=1:2, - * ther are only 0~3 for ui adjust, if ui value is larger than 3, adjust MCK. - * - * MCK:CK=1:4, (for LP4) - * ther are only 0~7 for ui adjust, if ui value is larger than 7, adjust MCK. - * - */ + ratio = (vGet_Div_Mode(p) == DIV4_MODE) ? 3 : 7; return ratio; @@ -1781,8 +1722,7 @@ static inline void put_ca_ui(DRAMC_CTX_T *p, u32 ca_ui) vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), dly); - // Note: CKE UI must sync CA UI (CA and CKE delay circuit are same) @Lin-Yi - // To avoid tXP timing margin issue + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), ca_ui & 0xF, SHU_SELPH_CA5_DLY_CKE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), ca_ui & 0xF, SHU_SELPH_CA6_DLY_CKE1); } @@ -1884,13 +1824,7 @@ static inline void put_cs_ui(DRAMC_CTX_T *p, u32 cs_ui) cs_ui, SHU_SELPH_CA5_DLY_CS); } -//void LP5_ShiftCSUI(DRAMC_CTX_T *p, S8 iShiftUI) -//{ -// REG_TRANSFER_T TransferUIRegs = {DRAMC_REG_SHU_SELPH_CA5, SHU_SELPH_CA5_DLY_CS}; -// REG_TRANSFER_T TransferMCKRegs = {DRAMC_REG_SHU_SELPH_CA1, SHU_SELPH_CA1_TXDLY_CS}; -// -// ExecuteMoveDramCDelay(p, TransferUIRegs[i], TransferMCKRegs[i], iShiftUI); -//} + static S16 adjust_cs_ui(DRAMC_CTX_T *p, u32 cs_mck, u32 cs_ui, S16 pi_dly) { @@ -1912,10 +1846,10 @@ static S16 adjust_cs_ui(DRAMC_CTX_T *p, u32 cs_mck, u32 cs_ui, S16 pi_dly) ratio = get_mck_ck_ratio(p); if (ratio) { - /* 1:1 */ + cs_bit_mask = 1; } else { - /* 1:2 */ + cs_bit_mask = 3; } @@ -1990,7 +1924,7 @@ void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM | P_Fld(0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1)); } } - else//(CmdOeDisChannelNUM ==CMDOE_DIS_TO_ONE_CHANNEL) + else { if (!isLP4_DSC) { @@ -2012,7 +1946,7 @@ void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay) { if (iDelay < 0) - { /* Set CLK delay */ + { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) | @@ -2030,7 +1964,7 @@ void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay) } */ else - { /* Set CA output delay */ + { // DramcCmdUIDelaySetting(p, 0); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), @@ -2041,13 +1975,7 @@ void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay) } #if CBT_AUTO_K_SUPPORT -/* - * cbt_catrain_autok -- ca autok - * @initpi: init pi select - * @steps: sweep how many pi step, 1 ~ 64 - * @respi: step resolution, 0,1,2,3. that means 1, 2, 4, 8 pis - * - */ + #if 0 static int cbt_catrain_autok(DRAMC_CTX_T *p, u8 initpi, u8 steps, u8 respi, @@ -2081,17 +2009,7 @@ static int cbt_cstrain_autok(DRAMC_CTX_T *p, initpi, lenpi, respi, cmp0, cmp1, 1); } -/* - * cbt_catrain_autok_next_window -- find next zero window - * @bitmap: window map - * @start_pos: start position to find - * @initpi: init pi select - * @steps: sweep how many pi step, 1 ~ 64 - * @respi: step resolution, 0, 1, 2, 3 - * @pwin: window boundary to store - * - * return 1 if found window, 0 otherwise. - */ + static int cbt_catrain_autok_next_window(DRAMC_CTX_T *p, u32 *bitmap, u8 start_pos, u8 initpi, u8 steps, u8 respi, @@ -2139,9 +2057,7 @@ static void cbt_autok_maxwindow(DRAMC_CTX_T *p, if (!res) { - /* - * autok not find pass window - */ + mcSHOW_DBG_MSG2(("no window @pi [%d, %d]\n", uiDelay + start_pos, uiDelay + pi_step - 1)); @@ -2149,8 +2065,8 @@ static void cbt_autok_maxwindow(DRAMC_CTX_T *p, if ((*iFirstPass != PASS_RANGE_NA) && (*iLastPass == PASS_RANGE_NA)) { - /* window has left boundary */ - if ((uiDelay - *iFirstPass) < 5) /* prevent glitch */ + + if ((uiDelay - *iFirstPass) < 5) { *iFirstPass = PASS_RANGE_NA; } @@ -2160,19 +2076,17 @@ static void cbt_autok_maxwindow(DRAMC_CTX_T *p, } } - /* ca no pass window yet, break while-1 loop */ + break; } else { - /* - * autok find pass window - */ + mcSHOW_DBG_MSG2(("find pi pass window [%d, %d] in [%d, %d]\n", win.first_pass, win.last_pass, uiDelay, uiDelay + pi_step - 1)); - /* adjust start_pos to find next pass window */ + start_pos = win.last_pass - uiDelay + 1; if (*iFirstPass == PASS_RANGE_NA) @@ -2181,26 +2095,26 @@ static void cbt_autok_maxwindow(DRAMC_CTX_T *p, } else if (*iLastPass != PASS_RANGE_NA) { - /* have pass window yet */ + if (*iLastPass + (1 << respi) >= win.first_pass) { *iLastPass = win.last_pass; } else { - /* wind is NOT continuous and larger size */ + if (win.last_pass - win.first_pass >= *iLastPass - *iFirstPass) { *iFirstPass = win.first_pass; *iLastPass = win.last_pass; } } - continue; /* find next window */ + continue; } if (*iLastPass == PASS_RANGE_NA) { - if ((win.last_pass - *iFirstPass) < 5) /* prevent glitch */ + if ((win.last_pass - *iFirstPass) < 5) { *iFirstPass = PASS_RANGE_NA; continue; @@ -2209,7 +2123,7 @@ static void cbt_autok_maxwindow(DRAMC_CTX_T *p, *iLastPass = win.last_pass; } } - } /* while (1) */ + } } #endif #endif @@ -2239,7 +2153,7 @@ static void CBTAdjustCS(DRAMC_CTX_T *p, int autok) } #endif - // if dual rank, use average position of both rank + if(backup_rank == RANK_1) { iCSFinalDelay = (CATrain_CsDelay[p->channel][RANK_0] + CATrain_CsDelay[p->channel][RANK_1]) >> 1; @@ -2249,8 +2163,7 @@ static void CBTAdjustCS(DRAMC_CTX_T *p, int autok) iCSFinalDelay = CATrain_CsDelay[p->channel][p->rank]; } - //Set CS output delay after training - /* p->rank = RANK_0, save to Reg Rank0 and Rank1, p->rank = RANK_1, save to Reg Rank1 */ + for (ii = RANK_0; ii <= backup_rank; ii++) { vSetRank(p, ii); @@ -2269,7 +2182,7 @@ static void CBTAdjustCS(DRAMC_CTX_T *p, int autok) vSetRank(p, backup_rank); - //Also for Dump_Reg + //mcSHOW_DBG_MSG(("CS delay=%d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass)); //mcDUMP_REG_MSG(("CS delay=%d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass)); } @@ -2290,7 +2203,7 @@ static void CATrainingSetPerBitDelayCell(DRAMC_CTX_T *p, S16 *iCAFinalCenter, U8 iCA_PerBit_DelayLine[uiLPDDR_CA_Mapping[u1CA]] = iCAFinalCenter[u1CA]; } - // Set CA perbit delay line calibration results + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY0), P_Fld(iCA_PerBit_DelayLine[0], SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) | P_Fld(iCA_PerBit_DelayLine[1], SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) | @@ -2303,13 +2216,13 @@ static void CATrainingSetPerBitDelayCell(DRAMC_CTX_T *p, S16 *iCAFinalCenter, U8 P_Fld(iCA_PerBit_DelayLine[6], SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) | P_Fld(iCA_PerBit_DelayLine[7], SHU_R0_CA_TXDLY1_TX_ARCA7_DLY)); } -#endif// end of CA_PER_BIT_DELAY_CELL +#endif static void CBTSetCACLKResult(DRAMC_CTX_T *p, U32 u4MCK, U32 u4UI, U8 ca_pin_num) { S8 iFinalCACLK; U8 backup_rank, rank_i, uiCA; - S16 iCAFinalCenter[CATRAINING_NUM]={0}; //for CA_PER_BIT + S16 iCAFinalCenter[CATRAINING_NUM]={0}; #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) if (p->femmc_Ready == 1) @@ -2392,11 +2305,11 @@ static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 ope fld = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0; - //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_WRITE_LEV), ((u1VrefRange&0x1) <<6) | (u1VrefLevel & 0x3f), WRITE_LEV_DMVREFCA); //MR12, bit[25:20]=OP[5:0] bit 26=OP[6] + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_WRITE_LEV), ((u1VrefRange&0x1) <<6) | (u1VrefLevel & 0x3f), WRITE_LEV_DMVREFCA); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), - u1VrefValue_pinmux, fld); //MR12, bit[25:20]=OP[5:0] bit 26=OP[6] + u1VrefValue_pinmux, fld); + - //DQS_SEL=1, DQS_B1_G=1, Toggle R_DMDQS_WLEV (1 to 0) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), (0x1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), 0xa, CBT_WLEV_CTRL3_DQSBX_G); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG); @@ -2418,7 +2331,7 @@ static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 ope DramcModeRegWriteByRank(p, p->rank, 12, u4DbgValue); } - //wait tVREF_LONG + mcDELAY_US(1); } @@ -2428,15 +2341,15 @@ static void CBTEntryLP45(DRAMC_CTX_T *p, U8 u1FSP, U16 u2Freq) { if(p->dram_fsp == FSP_1) { - //@Darren, Risk here!!!VDDQ term region between 300mv and 360mv. (CaVref_0x20 is 204mv) + CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL); cbt_switch_freq(p, CBT_LOW_FREQ); CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL); } -#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION //@Darren, debugging for DFS stress +#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION CmdBusTrainingLP4YWA(p, DISABLE); #endif - CBTEntryLP4(p, u1FSP, u2Freq); // @Darren, after CBT entry will not any CMD output (CKE low) + CBTEntryLP4(p, u1FSP, u2Freq); if(p->dram_fsp == FSP_1) { cbt_switch_freq(p, CBT_HIGH_FREQ); @@ -2446,17 +2359,13 @@ static void CBTEntryLP45(DRAMC_CTX_T *p, U8 u1FSP, U16 u2Freq) static void CBTExitLP45(DRAMC_CTX_T *p, U8 u1FSP, U8 u2Freq, U8 stateFlag) { - /* by yirong.wang - * if stateFlag == OUT_CBT, it means we finished CBT, exit CBT - * if stateFlag == IN_CBT, it means we are trying to setup vref by MRW - * IN_CBT case, only for LP5 mode 1 and LP4 byte mode - */ + { if (stateFlag == OUT_CBT || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) { (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL; CBTExitLP4(p, u1FSP, u2Freq); -#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION //@Darren, debugging for DFS stress +#if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION CmdBusTrainingLP4YWA(p, ENABLE); #endif } @@ -2468,7 +2377,7 @@ static void CBTSetVrefLP45(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 u1 { if (stateFlag == IN_CBT && p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) { - // BYTE MODE: We are not in CBT now, set Vref & enter CBT + (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL; CBTExitLP4(p, u1FSP, u2Freq); @@ -2494,13 +2403,13 @@ static void CBTScanPI(DRAMC_CTX_T *p, S16 *s2PIStart, S16 *s2PIEnd, S16 *s2PISte p2u = get_ca_pi_per_ui(p); if (is_discrete_lpddr4()) - *s2PIStart = -16; /* improve high frequency CA left boundary */ + *s2PIStart = -16; else *s2PIStart = 0; *s2PIEnd = p2u * 3 - 1; { - /* LPDDR4 */ + #if !CBT_MOVE_CA_INSTEAD_OF_CLK if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) { @@ -2579,12 +2488,12 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) (DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)), (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)), }; CBTScanPI(p, &pi_start, &pi_end, &pi_step, autok); @@ -2636,10 +2545,10 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) mcSHOW_DBG_MSG(("[CmdBusTrainingLP45] new_cbt_mode=%d, autok=%d\n", p->new_cbt_mode, autok)); mcSHOW_DBG_MSG2(("pi_start=%d, pi_end=%d, pi_step=%d\n", pi_start, pi_end, pi_step)); - //Back up dramC register + DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); - //default set FAIL + if (u1CBTEyeScanEnable == DISABLE) { vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAIL); @@ -2663,41 +2572,32 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) } #endif - /* read ca ui and mck */ + ca_ui_default = ca_ui = get_ca_ui(p); ca_mck = get_ca_mck(p); ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); - vAutoRefreshSwitch(p, DISABLE); //When doing CA training, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); + - /* - * TOOD - * - * here just pass simulation, - * remove after ACTiming OK(ACTiming Table includes CATRAIN_INTV) - */ //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), // P_Fld(0x1F, CBT_WLEV_CTRL1_CATRAIN_INTV)); set_cbt_wlev_intv(p); - /* - * tx_rank_sel is selected by SW - * Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed. - */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), p->rank, TX_SET0_TXRANK); - /* TXRANKFIX should be write after TXRANK or the rank will be fix at rank 1 */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); - //SW variable initialization + uiCAWinSumMax = 0; operating_fsp = p->dram_fsp; operation_frequency = p->frequency; - // free-run dramc/ddrphy clk (DCMEN2=0, MIOCKCTRLOFF=1, PHYCLKDYNGEN=0, COMBCLKCTRL=0) - // free-run dram clk(APHYCKCG_FIXOFF =1, TCKFIXON=1) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), P_Fld(0, DRAMC_PD_CTRL_DCMEN2) | P_Fld(1, DRAMC_PD_CTRL_MIOCKCTRLOFF) | @@ -2706,14 +2606,14 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) P_Fld(1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) | P_Fld(1, DRAMC_PD_CTRL_TCKFIXON)); - //Note : Assume that there is a default CS value that can apply for CA. + CBTEntryLP45(p, operating_fsp, operation_frequency); #if PINMUX_AUTO_TEST_PER_BIT_CA CheckCADelayCell(p); #endif - //Step 3: set vref range and step by ddr type + #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && (BYPASS_VREF_CAL || BYPASS_CBT)) if (p->femmc_Ready == 1) @@ -2735,18 +2635,17 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) gFinalCBTVrefCA[p->channel][p->rank] = u1FinalVref; #endif - //Set Vref after training - // BYTE MODE: Set Vref & enter CBT + CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, IN_CBT); #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) #if CBT_MOVE_CA_INSTEAD_OF_CLK - // scan UI from 0, not from the UI we used to enter CBT + DramcCmdUIDelaySetting(p, 0); ca_ui = get_ca_ui(p); #endif #endif put_ca_ui(p, ca_ui); - //Set CA_PI_Delay after training + if (u1CBTEyeScanEnable == DISABLE) { CBTSetCACLKResult(p, ca_mck, ca_ui, ca_pin_num); @@ -2769,15 +2668,14 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) gEyeScan_CaliDelay[0] = CATrain_CmdDelay[p->channel][p->rank] -pi_start; #endif - /* ------------- CS and CLK ---------- */ - /* delay ca 1UI before K CS */ + if (u1CBTEyeScanEnable == DISABLE) { CBTAdjustCS(p, autok); } -//------- Going to exit Command bus training(CBT) mode.------------- + CBTExitLP45(p, operating_fsp, operation_frequency, OUT_CBT); CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, OUT_CBT); @@ -2798,31 +2696,24 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) mcSHOW_DBG_MSG4(("\n[CmdBusTrainingLP45] Done\n")); - //tx_rank_sel is selected by HW //Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK or the rank will be fix at rank 1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); + - //Restore setting registers DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); return DRAM_OK; } #endif /* SIMUILATION_CBT */ -//------------------------------------------------------------------------- -/** DramcWriteLeveling - * start Write Leveling Calibration. - * @param p Pointer of context created by DramcCtxCreate. - * @param apply (U8): 0 don't apply the register we set 1 apply the register we set ,default don't apply. - * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL - */ -//------------------------------------------------------------------------- -#define WRITE_LEVELING_MOVD_DQS 1//UI + +#define WRITE_LEVELING_MOVD_DQS 1 U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p) { { - //in LP4 1:8 mode, 8 small UI = 1 large UI + if (vGet_Div_Mode(p) == DIV4_MODE) { return MCK_TO_4UI_SHIFT; @@ -2900,9 +2791,9 @@ static void _LoopAryToDelay(DRAMC_CTX_T *p, static void LP4_ShiftDQSUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) { - // DQS / DQS_OEN - REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS0}, // Byte0 - {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS1}}; // Byte1 + + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS0}, + {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS1}}; REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS0}, {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS1}}; @@ -2913,9 +2804,9 @@ static void LP4_ShiftDQSUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) { - // DQS / DQS_OEN - REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS0}, // Byte0 - {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS1}}; // Byte1 + + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS0}, + {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS1}}; REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS0}, {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS1}}; @@ -2926,11 +2817,11 @@ void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) static void ShiftDQUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) { - // Shift DQ / DQM / DQ_OEN / DQM_OEN - REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM0}, // Byte0 - {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM1}, // Byte1 - {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ0}, // Byte0 - {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ1}}; // Byte1 + + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM0}, + {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM1}, + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ0}, + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ1}}; REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM0}, {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM1}, {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ0}, @@ -2946,7 +2837,7 @@ static void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) U8 backup_rank, rk_i; backup_rank = u1GetRank(p); - // Shift DQ / DQM / DQ_OEN / DQM_OEN + for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++) { vSetRank(p, rk_i); @@ -2957,10 +2848,10 @@ static void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) static void ShiftDQ_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) { - REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM0}, // Byte0 - {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM1}, // Byte1 - {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ0}, // Byte0 - {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ1}}; // Byte1 + REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM0}, + {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM1}, + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ0}, + {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ1}}; REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0}, {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1}, {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0}, @@ -2976,7 +2867,7 @@ void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) U8 backup_rank, rk_i; backup_rank = u1GetRank(p); - // Shift DQ / DQM / DQ_OEN / DQM_OEN + for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++) { vSetRank(p, rk_i); @@ -3007,14 +2898,14 @@ U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p) return FALSE; } -//static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) + static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) { - // MR2 OP[7] to enable/disable write leveling + if (u1OnOff) - u1MR02Value[p->dram_fsp] |= 0x80; // OP[7] WR LEV =1 + u1MR02Value[p->dram_fsp] |= 0x80; else - u1MR02Value[p->dram_fsp] &= 0x7f; // OP[7] WR LEV =0 + u1MR02Value[p->dram_fsp] &= 0x7f; DramcModeRegWriteByRank(p, p->rank, 2, u1MR02Value[p->dram_fsp]); } @@ -3023,21 +2914,18 @@ U8 u1IsPhaseMode(DRAMC_CTX_T *p) { if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) || (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)) return TRUE; - else // DDR800_CLOSE_LOOP and NORMAL_CLOSE_LOOP + else return FALSE; } #if 0 static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg) { -// U32 u4TimeCnt = TIME_OUT_CNT; - // @Darren, Rx HW AutoK simulation time - // RX delay all range -511~255, step:4,DDR800semi + TEST2_OFF=0x100 => 8661us/per rank - // RX delay all range -327~252, step:8,DDR800semi, TEST2_OFF=0x100 => 3276us/per rank + U32 u4TimeCnt = DDR_HW_AUTOK_POLLING_CNT; DRAM_STATUS_T u4RespFlag = 0; - vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); // Init EN status + vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld); do { @@ -3046,7 +2934,7 @@ static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerR mcDELAY_US(1); }while ((u4RespFlag == 0) && (u4TimeCnt > 0)); - if (u4TimeCnt == 0)//time out + if (u4TimeCnt == 0) { mcSHOW_ERR_MSG(("[DramcTriggerAndWait] Wait 0x%x respond fail (time out)\n", RepondsReg.u4Addr)); return DRAM_FAIL; @@ -3057,19 +2945,19 @@ static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerR static DRAM_STATUS_T DramcTriggerAndWait_For_RX_AutoK_WorkAround(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg, U16 u16DelayStep) { - // Set step = 0 to let autoK non-stop + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0), 0, MISC_RX_AUTOK_CFG0_RX_CAL_STEP); - vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); // Init EN status + vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld); - // Trigger and then stop immediately + vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); - // PHY reset + DramPhyReset(p); - // Restor the original step + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0), u16DelayStep, MISC_RX_AUTOK_CFG0_RX_CAL_STEP); return DramcTriggerAndWait(p, TriggerReg, RepondsReg); @@ -3086,7 +2974,7 @@ static void WriteLevelingScanRange_PI(DRAMC_CTX_T *p, S32 *ps4DlyBegin, S32 *ps4 if (stDelayBase == PI_BASED) { - // Giving PI scan range + s4DlyBegin = WRITE_LEVELING_MOVD_DQS * 32 - MAX_CLK_PI_DELAY - 1; s4DlyEnd = s4DlyBegin + 64 - 1; @@ -3106,14 +2994,14 @@ static void WriteLevelingScanRange_PI(DRAMC_CTX_T *p, S32 *ps4DlyBegin, S32 *ps4 PI_bound = 64; } } - else // stDelayBase == DLY_BASED + else { - // Giving delay cell scan range + s4DlyBegin = 0; s4DlyEnd = 2 * STORAGED_DLY_UNIT; - u1PIStep = 1; // One step is 1/4 delay cell - PI_bound = 1024; // No bounadary as delay cell based + u1PIStep = 1; + PI_bound = 1024; } mcSHOW_DBG_MSG2(("Delay: %d->%d, Step: %d, Bound: %d\n", s4DlyBegin, s4DlyEnd, u1PIStep, PI_bound)); @@ -3152,14 +3040,14 @@ void WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase) { vSetRank(p, rank_i); - // set to best values for DQS + if (stDelayBase == PI_BASED) { - // Adjust DQS output delay. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1); } - else // stDelayBase == DLY_BASED + else { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); @@ -3177,7 +3065,7 @@ void WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase) #define SET_PATTERN_MANUALLY_FOR_DEBUG 1 DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase) { -// Note that below procedure is based on "ODT off" + DRAM_STATUS_T KResult = DRAM_FAIL; //U8 *uiLPDDR_O1_Mapping = NULL; @@ -3201,10 +3089,10 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T U8 u1OverBoundCnt = 0; //jj = 0 S16 PI_bound = 64; - //When doing WriteLeveling, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); - // error handling + if (!p) { mcSHOW_ERR_MSG(("context NULL\n")); @@ -3222,11 +3110,11 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T backup_rank = u1GetRank(p); //DramcRankSwap(p, p->rank); - //tx_rank_sel is selected by SW //Lewis@20180604: tx_rank_sel is selected by SW in WL if TMRRI design has changed. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), p->rank, TX_SET0_TXRANK); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); + - // backup mode settings U32 u4RegBackupAddress[] = { (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)), @@ -3234,18 +3122,18 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)), (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)), (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), //in O1PathOnOff() - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)), //in O1PathOnOff() + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)), (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)) }; DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - //default set DRAM FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAIL); #if MRW_CHECK_ONLY @@ -3254,7 +3142,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T if (p->isWLevInitShift[p->channel] == FALSE) { - // It must be PI_BASED or FAIL!! + #if __ETT__ while (stDelayBase != PI_BASED); #else @@ -3263,21 +3151,21 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T p->isWLevInitShift[p->channel] = TRUE; - // This flow would be excuted just one time, so all ranks(maybe rank0/1) should be adjusted at once. + ShiftDQUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); ShiftDQ_OENUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); ShiftDQSWCK_UI(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); - // Set DQS PI-based delay to 0 - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); } - // decide algorithm parameters according to freq.(PI mode/ phase mode) + WriteLevelingScanRange_PI(p, &s4DlyBegin, &s4DlyEnd, &u1PIStep, &PI_bound, stDelayBase); - // Not support autok to delay cell based mode. + if (stDelayBase == DLY_BASED) isAutoK = FALSE; @@ -3299,7 +3187,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T if (ucDoneFlg == 0xff) { - // all bytes are done + fgwrlevel_done = 1; KResult = DRAM_OK; } @@ -3335,26 +3223,26 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T #endif - vSetDramMRWriteLevelingOnOff(p, DISABLE); // Disable DDR write leveling mode: issue MR2[7] to enable write leveling + vSetDramMRWriteLevelingOnOff(p, DISABLE); + - // Write leveling enable OFF vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); - //Disable DQ_O1, SELO1ASO=0 for power saving + O1PathOnOff(p, OFF); - //tx_rank_sel is selected by HW + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); //TXRANKFIX should be write after TXRANK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); + - //restore registers. DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); - // Calculate DQS "PI" delay, nothing to do with delay cell + for (byte_i = 0; byte_i < DQS_BYTE_NUMBER; byte_i++) { - //Also for Dump_Reg + mcSHOW_DBG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i])); //DUMP_REG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i])); if (wrlevel_dqs_final_delay[p->rank][byte_i] >= PI_bound) @@ -3373,14 +3261,14 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T { vSetRank(p, rank_i); - // set to best values for DQS + if (stDelayBase == PI_BASED) { - // Adjust DQS output delay. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1); } - else // stDelayBase == DLY_BASED + else { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); @@ -3397,26 +3285,23 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T } #endif //SIMULATION_WRITE_LEVELING -#if (fcFOR_CHIP_ID == fcA60868) // Just work around for 868 test chip -// Set OPT6 = 1 after trigger, and OPT6 = 0 before release -// When WCKDUAL == 1, CAS-FS command, RTSWCMD_RK must be 2'b11 -// When WCKDUAL == 1, CAS-OFF command must be issue 2 times, RTSWCMD_RK must be 2'b00 and 2'b01 for each +#if (fcFOR_CHIP_ID == fcA60868) static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_sel) { U32 u4Response = 0; U32 u4TimeCnt = TIME_OUT_CNT; U32 u4BackupCKECTRL; - // Backup rank, CKE fix on/off, HW MIOCK control settings + u4BackupCKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); - // Work around case, set both rank CKE_FIXON for CAS-OFF + CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); - // Select a RT SW command + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), runtime_SW_cmd_sel, SWCMD_EN_RTSWCMD_SEL); - // Set _CNT, _AGE, _RANK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x30, RTSWCMD_CNT_RTSWCMD_CNT); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) | @@ -3426,7 +3311,7 @@ static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_se U8 _is_differential_mode = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), SHU_WCKCTRL_WCKDUAL); while (1) { - // Work around case, set specific rank value. + if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF) { if ( _is_differential_mode == 0) @@ -3438,7 +3323,7 @@ static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_se vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), 0x3, SWCMD_CTRL2_RTSWCMD_RK); } - // Trigger RT SW command + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); do @@ -3448,15 +3333,15 @@ static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_se mcDELAY_US(1); }while ((u4Response == 0) && (u4TimeCnt > 0)); - if (u4TimeCnt == 0)//time out + if (u4TimeCnt == 0) { mcSHOW_ERR_MSG(("[LP5 RT SW Cmd ] Resp fail (time out)\n")); } - // Release RT SW command + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); - // Work around case, loop again sending CAS-OFF command for RK1. + if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF) { if (_is_differential_mode == 0) @@ -3466,31 +3351,30 @@ static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_se break; } - // Restore rank, CKE fix on + vIO32Write4B_All(DRAMC_REG_CKECTRL, u4BackupCKECTRL); } -#else // Single end mode +#else #if 0 static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_sel) { U32 u4Response = 0; U32 u4TimeCnt = TIME_OUT_CNT; - // Select a RT SW command + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), runtime_SW_cmd_sel, SWCMD_EN_RTSWCMD_SEL); - // Set _CNT, _AGE, _RANK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x30, RTSWCMD_CNT_RTSWCMD_CNT); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) | P_Fld(p->rank, SWCMD_CTRL2_RTSWCMD_RK)); - // If command is CAS_FS/CAS_OFF, replace RTSWCMD_RK = 2'b11. - // Avoid this RK value at CAS_FS/CAS_OFF no match. + if ((runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_FS) || (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF)) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), 0x3, SWCMD_CTRL2_RTSWCMD_RK); - // Trigger RT SW command + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); do @@ -3500,12 +3384,12 @@ static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_se mcDELAY_US(1); }while ((u4Response == 0) && (u4TimeCnt > 0)); - if (u4TimeCnt == 0)//time out + if (u4TimeCnt == 0) { mcSHOW_ERR_MSG(("[LP5 RT SW Cmd ] Resp fail (time out)\n")); } - // Release RT SW command + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); } @@ -3526,7 +3410,7 @@ DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p) U8 backup_rank; // U8 u8ResultDutyCycMonitor[WHOLE_STEPS_NUM] = {0}; - // error handling + if (!p) { mcSHOW_ERR_MSG(("context NULL\n")); @@ -3543,44 +3427,43 @@ DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p) int i = -7; for (i = -7; i <= 7; i++) { - // MRW MR30 OP[7:4] = i(Set DCAU) and OP[3:0] = i(Set DCAL) + U8 u8RGSettingVal = FetchRGSettingVal(i); mcSHOW_ERR_MSG(("Set value %d into MR30\n", u8RGSettingVal)); MRWriteFldMulti(p, 30, P_Fld(u8RGSettingVal, MR30_DCAU) | P_Fld(u8RGSettingVal, MR30_DCAL), TO_MR); - // Start duty cycle monitor + DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_START_STOP, TO_MR); - // Delay tDCMM(2us) + mcDELAY_US(2); - // Duty cycle monitor Flip 0 -> 1, and store result of flip = 0 + DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_FLIP, TO_MR); - // Delay tDCMM(2us) + mcDELAY_US(2); - // Duty cycle monitor Flip 1 -> 0, and store result of flip = 1 + DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_FLIP, TO_MR); - // Delay tDCMM(2us) + mcDELAY_US(2); - // Stop Duty cycle monitor + DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_START_STOP, TO_MR); - // Delay tMRD + mcDELAY_US(2); mcSHOW_ERR_MSG(("Wait tMRD and MRR MR26\n")); - ///TODO: Read back result MR25[5:2] - // Store result into u8ResultDutyCycMonitor[] + } - ///TODO: Find and set a best MR30 variables + RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF); @@ -3589,7 +3472,7 @@ DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p) vSetRank(p, backup_rank); } -#endif // SIMULATION_DUTY_CYC_MONITOR +#endif void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p) @@ -3642,16 +3525,14 @@ void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p) } -//Reset PHY to prevent glitch when change DQS gating delay or RX DQS input delay -// [Lynx] Evere_st : cannot reset single channel. All DramC and All Phy have to reset together. + void DramPhyReset(DRAMC_CTX_T *p) { - // Evere_st change reset order : reset DQS before DQ, move PHY reset to final. - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 1, RX_SET0_RDATRST);// read data counter reset + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 1, RX_SET0_RDATRST); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMPHYRST); - //RG_ARCMD_RESETB & RG_ARDQ_RESETB_B0/1 only reset once at init, Justin Chan. - ///TODO: need to confirm RG_ARCMD_RESETB & RG_ARDQ_RESETB_B0/1 is reset at mem.c + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), P_Fld(0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0)); @@ -3667,17 +3548,11 @@ void DramPhyReset(DRAMC_CTX_T *p) P_Fld(1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0)); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMPHYRST); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, RX_SET0_RDATRST);// read data counter reset + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, RX_SET0_RDATRST); } #if SIMULATION_LP4_ZQ -//------------------------------------------------------------------------- -/** DramcZQCalibration - * start Dram ZQ calibration. - * @param p Pointer of context created by DramcCtxCreate. - * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL - */ -//------------------------------------------------------------------------- + #if ZQ_SWCMD_MODE static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) { @@ -3685,7 +3560,7 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) U32 u4TimeCnt = TIME_OUT_CNT; U32 u4SWCMDEN, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL; - // Backup rank, CKE fix on/off, HW MIOCK control settings + u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); @@ -3694,24 +3569,24 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); - // Disable HW MIOCK control to make CLK always on + DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL); mcDELAY_US(1); - //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL); - //select rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_SWTRIG_ZQ_RK); - //ZQCAL Start + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN_SWTRIG); do { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQC_SWTRIG_RESPONSE); u4TimeCnt --; - mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); @@ -3719,7 +3594,7 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN_SWTRIG); - if(u4TimeCnt==0)//time out + if(u4TimeCnt==0) { vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n")); @@ -3727,17 +3602,17 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) return DRAM_FAIL; } - // [JC] delay tZQCAL + mcDELAY_US(1); u4TimeCnt = TIME_OUT_CNT; - //ZQCAL Latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN_SWTRIG); do { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE); u4TimeCnt --; - mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d=\n\n", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); @@ -3753,10 +3628,10 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) return DRAM_FAIL; } - // [JC] delay tZQLAT + mcDELAY_US(1); - // Restore rank, CKE fix on, HW MIOCK control settings + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4SWCMDCTRL); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); @@ -3776,7 +3651,7 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) U32 u4TimeCnt = TIME_OUT_CNT; U32 u4SWCMDEN, u4SWCMDCTRL, u4MPCCTRL, u4RTSWCMD, u4SPDCTRL, u4CKECTRL; - // Backup rank, CKE fix on/off, HW MIOCK control settings + u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2)); u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL)); @@ -3787,15 +3662,15 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); - // Disable HW MIOCK control to make CLK always on + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); mcDELAY_US(1); - //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + //CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL); - //select rank + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), P_Fld(rank, SWCMD_CTRL2_RTSWCMD_RK) | P_Fld(0x20, SWCMD_CTRL2_RTSWCMD_AGE)); @@ -3803,7 +3678,7 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTSWCMD_HPRI_EN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x2a, RTSWCMD_CNT_RTSWCMD_CNT); - //ZQCAL Start + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x5, SWCMD_EN_RTSWCMD_SEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); @@ -3811,7 +3686,7 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); u4TimeCnt --; - mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); @@ -3819,7 +3694,7 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); - if(u4TimeCnt==0)//time out + if(u4TimeCnt==0) { vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n")); @@ -3827,11 +3702,11 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) return DRAM_FAIL; } - // [JC] delay tZQCAL + mcDELAY_US(1); u4TimeCnt = TIME_OUT_CNT; - //ZQCAL Latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x6, SWCMD_EN_RTSWCMD_SEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); @@ -3839,7 +3714,7 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); u4TimeCnt --; - mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d=", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); @@ -3847,7 +3722,7 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); - if(u4TimeCnt==0)//time out + if(u4TimeCnt==0) { vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n")); @@ -3855,10 +3730,10 @@ static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) return DRAM_FAIL; } - // [JC] delay tZQLAT + mcDELAY_US(1); - // Restore rank, CKE fix on, HW MIOCK control settings + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL); @@ -3880,7 +3755,7 @@ static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) U32 u4TimeCnt = TIME_OUT_CNT; U32 u4SWCMDEN, u4MPCCTRL, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL; - // Backup rank, CKE fix on/off, HW MIOCK control settings + u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION)); @@ -3890,29 +3765,24 @@ static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); - // Disable HW MIOCK control to make CLK always on + DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL); mcDELAY_US(1); - //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL); - //Use rank swap or MRSRK to select rank - //DramcRankSwap(p, p->rank); - //!!R_DMMRSRK(R_DMMPCRKEN=1) specify rank0 or rank1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRSRK); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN); - //ZQCAL Start - //R_DMZQCEN, 0x1E4[4]=1 for ZQCal Start - //Wait zqc_response=1 (dramc_conf_nao, 0x3b8[4]) - //R_DMZQCEN, 0x1E4[4]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN); do { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQC_RESPONSE); u4TimeCnt --; - mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); @@ -3920,7 +3790,7 @@ static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN); - if(u4TimeCnt==0)//time out + if(u4TimeCnt==0) { vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n")); @@ -3928,20 +3798,17 @@ static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) return DRAM_FAIL; } - // [JC] delay tZQCAL + mcDELAY_US(1); u4TimeCnt = TIME_OUT_CNT; - //ZQCAL Latch - //R_DMZQLATEN, 0x1E4[6]=1 for ZQCal latch - //Wait zqlat_response=1 (dramc_conf_nao, 0x3b8[28]) - //R_DMZQLATEN, 0x1E4[6]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN); do { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQLAT_RESPONSE); u4TimeCnt --; - mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d=", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); @@ -3949,7 +3816,7 @@ static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN); - if(u4TimeCnt==0)//time out + if(u4TimeCnt==0) { vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n")); @@ -3957,10 +3824,10 @@ static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) return DRAM_FAIL; } - // [JC] delay tZQLAT + mcDELAY_US(1); - // Restore rank, CKE fix on, HW MIOCK control settings + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL); @@ -3981,7 +3848,7 @@ DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank) return ZQ_SWCMD_MODE_Cal(p, rank); #elif ZQ_RTSWCMD_MODE return ZQ_RTSWCMD_MODE_Cal(p, rank); - #else //ZQ_SCSM_MODE + #else return ZQ_SCSM_MODE_Cal(p, rank); #endif } @@ -4004,7 +3871,7 @@ static U8 RXInputBuf_DelayExchange(S8 iOfst) return u1Value; } -// cannot be simulated in DV or DSim, it's analog feature. + DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) { S8 iOffset, s1begin, s1end; @@ -4042,7 +3909,7 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); - //Swith RX from Rank1 to Rank0 + DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), 0xf, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); @@ -4069,18 +3936,17 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) P_Fld(1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL)); } - //Enable VREF, (RG_RX_*DQ_VREF_EN_* =1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); if (!isLP4_DSC) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), 1, CA_CMD5_RG_RX_ARCMD_VREF_EN); - // Wait 1us. + mcDELAY_US(1); - //Enable RX input buffer (RG_RX_*DQ_IN_BUFF_EN_* =1, DA_RX_*DQ_IN_GATE_EN_* =1) - //Enable RX input buffer offset calibration (RG_RX_*DQ_OFFC_EN_*=1) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), P_Fld(1, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) | P_Fld(1, B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0)); if (!isLP4_DSC) { @@ -4091,7 +3957,7 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN) | P_Fld(1, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN)); } - // DQ_BUFF_EN_SEL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), 1, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0); if (!isLP4_DSC) { @@ -4124,7 +3990,7 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), 1, CA_CMD6_RG_RX_ARCMD_O1_SEL); - // SW parameter initialization + u1FinishCount =0; s1begin = -7; s1end = 8; @@ -4133,14 +3999,14 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) memset(s1DQFinalFlagChange, 0x7f, sizeof(s1DQFinalFlagChange)); memset(s1DQMFinalFlagChange, 0x7f, sizeof(s1DQMFinalFlagChange)); - //Sweep RX offset calibration code (RG_RX_*DQ*_OFFC<3:0>), the MSB is sign bit, sweep the code from -7(1111) to +7(0111) + for(iOffset = s1begin; iOffset < s1end; iOffset+=u1step) { u1Offc_RgValue = RXInputBuf_DelayExchange(iOffset); mcSHOW_DBG_MSG2(("iOffset= %2d, set %2d,", iOffset, u1Offc_RgValue)); - //Delay of B0/B1 DQ0~DQ7. + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ0), P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0) | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0) | @@ -4176,7 +4042,7 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) P_Fld(u1Offc_RgValue, SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ7_OFFSETC_C0)); } - //Delay of B0/B1 DQM0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ1), u1Offc_RgValue, SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0); if (!isLP4_DSC) { @@ -4187,11 +4053,10 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD1), u1Offc_RgValue, SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC); } - //For each code sweep, wait 0.1us to check the flag. + mcDELAY_US(1); - //Check offset flag of DQ (RGS_*DQ*_OFFSET_FLAG_*), the value will be from 1(-7) to 0(+7). Record the value when the flag becomes "0". - //Flag bit0 is for DQ0, Flag bit15 for DQ15 + u4RestltDQ_B0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0); if (!isLP4_DSC) { @@ -4208,11 +4073,11 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) for(u1BitIdx= 0; u1BitIdx < DQ_DATA_WIDTH ; u1BitIdx++) { - if(s1DQFinalFlagChange[u1BitIdx] == 0x7f) //invalid + if(s1DQFinalFlagChange[u1BitIdx] == 0x7f) { u1O1_value = (u4RestltDQ >> u1BitIdx) & 0x1; - if(u1O1_value ==0) // 1 -> 0 + if(u1O1_value ==0) { s1DQFinalFlagChange[u1BitIdx] = iOffset; u1FinishCount ++; @@ -4233,7 +4098,7 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) } } - //Check offset flag of DQM (RGS_*DQ*_OFFSET_FLAG_*), the value will be from 1(-7) to 0(+7). Record the value when the flag becomes "0". + u4RestltDQM[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0); if (!isLP4_DSC) { @@ -4248,9 +4113,9 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) for(u1ByteIdx= 0; u1ByteIdx < DQM_BYTE_NUM; u1ByteIdx++) { - if(s1DQMFinalFlagChange[u1ByteIdx]== 0x7f) //invalid + if(s1DQMFinalFlagChange[u1ByteIdx]== 0x7f) { - if(u4RestltDQM[u1ByteIdx]==0)// 1 -> 0 + if(u4RestltDQM[u1ByteIdx]==0) { s1DQMFinalFlagChange[u1ByteIdx]= iOffset; u1FinishCount++; @@ -4271,11 +4136,11 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) } } - if(u1FinishCount==(DQM_BYTE_NUM+DQ_DATA_WIDTH)) // (DQ8 bits, DQM 1bit, total 9 bits.) x2 bytes + if(u1FinishCount==(DQM_BYTE_NUM+DQ_DATA_WIDTH)) { vSetCalibrationResult(p, DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC, DRAM_OK); mcSHOW_DBG_MSG2(("All bits find pass window, early break!\n")); - break; //all bits done, early break + break; } } @@ -4358,14 +4223,14 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) } vSetRank(p, read_val_b0); - //need to set 0 after DramcRXInputBufferOffsetCal + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), 0x0, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0); //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1); DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); - //after K, must set OFFSET_BIAS_EN as1 and OFFSET_EN as 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0)); @@ -4392,10 +4257,7 @@ DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) #define GATING_PATTERN_NUM_LP5 0x23 #define GATING_GOLDEND_DQSCNT_LP5 0x4646 #define RXDQS_GATING_AUTO_DBG_REG_NUM 6 -/* Preamble & Postamble setting. Currently use macro to define. - * Later may use speed or MR setting to decide - * !!! REVIEW !!! - */ + #if GATING_ADJUST_TXDLY_FOR_TRACKING U8 u1TXDLY_Cal_min =0xff, u1TXDLY_Cal_max=0; @@ -4464,26 +4326,26 @@ U8 __wa__gating_autok_init_ui[RANK_MAX] = { 0 }; static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK) { - const U8 au1MR2MappingToRL[2][8] = {{6, 10, 14, 20, 24, 28, 32, 36}, //normal mode - {6, 10, 16, 22, 26, 32, 36, 40}}; //byte mode + const U8 au1MR2MappingToRL[2][8] = {{6, 10, 14, 20, 24, 28, 32, 36}, + {6, 10, 16, 22, 26, 32, 36, 40}}; //U8 u1CK2WCK, u1DVFSCEn; U8 u1MR0_LatencyMode; U8 u1MR2RLValue; - u1MR2RLValue = u1MR02Value[p->dram_fsp] & 0x7; //MR2 Op[2:0] + u1MR2RLValue = u1MR02Value[p->dram_fsp] & 0x7; U8 u1RX_Path_delay_UI, u1RealRL,u1StartUI, u1ExtraMCKfor1_4mode; U8 u1MCK2CK_UI, u1ReadDQSINCTL, u1DQSINCTL_UI; U8 u4TDQSCK_UI_min; U8 u1GatingAheadDQS_UI; - /* LPDDR5 uses same bit */ - if(gu2MR0_Value[p->rank] == 0xffff) //MR0 is not ready + + if(gu2MR0_Value[p->rank] == 0xffff) { u1MR0_LatencyMode = CBT_NORMAL_MODE; } else { - u1MR0_LatencyMode = (gu2MR0_Value[p->rank]>>1) & 0x1; //MR0 OP[1], 0:normal mode, 1:byte mode + u1MR0_LatencyMode = (gu2MR0_Value[p->rank]>>1) & 0x1; } { @@ -4491,7 +4353,7 @@ static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK) u1RealRL = au1MR2MappingToRL[u1MR0_LatencyMode][u1MR2RLValue]; } - ///TODO: A60868 does not support LP5 DIV4, current setting is not provided for LP5 + if(vGet_Div_Mode(p) == DIV4_MODE) { u1MCK2CK_UI = 4; @@ -4506,22 +4368,22 @@ static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK) } else { - /* DIV16, only for LP5 */ + u1MCK2CK_UI = 16; u1ExtraMCKfor1_4mode = 0; u1GatingAheadDQS_UI = 8; } - // RX_Path_delay_UI = RL*2 + tDQSCK_UI<1500~3500ps> - PHY_interanl<skip 30ps> - GatingAheadDQS<2UI> + if(1:4 mod)+1MCK + u1RX_Path_delay_UI = (u1RealRL<<1) + u4TDQSCK_UI_min - u1GatingAheadDQS_UI + (u1MCK2CK_UI*u1ExtraMCKfor1_4mode); u1ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL); u1DQSINCTL_UI = u1ReadDQSINCTL * u1MCK2CK_UI; if(u1AutoK) - u1RX_Path_delay_UI += 0; //HW K start position = gating min position(1500ns) + u1RX_Path_delay_UI += 0; else - u1RX_Path_delay_UI -= 3; //SW K start position = gating min position(1500ns) -3UI + u1RX_Path_delay_UI -= 3; if(u1RX_Path_delay_UI >= u1DQSINCTL_UI) u1StartUI = u1RX_Path_delay_UI - u1DQSINCTL_UI; @@ -4595,7 +4457,7 @@ static void rxdqs_gating_fastk_save_restore(DRAMC_CTX_T *p, /* Calculate P1 */ best_win->best_dqsien_dly_ui_p1[dqs_i] = best_win->best_dqsien_dly_mck[dqs_i] * ui_per_mck + - best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */ + best_win->best_dqsien_dly_ui[dqs_i] + freq_div; best_win->best_dqsien_dly_mck_p1[dqs_i] = best_win->best_dqsien_dly_ui_p1[dqs_i] / ui_per_mck; best_win->best_dqsien_dly_ui_p1[dqs_i] = @@ -4637,20 +4499,12 @@ static void rxdqs_gating_misc_process(DRAMC_CTX_T *p, "Gating_Center_", "PI", dqs_i, rxdqs_best_win->best_dqsien_dly_pi[dqs_i], NULL); #endif - /*TINFO="best DQS%d delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck[dqs_i], rxdqs_best_win.best_dqsien_dly_ui[dqs_i], rxdqs_best_win.best_dqsien_dly_pi[dqs_i])); */ + mcSHOW_DBG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win->best_dqsien_dly_mck[dqs_i], rxdqs_best_win->best_dqsien_dly_ui[dqs_i], rxdqs_best_win->best_dqsien_dly_pi[dqs_i])); - /*mcDUMP_REG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, - rxdqs_best_win->best_dqsien_dly_mck[dqs_i], - rxdqs_best_win->best_dqsien_dly_ui[dqs_i], - rxdqs_best_win->best_dqsien_dly_pi[dqs_i]));*/ - /* cc mark mcFPRINTF((fp_A60501,"best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, - rxdqs_best_win.best_dqsien_dly_mck[dqs_i], - rxdqs_best_win.best_dqsien_dly_ui[dqs_i], - rxdqs_best_win.best_dqsien_dly_pi[dqs_i])); - */ + #if GATING_ADJUST_TXDLY_FOR_TRACKING u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck[dqs_i] << 4) + @@ -4672,26 +4526,18 @@ static void rxdqs_gating_misc_process(DRAMC_CTX_T *p, } mcSHOW_DBG_MSG(("\n")); - //cc mark mcFPRINTF((fp_A60501,"\n")); + for (dqs_i=0; dqs_i<DQS_BYTE_NUMBER; dqs_i++) { - /*TINFO="best DQS%d P1 delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]*/ + mcSHOW_DBG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i], rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i], rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i])); - /*mcDUMP_REG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, - rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i], - rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i], - rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]));*/ - /* cc mark mcFPRINTF((fp_A60501,"best DQS%d P1 dly(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, - rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i], - rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i], - rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i])); - */ + #if GATING_ADJUST_TXDLY_FOR_TRACKING - // find max gating TXDLY (should be in P1) + u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i] << 4) + rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i]; @@ -4714,18 +4560,18 @@ static void rxdqs_gating_misc_process(DRAMC_CTX_T *p, if(p->frequency >= RDSEL_TRACKING_TH) { - //Byte 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), (ucbest_coarse_mck_backup[p->rank][0] << 4) | (ucbest_coarse_ui_backup[p->rank][0]), - SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), rxdqs_best_win->best_dqsien_dly_pi[0], - SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); //PI - //Byte 1 + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), (ucbest_coarse_mck_backup[p->rank][1] << 4) | (ucbest_coarse_ui_backup[p->rank][1]), - SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1);//UI + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), - rxdqs_best_win->best_dqsien_dly_pi[1], SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); //PI + rxdqs_best_win->best_dqsien_dly_pi[1], SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); } #endif @@ -4734,7 +4580,7 @@ static void rxdqs_gating_misc_process(DRAMC_CTX_T *p, #if GATING_AUTO_K_SUPPORT static void rxdqs_gating_auto_cal_reset(DRAMC_CTX_T *p) { - /* Reset internal autok status and logic */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) | P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) | @@ -4750,13 +4596,11 @@ static void rxdqs_gating_auto_cal_reset(DRAMC_CTX_T *p) static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, struct rxdqs_gating_auto_param *auto_param) { - /* Before start calibration, reset all state machine and all rank's state */ + rxdqs_gating_auto_cal_reset(p); - /*----------- - * Normal Setting, Same as SW calibration - *---------------*/ + if (p->frequency == 800) { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), 0x1, MISC_STBCAL1_STBCNT_SW_RST); @@ -4765,7 +4609,7 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), 0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN); - /* SELPH_MODE = BY RANK */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); @@ -4777,7 +4621,7 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), 0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD); - /* PICG_EARLY_EN */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), @@ -4785,7 +4629,7 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); - /* BURST_MODE */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), 0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE); @@ -4803,7 +4647,7 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0x1, MISC_STBCAL_DQSIENMODE); - /* New Rank Mode */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | @@ -4814,27 +4658,20 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1); - /* dummy read */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), 0x1, DUMMY_RD_DUMMY_RD_PA_OPT); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE); - //Yulia add workaround for auto K pattern length. : Apply for all project before IPM_V2 - //Dummy read BL should be controlled by DQSIEN_AUTOK_BURST_LENGTH, but now we can only use dummy read length(DMY_RD_LEN) - //DMY_RD_LEN (0 for BL8, 1 for BL16, 3 for BL32) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), 3/*auto_param->burst_len*/, RK_DUMMY_RD_ADR_DMY_RD_LEN); - /* Decide by HW Although Dummy read used, but TA2 has higher priority */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), 3, RK_DUMMY_RD_ADR_DMY_RD_LEN); + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0x4, TEST2_A4_TESTAGENTRKSEL); - //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, - // MISC_STBCAL2_STBENCMPEN); - /*----------- - * Auto calibration setting - *-------------------*/ vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), P_Fld(auto_param->init_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK) | P_Fld(auto_param->init_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI) | @@ -4852,9 +4689,7 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), auto_param->early_break, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN); - /*--------- - * DV settings - *-------------------*/ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0x0, MISC_STBCAL_PICGEN); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), @@ -4928,7 +4763,7 @@ static void rxdqs_gating_set_final_result(DRAMC_CTX_T *p, U8 mck2ui, } #endif - /* Set DQSIEN delay in MCK and UI */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(best_win->best_dqsien_dly_mck[0], SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -4981,7 +4816,7 @@ static void rxdqs_gating_set_final_result(DRAMC_CTX_T *p, U8 mck2ui, } #if GATING_AUTO_K_SUPPORT -/* By autoK: Set the result calibrated by HW to RG */ + static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p, struct rxdqs_gating_best_win *best_win, struct rxdqs_gating_cal *rxdqs_cal) @@ -4997,7 +4832,7 @@ static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p, U16 value; u8 dqs_i; - /* Transfer HW unit to RG unit */ + for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { mck = best_win->best_dqsien_dly_mck[dqs_i]; ui = best_win->best_dqsien_dly_ui[dqs_i]; @@ -5006,17 +4841,17 @@ static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p, freq_div = rxdqs_cal->dqsien_freq_div; if (vGet_Div_Mode(p) == DIV16_MODE) - total_ui = (mck << 4) + ui; /* 1:16 mode */ + total_ui = (mck << 4) + ui; else if (vGet_Div_Mode(p) == DIV8_MODE) - total_ui = (mck << 3) + ui; /* 1: 8 mode */ + total_ui = (mck << 3) + ui; else - total_ui = (mck << 2) + ui; /* 1: 4 mode */ + total_ui = (mck << 2) + ui; + - /* RG is always 1:16 mode */ mck = (total_ui >> 4); ui = (total_ui & 0xf); - value = mck * mck2ui + ui; /* Total UI number */ + value = mck * mck2ui + ui; mck_p1 = (value + freq_div) / mck2ui; ui_p1 = (value + freq_div) % mck2ui; @@ -5055,7 +4890,7 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, while (done_bytes < total_bytes) { for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { - /* If already done, skip this byte */ + if (done[dqs_i]) continue; @@ -5068,9 +4903,9 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0); - /* If autok fail, done flag will not be asserted. */ + if (done[dqs_i] || error[dqs_i]) { - /* Done and Pass */ + if (error[dqs_i] == 0) { mck_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), @@ -5092,7 +4927,7 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0); - /* If early break mode not enabled, right boundary could be found */ + if (auto_param->early_break == DISABLE) { mck_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), @@ -5107,7 +4942,7 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, } else { - /* If error occurred for this byte, it will be treated as a DONE condition */ + done[dqs_i] = 1; } @@ -5138,7 +4973,7 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, mcDELAY_MS(1); } - /* Log it */ + for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { mcSHOW_DBG_MSG(("[Gating][%s] AUTOK of CH-%d, Rk-%d, Byte-%d:\n", error[dqs_i]? "Fail" : "Pass", p->channel, p->rank, dqs_i)); @@ -5158,7 +4993,7 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, if (error[dqs_i]) { ret = DRAM_FAIL; } else { - /* If passed, shall set the result to RG */ + best_win->best_dqsien_dly_mck[dqs_i] = mck_center[dqs_i]; best_win->best_dqsien_dly_ui[dqs_i] = ui_center[dqs_i]; best_win->best_dqsien_dly_pi[dqs_i] = pi_center[dqs_i]; @@ -5218,14 +5053,14 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_auto_cal(DRAMC_CTX_T *p) start_ui = u1GetGatingStartPos(p, AUTOK_ON); end_ui = start_ui + 32; - /* Set auto calibration params */ + auto_param.early_break = ENABLE; auto_param.dbg_mode = ENABLE; auto_param.init_mck = start_ui / mck2ui_hw; auto_param.init_ui = start_ui % mck2ui_hw; auto_param.end_mck = end_ui / mck2ui_hw; auto_param.end_ui = end_ui % mck2ui_hw; - auto_param.pi_offset = 2; /* 2 ^ 2 = 4 */ + auto_param.pi_offset = 2; auto_param.burst_len = RXDQS_BURST_LEN_8; @@ -5240,11 +5075,11 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_auto_cal(DRAMC_CTX_T *p) auto_param.pi_offset = psra->dqsien_autok_pi_offset? ENABLE: DISABLE; } -#endif /* FOR_DV_SIMULATION_USED == 1 */ +#endif rxdqs_gating_auto_cal_cfg(p, &auto_param); - /* Trigger HW auto k */ + rxdqs_gating_auto_cal_trigger(p); ret = rxdqs_gating_auto_cal_status(p, &auto_param, &rxdqs_best_win); @@ -5270,12 +5105,10 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_auto_cal(DRAMC_CTX_T *p) static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) { - /* Disable Per-Bank ref */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0), 0, SHU_CONF0_PBREFEN); - /*---------------- - * From DV - *------------------------*/ + if (p->frequency == 800) { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), 0x1, MISC_STBCAL1_STBCNT_SW_RST); @@ -5284,7 +5117,7 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), 0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN); - /* SELPH_MODE = BY RANK */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); @@ -5296,7 +5129,7 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), 0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD); - /* PICG_EARLY_EN */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), @@ -5304,7 +5137,7 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); - /* BURST_MODE */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), 0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE); @@ -5322,7 +5155,7 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0x1, MISC_STBCAL_DQSIENMODE); - /* New Rank Mode */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | @@ -5341,14 +5174,14 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, RX_SET0_DM4TO1MODE); - /* enable &reset DQS counter */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, MISC_STBCAL2_DQSG_CNT_EN); - mcDELAY_US(4); /* wait 1 auto refresh after DQS Counter enable */ + mcDELAY_US(4); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, MISC_STBCAL2_DQSG_CNT_RST); - mcDELAY_US(1); /* delay 2T */ + mcDELAY_US(1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, MISC_STBCAL2_DQSG_CNT_RST); @@ -5358,7 +5191,7 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) 0xaa000000 | GATING_PATTERN_NUM_LP5, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT); if (use_enhanced_rdqs) { - /* TBD. Enter Enhanced RDQS training mode */ + } } @@ -5388,7 +5221,7 @@ static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui, value = (reg_mck * mck2ui) + reg_ui; if (value >= 11) { - /* For RODT, MCK2UI is different from Gating */ + U8 rodt_mck2ui = get_rodt_mck2ui(p); value -= 11; @@ -5407,7 +5240,7 @@ static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui, } #endif - /* Set DQSIEN delay in MCK and UI */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(reg_mck, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -5454,7 +5287,7 @@ static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui, static void rxdqs_gating_sw_cal_trigger(DRAMC_CTX_T *p, struct rxdqs_gating_cal *rxdqs_cal) { -#if 0//ENABLE_DDR800_OPEN_LOOP_MODE_OPTION -> No 0.5UI after A60868 +#if 0 if (u1IsPhaseMode(p) == TRUE) { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0); @@ -5476,7 +5309,7 @@ static void rxdqs_gating_sw_cal_trigger(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, MISC_STBCAL2_DQSG_CNT_RST); - /* enable TE2, audio pattern */ + DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); } @@ -5520,7 +5353,7 @@ static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p, rxdqs_trans->dqs_high[dqs_i]++; rxdqs_trans->dqs_transition[dqs_i] = 1; - /* Record the latest value that causes (lead, lag) = (1, 1) */ + rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] = rxdqs_cal->dqsien_dly_mck; rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] = @@ -5529,7 +5362,7 @@ static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p, rxdqs_cal->dqsien_dly_pi; } else if ((rxdqs_trans->dqs_high[dqs_i] * rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) { - /* Consecutive 16 PI DQS high for de-glitch */ + if (((rxdqs_trans->dqs_lead[dqs_i] == 1) && (rxdqs_trans->dqs_lag[dqs_i] == 0)) || ((rxdqs_trans->dqs_lead[dqs_i] == 0) && @@ -5541,7 +5374,7 @@ static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p, (rxdqs_trans->dqs_lag[dqs_i] == 0)){ if ((rxdqs_trans->dqs_low[dqs_i] * rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) { - /* (lead, lag) = (0, 0), transition done */ + rxdqs_trans->dqs_transitioned[dqs_i] = 1; } rxdqs_trans->dqs_low[dqs_i]++; @@ -5551,12 +5384,12 @@ static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p, } #else else { - /* (lead, lag) = (0, 0), transition done */ + rxdqs_trans->dqs_transitioned[dqs_i] = 1; } #endif } else { - /* Lead/lag = (1, 1) number is too few. Reset dqs_high */ + rxdqs_trans->dqs_high[dqs_i] = 0; #if GATING_LEADLAG_LOW_LEVEL_CHECK rxdqs_trans->dqs_low[dqs_i] = 0; @@ -5599,15 +5432,11 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p, MISC_STBERR_ALL_GATING_ERROR_B1_RK1); } - /* read DQS counter - * Note: DQS counter is no longer used as pass condition. Here - * Read it and log it is just as debug method. Any way, DQS counter - * can still be used as a clue: it will be n*0x23 when gating is correct - */ + debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0)); debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1)); - /* read (lead, lag) */ + rxdqs_gating_get_leadlag(p, rxdqs_trans, rxdqs_cal); mcSHOW_DBG_MSG2(("%2d %2d %2d | ", @@ -5621,13 +5450,13 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p, debug_pass_cnt = GATING_GOLDEND_DQSCNT_LP5; - /* Decide the window center */ + for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { if (passed_bytes & (1 << dqs_i)) continue; if ((gating_error[dqs_i] == 0) && (debug_cnt[dqs_i] == debug_pass_cnt)) { - /* Calcuate DQSIEN position */ + if (rxdqs_trans->dqs_transitioned[dqs_i] != 0) { U8 pass_count = rxdqs_trans->dqs_transition[dqs_i]; U8 offset = (pass_count * rxdqs_cal->dqsien_pi_adj_step) / 2; @@ -5638,23 +5467,23 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p, ui2pi = rxdqs_cal->dqsien_pi_per_ui; freq_div = rxdqs_cal->dqsien_freq_div; - /* PI */ + tmp = rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] + offset; best_win->best_dqsien_dly_pi[dqs_i] = tmp % ui2pi; best_win->best_dqsien_dly_pi_p1[dqs_i] = best_win->best_dqsien_dly_pi[dqs_i]; - /* UI & MCK - P0 */ + tmp /= ui2pi; tmp = rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] + tmp; best_win->best_dqsien_dly_ui[dqs_i] = tmp % mck2ui; best_win->best_dqsien_dly_mck[dqs_i] = rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] + (tmp / mck2ui); - /* UI & MCK - P1 */ + best_win->best_dqsien_dly_ui_p1[dqs_i] = best_win->best_dqsien_dly_mck[dqs_i] * mck2ui + - best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */ + best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /*mcSHOW_DBG_MSG(("Total UI for P1: %d, mck2ui %d\n", best_win->best_dqsien_dly_mck_p1[dqs_i], mck2ui));*/ best_win->best_dqsien_dly_mck_p1[dqs_i] = @@ -5677,9 +5506,7 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p, } } } else { - /* Clear lead lag info in case lead/lag flag toggled - * while gating counter & gating error still incorrect - */ + rxdqs_trans->dqs_high[dqs_i] = 0; rxdqs_trans->dqs_transition[dqs_i] = 0; rxdqs_trans->dqs_transitioned[dqs_i] = 0; @@ -5712,8 +5539,8 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, memset(&rxdqs_trans, 0, sizeof(struct rxdqs_gating_trans)); memset(&rxdqs_best_win, 0, sizeof(struct rxdqs_gating_best_win)); - pi_per_ui = DQS_GW_PI_PER_UI; /* 1 UI = ? PI. Sams as CBT, differ according to data rate?? */ - ui_per_mck = DQS_GW_UI_PER_MCK; /* 1 mck = ? UI. Decided by (Tmck/Tck) * (Tck/Twck) */ + pi_per_ui = DQS_GW_PI_PER_UI; + ui_per_mck = DQS_GW_UI_PER_MCK; if (vGet_Div_Mode(p) == DIV4_MODE) freq_div = 2; else @@ -5740,7 +5567,6 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), }; - /* Register backup */ DramcBackupRegisters(p, reg_backup_address, sizeof (reg_backup_address) / sizeof (U32)); @@ -5754,16 +5580,16 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, else if((is_lp5_family(p)) && (p->frequency == 2750)) dly_ui_start = 12; else - dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32; + dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF); #else - dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32; + dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF); #endif dly_ui_end = dly_ui_start+ 32; pass_byte_count = 0; #else { - dly_ui_start = 9; //12; Eddie change to 9 for Hynix Normal Mode + dly_ui_start = 9; if(p->freq_sel==LP4_DDR4266) { dly_ui_start = 16; @@ -5791,8 +5617,8 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, DramcEngine2End(p); - //check if there is no pass taps for each DQS - if (pass_byte_count == 0x3)//byte0 pass: pass_byte_count bit0=1, byte1 pass: pass_byte_count bit1=1 .LP4/LP5 pass=0x3(2 bytes). need modification for LP3 pass=0xf(4 bytes) + + if (pass_byte_count == 0x3) { u1GatingErrorFlag=0; vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK); @@ -5829,7 +5655,7 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, mcSHOW_DBG_MSG4(("[Gating] SW calibration Done\n")); - /* Set MCK & UI */ + rxdqs_gating_set_final_result(p, ui_per_mck, &rxdqs_best_win); DramcRestoreRegisters(p, reg_backup_address, @@ -5840,7 +5666,7 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, return DRAM_OK; } -/* LPDDR5 Rx DQS Gating */ + DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs) { @@ -5858,16 +5684,14 @@ DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, } #endif - // default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAIL); - /* Try HW auto calibration first. If failed, - * will try SW mode. - */ + #if GATING_AUTO_K_SUPPORT if (autok) { #if ENABLE_GATING_AUTOK_WA - if (rxdqs_gating_bypass(p)) /* Already done by SWK */ + if (rxdqs_gating_bypass(p)) return DRAM_OK; #endif @@ -5885,7 +5709,7 @@ DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, return dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs); } -///TODO: wait for porting +++ + #if GATING_ADJUST_TXDLY_FOR_TRACKING void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) { @@ -5909,7 +5733,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY if (vGet_Div_Mode(p) == DIV8_MODE) { - // wei-jen: DQSgated_min should be 2 when freq >= 1333, 1 when freq < 1333 + if (p->frequency >= 1333) { reg_TX_dly_DQSgated_min = 2; @@ -5919,13 +5743,12 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) reg_TX_dly_DQSgated_min = 1; } } - else // for LPDDR4 1:4 mode + else { - //tg: DDR800/400: reg_TX_dly_DQSgated (min) =1 reg_TX_dly_DQSgated_min = 1; } #else - // wei-jen: DQSgated_min should be 3 when freq >= 1333, 2 when freq < 1333 + if (p->frequency >= 1333) { reg_TX_dly_DQSgated_min = 3; @@ -5936,12 +5759,12 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) } #endif - //Sylv_ia MP setting is switched to new mode, so RANKRXDVS can be set as 0 (review by HJ Huang) + #if 0 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ7), u1RankRxDVS, SHU_B0_DQ7_R_DMRANKRXDVS_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B1_DQ7), u1RankRxDVS, SHU_B1_DQ7_R_DMRANKRXDVS_B1); #endif - // === End of DVS setting ===== + s1ChangeDQSINCTL = reg_TX_dly_DQSgated_min - u1TXDLY_Cal_min; @@ -5963,7 +5786,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) else mck2ui_shift = 2; - if (s1ChangeDQSINCTL != 0) // need to change DQSINCTL and TXDLY of each byte + if (s1ChangeDQSINCTL != 0) { u1TXDLY_Cal_min += s1ChangeDQSINCTL; u1TXDLY_Cal_max += s1ChangeDQSINCTL; @@ -6005,7 +5828,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = u4ReadTXDLY[u1RankIdx][dqs_i]; ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = u4ReadTXDLY_P1[u1RankIdx][dqs_i]; } - else // LP3 or LP4 1:4 mode + else { u4ReadTXDLY[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_backup[u1RankIdx][dqs_i] >> 2) & 0x1)); u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] >> 2) & 0x1)); @@ -6039,8 +5862,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) { vSetRank(p, u1RankIdx); - // 4T or 2T coarse tune - /* Set DQSIEN delay in MCK and UI */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), P_Fld(ucbest_coarse_mck_backup[u1RankIdx][0], SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | @@ -6063,14 +5885,14 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) #if RDSEL_TRACKING_EN if(p->frequency >= RDSEL_TRACKING_TH) { - //Byte 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), (ucbest_coarse_mck_backup[u1RankIdx][0] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][0]), - SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0);//UI - //Byte 1 + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), (ucbest_coarse_mck_backup[u1RankIdx][1] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][1]), - SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1);//UI + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1); } #endif } @@ -6086,9 +5908,9 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) if (p->DBI_R_onoff[p->dram_fsp]) { u4ReadDQSINCTL++; - #if 0//cc mark for reg not found + #if 0 u4ReadRODT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_RODT); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadRODT + 1, SHU_ODTCTRL_RODT); //update RODT value when READ_DBI is on + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadRODT + 1, SHU_ODTCTRL_RODT); #endif } #endif @@ -6121,8 +5943,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) #endif #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY - // Wei-Jen: RANKINCTL_RXDLY = RANKINCTL = RankINCTL_ROOT = u4ReadDQSINCTL-2, if XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY enable - // Wei-Jen: New algorithm : u4ReadDQSINCTL-2 >= 0 + if (u4ReadDQSINCTL >= 2) { u4RankINCTL_ROOT = u4ReadDQSINCTL - 2; @@ -6136,7 +5957,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) #endif } #else - //Modify for corner IC failed at HQA test XTLV + if (u4ReadDQSINCTL >= 3) { u4RankINCTL_ROOT = u4ReadDQSINCTL - 3; @@ -6148,23 +5969,21 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) } #endif - //DQSINCTL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), - u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); //Rank0 DQSINCTL + u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); vSetRank(p, RANK_1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), - u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); //Rank1 DQSINCTL + u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); vSetRank(p, backup_rank); - //No need to update RODT. If we update RODT, also need to update SELPH_ODTEN0_TXDLY - //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadDQSINCTL, SHU_ODTCTRL_RODT); //RODT = DQSINCTL vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), - u4ReadDQSINCTL, MISC_SHU_RANKCTL_RANKINCTL_PHY); //RANKINCTL_PHY = DQSINCTL + u4ReadDQSINCTL, MISC_SHU_RANKCTL_RANKINCTL_PHY); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), - u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL); //RANKINCTL= DQSINCTL -3 + u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), - u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1); //RANKINCTL_ROOT1= DQSINCTL -3 + u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1); #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), @@ -6177,12 +5996,9 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) //mcDUMP_REG_MSG(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); //mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); #else - //XRTR2R=A-phy forbidden margin(6T) + reg_TX_dly_DQSgated (max) +Roundup(tDQSCKdiff/MCK+0.25MCK)+1(05T sel_ph margin)-1(forbidden margin overlap part) - //Roundup(tDQSCKdiff/MCK+1UI) =1~2 all LP3 and LP4 timing - //u4XRTR2R= 8 + u1TXDLY_Cal_max; // 6+ u1TXDLY_Cal_max +2 - //Modify for corner IC failed at HQA test XTLV @ 3200MHz - u4XRTR2R = 8 + u1TXDLY_Cal_max + 1; // 6+ u1TXDLY_Cal_max +2 + + u4XRTR2R = 8 + u1TXDLY_Cal_max + 1; if (u4XRTR2R > 12) { u4XRTR2R = 12; @@ -6196,12 +6012,8 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) //mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); #endif -#if 0//ENABLE_RODT_TRACKING - //Because Ki_bo+,WE2,Bi_anco,Vin_son...or behind project support WDQS, they need to apply the correct new setting - //The following 2 items are indepentent - //1. if TX_WDQS on(by vendor_id) or p->odt_onoff = 1, ROEN/RODTE/RODTE2 = 1 - //2. if ENABLE_RODT_TRACKING on, apply new setting and RODTENSTB_TRACK_EN = ROEN - // LP4 support only +#if 0 + U8 u1ReadROEN; u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \ @@ -6209,7 +6021,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) #endif #ifdef XRTR2W_PERFORM_ENHANCE_RODTEN - // LP4 support only + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld(0x0fff, MISC_SHU_RODTENSTB_RODTENSTB_EXT) | P_Fld(1, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | @@ -6229,7 +6041,7 @@ void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p) u1TXDLY_Cal_max = 0; } #endif -///TODO: wait for porting --- + #endif @@ -6253,26 +6065,25 @@ static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) const U8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_NUM][16] = { { - // for EMCP - //CH-A + { 0, 1, 2, 3, 7, 4, 6, 5, 9, 8, 12, 14, 15, 10, 13, 11 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 7, 4, 3, 2, 6, 5, 9, 8, 12, 14, 15, 10, 11, 13 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 7, 4, 6, 5, 9, 8, 12, 14, 15, 10, 13, 11 }, - //CH-D + { 0, 1, 7, 4, 3, 2, 6, 5, 9, 8, 12, 14, 15, 10, 11, 13 @@ -6280,26 +6091,25 @@ static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) #endif }, { - // for DSC_2CH, HFID RESERVED - //CH-A + { 0, 1, 4, 3, 2, 5, 7, 6, 9, 8, 10, 11, 15, 13, 12, 14 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 2, 5, 3, 4, 7, 6, 8, 9, 10, 11, 15, 14, 13, 12 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, - //CH-D + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 @@ -6307,26 +6117,25 @@ static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) #endif }, { - // for MCP - //CH-A + { 0, 1, 6, 2, 4, 7, 3, 5, 8, 9, 10, 12, 13, 11, 15, 14 }, #if (CHANNEL_NUM>1) - //CH-B + { 0, 1, 7, 4, 2, 5, 6, 3, 9, 8, 10, 12, 11, 14, 13, 15 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 12, 15, 14, 11, 13 }, - //CH-D + { 0, 1, 7, 4, 2, 5, 6, 3, 9, 8, 10, 12, 11, 14, 13, 15 @@ -6334,26 +6143,25 @@ static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) #endif }, { - // for DSC_180 - //CH-A + { 8, 9, 14, 15, 12, 13, 11, 10, 1, 0, 3, 2, 7, 6, 4, 5 }, #if (CHANNEL_NUM>1) - //CH-B + { 9, 8, 13, 12, 15, 10, 11, 14, 0, 1, 3, 2, 4, 6, 5, 7 }, #endif #if (CHANNEL_NUM>2) - //CH-C + { 0, 1, 6, 7, 4, 5, 3, 2, 9, 8, 11, 10, 15, 14, 12, 13 }, - //CH-D + { 1, 0, 5, 4, 7, 2, 3, 6, 8, 9, 11, 10, 12, 14, 13, 15 @@ -6367,7 +6175,7 @@ static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) } - //Set RDDQC pinmux + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_RDDQC_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_RDDQC_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) | @@ -6403,27 +6211,22 @@ static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p) RDDQC_Pattern_A = psra->mr_dq_a_golden; RDDQC_Pattern_B = psra->mr_dq_b_golden; - /* - * TODO - * - * sv also passes mr20_6 and mr20_7 to sa. - * currently, sa does NOT use these two random arguments. - */ + } -#endif /* FOR_DV_SIMULATION_USED == 1 */ +#endif + - // Disable Read DBI vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); #if RDDQC_PINMUX_WORKAROUND - // Translate pin order by MRR bit sel + RDDQCPinmuxWorkaround(p); #endif - // Set golden values into dram MR + { DramcModeRegWriteByRank(p, p->rank, 15, RDDQC_Bit_Ctrl_Lower); DramcModeRegWriteByRank(p, p->rank, 20, RDDQC_Bit_Ctrl_Upper); @@ -6431,14 +6234,14 @@ static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p) DramcModeRegWriteByRank(p, p->rank, 40, RDDQC_Pattern_B); } - //Set golden values into RG, watch out the MR_index of RGs are reference LP4 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN), P_Fld(RDDQC_Bit_Ctrl_Lower, RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER) | P_Fld(RDDQC_Bit_Ctrl_Upper, RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER) | P_Fld(RDDQC_Pattern_A, RDDQCGOLDEN_LP5_MR32_PATTERN_A) | P_Fld(RDDQC_Pattern_B, RDDQCGOLDEN_LP5_MR33_PATTERN_B)); - // Open gated clock, by KaiHsin (DCM) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), @@ -6449,7 +6252,7 @@ static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p) #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK static U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p) { - // Recover MPC Rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRSRK); return 0; @@ -6499,51 +6302,44 @@ static void SetRxDqDqsDelay(DRAMC_CTX_T *p, S16 iDelay) } else { - // Adjust DQM output delay. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), iDelay, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), iDelay, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); //DramPhyReset(p); - // Adjust DQ output delay. + for (ii = 0; ii < 4; ii++) SetRxDqDelay(p, ii, iDelay); } } -/* Issue "RD DQ Calibration" - * 1. SWCMD_CTRL1_RDDQC_LP_ENB = 1 to stop RDDQC burst - * 2. RDDQCEN = 1 for RDDQC - * 3. Wait rddqc_response = 1 - * 4. Read compare result - * 5. RDDQCEN = 0 - */ static U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p) { U32 u4Result = 0, u4TmpResult; DRAM_STATUS_T u4Response = DRAM_FAIL; - //Issue RD DQ calibration + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 1, SWCMD_CTRL1_RDDQC_LP_ENB); - // Trigger and wait + REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN}; REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE}; u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg); - // Read RDDQC compare result + u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP)); - u4Result = (0xFFFF) & ((u4TmpResult) | (u4TmpResult >> 16)); // (BL0~7) | (BL8~15) + u4Result = (0xFFFF) & ((u4TmpResult) | (u4TmpResult >> 16)); #if (FEATURE_RDDQC_K_DMI == TRUE) - // Read DQM compare result + u4TmpResult = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR); u4TmpResult |= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR); u4Result |= (u4TmpResult << 16); #endif - //R_DMRDDQCEN -> 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RDDQCEN); return u4Result; @@ -6587,7 +6383,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, U8 backup_rank, rank_i, u1KnownVref[2]={0xff, 0xff}; BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - // error handling + if (!p) { mcSHOW_ERR_MSG(("context NULL\n")); @@ -6609,7 +6405,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, #endif }; - //Back up dramC register + DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); #if (FEATURE_RDDQC_K_DMI == TRUE) @@ -6672,7 +6468,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, #endif } - //RX_ARDQS_DLY_LAT_EN=1: RX delay will update when GATE_EN=0, and can prevent glitch in ACD. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10), 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0); if (!isLP4_DSC) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10), 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1); @@ -6680,13 +6476,13 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10), 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); - //When doing RxWindowPerbitCal, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); backup_rank = u1GetRank(p); - //defult set result fail. When window found, update the result as oK + if (u1UseTestEngine == PATTERN_TEST_ENGINE) { if (u1RXEyeScanEnable == DISABLE) @@ -6694,7 +6490,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAIL); } - // Something wrong with TA2 pattern -- SI, which causes RX autoK fail. + if (isAutoK == TRUE) { DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); @@ -6702,7 +6498,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, else { #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); #else DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern, 0, TE_NO_UI_SHIFT); #endif @@ -6717,7 +6513,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, DramcRxWinRDDQCInit(p); } - // Intialize, diable RX Vref + u2VrefBegin = 0; u2VrefEnd = 0; u2VrefStep = 1; @@ -6745,7 +6541,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, //mcDUMP_REG_MSG(("\n[dumpRG] %s\n",u1UseTestEngine==PATTERN_RDDQC?"RDDQC":"DramcRxWindowPerbitCal")); #if VENDER_JV_LOG -#if 0 //BU don't want customer knows our RX's ability +#if 0 if (u1UseTestEngine == 1) vPrintCalibrationBasicInfo_ForJV(p); #endif @@ -6763,8 +6559,8 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, { u2VrefBegin = 0; u2VrefEnd = 0; - u1KnownVref[0] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][0];// byte 0 - u1KnownVref[1] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][1];// byte 1 + u1KnownVref[0] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][0]; + u1KnownVref[1] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][1]; if (u1UseTestEngine == PATTERN_TEST_ENGINE && ((u1KnownVref[0] == 0) || (u1KnownVref[1] == 0))) { @@ -6774,12 +6570,12 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, #endif } } - else if (u1AssignedVref != NULL) // need to specify RX Vref and don't scan RX Vref. + else if (u1AssignedVref != NULL) { u2VrefBegin = 0; u2VrefEnd = 0; - u1KnownVref[0] = u1AssignedVref[0]; // byte 0 - u1KnownVref[1] = u1AssignedVref[1]; // byte 1 + u1KnownVref[0] = u1AssignedVref[0]; + u1KnownVref[1] = u1AssignedVref[1]; } else { @@ -6802,7 +6598,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, } else { - u2VrefBegin = 0;//Lewis@20160817: Enlarge RX Vref range for eye scan + u2VrefBegin = 0; u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1; //mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); } @@ -6824,26 +6620,26 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), 1, CA_CMD5_RG_RX_ARCMD_VREF_EN); } - else // Disable RX Vref + else { u2VrefBegin = 0; u2VrefEnd = 0; u2VrefStep = 1; } - //if RDDQD, roughly calibration + if (u1UseTestEngine == PATTERN_RDDQC) u16DelayStep <<= 1; #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) { - // load RX DQS and DQM delay from eMMC + for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) { if (u1VrefScanEnable) { - // load RX Vref from eMMC + #if ( SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL) u2FinalVref[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbitVref_Save[p->channel][p->rank][u1ByteIdx]; #endif @@ -6853,7 +6649,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, iDQMDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQM[p->channel][p->rank][u1ByteIdx]; } - // load RX DQ delay from eMMC + for (u1BitIdx = 0; u1BitIdx < 16; u1BitIdx++) { FinalWinPerBit[u1BitIdx].best_dqdly = p->pSavetimeData->u1RxWinPerbit_DQ[p->channel][p->rank][u1BitIdx]; @@ -6890,7 +6686,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, if (u1VrefScanEnable == TRUE) { - // When only calibrate RX Vref for Rank 0, apply the same value for Rank 1. + for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++) { vSetRank(p, rank_i); @@ -6911,7 +6707,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, mcSHOW_DBG_MSG(("\n")); #if DUMP_TA2_WINDOW_SIZE_RX_TX - //RX + if (u1UseTestEngine == PATTERN_TEST_ENGINE) { U32 u4B0Tatal =0; @@ -6933,7 +6729,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, } #endif - // set dqs delay, (dqm delay) + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), P_Fld((U32)iDQSDlyPerbyte[0], SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), @@ -6943,7 +6739,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), P_Fld((U32)iDQMDlyPerbyte[1], SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); - // set dq delay + for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), @@ -7012,65 +6808,6 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, return DRAM_OK; - // Log example ==> Neec to update - /* ------------------------------------------------------- -Start calculate dq time and dqs time / -Find max DQS delay per byte / Adjust DQ delay to align DQS... ------------------------------------------------------- -bit# 0 : dq time=11 dqs time= 8 -bit# 1 : dq time=11 dqs time= 8 -bit# 2 : dq time=11 dqs time= 6 -bit# 3 : dq time=10 dqs time= 8 -bit# 4 : dq time=11 dqs time= 8 -bit# 5 : dq time=10 dqs time= 8 -bit# 6 : dq time=11 dqs time= 8 -bit# 7 : dq time= 9 dqs time= 6 -----seperate line---- -bit# 8 : dq time=12 dqs time= 7 -bit# 9 : dq time=10 dqs time= 8 -bit#10 : dq time=11 dqs time= 8 -bit#11 : dq time=10 dqs time= 8 -bit#12 : dq time=11 dqs time= 8 -bit#13 : dq time=11 dqs time= 8 -bit#14 : dq time=11 dqs time= 8 -bit#15 : dq time=12 dqs time= 8 -----seperate line---- -bit#16 : dq time=11 dqs time= 7 -bit#17 : dq time=10 dqs time= 8 -bit#18 : dq time=11 dqs time= 7 -bit#19 : dq time=11 dqs time= 6 -bit#20 : dq time=10 dqs time= 9 -bit#21 : dq time=11 dqs time=10 -bit#22 : dq time=11 dqs time=10 -bit#23 : dq time= 9 dqs time= 9 -----seperate line---- -bit#24 : dq time=12 dqs time= 6 -bit#25 : dq time=13 dqs time= 6 -bit#26 : dq time=13 dqs time= 7 -bit#27 : dq time=11 dqs time= 7 -bit#28 : dq time=12 dqs time= 8 -bit#29 : dq time=10 dqs time= 8 -bit#30 : dq time=13 dqs time= 7 -bit#31 : dq time=11 dqs time= 8 -----seperate line---- -================================================== - dramc_rxdqs_perbit_swcal_v2 - channel=2(2:cha, 3:chb) apply = 1 -================================================== -DQS Delay : - DQS0 = 0 DQS1 = 0 DQS2 = 0 DQS3 = 0 -DQ Delay : -DQ 0 = 1 DQ 1 = 1 DQ 2 = 2 DQ 3 = 1 -DQ 4 = 1 DQ 5 = 1 DQ 6 = 1 DQ 7 = 1 -DQ 8 = 2 DQ 9 = 1 DQ10 = 1 DQ11 = 1 -DQ12 = 1 DQ13 = 1 DQ14 = 1 DQ15 = 2 -DQ16 = 2 DQ17 = 1 DQ18 = 2 DQ19 = 2 -DQ20 = 0 DQ21 = 0 DQ22 = 0 DQ23 = 0 -DQ24 = 3 DQ25 = 3 DQ26 = 3 DQ27 = 2 -DQ28 = 2 DQ29 = 1 DQ30 = 3 DQ31 = 1 -_______________________________________________________________ - */ } #if SIMULATION_RX_DVS @@ -7085,7 +6822,7 @@ static U8 DramcRxDVSCal(DRAMC_CTX_T *p, U8 u1byte) u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0); u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0); } - else //byte1 + else { u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1); u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1); @@ -7120,7 +6857,7 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)), }; - // error handling + if (!p) { mcSHOW_ERR_MSG(("context NULL\n")); @@ -7129,16 +6866,16 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("[RX DVS calibration]\n")); - //When doing RxWindowPerbitCal, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1); - //defult set result fail. When window found, update the result as oK + #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//PIC Need to check if need to use UI_SHIFT;//UI_SHIFT + LEN1 + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); #else DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); #endif @@ -7146,14 +6883,14 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) { u16DelayStep = 4; } - // Just for DV SIM test + S16DelayBegin = -80; u16DelayEnd = 100; mcSHOW_DBG_MSG2(("\nRX Delay %d -> %d, step: %d\n", S16DelayBegin, u16DelayEnd, u16DelayStep)); { - // Adjust DQM output delay to 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); @@ -7161,12 +6898,11 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); - // Adjust DQ output delay to 0 - //every 2bit dq have the same delay register address + for (ii = 0; ii < 4; ii++) SetRxDqDelay(p, ii, 0); { - // non-autok flow + for (iDelay = S16DelayBegin; iDelay <= u16DelayEnd; iDelay += u16DelayStep) { SetRxDqDqsDelay(p, iDelay); @@ -7190,7 +6926,7 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) { u1DVS_pass_window[u1ByteIdx] = iDelay - u1DVS_first_pass[u1ByteIdx] - u16DelayStep; - if (u1DVS_pass_window[u1ByteIdx] < 7) //if window size bigger than 7, consider as real pass window. + if (u1DVS_pass_window[u1ByteIdx] < 7) { u1DVS_pass_window[u1ByteIdx] = 0; u1DVS_first_flag[u1ByteIdx] = 0; @@ -7252,7 +6988,7 @@ void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p) u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0)); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0); } - else //byte1 + else { u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1)); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1); @@ -7266,7 +7002,7 @@ void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p) DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF, NORMAL_K); } - if ((DramcRxDVSCal(p, 0) == 1) || (DramcRxDVSCal(p, 1) == 1)) //Prevent set wrong DV dly + if ((DramcRxDVSCal(p, 0) == 1) || (DramcRxDVSCal(p, 1) == 1)) { mcSHOW_ERR_MSG(("Final DVS delay is out of RX window\n")); for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) @@ -7278,7 +7014,7 @@ void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p) { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0); } - else //byte1 + else { vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1); } @@ -7306,8 +7042,7 @@ static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val) U8 u1DLECG_OptionEXT2 = 0; U8 u1DLECG_OptionEXT3 = 0; - // If (RX_PIPE_BYPASS_ENABLE == 1) bypass RX PIPE, so RG_DATLAT_DSEL = RG_DATLAT - // else RG_DATLAT_DSEL = RG_DATLAT - 1 + if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) { u1DATLAT_DSEL = curr_val; @@ -7327,10 +7062,7 @@ static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val) P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); - // Had been adjusted for 868 already. - //(>=8 & <14) set EXT1 =1, EXT2=0, EXT3=0 - //(>= 14 & <19) set EXT1=1, EXT2=1, EXT3=0 - //(>=19) set EXT1=1, EXT2=1, EXT3=1 + u1DLECG_OptionEXT1 = (curr_val >= 8)? (1): (0); u1DLECG_OptionEXT2 = (curr_val >= 14)? (1): (0); u1DLECG_OptionEXT3 = (curr_val >= 19)? (1): (0); @@ -7356,7 +7088,7 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) U8 ucfirst, ucbegin, ucsum, ucbest_step; //ucpipe_num = 0; U16 u2DatlatBegin; - // error handling + if (!p) { mcSHOW_ERR_MSG(("context NULL\n")); @@ -7371,29 +7103,23 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) #endif mcSHOW_DBG_MSG(("[RxdatlatCal]\n")); - // pre-save - // 0x07c[6:4] DATLAT bit2-bit0 + u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); - //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL); - // init best_step to default + ucbest_step = (U8) u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), MISC_SHU_RDAT_DATLAT); mcSHOW_DBG_MSG2(("DATLAT Default: 0x%x\n", ucbest_step)); //mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step)); - // 1.set DATLAT 0-15 (0-21 for MT6595) - // 2.enable engine1 or engine2 - // 3.check result ,3~4 taps pass - // 4.set DATLAT 2nd value for optimal - // Initialize ucfirst = 0xff; ucbegin = 0; ucsum = 0; - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); u2DatlatBegin = 0; #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) @@ -7494,33 +7220,22 @@ DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p) return DRAM_OK; } -#endif // SIMULATION_DATLAT +#endif #if SIMULATION_TX_PERBIT -//============================================================= -///// DramC TX perbi calibration ----------Begin-------------- -//============================================================= -//------------------------------------------------------------------------- -/** DramcTxWindowPerbitCal (v2) - * TX DQS per bit SW calibration. - * @param p Pointer of context created by DramcCtxCreate. - * @param apply (U8): 0 don't apply the register we set 1 apply the register we set ,default don't apply. - * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL - */ -//------------------------------------------------------------------------- #if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED) #define TX_VREF_RANGE_BEGIN 0 -#define TX_VREF_RANGE_END 2 // binary 110010 +#define TX_VREF_RANGE_END 2 #define TX_VREF_RANGE_STEP 2 #else #define TX_VREF_RANGE_BEGIN 16 -#define TX_VREF_RANGE_END 50 // binary 110010 +#define TX_VREF_RANGE_END 50 #define TX_VREF_RANGE_STEP 2 #endif -#define TX_DQ_UI_TO_PI_TAP 64 // 1 PI = tCK/64, total 128 PI, 1UI = 32 PI -#define TX_PHASE_DQ_UI_TO_PI_TAP 32 // 1 PI = tCK/64, total 128 PI, 1UI = 32 PI for DDR800 semi open loop mode +#define TX_DQ_UI_TO_PI_TAP 64 +#define TX_PHASE_DQ_UI_TO_PI_TAP 32 #define LP4_TX_VREF_DATA_NUM 50 #define LP4_TX_VREF_PASS_CONDITION 0 #define TX_PASS_WIN_CRITERIA 7 @@ -7587,12 +7302,12 @@ void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter *pu1PI =u1PI; } - if (u1IsLP4Div4DDR800(p) /*DDR800 close loop mode*/ || u1IsPhaseMode(p)) + if (u1IsLP4Div4DDR800(p) || u1IsPhaseMode(p)) u164PIto1UI = 0; else u164PIto1UI = 1; - u2TmpValue = (uiDelay /u1PiTap)<<u164PIto1UI; // 1:8 mode for 2UI carry, DDR800 1:4 mode for 1UI carry + u2TmpValue = (uiDelay /u1PiTap)<<u164PIto1UI; if (u1AdjustPIToCenter && (pu1PI != NULL) && (eDdr800Mode == CLOSE_LOOP_MODE)) { @@ -7617,17 +7332,17 @@ void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter *pu1UISmall_DQ = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large); *pu1UILarge_DQ = (u2TmpValue >> u1Small_ui_to_large); #endif - // calculate DQ OE according to DQ UI + { u2TmpValue -= u1TxDQOEShift; } - if(((u1MR03Value[p->dram_fsp]&0x80)>>7)==1) //if WDBI is on, OE_DLY don't need to shift 1 MCK with DLY + if(((u1MR03Value[p->dram_fsp]&0x80)>>7)==1) { if (vGet_Div_Mode(p) == DIV4_MODE) - u2DQOE_shift = 4; //OE_shift = OE_shift - 3(original OE position) + 4 (MCK) + u2DQOE_shift = 4; else - u2DQOE_shift = 8; //OE_shift = OE_shift - 3(original OE position) + 8 (MCK) + u2DQOE_shift = 8; u2TmpValue += u2DQOE_shift; } @@ -7682,14 +7397,14 @@ static void TxPrintWidnowInfo(DRAMC_CTX_T *p, PASS_WIN_DATA_T WinPerBitData[]) static void TXPerbitCalibrationInit(DRAMC_CTX_T *p, U8 calType) { - //Set TX delay chain to 0 + if (calType != TX_DQ_DQS_MOVE_DQM_ONLY) { #if 1 #if PINMUX_AUTO_TEST_PER_BIT_TX if(gTX_check_per_bit_flag == 1) { - //not reset delay cell + } else #endif @@ -7722,25 +7437,13 @@ static void TXPerbitCalibrationInit(DRAMC_CTX_T *p, U8 calType) } - //Use HW TX tracking value - //R_DMARPIDQ_SW :drphy_conf (0x170[7])(default set 1) - // 0: DQS2DQ PI setting controlled by HW - //R_DMARUIDQ_SW : Dramc_conf(0x156[15])(default set 1) - // 0: DQS2DQ UI setting controlled by HW - ///TODO: need backup original setting? - //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW); - //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW); } #define TX_TDQS2DQ_PRE_CAL 0 #if TX_TDQS2DQ_PRE_CAL -// (1) DDR800 1:4 mode -// (2) DDR1200/1600 1:4 mode -// (3) 1:8 mode -// The 3 condition have different MCK2UI/UI2PI. Therefore, TX DQS2DQ should be record separately. -// Here, we record (2) and (3). DDR800 1:4 skip recording DQS2DQ. -U16 u2DQS2DQ_Pre_Cal[CHANNEL_NUM][RANK_MAX][2/*DIV_Mode*/] = {0}; + +U16 u2DQS2DQ_Pre_Cal[CHANNEL_NUM][RANK_MAX][2] = {0}; #endif static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U16 *pu2Begin, U16 *pu2End) @@ -7764,15 +7467,12 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca u1UI2PI = 5; - // find smallest DQS delay + for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) { - ucdq_ui_large_bak[u1ByteIdx] = (u4RegValue_TXDLY >> (u1ByteIdx << 2)) & 0x7;// MCK - ucdq_ui_small_bak[u1ByteIdx] = (u4RegValue_dly >> (u1ByteIdx << 2)) & 0x7;// UI - //wrlevel_dqs_final_delay[p->rank][u1ByteIdx] ==> PI + ucdq_ui_large_bak[u1ByteIdx] = (u4RegValue_TXDLY >> (u1ByteIdx << 2)) & 0x7; + ucdq_ui_small_bak[u1ByteIdx] = (u4RegValue_dly >> (u1ByteIdx << 2)) & 0x7; - //LP4 : Virtual Delay = 256 * MCK + 32*UI + PI; - //LP3 : Virtual Delay = 128 * MCK + 32*UI + PI; u2TempVirtualDelay = (((ucdq_ui_large_bak[u1ByteIdx] << u1MCK2UI) + ucdq_ui_small_bak[u1ByteIdx]) << u1UI2PI) + wrlevel_dqs_final_delay[p->rank][u1ByteIdx]; if (u2TempVirtualDelay < u2SmallestVirtualDelay) @@ -7809,17 +7509,17 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca #if TX_K_DQM_WITH_WDBI if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) { - // DBI on, calibration range -1MCK + u2DQDelayBegin -= (1 << (u1MCK2UI + 5)); } #endif - /* Scan range: 1MCK */ + u2DQDelayEnd = u2DQDelayBegin + ((1 << u1MCK2UI) << u1UI2PI); *pu2Begin = u2DQDelayBegin; *pu2End = u2DQDelayEnd; - #if 0//TX_TDQS2DQ_PRE_CAL + #if 0 mcSHOW_DBG_MSG(("TXScanRange_PI %d~%d\n", u2DQDelayBegin, u2DQDelayEnd)); #endif } @@ -7834,13 +7534,13 @@ static void TXScanRange_Vref(DRAMC_CTX_T *p, U8 u1VrefScanEnable, U16* pu2Range, #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL) if (p->femmc_Ready == 1) { - // if fast K, use TX Vref that saved. + u2VrefBegin = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank]; u2VrefEnd = u2VrefBegin + 1; } #endif } - else //LPDDR3, the for loop will only excute u2VrefLevel=TX_VREF_RANGE_END/2. + else { u2VrefBegin = 0; u2VrefEnd = 0; @@ -7914,14 +7614,14 @@ static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8 //if((u1VrefPassBegin_Final !=LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd_Final!=LP4_TX_VREF_BOUNDARY_NOT_READY)) if (u1MaxVerfPassNum > 0) { - // vref pass window found + u2FinalVref = (u1VrefPassBegin_Final + u1VrefPassEnd_Final) >> 1; mcSHOW_DBG_MSG(("[TxChooseVref] Window > %d, Vref (%d~%d), Final Vref %d\n", LP4_TX_VREF_PASS_CONDITION, u1VrefPassBegin_Final, u1VrefPassEnd_Final, u2FinalVref)); } else #endif { - // not vref found + for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++) { if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > u1WinSizeOfWorseBit) || @@ -7949,7 +7649,7 @@ static void DramcTXSetVref(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefValue) u1TempOPValue = ((u1VrefValue & 0x3f) | (u1VrefRange << 6)); u1MR14Value[p->channel][p->rank][p->dram_fsp] = u1TempOPValue; - //For TX VREF of different byte + DramcModeRegWriteByRank(p, p->rank, 14, u1TempOPValue); @@ -7987,17 +7687,17 @@ void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calTy { if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQM_ONLY) { - //make a copy to dramc reg for TX DQ tracking used + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), P_Fld(ucdq_pi[0], SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_pi[1], SHURK_PI_RK0_ARPI_DQ_B1)); - // Source DQ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1), P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1) | P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0)); - // Target DQ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2), P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1) | P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0)); @@ -8008,7 +7708,7 @@ void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calTy vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), P_Fld(ucdqm_pi[0], SHURK_PI_RK0_ARPI_DQM_B0) | P_Fld(ucdqm_pi[1], SHURK_PI_RK0_ARPI_DQM_B1)); - // Target DQM + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5), P_Fld(ucdqm_pi[1], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1) | P_Fld(ucdqm_pi[0], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0)); @@ -8016,8 +7716,7 @@ void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calTy } -#if 0// for LP3 , TX tracking will be disable, don't need to set DQ delay in DramC. - ///TODO: check LP3 byte mapping of dramC +#if 0 vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + (CHANNEL_A << POS_BANK_NUM), \ P_Fld(ucdq_final_pi[0], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[1], SHURK0_PI_RK0_ARPI_DQ_B1)); @@ -8026,7 +7725,7 @@ void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calTy #endif } -#endif //End ENABLE_TX_TRACKING +#endif #if !BYPASS_CALIBRATION static @@ -8041,7 +7740,7 @@ void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdq_ui_large[], U8 u P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1)); - // DLY_DQ[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ P_Fld(ucdq_ui_small[0], SHURK_SELPH_DQ2_DLY_DQ0) | P_Fld(ucdq_ui_small[1], SHURK_SELPH_DQ2_DLY_DQ1) | @@ -8067,7 +7766,7 @@ void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 P_Fld(ucdqm_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | P_Fld(ucdqm_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); - // DLY_DQM[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), P_Fld(ucdqm_ui_small[0], SHURK_SELPH_DQ3_DLY_DQM0) | P_Fld(ucdqm_ui_small[1], SHURK_SELPH_DQ3_DLY_DQM1) | @@ -8102,13 +7801,13 @@ static void Tx_Auto_K_Init(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca if (calType == TX_DQ_DQS_MOVE_DQ_DQM) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), - P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN) | //enable TX DQ auto K - P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN)); //enable TX DQM auto K + P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN) | + P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), - P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | //Set begin position of DQ B0 - P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | //Set begin position of DQ B1 - P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | //Set begin position of DQM B0 - P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); //Set begin position of DQM B1 + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | + P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); } else if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) { @@ -8125,18 +7824,18 @@ static void Tx_Auto_K_Init(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT)); } - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW); //Switch PI SW mode to HW mode (control by DRAMC not APHY) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), - P_Fld(u1PI_Len, TX_ATK_SET1_TX_ATK_PI_LEN) | //enable TX auto k len - P_Fld(pi_thrd, TX_ATK_SET1_TX_ATK_PASS_PI_THRD)); //Set threshold of PI pass window -#if (fcFOR_CHIP_ID == fcIPM) //Fix at Mar_gaux - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), early_break, TX_ATK_SET1_TX_ATK_EARLY_BREAK); //Enable early break + P_Fld(u1PI_Len, TX_ATK_SET1_TX_ATK_PI_LEN) | + P_Fld(pi_thrd, TX_ATK_SET1_TX_ATK_PASS_PI_THRD)); +#if (fcFOR_CHIP_ID == fcIPM) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), early_break, TX_ATK_SET1_TX_ATK_EARLY_BREAK); #endif { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | - P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN)); //Enable OE auto adjust + P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN)); } #if TX_AUTO_K_DEBUG_ENABLE @@ -8173,11 +7872,11 @@ static void Tx_Auto_K_complete_check(DRAMC_CTX_T *p) static void Tx_Auto_K_Clear(DRAMC_CTX_T *p) { - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_TRIG); //Disable Tx auto K + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_TRIG); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMARPIDQ_SW); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_DBG_EN); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_CLR); //Clear state machine + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_CLR); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_CLR); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), P_Fld(0x0, TX_ATK_SET1_TX_ATK_PI_LEN) | @@ -8192,7 +7891,7 @@ static void Tx_Auto_K_Clear(DRAMC_CTX_T *p) static void Tx_Auto_K_DQM_Workaround(DRAMC_CTX_T *p) { //U32 u4DQM_MCK, u4DQM_UI, u4DQM_PI_B0, u4DQM_PI_B1; - //Set RK1 DQM DLY to RK0 + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), u4DQM_MCK_RK1_backup); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), u4DQM_UI_RK1_backup); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQM_PI_RK1_backup[0]); @@ -8201,7 +7900,7 @@ static void Tx_Auto_K_DQM_Workaround(DRAMC_CTX_T *p) static void Tx_Auto_K_DQ_Workaround(DRAMC_CTX_T *p) { //U32 u4DQ_MCK, u4DQ_UI, u4DQ_PI_B0, u4DQ_PI_B1; - //Set RK1 DQM DLY to RK0 + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), u4DQ_MCK_RK1_backup); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), u4DQ_UI_RK1_backup); vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQ_PI_RK1_backup[0]); @@ -8269,7 +7968,7 @@ void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff) S8 u1TXShiftMCK; u1TXShiftMCK = (u1OnOff)? -1: 1; - DramcWriteShiftMCKForWriteDBI(p, u1TXShiftMCK); //Tx DQ/DQM -1 MCK for write DBI ON + DramcWriteShiftMCKForWriteDBI(p, u1TXShiftMCK); SetDramModeRegForWriteDBIOnOff(p, p->dram_fsp, u1OnOff); DramcWriteDBIOnOff(p, u1OnOff); @@ -8295,7 +7994,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION U16 uiDelay, u2DQDelayBegin, u2DQDelayEnd, u2DQDelayStep = 1; U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large, ucdq_oen_ui_small, ucdq_oen_ui_large; - U8 ucdq_ui_small_reg_value, u1UpdateRegUI; // for UI and TXDLY change check, if different , set reg. + U8 ucdq_ui_small_reg_value, u1UpdateRegUI; U8 ucdq_reg_pi[DQS_BYTE_NUMBER], ucdq_reg_ui_large[DQS_BYTE_NUMBER], ucdq_reg_ui_small[DQS_BYTE_NUMBER]; U8 ucdq_reg_oen_ui_large[DQS_BYTE_NUMBER], ucdq_reg_oen_ui_small[DQS_BYTE_NUMBER]; @@ -8303,8 +8002,8 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION U8 ucdq_reg_dqm_pi[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_ui_small[DQS_BYTE_NUMBER] = {0}; U8 ucdq_reg_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0}; - #if 1//TX_DQM_CALC_MAX_MIN_CENTER - U16 u2DQM_Delay; // LP4 only + #if 1 + U16 u2DQM_Delay; U16 u2Center_min[DQS_BYTE_NUMBER] = {0}, u2Center_max[DQS_BYTE_NUMBER] = {0}; #endif U8 u1EnableDelayCell = 0; @@ -8381,15 +8080,15 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION TXScanRange_PI(p, calType, &u2DQDelayBegin, &u2DQDelayEnd); TXScanRange_Vref(p, u1VrefScanEnable, &u2FinalRange, &u2VrefBegin, &u2VrefEnd, &u2VrefStep); - //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAIL); if (isAutoK) { #if TX_AUTO_K_SUPPORT - //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); //Let CLK always on + //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); + - //Set base address of TX MCK and UI u1UpdateRegUI = 1; uiDelay = u2DQDelayBegin; u1PI_Len = 3; @@ -8430,7 +8129,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION #if TX_AUTO_K_WORKAROUND if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1backup_Rank == 1)) - Tx_Auto_K_DQM_Workaround(p); //Set best DLY value of RK1 DQM to RK0 DQM + Tx_Auto_K_DQM_Workaround(p); #endif } if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) @@ -8441,7 +8140,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION #if TX_AUTO_K_WORKAROUND if ((calType == TX_DQ_DQS_MOVE_DQM_ONLY) && (u1backup_Rank == 1)) - Tx_Auto_K_DQ_Workaround(p); //Set best DLY value of RK1 DQ to RK0 DQ + Tx_Auto_K_DQ_Workaround(p); #endif } @@ -8450,7 +8149,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION p->rank = 1; #endif - //Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); //u1PI_Len = 1 means that PI len is 64 PI + #endif } else @@ -8495,14 +8194,14 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION #endif { #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); #else DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); #endif for (u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep) { - // SET tx Vref (DQ) here, LP3 no need to set this. + if (u1VrefScanEnable) { #if (!REDUCE_LOG_FOR_PRELOADER) @@ -8523,7 +8222,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION mcSHOW_DBG_MSG(("\n\tTX Vref Scan disable\n")); } - // initialize parameters + uiFinishCount = 0; u2TempWinSum = 0; ucdq_ui_small_reg_value = 0xff; @@ -8539,20 +8238,18 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION if (isAutoK) { #if TX_AUTO_K_SUPPORT - Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); //u1PI_Len = 1 means that PI len is 64 PI - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_TRIG); //TX Auto K start + Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_TRIG); #endif } else { - //Move DQ delay , 1 PI = tCK/64, total 128 PI, 1UI = 32 PI - //For data rate 3200, max tDQS2DQ is 2.56UI (82 PI) - //For data rate 4266, max tDQS2DQ is 3.41UI (109 PI) + for (uiDelay = u2DQDelayBegin; uiDelay < u2DQDelayEnd; uiDelay += u2DQDelayStep) { TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); - // Check if TX UI changed, if not change , don't need to set reg again + if (ucdq_ui_small_reg_value != ucdq_ui_small) { u1UpdateRegUI = 1; @@ -8592,21 +8289,16 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION u4err_value = 0; #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT); + u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); #else - //audio + xtalk pattern + DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); #endif - //audio + xtalk pattern - //u4err_value = 0; - //DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0); - //u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); - //DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1); - //u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); + if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) { @@ -8621,7 +8313,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION #endif } - // check fail bit ,0 ok ,others fail + for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) { u4fail_bit = u4err_value & ((U32)1 << u1BitIdx); @@ -8648,7 +8340,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION if (WinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) { - if (u4fail_bit == 0) //compare correct: pass + if (u4fail_bit == 0) { WinPerBit[u1BitIdx].first_pass = uiDelay; @@ -8673,7 +8365,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION } else if (WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA) { - if (u4fail_bit != 0) //compare error : fail + if (u4fail_bit != 0) { WinPerBit[u1BitIdx].last_pass = uiDelay - u2DQDelayStep; } @@ -8696,17 +8388,17 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION (WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass), (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass))); } - //if window size bigger than TX_PASS_WIN_CRITERIA, consider as real pass window. If not, don't update finish counte and won't do early break; + if (((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) > TX_PASS_WIN_CRITERIA) - ||((u2DQDelayStep>=16) && (WinPerBit[u1BitIdx].first_pass!=PASS_RANGE_NA))) //DDR400 stepsize is too big, can't find last pass. + ||((u2DQDelayStep>=16) && (WinPerBit[u1BitIdx].first_pass!=PASS_RANGE_NA))) uiFinishCount |= (1 << u1BitIdx); - //update bigger window size + VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass; VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass; } - //reset tmp window + WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA; WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA; } @@ -8721,7 +8413,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION } } - //if all bits widnow found and all bits turns to fail again, early break; + if (uiFinishCount == 0xffff) { vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK); @@ -8732,7 +8424,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION mcSHOW_DBG_MSG3(("TX calibration finding left boundary early break. PI DQ delay=0x%2x\n", uiDelay)); #endif #endif - break; //early break + break; } } } @@ -8747,9 +8439,6 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION #endif } - // (1) calculate per bit window size - // (2) find out min win of all DQ bits - // (3) calculate perbit window center u1min_winsize = 0xff; u1min_bit = 0xff; for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) @@ -8795,7 +8484,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION u1min_winsize = VrefWinPerBit[u1BitIdx].win_size; } - u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; //Sum of CA Windows for vref selection + u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; #if VENDER_JV_LOG if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) @@ -8805,7 +8494,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION #endif - // calculate per bit window position and print + VrefWinPerBit[u1BitIdx].win_center = (VrefWinPerBit[u1BitIdx].first_pass + VrefWinPerBit[u1BitIdx].last_pass) >> 1; #if PINMUX_AUTO_TEST_PER_BIT_TX gFinalTXPerbitFirstPass[p->channel][u1BitIdx] = VrefWinPerBit[u1BitIdx].first_pass; @@ -8864,13 +8553,12 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION } #endif - if (u1VrefScanEnable == 0)// ..if time domain (not vref scan) , calculate window center of all bits. + if (u1VrefScanEnable == 0) { - // Calculate the center of DQ pass window - // Record center sum of each byte + for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) { - #if 1//TX_DQM_CALC_MAX_MIN_CENTER + #if 1 u2Center_min[u1ByteIdx] = 0xffff; u2Center_max[u1ByteIdx] = 0; #endif @@ -8897,7 +8585,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION } } - // SET tx Vref (DQ) = u2FinalVref, LP3 no need to set this. + if (u1VrefScanEnable) { #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL @@ -8916,7 +8604,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION } #ifdef FOR_HQA_TEST_USED - // LP4 DQ time domain || LP3 DQ_DQM time domain + if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) { gFinalTXPerbitWin_min_max[p->channel][p->rank] = u1min_winsize; @@ -8930,8 +8618,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION } #endif - // LP3 only use "TX_DQ_DQS_MOVE_DQ_DQM" scan - // first freq 800(LP4-1600) doesn't support jitter meter(data < 1T), therefore, don't use delay cell + if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (p->frequency >= 1333) && (p->u2DelayCellTimex100 != 0)) { u1EnableDelayCell = 1; @@ -8939,23 +8626,22 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION //mcDUMP_REG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100)); } - //Calculate the center of DQ pass window - //average the center delay + for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) { mcSHOW_DBG_MSG((" == TX Byte %d ==\n", u1ByteIdx)); //mcDUMP_REG_MSG((" == TX Byte %d ==\n", u1ByteIdx)); - u2DQM_Delay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx]) >> 1); //(max +min)/2 + u2DQM_Delay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx]) >> 1); if (u1EnableDelayCell == 0) { uiDelay = u2DQM_Delay; } - else// if(calType == TX_DQ_DQS_MOVE_DQ_ONLY) + else { - uiDelay = u2Center_min[u1ByteIdx]; // for DQ PI delay , will adjust with delay cell + uiDelay = u2Center_min[u1ByteIdx]; + - // calculate delay cell perbit for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) { u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; @@ -9057,7 +8743,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION RegLogEnable = 1; #endif - /* p->rank = RANK_0, save to Reg Rank0 and Rank1, p->rank = RANK_1, save to Reg Rank1 */ + for (u1RankIdx = p->rank; u1RankIdx < RANK_MAX; u1RankIdx++) { vSetRank(p, u1RankIdx); @@ -9107,7 +8793,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION P_Fld(ucdq_reg_pi[0], TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | P_Fld(ucdq_reg_pi[1], TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | P_Fld(ucdq_reg_dqm_pi[0], TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | - P_Fld(ucdq_reg_dqm_pi[1], TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); //If TX auto-k is enable, TX_PI will be switch to PI_INIT + P_Fld(ucdq_reg_dqm_pi[1], TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); #endif #endif } @@ -9133,13 +8819,13 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION mcSHOW_DBG_MSG4(("[TxWindowPerbitCal] Done\n\n")); #if 0 - vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_PADCTL4), 1, PADCTL4_CKEFIXON); // test only + vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_PADCTL4), 1, PADCTL4_CKEFIXON); #endif return DRAM_OK; } -#endif //SIMULATION_TX_PERBIT +#endif #if ENABLE_EYESCAN_GRAPH void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) @@ -9154,7 +8840,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) U32 uiFinishCount; U16 u2TempWinSum, u2tx_window_sum=0; U32 u4err_value, u4fail_bit; - #if 1//TX_DQM_CALC_MAX_MIN_CENTER + #if 1 U16 u2Center_min[DQS_BYTE_NUMBER],u2Center_max[DQS_BYTE_NUMBER]; #endif @@ -9183,15 +8869,15 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) //if (gTX_EYE_Scan_only_higheset_freq_flag==1 && p->frequency != u2DFSGetHighestFreq(p)) return; - //backup register value + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); backup_u1MR14Value = u1MR14Value[p->channel][p->rank][p->dram_fsp]; - if (gFinalTXVrefDQ[p->channel][p->rank] ==0) //Set final TX Vref as default value + if (gFinalTXVrefDQ[p->channel][p->rank] ==0) gFinalTXVrefDQ[p->channel][p->rank] = u1MR14Value[p->channel][p->rank][p->dram_fsp]; - //set initial values + for(u1vrefidx=0; u1vrefidx<=VREF_VOLTAGE_TABLE_NUM_LP5-1;u1vrefidx++) { for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) @@ -9255,7 +8941,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) mcSHOW_DBG_MSG3(("\nTX Vref %d -> %d, step: %d\n", u2VrefBegin, u2VrefEnd, u2VrefStep)); #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 + DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); #else DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); #endif @@ -9263,12 +8949,11 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) for(u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep) { - //set vref -//fra u1MR14Value[p->channel][p->rank][p->dram_fsp] = (u2VrefLevel | (u2VrefRange<<6)); + DramcTXSetVref(p, u2VrefRange, u2VrefLevel); mcSHOW_DBG_MSG3(("\n\n Set TX VrefRange %d, VrefLevel=%d\n", u2VrefRange, u2VrefLevel)); - // initialize parameters + uiFinishCount = 0; u2TempWinSum =0; @@ -9328,20 +9013,13 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT); u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); #else - //audio + xtalk pattern + DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); #endif - // audio + xtalk pattern - //u4err_value=0; - //DramcEngine2SetPat(p,TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); - //u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); - //DramcEngine2SetPat(p,TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); - //u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); - // check fail bit ,0 ok ,others fail for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) { u4fail_bit = u4err_value&((U32)1<<u1BitIdx); @@ -9353,7 +9031,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) if(WinPerBit[u1BitIdx].first_pass== PASS_RANGE_NA) { - if(u4fail_bit==0) //compare correct: pass + if(u4fail_bit==0) { WinPerBit[u1BitIdx].first_pass = uiDelay; u1pass_in_this_vref_flag[u1BitIdx] = 1; @@ -9361,7 +9039,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) } else if(WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA) { - if(u4fail_bit !=0) //compare error : fail + if(u4fail_bit !=0) { WinPerBit[u1BitIdx].last_pass = (uiDelay-1); } @@ -9374,11 +9052,11 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) { if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass -VrefWinPerBit[u1BitIdx].first_pass)) { - //if window size bigger than 7, consider as real pass window. If not, don't update finish counte and won't do early break; + if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >7) uiFinishCount |= (1<<u1BitIdx); - //update bigger window size + VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass; VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass; } @@ -9390,18 +9068,17 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass; gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass; #else -//fra gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass + tx_pi_delay[u1BitIdx/8]-32; -//fra gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass + tx_pi_delay[u1BitIdx/8]-32; + gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].first_pass; gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].last_pass; mcSHOW_DBG_MSG3(("VrefRange %d, VrefLevel=%d, u1BitIdx=%d, index=%d (%d, %d)==\n",u2VrefRange,u2VrefLevel, u1BitIdx, EyeScan_index[u1BitIdx], gEyeScan_Min[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]], gEyeScan_Max[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]])); - gEyeScan_MinMax_store_delay[u1BitIdx/8] = tx_pi_delay[u1BitIdx/8]-32; /* save this information for HQA pass/fail judgement used */ + gEyeScan_MinMax_store_delay[u1BitIdx/8] = tx_pi_delay[u1BitIdx/8]-32; #endif EyeScan_index[u1BitIdx]=EyeScan_index[u1BitIdx]+1; } - //reset tmp window + WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA; WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA; } @@ -9421,7 +9098,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) min_winsize = VrefWinPerBit[u1BitIdx].win_size; } - u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; //Sum of CA Windows for vref selection + u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; gEyeScan_WinSize[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size; @@ -9441,11 +9118,10 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) u2FinalRange = u2VrefRange; u2FinalVref = u2VrefLevel; - //Calculate the center of DQ pass window - // Record center sum of each byte + for (u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) { - #if 1//TX_DQM_CALC_MAX_MIN_CENTER + #if 1 u2Center_min[u1ByteIdx] = 0xffff; u2Center_max[u1ByteIdx] = 0; #endif @@ -9476,17 +9152,16 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) { - if (u1pass_in_this_vref_flag[u1BitIdx]) gEyeScan_ContinueVrefHeight[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP; //count pass number of continue vref + if (u1pass_in_this_vref_flag[u1BitIdx]) gEyeScan_ContinueVrefHeight[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP; } } DramcEngine2End(p); - //Calculate the center of DQ pass window - //average the center delay + for (u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) { - uiDelay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx])>>1); //(max +min)/2 + uiDelay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx])>>1); #if VENDER_JV_LOG || defined(RELEASE) gEyeScan_CaliDelay[u1ByteIdx] = uiDelay; @@ -9496,10 +9171,10 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) } - //restore to orignal value + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); - //restore Vref + { u2VrefRange = backup_u1MR14Value>>6; u2VrefLevel = backup_u1MR14Value & 0x3f; @@ -9544,7 +9219,7 @@ void DramcTxOECalibration(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] DMA\n")); #endif - //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAIL); #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION) @@ -9573,11 +9248,11 @@ void DramcTxOECalibration(DRAMC_CTX_T *p) vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | \ P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); - // DLY_DQ[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) | \ P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1) ); - // DLY_DQM[2:0] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) | \ P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1)); @@ -9589,10 +9264,7 @@ void DramcTxOECalibration(DRAMC_CTX_T *p) ((_reg & Fld2Msk32(_fld)) >> Fld_shft(_fld)) static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) { - /* In case to prevent illegal command during JM/8Phase cal and Duty cal, - * OE for CK/CKE/CA/CS will be disabled. But CK/CKE has timing requirement. - * Adding this flow to fix it - */ + static U32 u4CA_CMD2_backup = 0; static U32 u4SHU_CA_CMD13_backup = 0; static U32 u4CS_CTRL_backup = 0; @@ -9623,24 +9295,23 @@ static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) } u4backup_done = 1; - /* CS/CKE/CA */ - /* CKE need disable before CS */ + if (!isLP4_DSC) { - /* CKE/CA */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \ | P_Fld( 1, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \ | P_Fld( 0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \ | P_Fld( 0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); - /* CS */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL), P_Fld( 0, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)); } else { - /* CKE */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld( 0, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \ | P_Fld( 1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1)); - /* CS/CA */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \ | P_Fld( 1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) \ | P_Fld( 0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \ @@ -9650,21 +9321,21 @@ static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) mcDELAY_US(1); if (!isLP4_DSC) { - /* CLK */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA) \ | P_Fld( 1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA)); - /* CLKB */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( 0, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \ | P_Fld( 1, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA)); } else { - /* CLK */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0, B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1) \ | P_Fld( 1, B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1)); - /* CLKB */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld( 0, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1) \ | P_Fld( 1, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1)); } @@ -9695,7 +9366,7 @@ static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) u4CSOE_TieSel = fld_val(u4CS_CTRL_backup, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0); u4CSOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA); u4CKEOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA); - /* CKE OE controlled by CS OE */ + u4CKEOE_TieEN = u4CSOE_TieEn; } else @@ -9708,33 +9379,32 @@ static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) if (!isLP4_DSC) { - /* CLK */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( u4CKOE_TieSel, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA) \ | P_Fld( u4CKOE_TieEn, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA)); - /* CLKB */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( u4CKBOE_TieSel, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ | P_Fld( u4CKBOE_TieEn, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA)); } else { - /* CLK */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( u4CKOE_TieSel, B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1) \ | P_Fld( u4CKOE_TieEn, B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1)); - /* CLKB */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld( u4CKBOE_TieSel, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \ | P_Fld( u4CKBOE_TieEn, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1)); } mcDELAY_US(1); - /* CS/CKE/CA */ - /* CS need enable before CKE */ + if (!isLP4_DSC) { - /* CS */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL), P_Fld( u4CSOE_TieSel, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)); - /* CKE/CA */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( u4CKEOE_TieSel, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \ | P_Fld( u4CSOE_TieEn, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \ | P_Fld( u4CAOE_TieSel, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \ @@ -9742,12 +9412,12 @@ static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) } else { - /* CS/CA */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( u4CSOE_TieSel, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \ | P_Fld( u4CSOE_TieEn, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) \ | P_Fld( u4CAOE_TieSel, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \ | P_Fld( u4CAOE_TieEn, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1)); - /* CKE */ + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld( u4CKEOE_TieSel, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \ | P_Fld( u4CKEOE_TieEN, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1)); } @@ -9760,7 +9430,7 @@ static void OEDisable(DRAMC_CTX_T *p) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; - //OE disable - start + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), P_Fld( 0 , B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 ) \ | P_Fld( 1 , B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0 ) \ | P_Fld( 0 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \ @@ -9809,11 +9479,11 @@ static void OEDisable(DRAMC_CTX_T *p) | P_Fld( 1 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA )); } - //OE disable - end + } #ifdef FOR_HQA_TEST_USED -// P_lm_r is 6nm, use same table with M_rg__x + VCORE_DELAYCELL_T gVcoreDelayCellTable[49]={ {500000, 512}, {506250, 496}, {512500, 482}, @@ -9904,28 +9574,20 @@ static U16 GetVcoreDelayCellTimeFromTable(DRAMC_CTX_T *p) } #endif -//------------------------------------------------------------------------- -/** DramcJmeterCalib - * start MIOCK jitter meter. - * @param p Pointer of context created by DramcCtxCreate. - * @param *pJmtrInfo DQSIEN signal high/low level transaction status - * @param u2JmDlyStep Clk delay step w/ DQSIEN signal - */ -//------------------------------------------------------------------------- + #if ENABLE_8PHASE_CALIBRATION || defined(ENABLE_MIOCK_JMETER) static void DramcJmeterInit(DRAMC_CTX_T *p, U8 u1IsJmtrK) { OEDisable(p); - //DramcHWGatingOnOff(p, 0); // disable Gating tracking for DQS PI, Remove to vApplyConfigBeforeCalibration + //DramcHWGatingOnOff(p, 0); if(u1IsJmtrK != TRUE) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN)); } -#if 0 // 8-Phase calib must to do before DLL init for test only - //@A60868, Reset PI code to avoid 8-phase offset +#if 0 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); @@ -9933,23 +9595,18 @@ static void DramcJmeterInit(DRAMC_CTX_T *p, U8 u1IsJmtrK) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); - //@A60868, End - // @A60868, DQSIEN PI offset clear to 0 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6), 0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6), 0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6), 0, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA); #endif - // @A60868 for *RANK_SEL_SER_EN* = 0 to DA_RX_ARDQ_RANK_SEL_TXD_*[0] - // for *RANK_SEL_SER_EN* = 1 to DA_RX_ARDQ_RANK_SEL_TXD_*[7:0] - // The *RANK_SEL_SER_EN* = 0 is old mode. - // The *RANK_SEL_SER_EN* = 1 is new mode when background no any access. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA); - //@Darren, DLL off to stable fix middle transion from high to low or low to high at high vcore + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) @@ -9957,25 +9614,19 @@ static void DramcJmeterInit(DRAMC_CTX_T *p, U8 u1IsJmtrK) vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1)); - //MCK4X CG + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMDQSIENCG_EN); - //@A60868, DQS PI mode for JMTR - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), 0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0); // DQS PI mode - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), 0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1); // DQS PI mode - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); // enable toggle cnt - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), 0, MISC_CTRL4_R_OPT2_CG_DQSIEN); // Remove to Golden settings for Jmeter clock - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); // @Darren need confirm for DQS*_ERR_CNT, APHY PICG freerun - //@A60868, End - - // Bypass DQS glitch-free mode - // RG_RX_*RDQ_EYE_DLY_DQS_BYPASS_B** + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), 0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), 0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), 0, MISC_CTRL4_R_OPT2_CG_DQSIEN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1); - //Enable DQ eye scan - //RG_*_RX_EYE_SCAN_EN - //RG_*_RX_VREF_EN - //RG_*_RX_SMT_EN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN) | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN) @@ -9986,26 +9637,25 @@ static void DramcJmeterInit(DRAMC_CTX_T *p, U8 u1IsJmtrK) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); - //@A60868, JMTR en + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_EN_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_EN_B1); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER), 1, MISC_JMETER_JMTR_EN); - //@A60868, End - //@A60868, JM_SEL = 1, JM_SEL = 0 for LPBK + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1); - //@A60868, End - //Enable MIOCK jitter meter mode ( RG_RX_MIOCK_JIT_EN=1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN); - //Disable DQ eye scan (b'1), for counter clear + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); #if MIOCK_JMETER_CNT_WA - //Fix problem of diff between sample_cnt and ones_cnt. Should be removed after IPMV2.1 (except 60892) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_EYESCAN_DQS_OPT); #endif @@ -10023,25 +9673,25 @@ static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlySte for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step) { - //@A60868, Set CLK delay (RG_*_RX_ARDQS_JM_DLY_B*) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), ucdqs_dly, B0_PHY2_RG_RX_ARDQS_JM_DLY_B0); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), ucdqs_dly, B1_PHY2_RG_RX_ARDQS_JM_DLY_B1); - //@A60868, End - //Reset eye scan counters (reg_sw_rst): 1 to 0 + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_REG_SW_RST); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_REG_SW_RST); - //Enable DQ eye scan (b'1) + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); - //2ns/sample, here we delay 1ms about 500 samples + mcDELAY_US(10); - //Disable DQ eye scan (b'1), for counter latch + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); - //Read the counter values from registers (toggle_cnt*, dqs_err_cnt*); + u4sample_cnt = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_TOGGLE_CNT), MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); u4ones_cnt[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT), MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); //u4ones_cnt[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT), MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT); @@ -10053,7 +9703,7 @@ static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlySte } #endif - //change to boolean value + if (u4ones_cnt[0] < (u4sample_cnt / 2)) { fgcurrent_value = 0; @@ -10066,16 +9716,16 @@ static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlySte if (ucsearch_state == 0xffff) { - //record initial value at the beginning + fginitial_value = fgcurrent_value; ucsearch_state = 0; } else { - // check if change value + if (fgcurrent_value != fginitial_value) { - // start of the period + fginitial_value = fgcurrent_value; pJmtrInfo->JmtrInfo[ucsearch_state].u1JmDelay = ucdqs_dly; pJmtrInfo->JmtrInfo[ucsearch_state].u1TransLevel = fgcurrent_value; @@ -10083,27 +9733,16 @@ static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlySte ucsearch_state++; pJmtrInfo->u1TransCnt = ucsearch_state; if (ucsearch_state == CYCLE_1T) - break; // 1T early break; + break; } } } } #endif -//------------------------------------------------------------------------- -/** DramcMiockJmeter - * start MIOCK jitter meter. - * @param p Pointer of context created by DramcCtxCreate. - * @param block_no (U8): block 0 or 1. - * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL - */ -//------------------------------------------------------------------------- #ifdef ENABLE_MIOCK_JMETER -/* "picoseconds per delay cell" depends on Vcore only (frequency doesn't matter) - * 1. Retrieve current freq's vcore voltage using pmic API - * 2. Perform delay cell time calculation (Bypass if shuffle vcore value is the same as before) - */ + U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p) { @@ -10125,7 +9764,7 @@ void Get_RX_DelayCell(DRAMC_CTX_T *p) #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if(p->femmc_Ready == 1) { - return; //gHQALOG_RX_delay_cell_ps_075V is not used in fastk (Only needed in HQA report and eyescan log). + return; } #endif @@ -10146,27 +9785,19 @@ void Get_RX_DelayCell(DRAMC_CTX_T *p) break; } #else - // set vcore to RX used 0.75V - dramc_set_vcore_voltage(SEL_PREFIX_VMDDR); //set vmddr voltage to vcore to K RX delay cell + + dramc_set_vcore_voltage(SEL_PREFIX_VMDDR); #endif gHQALOG_RX_delay_cell_ps_075V = GetVcoreDelayCellTime(p); - // set vocre back + vSetVcoreByFreq(p); } #endif } #endif -//------------------------------------------------------------------------- -/** Dramc8PhaseCal - * start 8-Phase Calibration. - * @param p Pointer of context created by DramcCtxCreate. - * @param block_no (U8): block 0 or 1. - * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL - */ -//------------------------------------------------------------------------- DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) { @@ -10183,20 +9814,20 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) U8 backup_rank, u1RankIdx, u18PhDlyBackup = 0; U8 u1loop_cnt = 0, u1early_break_cnt = 5; - // Jmeter Scan + JMETER_T JmtrInfo; U8 u1JmtrPrintCnt = 0; U32 u4backup_broadcast= GetDramcBroadcast(); DRAM_STATUS_T eDRAMStatus = DRAM_OK; -#ifdef DUMP_INIT_RG_LOG_TO_DE //for FT dump 3733 dram_init.c +#ifdef DUMP_INIT_RG_LOG_TO_DE return DRAM_OK; #endif u1DqsienPI = 0x0; - // error handling + if (!p) { mcSHOW_ERR_MSG(("context NULL\n")); @@ -10237,12 +9868,12 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)), (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), // need porting to Jmeter - (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), // need porting to Jmeter + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), + (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)), - //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), // for gating on/off backup/restore - //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), // for gating on/off backup/restore - (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), // for gating on/off backup/restore + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), + //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), + (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), #if 0 (DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)), (DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)), @@ -10267,7 +9898,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) memset(&JmtrInfo, 0, sizeof(JmtrInfo)); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); - //backup register value + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); DramcJmeterInit(p, FALSE); @@ -10302,13 +9933,12 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) mcSHOW_DBG_MSG2(("\n[Dramc8PhaseCal] 8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", u18Phase_SM, u18Ph_start, u18Ph_end, u1DqsienPI, u18PhDlyBackup)); - //to see 1T(H,L) or 1T(L,H) from delaycell=0 to 127 - //NOTE: Must set dual ranks for Rx path + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); - // SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0[6] no use (ignore) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1DqsienPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); // for rank*_B0 + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1DqsienPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); } vSetRank(p, backup_rank); @@ -10324,7 +9954,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) for (u1JmtrPrintCnt = 0; u1JmtrPrintCnt < JmtrInfo.u1TransCnt; u1JmtrPrintCnt++) { - if (JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1TransLevel == 1) // find the High Level + if (JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1TransLevel == 1) { ucdqs_dly = JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1JmDelay; @@ -10332,24 +9962,24 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) { u2R0 = ucdqs_dly; mcSHOW_DBG_MSG2(("R0 (H) = %d\n", u2R0)); - break; // break ucdqs_dly for loop + break; } else if (u18Phase_SM == DQS_8PH_DEGREE_180) { u2R180 = ucdqs_dly; if (u2R180 > u2R0) { - u2R = u2R0 + ((u2R180 - u2R0) >> 2); // u2R180 >= u2R0 for (u1R180 - u1R0)/4 for 180 degree. /2 for 90 degree + u2R = u2R0 + ((u2R180 - u2R0) >> 2); mcSHOW_DBG_MSG2(("R = %d, R180 (H) = %d\n", u2R, u2R180)); - break; // break ucdqs_dly for loop + break; } } else if (u18Phase_SM == DQS_8PH_DEGREE_45) { u2P = ucdqs_dly; - if (u2P > u2R0) // u2P ~= DQS_8PH_DEGREE_180 + if (u2P > u2R0) { - // Absolute to find min diff + if (u2R > u2P) s2Err_code = u2R - u2P; else @@ -10369,7 +9999,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) } else if (s2Err_code >= s2Err_code_min) { - // check early break for u18Ph_dly for loop + u1loop_cnt++; if (u1loop_cnt > u1early_break_cnt) u18Ph_dly_loop_break = 1; @@ -10377,7 +10007,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) mcSHOW_DBG_MSG2(("diff (P-R) = %d, min = %d, early break count = %d, R45 (H) = %d\n", s2Err_code, s2Err_code_min, u1loop_cnt, u2P)); - break; // if (s2Err_code == s2Err_code_min) for next u18Ph_dly + break; } } else @@ -10390,15 +10020,15 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) } } - // Error handing when not find transaction + if (JmtrInfo.u1TransCnt == u1JmtrPrintCnt) { - u18Ph_dly_final = u18PhDlyBackup; //rollback to init settings + u18Ph_dly_final = u18PhDlyBackup; eDRAMStatus = DRAM_FAIL; mcSHOW_ERR_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d is fail (to Default) !!!\n", u18Phase_SM)); goto exit; } else if (u18Ph_dly_loop_break == 1) - break; // early break + break; } } @@ -10410,7 +10040,7 @@ exit: vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ1, u18Ph_dly_final, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD1, u18Ph_dly_final, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA); - //restore to orignal value + OECKCKE_Control(p, ENABLE); DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); @@ -10421,34 +10051,25 @@ exit: } #if SIMULATION_SW_IMPED -/* Impedance have a total of 19 steps, but the HW value mapping to hardware is 0~15, 29~31 -* This function adjusts passed value u1ImpVal by adjust step count "u1AdjStepCnt" -* After adjustment, if value is 1. Too large (val > 31) -> set to max 31 -* 2. Too small (val < 0) -> set to min 0 -* 3. Value is between 15 & 29, adjust accordingly ( 15 < value < 29 ) -* returns: Impedance value after adjustment -*/ + #if 0 static U32 SwImpedanceAdjust(U32 u4ImpVal, S8 s1StepCnt) { S32 S4ImpedanceTemp = (S32)u4ImpVal; - // Perform impedance value adjustment + S4ImpedanceTemp += s1StepCnt; - /* After adjustment, if value is 1. Too large (val > 31) -> set to max 31 - * 2. Too small (val < 0) -> set to min 0 - * 3. Value is between 15 & 29, adjust accordingly ( 15 < value < 29 ) - */ - if ((S4ImpedanceTemp > 15) && (S4ImpedanceTemp < 29)) //Value is between 15 & 29 ( 15 < value < 29) + + if ((S4ImpedanceTemp > 15) && (S4ImpedanceTemp < 29)) { S4ImpedanceTemp = S4ImpedanceTemp - 16 + 29; } - if (S4ImpedanceTemp > 31) //Value after adjustment too large -> set to max 31 + if (S4ImpedanceTemp > 31) { S4ImpedanceTemp = 31; } - else if (S4ImpedanceTemp < 0) //Value after adjustment too small -> set to min 0 + else if (S4ImpedanceTemp < 0) { S4ImpedanceTemp = 0; } @@ -10456,47 +10077,35 @@ static U32 SwImpedanceAdjust(U32 u4ImpVal, S8 s1StepCnt) return (U32)S4ImpedanceTemp; } #endif -//------------------------------------------------------------------------- -/** vImpCalVrefSel - * Set IMP_VREF_SEL for DRVP, DRVN, Run-time/Tracking - * (Refer to "IMPCAL Settings" document register "RG_RIMP_VREF_SEL" settings) - * @param p Pointer of context created by DramcCtxCreate. - * @param freq_region (enum): pass freq_region (IMP_LOW_FREQ/IMP_HIGH_FREQ) for LP4X - * @param u1ImpCalStage (U8): During DRVP, DRVN, run-time/tracking stages - * some vref_sel values are different - */ -//------------------------------------------------------------------------- -/* Definitions to make IMPCAL_VREF_SEL function more readable */ + #define IMPCAL_STAGE_DRVP 0 #define IMPCAL_STAGE_DRVN 1 #define IMPCAL_STAGE_ODTP 2 #define IMPCAL_STAGE_ODTN 3 #define IMPCAL_STAGE_TRACKING 4 -/* LP4X IMP_VREF_SEL w/o term ==== */ -#define IMP_TRACK_LP4X_LOWFREQ_VREF_SEL 0x37 // for <= DDR3733 -#define IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL 0x3a // for > 3733 and Samsung NT-ODTN -/* LPDDR5 IMP_VREF_SEL w/o term ==== */ -#define IMP_TRACK_LP5_LOWFREQ_VREF_SEL 0x38 // for <= DDR3733 -#define IMP_TRACK_LP5_HIGHFREQ_VREF_SEL 0x3a // for > 3733 and Samsung NT-ODTN + +#define IMP_TRACK_LP4X_LOWFREQ_VREF_SEL 0x37 +#define IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL 0x3a + +#define IMP_TRACK_LP5_LOWFREQ_VREF_SEL 0x38 +#define IMP_TRACK_LP5_HIGHFREQ_VREF_SEL 0x3a static const U8 ImpLP4VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = { - /* DRVP DRVN ODTP ODTN */ -/* IMP_LOW_FREQ */ {0x37, 0x33, 0x00, 0x37}, -/* IMP_HIGH_FREQ */ {0x3a, 0x33, 0x00, 0x3a}, -/* IMP_NT_ODTN */ {0x2a, 0x2a, 0x00, 0x3a} + + {0x37, 0x33, 0x00, 0x37}, + {0x3a, 0x33, 0x00, 0x3a}, + {0x2a, 0x2a, 0x00, 0x3a} }; static const U8 ImpLP5VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = { - /* DRVP DRVN ODTP ODTN */ -/* IMP_LOW_FREQ */ {0x38, 0x33, 0x00, 0x38}, -/* IMP_HIGH_FREQ */ {0x3a, 0x33, 0x00, 0x3a}, -/* IMP_NT_ODTN */ {0x2a, 0x2a, 0x00, 0x3a} + + {0x38, 0x33, 0x00, 0x38}, + {0x3a, 0x33, 0x00, 0x3a}, + {0x2a, 0x2a, 0x00, 0x3a} }; -/* Refer to "IMPCAL Settings" document register "RG_RIMP_VREF_SEL" settings */ -// @Maoauo: DRVP/ODTN for IMP tracking. But DRVN not support IMP tracking. (before La_fite) -// DRVP/DRVN/ODTN for IMP tracking after Pe_trus + static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCalStage) { U8 u1RegTmpValue = 0; @@ -10542,13 +10151,13 @@ static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCal break; } - // dbg msg after vref_sel selection + mcSHOW_DBG_MSG3(("[vImpCalVrefSel] IMP_VREF_SEL 0x%x, IMPCAL stage:%u, freq_region:%u\n", u1RegTmpValue, u1ImpCalStage, efreq_region)); - /* Set IMP_VREF_SEL register field's value */ + if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) { - /* SEL_DVRP/ODTN shall diff by freq, value of them are equal */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN); } else { @@ -10567,16 +10176,16 @@ void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_ DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - /* Save RIMP_VREF_SEL by shuffle. Will be broadcasted to ALL CH even if unused */ + vImpCalVrefSel(p, dq_freq_option, IMPCAL_STAGE_TRACKING); - //DQ + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQDRVP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQDRVN2)); vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING2_DQDRVP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING2_DQDRVN1)); vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQODTP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQODTN2)); vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING4_DQODTP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING4_DQODTN1)); - //DQS + #if SUPPORT_HYNIX_RX_DQS_WEAK_PULL if (p->vendor_id == VENDOR_HYNIX) { U32 temp_value[4]; @@ -10599,33 +10208,18 @@ void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_ vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN)); } - //CMD & CLK + vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(gDramcImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN2)); vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(gDramcImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN1)); vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP2) | P_Fld(gDramcImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN2)); vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP1) | P_Fld(gDramcImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN1)); - //RG_TX_*RCKE_DRVP/RG_TX_*RCKE_DRVN doesn't set, so set 0xA first - //@Maoauo confirm, RG no function - //vIO32WriteFldAlign((DDRPHY_SHU_CA_CMD11 + save_to_where * SHU_GRP_DDRPHY_OFFSET), gDramcImpedanceResult[ca_freq_option][DRVP], SHU_CA_CMD11_RG_TX_ARCKE_DRVP); - //vIO32WriteFldAlign((DDRPHY_SHU_CA_CMD11 + save_to_where * SHU_GRP_DDRPHY_OFFSET), gDramcImpedanceResult[ca_freq_option][DRVN], SHU_CA_CMD11_RG_TX_ARCKE_DRVN); - - //CKE - // CKE is full swing. - // LP4/LP4X set DRVP/DRVN as LP3's default value - // DRVP=8 -> 0xA for 868 by Alucary Chen - // DRVN=9 -> 0xA for 868 by Alucary Chen - //DRVP[4:0] = RG_TX_ARCMD_PU_PRE<1:0>, RG_TX_ARCLK_DRVN_PRE<2:0> for La_fite only - //@Darren-vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), (8>>3)&0x3, SHU_CA_CMD3_RG_TX_ARCMD_PU_PRE); //Darren need confirm - //@Darren-vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD0 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 8&0x7, SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE); //Darren need confirm - //DRVN[4:0] = RG_ARCMD_REV<12:8> - //@Darren-vIO32WriteFldAlign_All((DDRPHY_SHU_CA_DLL2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 9, SHU_CA_DLL2_RG_TX_ARCKE_DRVN_B0); - #if (fcFOR_CHIP_ID == fcA60868) // for 868 CS and CKE control together + + #if (fcFOR_CHIP_ID == fcA60868) vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVP); vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVN); #elif (fcFOR_CHIP_ID == fc8195) - // @Darren, confirm with ACD Alucary, - // MISC_SHU_DRVING8_CS_DRVP & MISC_SHU_DRVING8_CS_DRVN -> DA_TX_ARCKE_DRVP_C0[4:0] & DA_TX_ARCKE_DRVN_C0[4:0] + vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xF, MISC_SHU_DRVING8_CS_DRVP); vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0x14, MISC_SHU_DRVING8_CS_DRVN); #endif @@ -10642,29 +10236,28 @@ static void Dramc_Hw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region) vAutoRefreshSwitch(p, ENABLE); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0), 0, SHU_CONF0_PBREFEN); - for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) // Calibration sequence for DRVP, DRVN and ODTN + for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) { - if (u1DrvType == ODTP) // no use, skip ODTP + if (u1DrvType == ODTP) continue; - /* Set IMP_VREF_SEL value for DRVP/DRVN and ODTN */ + vImpCalVrefSel(p, freq_region, u1DrvType); } ImpedanceTracking_DisImpHw_Setting(p, DISABLE); - //IMPCALCNT should be bigger than 0x4 (set as minimum value to save calibration time) - //clock_period *IMPCAL_CHKCYCLE* 16 should be bigger than 200ns. + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(4, SHU_MISC_IMPCAL1_IMPCALCNT) | P_Fld(1, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE)); DramcImpedanceTrackingEnable(p); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 0, MISC_IMPCAL_IMPCAL_ECO_OPT); //No need to wait slave channel's handshake signal in calibration + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 0, MISC_IMPCAL_IMPCAL_ECO_OPT); - mcDELAY_US(16); //Need to wait IMPCALCNT times of all-bank refresh + mcDELAY_US(16); u4DRVN_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1); u4DRVP_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1); u4ODTN_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1); - //DRVP=DRVP_FINAL + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP); vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVN_Result, SHU_MISC_IMPCAL1_IMPDRVN); @@ -10687,8 +10280,8 @@ static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld) for (u4ImpxDrv = 0; u4ImpxDrv < 32; u4ImpxDrv++) { -#if 0 // for A60868 no need - if (u4ImpxDrv == 16) //0~15, 29~31 +#if 0 + if (u4ImpxDrv == 16) u4ImpxDrv = 29; #endif @@ -10697,14 +10290,14 @@ static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld) u4ImpCalResult = u4IO32ReadFldAlign((DDRPHY_REG_MISC_PHY_RGS_CMD), MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); mcSHOW_DBG_MSG2(("OCD %s=%d ,CALOUT=%d\n", drvType, u4ImpxDrv, u4ImpCalResult)); - if (u4ImpCalResult == u4CheckImpChange)//first found + if (u4ImpCalResult == u4CheckImpChange) { mcSHOW_DBG_MSG2(("\nOCD %s calibration OK! %s=%d\n\n", drvType, drvType, u4ImpxDrv)); break; } } - if (u4ImpxDrv == 32) // Can't find SwImp drv results + if (u4ImpxDrv == 32) { u4ImpxDrv = 31; mcSHOW_DBG_MSG2(("\nOCD %s calibration FAIL! %s=%d\n\n", drvType, drvType, u4ImpxDrv)); @@ -10723,13 +10316,13 @@ static void Dramc_Sw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region) vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 1, MISC_IMPCAL_IMPCAL_CALI_EN); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVP)); - //LP4X: ODTN/DRVN/DRVP calibration start - for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) // Calibration sequence for DRVP, DRVN and ODTN + + for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) { - if (u1DrvType == ODTP) // no use, skip ODTP + if (u1DrvType == ODTP) continue; - /* Set IMP_VREF_SEL value for DRVP/DRVN and ODTN */ + vImpCalVrefSel(p, freq_region, u1DrvType); switch (u1DrvType) @@ -10745,7 +10338,7 @@ static void Dramc_Sw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region) case ODTN: drvStr = (u1DrvType == DRVN)? "DRVN" : "ODTN"; u1CALI_ENP = 0x0; - u1CALI_ENN = (u1DrvType == DRVN)? 0x0: 0x1; // 0x1 change to ODTN path + u1CALI_ENN = (u1DrvType == DRVN)? 0x0: 0x1; u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVN; break; default: @@ -10753,18 +10346,16 @@ static void Dramc_Sw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region) break; } - // @A60868 for DRVn/p and ODTn select - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENP, MISC_IMPCAL_IMPCAL_CALI_ENP); //MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN move to CALI_ENP - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENN, MISC_IMPCAL_IMPCAL_CALI_ENN); //MISC_IMP_CTRL1_RG_RIMP_ODT_EN move to CALI_ENN + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENP, MISC_IMPCAL_IMPCAL_CALI_ENP); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENN, MISC_IMPCAL_IMPCAL_CALI_ENN); mcSHOW_DBG_MSG2(("\n\n\tK %s\n", drvStr)); - //DRVP=DRVP_FINAL - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP); //PUCMP_EN move to CALI_ENP - //If RGS_TX_OCD_IMPCALOUTX=1 - //RG_IMPX_DRVN++; - //Else save RG_IMPX_DRVN value and assign to DRVN + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP); + + u4SwImpCalResult = DramcSwImpCalResult(p, drvStr, u4DrvFld); switch (u1DrvType) @@ -10825,7 +10416,7 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi backup_broadcast = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); - //default set FAIL + vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAIL); #if VENDER_JV_LOG @@ -10836,18 +10427,17 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi mcSHOW_DBG_MSG(("[DramcImpedenceCal]\n")); - //Suspend: DA_RIMP_DMSUS=1 + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_LP_CTRL, P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10) | \ P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL) | \ P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10) | \ P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL)); - //Disable IMP HW Tracking - //Hw Imp tracking disable for all channels Because SwImpCal will be K again when resume from DDR reserved mode + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0, MISC_IMPCAL_IMPCAL_HW); backup_channel = p->channel; vSetPHY2ChannelMapping(p, CHANNEL_A); - //Register backup + //u4BaklReg_DDRPHY_MISC_IMP_CTRL0 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL0)); //u4BaklReg_DDRPHY_MISC_IMP_CTRL1 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL1)); //u4BaklReg_DRAMC_REG_IMPCAL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL)); @@ -10859,11 +10449,10 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi | P_Fld(1, DRAMC_PD_CTRL_DCMEN)); #endif - //RG_IMPCAL_VREF_SEL (now set in vImpCalVrefSel()) - //RG_IMPCAL_LP3_EN=0, RG_IMPCAL_LP4_EN=1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN); vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), P_Fld(0, MISC_IMPCAL_IMPCAL_CALI_ENN) | P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDP) | \ - P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDN)); //RG_RIMP_BIAS_EN and RG_RIMP_VREF_EN move to IMPPDP and IMPPDN + P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDN)); u1DDR4 = 1; @@ -10873,7 +10462,7 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi P_Fld(u1DDR4, MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL)); mcDELAY_US(1); - //RIMP_DRV05 for LP4/5 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1Drv05, SHU_CA_CMD12_RG_RIMP_DRV05); #if IMPEDANCE_HW_CALIBRATION @@ -10881,21 +10470,15 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi #else Dramc_Sw_ImpedanceCal(p, freq_region); #endif - //Register Restore + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); //vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u4BaklReg_DRAMC_REG_IMPCAL); //vIO32Write4B((DDRPHY_MISC_IMP_CTRL0), u4BaklReg_DDRPHY_MISC_IMP_CTRL0); //vIO32Write4B((DDRPHY_MISC_IMP_CTRL1), u4BaklReg_DDRPHY_MISC_IMP_CTRL1); -/*** default value if K fail - LP3: DRVP=8, DRVN=9 - LP4: DRVP=6, DRVN=9, ODTN=14 - LP4X(UT): DRVP=12, DRVN=9 - LP4X(T): DRVP=5, DRVN=9, ODTN=14 - LP4P: DRVP=8, DRVN=10 -***/ - #if 0//HYNIX_IMPX_ADJUST + + #if 0 if (u1Para) { u4ODTN_Result = ImpedanceAdjustment_Hynix(u4ODTN_Result, u1Para); @@ -10937,17 +10520,13 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi #endif #if 0 - //YingYu: only check for freq_region = 0 (un-term, DQ) + if (gDramcSwImpedanceResult[freq_region][DRVP] >= 31 && (freq_region == 0) ) { mcSHOW_DBG_MSG(("SLT_BIN2\n")); while (1); } #else - // Alucary @ 2019/8/21 - // freq_region == 0 - // DRVP 0x1~0x16 - // DRVN 10~23 - // ODTN 0x3~0x13 + if (freq_region==0) { if (!(gDramcImpedanceResult[freq_region][DRVP] >= 1 && gDramcImpedanceResult[freq_region][DRVP] <= 0x16) || @@ -10967,14 +10546,8 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi } } else - { // freq_region == 1 - // DRVP 1~24 @ 2020/4/7 - // 4266 VOH is K 395mV - // SS 130 LV DRVP 395mV will got 22 - // need add 2 for margin - // so spec change to 24 - // DRVN 10~30 - // ODTN 3~12 + { + if (!(gDramcImpedanceResult[freq_region][DRVP] >= 1 && gDramcImpedanceResult[freq_region][DRVP] <= 24) || !(gDramcImpedanceResult[freq_region][DRVN] >= 10 && gDramcImpedanceResult[freq_region][DRVN] <= 30) || !(gDramcImpedanceResult[freq_region][ODTN] >= 3 && gDramcImpedanceResult[freq_region][ODTN] <= 12)) { @@ -11018,7 +10591,7 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi return DRAM_OK; } -#endif //SIMULATION_SW_IMPED +#endif #if ENABLE_WRITE_DBI || TX_K_DQM_WITH_WDBI void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK) @@ -11049,14 +10622,11 @@ void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK) #define CLOCK_PI_STEP 2 #endif -#define ClockDutyFailLowerBound 4500 // 45% -#define ClockDutyFailUpperBound 5500 // 55% -#define ClockDutyMiddleBound 5000 // 50% +#define ClockDutyFailLowerBound 4500 +#define ClockDutyFailUpperBound 5500 +#define ClockDutyMiddleBound 5000 + -/* -* duty form smallest to biggest -* 011111->011110->...->000001-->000000=100000->100001-->...->111111 -*/ static U8 DramcDutyDelayRGSettingConvert(DRAMC_CTX_T *p, S8 scDutyDelay, U8 *tDly) { @@ -11216,7 +10786,7 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) U32 backup_DDRPHY_REG_SHU_B0_DQ13=0, backup_DDRPHY_REG_SHU_B1_DQ13=0, backup_DDRPHY_REG_SHU_CA_CMD13=0; #if(DQS_DUTY_SLT_CONDITION_TEST) - U16 u2TestCnt, u2FailCnt=0, u2TestCntTotal =20; //fra 400; + U16 u2TestCnt, u2FailCnt=0, u2TestCntTotal =20; U8 u1ByteIdx, u1PI_FB; U32 u4Variance; #endif @@ -11225,7 +10795,7 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) u1backup_rank = u1GetRank(p); vSetRank(p, RANK_0); - //backup OE releated RG , must put at begin of duty function !! + backup_DDRPHY_REG_B0_DQ2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)); if (!isLP4_DSC) backup_DDRPHY_REG_B1_DQ2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)); @@ -11237,14 +10807,14 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) else backup_DDRPHY_REG_SHU_CA_CMD13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)); - //default set fail + vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAIL); #if !FT_DSIM_USED #if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ if (p->frequency == u2DFSGetHighestFreq(p)) #else - //TODO if(Get_PRE_MIOCK_JMETER_HQA_USED_flag()==0) + #endif #endif { @@ -11273,7 +10843,7 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) } OECKCKE_Control(p, ENABLE); - //restore OE releated RG , must put at end of duty function !! + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), backup_DDRPHY_REG_B0_DQ2); if (!isLP4_DSC) vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), backup_DDRPHY_REG_B1_DQ2); diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index 02ba357664..e7e8f899a5 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -28,29 +28,29 @@ bool gUpdateHighestFreq = FALSE; SAVE_TIME_FOR_CALIBRATION_T SavetimeData; #endif -U8 gHQA_Test_Freq_Vcore_Level = 0; // 0: only 1 freq , others are multi freq 1: low vcore 2: high vcore +U8 gHQA_Test_Freq_Vcore_Level = 0; -u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733 +u8 ett_fix_freq = 0xff; DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. - {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION {LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE}, #endif - {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) - {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, + {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, }; DRAMC_CTX_T DramCtx_LPDDR4 = { - CHANNEL_SINGLE, // Channel number - CHANNEL_A, // DRAM_CHANNEL - RANK_DUAL, //DRAM_RANK_NUMBER_T - RANK_0, //DRAM_RANK_T + CHANNEL_SINGLE, + CHANNEL_A, + RANK_DUAL, + RANK_0, #ifdef MTK_FIXDDR1600_SUPPORT LP4_DDR1600, @@ -66,71 +66,71 @@ DRAMC_CTX_T DramCtx_LPDDR4 = #endif #endif #if DV_SIMULATION_LP4 - TYPE_LPDDR4X, // DRAM_DRAM_TYPE_T + TYPE_LPDDR4X, #else TYPE_LPDDR5, #endif - FSP_0 , //// DRAM Fast switch point type, only for LP4, useless in LP3 - FSP_0 , //// boot_fsp + FSP_0 , + FSP_0 , ODT_OFF, - {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, // bring up LP4X rank0 & rank1 use normal mode + {CBT_NORMAL_MODE, CBT_NORMAL_MODE}, #if ENABLE_READ_DBI - {DBI_OFF,DBI_ON}, //read DBI + {DBI_OFF,DBI_ON}, #else - {DBI_OFF,DBI_OFF}, //read DBI + {DBI_OFF,DBI_OFF}, #endif #if ENABLE_WRITE_DBI - {DBI_OFF,DBI_ON}, // write DBI + {DBI_OFF,DBI_ON}, #else - {DBI_OFF,DBI_OFF}, // write DBI + {DBI_OFF,DBI_OFF}, #endif - DATA_WIDTH_16BIT, // DRAM_DATA_WIDTH_T - DEFAULT_TEST2_1_CAL, // test2_1; - DEFAULT_TEST2_2_CAL, // test2_2; + DATA_WIDTH_16BIT, + DEFAULT_TEST2_1_CAL, + DEFAULT_TEST2_2_CAL, #if ENABLE_K_WITH_WORST_SI_UI_SHIFT - TEST_WORST_SI_PATTERN, // test_pattern; + TEST_WORST_SI_PATTERN, #else TEST_XTALK_PATTERN, #endif #if (DV_SIMULATION_LP4 == 1) - 800, // frequency - 800, // freqGroup + 800, + 800, #else 1600, 1600, #endif - 0x88, //vendor_id initial value + 0x88, REVISION_ID_MAGIC, - 0xff, //density + 0xff, {0,0}, - 270, // u2DelayCellTimex100; + 270, #if PRINT_CALIBRATION_SUMMARY - //aru4CalResultFlag[CHANNEL_NUM][RANK_MAX] + {{0,0,}}, - //aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX] + {{0,0,}}, 1, 0, #endif - {0}, //BOOL arfgWriteLevelingInitShif; + {0}, #if SUPPORT_SAVE_TIME_FOR_CALIBRATION - FALSE, //femmc_Ready + FALSE, 0, 0, 0, &SavetimeData, #endif - &gFreqTbl[DRAM_DFS_SRAM_MAX-1], // default is DDR1600 1:8 mode + &gFreqTbl[DRAM_DFS_SRAM_MAX-1], DRAM_DFS_REG_SHU0, TRAINING_MODE2, CBT_PHASE_RISING, - 0, //new CBT pattern + 0, PHYPLL_MODE, DBI_OFF, FSP_MAX, PINMUX_EMCP, - {DISABLE,DISABLE}, // disable 10GB + {DISABLE,DISABLE}, 0, }; @@ -156,31 +156,31 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); #elif defined(VCORE_BIN) switch (vGet_Current_SRAMIdx(p)) { - case SRAM_SHU0: //4266 + case SRAM_SHU0: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU0); if (!vcore) #endif vcore = get_vcore_uv_table(0); break; - case SRAM_SHU1: //3200 + case SRAM_SHU1: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU1); if (!vcore) #endif vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(1)) >> 1; break; - case SRAM_SHU2: //2400 - case SRAM_SHU3: //1866 + case SRAM_SHU2: + case SRAM_SHU3: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU2); if (!vcore) #endif vcore = (get_vcore_uv_table(0) + get_vcore_uv_table(2)) >> 1; break; - case SRAM_SHU4: //1600 - case SRAM_SHU5: //1200 - case SRAM_SHU6: //800 + case SRAM_SHU4: + case SRAM_SHU5: + case SRAM_SHU6: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU4); if (!vcore) @@ -190,33 +190,33 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) } #else switch (vGet_Current_SRAMIdx(p)) { - case SRAM_SHU0: // 4266 + case SRAM_SHU0: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU0); #else vcore = SEL_PREFIX_VCORE(LP4, KSHU0); #endif break; - case SRAM_SHU1: // 3200 + case SRAM_SHU1: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU1); #else vcore = SEL_PREFIX_VCORE(LP4, KSHU1); #endif break; - case SRAM_SHU2: // 2400 - case SRAM_SHU3: //1866 + case SRAM_SHU2: + case SRAM_SHU3: #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU2); #else vcore = SEL_PREFIX_VCORE(LP4, KSHU2); #endif break; - case SRAM_SHU4: //1600 - case SRAM_SHU5: //1200 - case SRAM_SHU6: //800 + case SRAM_SHU4: + case SRAM_SHU5: + case SRAM_SHU6: #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION - case SRAM_SHU7: //400 + case SRAM_SHU7: #endif #ifdef VOLTAGE_SEL vcore = vcore_voltage_select(KSHU4); @@ -249,17 +249,17 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) #ifdef FOR_HQA_REPORT_USED switch (vGet_Current_SRAMIdx(p)) { - case SRAM_SHU0: //3733 - case SRAM_SHU1: //3200 - case SRAM_SHU2: //2400 - case SRAM_SHU3: //1866 - case SRAM_SHU4: //1600 - case SRAM_SHU5: //1200 - case SRAM_SHU6: //800 + case SRAM_SHU0: + case SRAM_SHU1: + case SRAM_SHU2: + case SRAM_SHU3: + case SRAM_SHU4: + case SRAM_SHU5: + case SRAM_SHU6: #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION - case SRAM_SHU7: //400 + case SRAM_SHU7: #endif - gHQA_Test_Freq_Vcore_Level = 0; //only 1 freq + gHQA_Test_Freq_Vcore_Level = 0; break; default: print("[HQA] undefined shuffle level for Vcore (SHU%d)\r\n", vGet_Current_SRAMIdx(p)); @@ -365,7 +365,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) FinalWinPerBit[u1BitIdx].last_pass=p->pSavetimeData->u1RxWinPerbitDQ_lastbypass_Save[p->channel][p->rank][u1BitIdx+RUNTIME_SHMOO_TEST_BYTE*8]; } - //find smallest first and largest last pass + for (u1BitIdx=0; u1BitIdx<8; u1BitIdx++) { if (FinalWinPerBit[u1BitIdx].first_pass < rx_first_delay) @@ -390,10 +390,10 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #endif if (p->femmc_Ready==0 || - ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) //first K + ((p->pSavetimeData->Runtime_Shmoo_para.TX_Channel!=RUNTIME_SHMOO_TEST_CHANNEL) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Rank!=RUNTIME_SHMOO_TEST_RANK) || (p->pSavetimeData->Runtime_Shmoo_para.TX_Byte!=RUNTIME_SHMOO_TEST_BYTE))) { #if RUNTIME_SHMOO_TX - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; //on going + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay = tx_pi_delay-32+RUNTIME_SHMOO_TEST_PI_DELAY_START; p->pSavetimeData->Runtime_Shmoo_para.TX_Original_PI_delay = p->pSavetimeData->Runtime_Shmoo_para.TX_PI_delay; @@ -415,7 +415,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #endif #if RUNTIME_SHMOO_RX - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; //on going + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_ON_GOING; p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range = 0; p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value = 0; @@ -429,10 +429,10 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Byte = RUNTIME_SHMOO_TEST_BYTE; #endif } -//fra else if (dramc_get_rshmoo_step()) + else if ((dramc_get_rshmoo_step()) && (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END)) { - //judge scan direction + if (RUNTIME_SHMOO_FAST_K == 0) { p->pSavetimeData->Runtime_Shmoo_para.Scan_Direction=0; @@ -467,7 +467,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } else { @@ -503,7 +503,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } } #endif @@ -519,7 +519,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } else { @@ -555,7 +555,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value += RUNTIME_SHMOO_TEST_VREF_STEP; if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } } #endif @@ -572,7 +572,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value+p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range*30) > RUNTIME_SHMOO_TEST_VREF_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } else { @@ -598,7 +598,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) if ((p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value) > RUNTIME_SHMOO_RX_VREF_RANGE_END) { - p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; //test finish + p->pSavetimeData->Runtime_Shmoo_para.flag= RUNTIME_SHMOO_END; } #endif } @@ -627,7 +627,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) print("Fra RunTime Shmoo CH%d, Rank%d, Byte%d\n",RUNTIME_SHMOO_TEST_CHANNEL, RUNTIME_SHMOO_TEST_RANK, RUNTIME_SHMOO_TEST_BYTE ); #endif -//fra if (p->pSavetimeData->Runtime_Shmoo_para.flag != RUNTIME_SHMOO_END) + { #if RUNTIME_SHMOO_TX #if __ETT__ @@ -676,7 +676,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) } DramcTXSetVref(p, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value); - //DLL all off from Justin + #if 0 #if ENABLE_MCK8X_MODE vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_SHU_CA_DLL0), 0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU); @@ -697,41 +697,41 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #if RUNTIME_SHMOO_RX - // here has a problem, RX dq is perbit but I just can choose one (bit0) to do compare and setting + if (p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0] <=0) { #if 0 - // Set DQS delay + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld((-p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0]),SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0)); - // Set DQM delay to 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0)); DramPhyReset(p); #endif - // Set DQ delay to 0 + for (u1BitIdx=0; u1BitIdx<4; u1BitIdx++) { - vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE + u1BitIdx*4), 0);//DQ0~DQ7 + vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE + u1BitIdx*4), 0); } } else { #if 0 - // Set DQS delay to 0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0) |P_Fld(0,SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0)); - // Adjust DQM output delay. + vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU1_R0_B0_DQ6 + 0x50*RUNTIME_SHMOO_TEST_BYTE), \ P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0) |P_Fld(p->pSavetimeData->Runtime_Shmoo_para.RX_delay,SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0)); DramPhyReset(p); #endif - // Adjust DQ output delay. + for (u1BitIdx=0; u1BitIdx<8; u1BitIdx+=2) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0+ (DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE) +u1BitIdx*2), \ @@ -741,19 +741,18 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) } } - //Set Vref - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE), p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0); // LP4 and LP4x with term: 0xe + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ5 + DDRPHY_AO_B0_B1_OFFSET*RUNTIME_SHMOO_TEST_BYTE), p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0); #endif } - //save parameters to eMMC + #if EMMC_READY write_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData); #endif mcSHOW_ERR_MSG(("Fra Save calibration result to emmc\n")); - //copy parameters to memory for kernel test script used - //wait for YiRong's SRAM copy function + #if RUNTIME_SHMOO_TX dramc_set_rshmoo_info(p->pSavetimeData->Runtime_Shmoo_para.TX_Rank, p->pSavetimeData->Runtime_Shmoo_para.TX_Channel, p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, @@ -765,7 +764,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) p->pSavetimeData->Runtime_Shmoo_para.TX_Byte, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Range, p->pSavetimeData->Runtime_Shmoo_para.TX_Vref_Value, p->pSavetimeData->Runtime_Shmoo_para.RX_delay[0], 1, (p->pSavetimeData->Runtime_Shmoo_para.flag == RUNTIME_SHMOO_END) ? 1 : 0); -// vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable +// vAutoRefreshSwitch(p, DISABLE); #endif @@ -775,7 +774,7 @@ void RunTime_Shmoo_update_parameters(DRAMC_CTX_T *p) #endif -///TODO: wait for porting +++ + #ifdef FIRST_BRING_UP void Test_Broadcast_Feature(DRAMC_CTX_T *p) { @@ -872,7 +871,7 @@ static void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p) pass_count=0; #if !__ETT__ - // scy: not to test rank1 (wrong addr 0x0000_0000) + if (u1RankIdx >= 1) continue; #endif @@ -940,7 +939,7 @@ static void vDramCPUReadWriteTestAfterCalibration(DRAMC_CTX_T *p) if(u1DumpInfo) { - // Read gating error flag + #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) DramcDumpDebugInfo(p); #endif @@ -990,13 +989,9 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) if (doe_get_config("fullk")) return DRAM_FAIL; - // Parepare fask k data + #if EMMC_READY - // scy: only need to read emmc one time for each boot-up - //if (g_dram_save_time_init_done == 1) - // return DRAM_OK; - //else - // g_dram_save_time_init_done = 1; + if (read_offline_dram_calibration_data(vGet_Current_SRAMIdx(p), p->pSavetimeData) < 0) { p->femmc_Ready = 0; @@ -1007,7 +1002,7 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) p->femmc_Ready = 1; } - #else //EMMC is not avaliable, load off-line data + #else if (g_dram_save_time_init_done[vGet_Current_SRAMIdx(p)] == 0) { @@ -1024,7 +1019,7 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p) if (p->femmc_Ready == 1) { if (p->frequency < 1600) - { // freq < 1600, TX and RX tracking are disable. Therefore, bypass calibration. + { p->Bypass_RDDQC = 1; p->Bypass_RXWINDOW = 1; p->Bypass_TXWINDOW = 1; @@ -1059,24 +1054,24 @@ static void DramRankNumberDetection(DRAMC_CTX_T *p) { U8 u1RankBak; - u1RankBak = u1GetRank(p); // backup current rank setting + u1RankBak = u1GetRank(p); - vSetPHY2ChannelMapping(p, CHANNEL_A); // when switching channel, must update PHY to Channel Mapping + vSetPHY2ChannelMapping(p, CHANNEL_A); vSetRank(p, RANK_1); if (DramcWriteLeveling(p, AUTOK_ON, PI_BASED) == DRAM_OK) { p->support_rank_num = RANK_DUAL; - vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK); //keep support_rank_num to reserved rg + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 0, SA_RESERVE_SINGLE_RANK); } else { p->support_rank_num = RANK_SINGLE; - vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK); //keep support_rank_num to reserved rg + vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK); } mcSHOW_DBG_MSG2(("[RankNumberDetection] %d\n", p->support_rank_num)); - vSetRank(p, u1RankBak); // restore rank setting + vSetRank(p, u1RankBak); } #endif @@ -1107,17 +1102,17 @@ void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p) { vSetRank(p, s1RankIdx); - vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable + vAutoRefreshSwitch(p, ENABLE); dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF, NORMAL_K); #if MRW_CHECK_ONLY mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); #endif - vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable + vAutoRefreshSwitch(p, DISABLE); } - vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate()) + vSetRank(p, RANK_0); #if GATING_ADJUST_TXDLY_FOR_TRACKING DramcRxdqsGatingPostProcess(p); @@ -1139,15 +1134,15 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf vSetPHY2ChannelMapping(p, CHANNEL_A); - // Read MR5 for Vendor ID - DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id));// for byte mode, don't show value of another die. + + DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id)); p->vendor_id &= 0xFF; mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id)); - // Read MR6 for Revision ID - DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id));// for byte mode, don't show value of another die. + + DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id)); mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id)); - // Read MR6 for Revision ID2 - DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7);// for byte mode, don't show value of another die. + + DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7); mcSHOW_DBG_MSG2(("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7)); #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) set_dram_mr(5, p->vendor_id); @@ -1163,10 +1158,10 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf DramInfo->u8MR8Density[u1RankIdx] =0; } - // Read MR8 for dram density + for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) { - #if 0//PRINT_CALIBRATION_SUMMARY + #if 0 if ((p->aru4CalExecuteFlag[u1ChannelIdx][u1RankIdx] != 0) && \ (p->aru4CalResultFlag[u1ChannelIdx][u1RankIdx] == 0)) #endif @@ -1179,7 +1174,7 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf u2MR8 |= (u2Density & 0xFF) << (u1RankIdx * 8); u1DieNumber = 1; - if (((u2Density >> 6) & 0x3) == 1) //OP[7:6] =0, x16 (normal mode) + if (((u2Density >> 6) & 0x3) == 1) u1DieNumber = 2; if (DramInfo != NULL) @@ -1189,33 +1184,33 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf switch (u2Density) { - ///TODO: Darren, please check the value of u8Size. + case 0x0: - u8Size = 0x20000000; //4Gb = 512MB + u8Size = 0x20000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 4Gb\n")); break; case 0x1: - u8Size = 0x30000000; //6Gb = 768MB + u8Size = 0x30000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 6Gb\n")); break; case 0x2: - u8Size = 0x40000000; //8Gb = 1GB = 2^30 bytes = 0x40000000 bytes + u8Size = 0x40000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 8Gb\n")); break; case 0x3: - u8Size = 0x60000000; //12Gb = 1.5GB = 3^30 bytes = 0x60000000 bytes + u8Size = 0x60000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 12Gb\n")); break; case 0x4: - u8Size = 0x80000000; //16Gb = 2GB = 4^30 bytes = 0x80000000 bytes + u8Size = 0x80000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 16Gb\n")); break; case 0x5: - u8Size = 0xc0000000; //24Gb = 3GB = 6^30 bytes = 0xc0000000 bytes + u8Size = 0xc0000000; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 24Gb\n")); break; case 0x6: - u8Size = 0x100000000L; //32Gb = 4GB = 8^30 bytes = 0x10000000 bytes + u8Size = 0x100000000L; //mcSHOW_DBG_MSG(("[EMI]DRAM density = 32Gb\n")); break; default: @@ -1227,13 +1222,13 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf u8Size >>= 1; #endif - if (u8Size_backup < u8Size) // find max dram size for vDramcACTimingOptimize + if (u8Size_backup < u8Size) { u8Size_backup = u8Size; p->density = u2Density; } - p->ranksize[u1RankIdx] = u8Size * u1DieNumber; //dram rank size = density * DieNumber + p->ranksize[u1RankIdx] = u8Size * u1DieNumber; if (DramInfo != NULL) { @@ -1241,8 +1236,7 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf } } DramInfo->u4RankNum = p->support_rank_num; - // 1GB = 2^30 bytes - // u8Size * (2^3) / (2^30) ==>Gb + mcSHOW_DBG_MSG2(("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27))); } #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0) @@ -1262,8 +1256,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) TimeProfileBegin(); #endif -#if 0//SIMULATION_RX_INPUT_BUF // skip when bring up - //TODO: no shuffle, only need to do once under highest freq. +#if 0 if((p->frequency >= 2133) && (p->rank == RANK_0)) //if (p->rank == RANK_0) DramcRXInputBufferOffsetCal(p); @@ -1284,10 +1277,10 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) else u1RankMax = RANK_1; - //vAutoRefreshSwitch(p, DISABLE); //auto refresh is set as disable in LP4_DramcSetting, so don't need to disable again + //vAutoRefreshSwitch(p, DISABLE); vAutoRefreshSwitch(p, DISABLE); -#if 1//(SIMUILATION_CBT == 1) +#if 1 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) { vSetRank(p, s1RankIdx); @@ -1301,7 +1294,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) if (GetEyeScanEnable(p, EYESCAN_TYPE_CBT) == ENABLE) { CmdBusTrainingLP45(p, AUTOK_OFF, EYESCAN_K); - print_EYESCAN_LOG_message(p, EYESCAN_TYPE_CBT); //draw CBT eyescan + print_EYESCAN_LOG_message(p, EYESCAN_TYPE_CBT); } #endif @@ -1317,23 +1310,22 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) No_Parking_On_CLRPLL(p); #endif - //@Darren, Fix high freq keep FSP0 for CA term workaround (PPR abnormal) - // The patch must to do after cbt training + ShuffleDfsToOriginalFSP(p); #endif -#if 0//(SIMULATION_WRITE_LEVELING == 1) +#if 0 for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) { vSetRank(p, s1RankIdx); - vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + vAutoRefreshSwitch(p, DISABLE); #if (!WCK_LEVELING_FM_WORKAROUND) if (u1IsLP4Family(p->dram_type)) #endif { - if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1 + if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) { mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); @@ -1351,27 +1343,27 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) } vSetRank(p, RANK_0); - #if ENABLE_WDQS_MODE_2 // <=DDR1600 reduce PI change code time - if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) // skip DDR800semi, for DDR1200/DDR1600 only + #if ENABLE_WDQS_MODE_2 + if (!(u1IsLP4Div4DDR800(p)) && (p->frequency <= 800) && (p->support_rank_num == RANK_DUAL)) WriteLevelingPosCal(p, PI_BASED); - #elif ENABLE_TX_WDQS // for WDQS mode 1 to avoid dual rank PI code incorrect + #elif ENABLE_TX_WDQS if (!(u1IsLP4Div4DDR800(p)) && (p->support_rank_num == RANK_DUAL)) WriteLevelingPosCal(p, PI_BASED); #endif -#endif /* (SIMULATION_WRITE_LEVELING == 1) */ +#endif for(s1RankIdx=RANK_0; s1RankIdx<u1RankMax; s1RankIdx++) { vSetRank(p, s1RankIdx); -#if 1//(SIMULATION_WRITE_LEVELING == 1) - vAutoRefreshSwitch(p, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable +#if 1 + vAutoRefreshSwitch(p, DISABLE); #if (!WCK_LEVELING_FM_WORKAROUND) if (u1IsLP4Family(p->dram_type)) #endif { - if ((!((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (p->rank == RANK_1))) // skip for DDR800 RANK1 + if ((!((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (p->rank == RANK_1))) && (!(vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE))) // skip for DDR400 { //mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n")); @@ -1387,13 +1379,13 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) TimeProfileBegin(); #endif } -#endif /* (SIMULATION_WRITE_LEVELING == 1) */ +#endif #if LJPLL_FREQ_DEBUG_LOG DDRPhyFreqMeter(p); #endif - vAutoRefreshSwitch(p, ENABLE); //when doing gating, RX and TX calibration, auto refresh should be enable + vAutoRefreshSwitch(p, ENABLE); dramc_rx_dqs_gating_cal(p, AUTOK_OFF, 0); @@ -1407,7 +1399,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) DDRPhyFreqMeter(p); #endif -#if ENABLE_RX_INPUT_BUFF_OFF_K // skip when bring up +#if ENABLE_RX_INPUT_BUFF_OFF_K if((p->frequency >= 2133) && (p->rank == RANK_0)) DramcRXInputBufferOffsetCal(p); @@ -1449,7 +1441,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) #if TX_K_DQM_WITH_WDBI if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON)) { - // K DQM with DBI_ON, and check DQM window spec. + //mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n")); vSwitchWriteDBISettings(p, DBI_ON); DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, FALSE, AUTOK_OFF); @@ -1461,7 +1453,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) if (GetEyeScanEnable(p, EYESCAN_TYPE_TX) == ENABLE) { Dramc_K_TX_EyeScan_Log(p); - print_EYESCAN_LOG_message(p, EYESCAN_TYPE_TX); //draw TX eyescan + print_EYESCAN_LOG_message(p, EYESCAN_TYPE_TX); } #endif @@ -1491,7 +1483,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) CheckRxPinMux(p); #endif - DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, NORMAL_K); + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, NORMAL_K); #ifdef DDR_INIT_TIME_PROFILING CPU_Cycle=TimeProfileEnd(); @@ -1503,8 +1495,8 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) #if ENABLE_EYESCAN_GRAPH if (GetEyeScanEnable(p, EYESCAN_TYPE_RX) == ENABLE) { - DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, EYESCAN_K); - print_EYESCAN_LOG_message(p, EYESCAN_TYPE_RX); //draw RX eyescan + DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, EYESCAN_K); + print_EYESCAN_LOG_message(p, EYESCAN_TYPE_RX); } #endif @@ -1534,7 +1526,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) if(p->femmc_Ready==0) #endif { - if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) // for 3733/4266 + if(p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) { U8 u1ByteIdx, u1HighFreqRXVref[2]; for(u1ByteIdx =0 ; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) @@ -1552,7 +1544,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p) } #endif - vSetRank(p, RANK_0); // Set p's rank back to 0 (Avoids unexpected auto-rank offset calculation in u4RegBaseAddrTraslate()) + vSetRank(p, RANK_0); #if ENABLE_TX_TRACKING DramcDQSOSCShuSettings(p); @@ -1619,7 +1611,7 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL); for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) { - vSetPHY2ChannelMapping(p, channel_idx);// when switching channel, must update PHY to Channel Mapping + vSetPHY2ChannelMapping(p, channel_idx); CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL); vDramCalibrationSingleChannel(p); } @@ -1651,9 +1643,9 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) } #endif - /* Enable/Disable calibrated rank's DBI function accordingly */ + #if ENABLE_READ_DBI - //Read DBI ON + vSetRank(p, RANK_0); vSetPHY2ChannelMapping(p, CHANNEL_A); @@ -1661,7 +1653,7 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) #endif #if ENABLE_WRITE_DBI - // Just settle the DBI parameters which would be stored into shuffle space. + if (p->DBI_W_onoff[p->dram_fsp]) { for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++) @@ -1671,13 +1663,13 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p) for (rank_idx = RANK_0; rank_idx < RANK_MAX; rank_idx++) { vSetRank(p, rank_idx); - DramcWriteShiftMCKForWriteDBI(p, -1); //Tx DQ/DQM -1 MCK for write DBI ON + DramcWriteShiftMCKForWriteDBI(p, -1); } vSetRank(p, RANK_0); } vSetPHY2ChannelMapping(p, CHANNEL_A); - // Improve Write DBI Power + ApplyWriteDBIPowerImprove(p, ENABLE); #if ENABLE_WRITE_DBI_Protect @@ -1782,7 +1774,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e p = &gTimeProfilingDramCtx; gfirst_init_flag = 0; - //DramcConfInfraReset(p); //No need when DDR_INIT_TIME_PROFILING_TEST_CNT=1 + //DramcConfInfraReset(p); #else p = psCurrDramCtx; #endif @@ -1793,7 +1785,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e p->dram_type = dram_type; - /* Convert DRAM_CBT_MODE_EXTERN_T to DRAM_CBT_MODE_T */ + switch ((int)dram_cbt_mode_extern) { case CBT_R0_R1_NORMAL: @@ -1835,7 +1827,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e while (1); #endif - DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); if (gfirst_init_flag == 0) { @@ -1855,7 +1847,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e backup_broadcast = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); mdl_setting(p); - UpdateGlobal10GBEnVariables(p); // @Darren, for 10GB + UpdateGlobal10GBEnVariables(p); TA2_Test_Run_Time_HW_Set_Column_Num(p); DramcBroadcastOnOff(backup_broadcast); } @@ -1867,26 +1859,25 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e vDramcInit_PreSettings(p); #endif - // DramC & PHY init for all channels - //=== First frequency ====== + #if defined(DUMP_INIT_RG_LOG_TO_DE) - vSetDFSFreqSelByTable(p, &gFreqTbl[1]); //0:3200 1:4266, 2:800, 3:1866, 4:1200, 5:2400, 6:1600 + vSetDFSFreqSelByTable(p, &gFreqTbl[1]); #else vSetDFSFreqSelByTable(p, &gFreqTbl[DRAM_DFS_SRAM_MAX-1]); //vSetDFSFreqSelByTable(p, &gFreqTbl[1]); #endif #if (DUAL_FREQ_K==0) || (__FLASH_TOOL_DA__) - gAndroid_DVFS_en = FALSE; //skip ETT DVFS stress + gAndroid_DVFS_en = FALSE; #endif #if RUNTIME_SHMOO_RELEATED_FUNCTION - ett_fix_freq = 1; /* only 1600 & 4266 */ + ett_fix_freq = 1; #endif if (!CONFIG(MEDIATEK_DRAM_DVFS)) - ett_fix_freq = 0x1; // 4266, 1600 + ett_fix_freq = 0x1; if (ett_fix_freq != 0xff) gAndroid_DVFS_en = FALSE; @@ -1895,14 +1886,13 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e DramcSave_Time_For_Cal_Init(p); #endif #ifndef LOOPBACK_TEST - if (p->dram_type == TYPE_LPDDR4X) // LP4/LP4P need confirm + if (p->dram_type == TYPE_LPDDR4X) { - // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 - // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + DramcImpedanceCal(p, 1, IMP_LOW_FREQ); DramcImpedanceCal(p, 1, IMP_HIGH_FREQ); #if ENABLE_SAMSUNG_NT_ODT - DramcImpedanceCal(p, 1, IMP_NT_ODTN); // for Samsung NT ODTN + DramcImpedanceCal(p, 1, IMP_NT_ODTN); #endif } else @@ -1924,7 +1914,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e mcSHOW_DUMP_INIT_RG_MSG(("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1)); #endif - //Clk free run + //EnableDramcPhyDCM(p, 0); DFSInitForCalibration(p); @@ -1947,7 +1937,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e if (Get_MDL_Used_Flag()==GET_MDL_USED) { DramRankNumberDetection(p); - DFSInitForCalibration(p); // Restore setting after rank dection (especially DQ= DQS+16) + DFSInitForCalibration(p); } #endif @@ -1966,13 +1956,13 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e if (Get_MDL_Used_Flag()==GET_MDL_USED) { - // only K CHA to save time + vSetPHY2ChannelMapping(p, CHANNEL_A); - vCalibration_Flow_For_MDL(p); // currently for LP4 + vCalibration_Flow_For_MDL(p); GetDramInforAfterCalByMRR(p, DramInfo); return 0; } - else //NORMAL_USED + else { vDramCalibrationAllChannel(p); GetDramInforAfterCalByMRR(p, DramInfo); @@ -1990,7 +1980,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #if SUPPORT_SAVE_TIME_FOR_CALIBRATION DramcSave_Time_For_Cal_End(p); #endif - LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); S8 u1ShuIdx; S8 s1ShuStart, s1ShuEnd; @@ -2028,7 +2018,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e DramcSave_Time_For_Cal_End(p); #endif } -#endif //(DUAL_FREQ_K) && (!__FLASH_TOOL_DA__) +#endif #ifdef DDR_INIT_TIME_PROFILING @@ -2043,7 +2033,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #if __Petrus_TO_BE_PORTING__ -#if 0//TX_OE_CALIBATION, for DMA test +#if 0 U8 u1ChannelIdx, u1RankIdx; for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++) for (u1RankIdx = 0; u1RankIdx < (p->support_rank_num); u1RankIdx++) @@ -2073,13 +2063,13 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e DramcRegDump(p, SRAM_SHU0); #endif -// ETT_NO_DRAM #endif + #if ETT_NO_DRAM //NoDramDramcRegDump(p); NoDramRegFill(); #endif -#endif //#if __Petrus_TO_BE_PORTING__ +#endif #if DRAMC_MODEREG_CHECK DramcModeReg_Check(p); @@ -2104,22 +2094,22 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (!(p->femmc_Ready == 0)) #elif defined(DDR_INIT_TIME_PROFILING) -if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of loop +if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) #endif #endif { EnableDFSHwModeClk(p); mcSHOW_DBG_MSG2(("DFS_SHUFFLE_HW_MODE: ON\n")); - if (gAndroid_DVFS_en == TRUE) // shuffle to DDR3733 boot + if (gAndroid_DVFS_en == TRUE) { #if defined(SLT) #ifdef SLT_2400_EXIT_PRELOADER - final_shu = SRAM_SHU0; //DDR2400 + final_shu = SRAM_SHU0; #else - final_shu = SRAM_SHU0; //DDR3200 + final_shu = SRAM_SHU0; #endif #else - final_shu = SRAM_SHU0; //DDR4266 + final_shu = SRAM_SHU0; #endif vSetDFSFreqSelByTable(p, get_FreqTbl_by_SRAMIndex(p, final_shu)); @@ -2135,7 +2125,7 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l #if __Petrus_TO_BE_PORTING__ #if (DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM && defined(DUMMY_READ_FOR_TRACKING)) - DramcDummyReadForSPMSideBand(p); // SPM dummy read 1us <-> 4us for DVT only (it must call after TransferPLLToSPMControl) + DramcDummyReadForSPMSideBand(p); #endif EnableDramcTrackingBySPMControl(p); @@ -2164,7 +2154,7 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l #if (__ETT__ && CPU_RW_TEST_AFTER_K) - /* 0x46000000 is LK base addr */ + //while(1) { //if ((s4value = dramc_complex_mem_test (0x46000000, 0x2000)) == 0) @@ -2190,9 +2180,9 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l #ifdef DDR_INIT_TIME_PROFILING CPU_Cycle = TimeProfileEnd(); mcSHOW_TIME_MSG((" (5) After calibration takes %d ms\n\r", CPU_Cycle / 1000)); -#endif // end of DDR_INIT_TIME_PROFILING +#endif -#endif//SW_CHANGE_FOR_SIMULATION +#endif #if defined(FOR_HQA_REPORT_USED) print_HQA_SLT_BIN_message(p); @@ -2212,21 +2202,21 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l return 0; } -///TODO: wait for porting --- + #if FOR_DV_SIMULATION_USED -///TODO: wait for porting +++ + void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t *psra) { U8 ii; - ///TODO: wait for porting +++ + #if GATING_ADJUST_TXDLY_FOR_TRACKING DramcRxdqsGatingPreProcess(DramConfig); #endif - ///TODO: wait for porting --- + vAutoRefreshSwitch(DramConfig, DISABLE); @@ -2239,7 +2229,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args mcSHOW_DBG_MSG6(("\n----->DramcCBT begin...\n")); timestamp_show(); #if CBT_O1_PINMUX_WORKAROUND - CmdBusTrainingLP45(DramConfig, AUTOK_OFF); //Cannot use aito-k in A60868 + CmdBusTrainingLP45(DramConfig, AUTOK_OFF); #else if (psra) CmdBusTrainingLP45(DramConfig, psra->cbt_autok, NORMAL_K); @@ -2254,7 +2244,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args { mcSHOW_DBG_MSG6(("CBT EYESCAN start<-----\n\n")); CmdBusTrainingLP45(DramConfig, AUTOK_OFF, EYESCAN_K); - print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_CBT); //draw CBT eyescan + print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_CBT); mcSHOW_DBG_MSG6(("CBT EYESCAN end<-----\n\n")); } #endif @@ -2264,25 +2254,25 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args ShuffleDfsToOriginalFSP(DramConfig); - ///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ No_Parking_On_CLRPLL(DramConfig); -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- -#endif /* (SIMUILATION_CBT == 1) */ +#endif + +#endif for (ii = RANK_0; ii < DramConfig->support_rank_num; ii++) { vSetRank(DramConfig, ii); - vAutoRefreshSwitch(DramConfig, DISABLE); //When doing WriteLeveling, should make sure that auto refresh is disable + vAutoRefreshSwitch(DramConfig, DISABLE); #if (SIMULATION_WRITE_LEVELING == 1) #if (!WCK_LEVELING_FM_WORKAROUND) if (u1IsLP4Family(DramConfig->dram_type)) #endif { - if (!(u1IsPhaseMode(DramConfig) && (DramConfig->rank == RANK_1))) // skip for DDR800 and DDR400 rank1 + if (!(u1IsPhaseMode(DramConfig) && (DramConfig->rank == RANK_1))) { if (!psra || psra->wl) { mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(PI) begin...\n")); @@ -2299,7 +2289,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args } } } -#endif /* (SIMULATION_WRITE_LEVELING == 1) */ +#endif vAutoRefreshSwitch(DramConfig, ENABLE); @@ -2321,9 +2311,9 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args mcSHOW_DBG_MSG6(("\n----->DramcRxWindowPerbitCal RDDQC begin...\n")); timestamp_show(); - #if 0 // Used when testing LP5 RK1 WCK2CK in high efficiency mode and differential mode. + #if 0 p->rank = 1; - // For test HEFF = 1 / WCKDUAL = 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), 0, SHU_WCKCTRL_WCKDUAL); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), P_Fld(1, SHU_COMMON0_LP5WCKON) | @@ -2335,7 +2325,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n")); } -#endif // (SIMULATION_RX_RDDQC == 1) +#endif #if (SIMULATION_TX_PERBIT == 1) if (!psra || psra->tx_perbit) { @@ -2369,15 +2359,15 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args { mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN begin...\n")); Dramc_K_TX_EyeScan_Log(DramConfig); - print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_TX); //draw TX eyescan + print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_TX); mcSHOW_DBG_MSG6(("\n----->DramcTxEYESCAN end...\n")); } #endif } -#endif // (SIMULATION_TX_PERBIT == 1) +#endif #if (SIMULATION_DATLAT == 1) - if (1) { // No parameter in correspondence with by now + if (1) { mcSHOW_DBG_MSG6(("\n----->DramcRxdatlatCal begin...\n")); timestamp_show(); @@ -2386,7 +2376,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args timestamp_show(); mcSHOW_DBG_MSG6(("DramcRxdatlatCal end<-----\n\n")); } -#endif // (SIMULATION_DATLAT == 1) +#endif #if (SIMULATION_RX_PERBIT == 1) if (!psra || psra->rx_perbit) { @@ -2394,10 +2384,10 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args timestamp_show(); if (psra) DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, - NULL /*Set Vref = 0 to test*/, psra->rx_auto_cal, NORMAL_K); + NULL , psra->rx_auto_cal, NORMAL_K); else DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, - NULL /*Set Vref = 0 to test*/, AUTOK_OFF, NORMAL_K); + NULL , AUTOK_OFF, NORMAL_K); timestamp_show(); mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal end<-----\n\n")); @@ -2405,13 +2395,13 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args if (GetEyeScanEnable(DramConfig, EYESCAN_TYPE_RX) == ENABLE) { mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN start<-----\n\n")); - DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, NULL /*Set Vref = 0 to test*/, AUTOK_ON, EYESCAN_K); - print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_RX); //draw RX eyescan + DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE, NULL , AUTOK_ON, EYESCAN_K); + print_EYESCAN_LOG_message(DramConfig, EYESCAN_TYPE_RX); mcSHOW_DBG_MSG6(("DramcRxWindowPerbitCal EYESCAN end<-----\n\n")); } #endif } -#endif // (SIMULATION_RX_PERBIT == 1) +#endif #if (SIMULATION_RX_DVS == 1) if (DramConfig->frequency >=2133) @@ -2423,10 +2413,10 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args { DramcTxOECalibration(DramConfig); } -#endif // TX_OE_CALIBATION +#endif #if ENABLE_TX_TRACKING - #if 0 /* Starting from Vinson, no need to pre-calculate MR23 for different freqs */ + #if 0 if (gu1MR23Done == FALSE) { DramcDQSOSCAuto(p); @@ -2444,7 +2434,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args DramcDQSOSCShuSettings(DramConfig); #endif -///TODO: wait for porting +++ + #if GATING_ADJUST_TXDLY_FOR_TRACKING DramcRxdqsGatingPostProcess(DramConfig); #endif @@ -2474,7 +2464,7 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args RDSELRunTimeTracking_preset(DramConfig); #endif -///TODO: wait for porting --- + } @@ -2485,20 +2475,20 @@ void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL); for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) { - vSetPHY2ChannelMapping(DramConfig, channel_idx);// when switching channel, must update PHY to Channel Mapping + vSetPHY2ChannelMapping(DramConfig, channel_idx); CKEFixOnOff(DramConfig, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL); DPI_vDramCalibrationSingleChannel(DramConfig, psra); } vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); -///TODO: wait for porting +++ + #if ENABLE_READ_DBI DramcReadDBIOnOff(DramConfig, DramConfig->DBI_R_onoff[DramConfig->dram_fsp]); #endif #if ENABLE_WRITE_DBI - // Just settle the DBI parameters which would be stored into shuffle space. + if (DramConfig->DBI_W_onoff[DramConfig->dram_fsp]) { for (channel_idx = CHANNEL_A; channel_idx < DramConfig->support_channel_num; channel_idx++) @@ -2508,13 +2498,13 @@ void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t for (rank_idx = RANK_0; rank_idx < DramConfig->support_rank_num; rank_idx++) { vSetRank(DramConfig, rank_idx); - DramcWriteShiftMCKForWriteDBI(DramConfig, -1); //Tx DQ/DQM -1 MCK for write DBI ON + DramcWriteShiftMCKForWriteDBI(DramConfig, -1); } vSetRank(DramConfig, RANK_0); } vSetPHY2ChannelMapping(DramConfig, CHANNEL_A); - // Improve Write DBI Power + ApplyWriteDBIPowerImprove(DramConfig, ENABLE); #if ENABLE_WRITE_DBI_Protect @@ -2559,11 +2549,11 @@ void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args_t mcSHOW_DBG_MSG6(("TX_TRACKING: OFF\n")); #endif -///TODO: wait for porting --- + } -///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern) { @@ -2574,10 +2564,10 @@ void RG_dummy_write(DRAMC_CTX_T *p, U32 pattern) void EnablePLLtoSPMControl(DRAMC_CTX_T *p) { - vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); // DFS SPM mode for calibration + vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL); } -#endif // __A60868_TO_BE_PORTING__ -///TODO: wait for porting --- +#endif + void dump_dramc_ctx(DRAMC_CTX_T *p) { @@ -2614,7 +2604,7 @@ void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra) S8 s1ShuIdx; #endif - DRAMC_CTX_T *p = &DramCtx_LPDDR4; //default; + DRAMC_CTX_T *p = &DramCtx_LPDDR4; p->dram_type = ExtConfig->dram_type; if(p->dram_type==TYPE_LPDDR5) @@ -2633,15 +2623,15 @@ void DPI_SW_main_LP4(DRAMC_CTX_T *ExtConfig, cal_sv_rand_args_t *psra) p->freqGroup = ExtConfig->freqGroup; p->new_cbt_mode = ExtConfig->new_cbt_mode; -#if 0 // for Refs +#if 0 DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. - {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. - {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) - {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of unterm group (2400) must k first. - {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR800 /*2*/, DIV4_MODE, SRAM_SHU6, DUTY_DEFAULT, VREF_CALI_OFF, SEMI_OPEN_LOOP_MODE}, + {LP4_DDR1866 /*3*/, DIV8_MODE, SRAM_SHU3, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR1200 /*4*/, DIV8_MODE, SRAM_SHU5, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, + {LP4_DDR2400 /*5*/, DIV8_MODE, SRAM_SHU2, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, + {LP4_DDR1600 /*6*/, DIV8_MODE, SRAM_SHU4, DUTY_DEFAULT, VREF_CALI_ON, CLOSE_LOOP_MODE}, }; #endif if (u1IsLP4Family(p->dram_type)) @@ -2669,36 +2659,34 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { enter_function(); if (!psra) { - /* - * for SA's simulation - */ + mcSHOW_DBG_MSG6(("enter SA's simulation flow.\n")); p->support_channel_num = CHANNEL_SINGLE; p->channel = CHANNEL_A; p->support_rank_num = RANK_DUAL; - /* DramRank */ + p->rank = RANK_0; - /* DRAMC operation clock frequency in MHz */ + #if (fcFOR_CHIP_ID == fcA60868) #if DV_SIMULATION_DFS p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1]; #endif #endif #if 0 - /* DRAM type */ + #if DV_SIMULATION_LP4 p->dram_type = TYPE_LPDDR4X; - //p->freq_sel = LP4_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL; - //p->frequency = 1600;//DV_SIMULATION_RUN_FREQ; - p->freq_sel = LP4_DDR1600;//DV_SIMULATION_RUN_FREQ_SEL; - p->frequency = 800;//DV_SIMULATION_RUN_FREQ; + //p->freq_sel = LP4_DDR3200; + //p->frequency = 1600; + p->freq_sel = LP4_DDR1600; + p->frequency = 800; #else p->dram_type = TYPE_LPDDR5; - p->freq_sel = LP5_DDR3200;//DV_SIMULATION_RUN_FREQ_SEL; - p->frequency = 1600;//DV_SIMULATION_RUN_FREQ; + p->freq_sel = LP5_DDR3200; + p->frequency = 1600; #endif #endif - /* DRAM Fast switch point type, only for LP4, useless in LP3 */ + p->dram_fsp = FSP_0; #if 0 @@ -2710,31 +2698,31 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; #endif #endif - /* IC and DRAM read DBI */ - p->DBI_R_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */ - p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + + p->DBI_R_onoff[FSP_0] = DBI_OFF; + p->DBI_R_onoff[FSP_1] = DBI_OFF; #if ENABLE_READ_DBI - p->DBI_R_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_1] = DBI_ON; #else - p->DBI_R_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + p->DBI_R_onoff[FSP_1] = DBI_OFF; #endif - /* IC and DRAM write DBI */ - p->DBI_W_onoff[FSP_0] = DBI_OFF; /* only for LP4, uesless in LP3 */ - p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + + p->DBI_W_onoff[FSP_0] = DBI_OFF; + p->DBI_W_onoff[FSP_1] = DBI_OFF; #if ENABLE_WRITE_DBI - p->DBI_W_onoff[FSP_1] = DBI_ON; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_1] = DBI_ON; #else - p->DBI_W_onoff[FSP_1] = DBI_OFF; /* only for LP4, uesless in LP3 */ + p->DBI_W_onoff[FSP_1] = DBI_OFF; #endif - /* bus width */ + p->data_width = DATA_WIDTH_16BIT; - /* DRAMC internal test engine-2 parameters in calibration */ + p->test2_1 = DEFAULT_TEST2_1_CAL; p->test2_2 = DEFAULT_TEST2_2_CAL; - /* DRAMC test pattern in calibration */ + p->test_pattern = TEST_XTALK_PATTERN; - /* u2DelayCellTimex100 */ - p->u2DelayCellTimex100 = 250; // @Darren, 2.5ps + + p->u2DelayCellTimex100 = 250; p->vendor_id = 0x1; p->density = 0; /* p->ranksize = {0,0}; */ @@ -2751,50 +2739,48 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->lp5_cbt_phase = CBT_PHASE_FALLING; #endif } else { - /* - * for DV's regression - */ + mcSHOW_DBG_MSG6(("enter DV's regression flow.\n")); p->support_channel_num = CHANNEL_SINGLE; p->channel = psra->calibration_channel; p->support_rank_num = RANK_DUAL; - /* DramRank */ + p->rank = psra->calibration_rank; - /* DRAMC operation clock frequency in MHz */ + #if (fcFOR_CHIP_ID == fcA60868) #if DV_SIMULATION_DFS p->pDFSTable = &gFreqTbl[DRAM_DFS_SRAM_MAX-1]; #endif #endif - /* DRAM type */ + //p->dram_type = psra->dram_type; - //p->freq_sel = LP5_DDR4266;//DV_SIMULATION_RUN_FREQ_SEL; - //p->frequency = 2133;//DV_SIMULATION_RUN_FREQ; + //p->freq_sel = LP5_DDR4266; + //p->frequency = 2133; set_type_freq_by_svargs(p, psra); - /* DRAM Fast switch point type, only for LP4, useless in LP3 */ + p->dram_fsp = FSP_0; p->dram_cbt_mode[RANK_0] = psra->rk0_cbt_mode; p->dram_cbt_mode[RANK_1] = psra->rk1_cbt_mode; - /* IC and DRAM read DBI */ - p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */ - p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; /* only for LP4, uesless in LP3 */ + + p->DBI_R_onoff[FSP_0] = (psra->mr3_value >> 6) & 0x1; + p->DBI_R_onoff[FSP_1] = (psra->mr3_value >> 6) & 0x1; p->DBI_R_onoff[FSP_2] = (psra->mr3_value >> 6) & 0x1; - /* IC and DRAM write DBI */ - p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */ - p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; /* only for LP4, uesless in LP3 */ + + p->DBI_W_onoff[FSP_0] = (psra->mr3_value >> 7) & 0x1; + p->DBI_W_onoff[FSP_1] = (psra->mr3_value >> 7) & 0x1; p->DBI_W_onoff[FSP_2] = (psra->mr3_value >> 7) & 0x1; - /* bus width */ + p->data_width = DATA_WIDTH_16BIT; - /* DRAMC internal test engine-2 parameters in calibration */ + p->test2_1 = DEFAULT_TEST2_1_CAL; p->test2_2 = DEFAULT_TEST2_2_CAL; - /* DRAMC test pattern in calibration */ + p->test_pattern = TEST_XTALK_PATTERN; - /* u2DelayCellTimex100 */ + p->u2DelayCellTimex100 = 0; p->vendor_id = 0x1; p->density = 0; @@ -2815,8 +2801,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->dram_fsp = (psra->mr13_value >> 7) & 0x1; } -// p->dram_type = TYPE_LPDDR5; -// #define __FW_VER__ "WCK leveling with DLY +16! and MRinit for FSP1 -- 777" + #define __FW_VER__ "All struct move done, new RX range -- 444" if (u1IsLP4Family(p->dram_type)) { @@ -2859,7 +2844,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { value = u4Dram_Register_Read(p, DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL ); mcSHOW_DBG_MSG6(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value)); - DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on + DramcBroadcastOnOff(DRAMC_BROADCAST_ON); Global_Option_Init(p); @@ -2869,15 +2854,14 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { DDRPhyFreqSel(p, p->pDFSTable->freq_sel); vSetPHY2ChannelMapping(p, p->channel); -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- +#endif if (u1IsLP4Family(p->dram_type)) { - vSetDFSFreqSelByTable(p, p->pDFSTable); // for LP4x + vSetDFSFreqSelByTable(p, p->pDFSTable); } - else ///TODO: Jeremy, modify this when LP5 gFreqtbl ready + else { DDRPhyFreqSel(p, p->freq_sel); } @@ -2885,19 +2869,18 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { #if (SIMULATION_SW_IMPED == 1) mcSHOW_DBG_MSG6(("\n----->DramcImpedanceCal begin...\n")); timestamp_show(); - // LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 - // LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266 + DramcImpedanceCal(p, 1, IMP_LOW_FREQ); DramcImpedanceCal(p, 1, IMP_HIGH_FREQ); timestamp_show(); mcSHOW_DBG_MSG6(("DramcImpedanceCal end<-----\n\n")); -#endif /* (SIMULATION_SW_IMPED == 1) */ +#endif #if DV_SIMULATION_INIT_C - ///TODO: wait for porting +++ + DramcInit(p); - // Before calibration setting + vBeforeCalibration(p); #if __A60868_TO_BE_PORTING__ #if DV_SIMULATION_BEFORE_K @@ -2906,15 +2889,14 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { #endif #ifdef DUMP_INIT_RG_LOG_TO_DE - #if 0 //Dump RG to other shuffle for FT used, don't delete + #if 0 mcSHOW_DUMP_INIT_RG_MSG(("\n\n\n\n\n\n===== Save to Shuffle RG ======\n")); DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); #endif while (1); #endif #endif -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- +#endif #if (SIMULATION_MIOCK_JMETER == 1) @@ -2923,26 +2905,24 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { p->u2DelayCellTimex100 = GetVcoreDelayCellTime(p); timestamp_show(); mcSHOW_DBG_MSG6(("DramcMiockJmeter end<-----\n\n")); -#endif /* (SIMULATION_MIOCK_JMETER == 1) */ +#endif #if (SIMULATION_8PHASE == 1) if(is_lp5_family(p) && (p->frequency >= 2133)) { mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n")); timestamp_show(); - Dramc8PhaseCal(p); // it must set before duty calib + Dramc8PhaseCal(p); timestamp_show(); mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n")); } -#endif /* (SIMULATION_8PHASE == 1) */ - - ///TODO: wait for porting +++ - #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings - DPI_vDramCalibrationAllChannel(p, psra); // for DDR1600 1:8 mode +#endif + #if !DV_SIMULATION_DFS + DPI_vDramCalibrationAllChannel(p, psra); #endif #if DV_SIMULATION_DFS DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, vGet_Current_SRAMIdx(p)); - LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + LoadShuffleSRAMtoDramc(p, vGet_Current_SRAMIdx(p), DRAM_DFS_REG_SHU1); #if (fcFOR_CHIP_ID == fcA60868) for (s1ShuIdx = DRAM_DFS_SRAM_MAX - 10; s1ShuIdx >= 0; s1ShuIdx--) @@ -2952,7 +2932,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { { vSetDFSFreqSelByTable(p, &gFreqTbl[s1ShuIdx]); DramcInit(p); - // Before calibration setting + vBeforeCalibration(p); #if DV_SIMULATION_BEFORE_K @@ -2963,31 +2943,31 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { if(is_lp5_family(p) && (p->frequency >= 2133)) { mcSHOW_DBG_MSG6(("\n----->Dramc8PhaseCal begin...\n")); timestamp_show(); - Dramc8PhaseCal(p); // it must set before duty calib + Dramc8PhaseCal(p); timestamp_show(); mcSHOW_DBG_MSG6(("Dramc8PhaseCal end<-----\n\n")); } - #endif /* (SIMULATION_8PHASE == 1) */ + #endif - #if !DV_SIMULATION_DFS // No calib will use legacy mode init settings - DPI_vDramCalibrationAllChannel(p, psra); // for gDVDFSTbl + #if !DV_SIMULATION_DFS + DPI_vDramCalibrationAllChannel(p, psra); #endif DramcSaveToShuffleSRAM(p, DRAM_DFS_REG_SHU0, gFreqTbl[s1ShuIdx].SRAMIdx); } #endif - ///TODO: wait for porting --- - ///TODO: wait for porting +++ + + vAfterCalibration(p); #if SIMULATION_RUNTIME_CONFIG DramcRunTimeConfig(p); #endif -#if 0//__A60868_TO_BE_PORTING__ +#if 0 #if DV_SIMULATION_AFTER_K vApplyConfigAfterCalibration(p); #endif @@ -3003,11 +2983,10 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { mcSHOW_DBG_MSG(("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3)); #endif -#if 0//DV_SIMULATION_DFS // NOTE: Don't use DramcDFSDirectJump_SPMMode. it will cause NULL object access. - // high freq -> low freq +#if 0 for (s1ShuIdx = 0; s1ShuIdx < DV_SIMULATION_DFS_SHU_MAX; s1ShuIdx++) DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx); - // low freq -> high freq + for (s1ShuIdx = DV_SIMULATION_DFS_SHU_MAX - 1; s1ShuIdx >= DRAM_DFS_SHUFFLE_1; s1ShuIdx--) DramcDFSDirectJump_SRAMShuRGMode(p, gDVDFSTbl[s1ShuIdx].SRAMIdx); #endif @@ -3017,8 +2996,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { #endif RG_dummy_write(p, 0xAAAAAAAA); -#endif // __A60868_TO_BE_PORTING__ - ///TODO: wait for porting --- +#endif //Temp_TA2_Test_After_K(p); @@ -3033,9 +3011,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { exit_function(); } -/* - * start_dramk -- c calibration entry for SA's simulation - */ + void start_dramk(void) { DRAMC_CTX_T *p; @@ -3047,11 +3023,7 @@ void start_dramk(void) exit_function(); } -/* - * sa_calibration -- c calibration entry for DV's regression - * - * @psra: random arguments from sv to c for calibration controlling - */ + void sa_calibration(cal_sv_rand_args_t *psra) { DRAMC_CTX_T *p; @@ -3083,7 +3055,7 @@ out: } -///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ #if SW_CHANGE_FOR_SIMULATION void main(void) @@ -3092,37 +3064,37 @@ void main(void) DRAMC_CTX_T DramConfig; DramConfig.channel = CHANNEL_A; DramConfig.support_rank_num = RANK_DUAL; - // DramRank + DramConfig.rank = RANK_0; - // DRAM type + DramConfig.dram_type = TYPE_LPDDR4X; - // DRAM Fast switch point type, only for LP4, useless in LP3 + DramConfig.dram_fsp = FSP_0; - // DRAM CBT mode, only for LP4, useless in LP3 + DramConfig.dram_cbt_mode[RANK_0] = CBT_NORMAL_MODE; DramConfig.dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE; - // IC and DRAM read DBI - DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3 + + DramConfig.DBI_R_onoff[FSP_0] = DBI_OFF; #if ENABLE_READ_DBI - DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3 + DramConfig.DBI_R_onoff[FSP_1] = DBI_ON; #else - DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3 + DramConfig.DBI_R_onoff[FSP_1] = DBI_OFF; #endif - // IC and DRAM write DBI - DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; // only for LP4, uesless in LP3 + + DramConfig.DBI_W_onoff[FSP_0] = DBI_OFF; #if ENABLE_WRITE_DBI - DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; // only for LP4, uesless in LP3 + DramConfig.DBI_W_onoff[FSP_1] = DBI_ON; #else - DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF; // only for LP4, uesless in LP3 + DramConfig.DBI_W_onoff[FSP_1] = DBI_OFF; #endif - // bus width + DramConfig.data_width = DATA_WIDTH_32BIT; - // DRAMC internal test engine-2 parameters in calibration + DramConfig.test2_1 = DEFAULT_TEST2_1_CAL; DramConfig.test2_2 = DEFAULT_TEST2_2_CAL; - // DRAMC test pattern in calibration + DramConfig.test_pattern = TEST_XTALK_PATTERN; - // DRAMC operation clock frequency in MHz + DramConfig.frequency = 800; //DramConfig.enable_rx_scan_vref =DISABLE; @@ -3133,7 +3105,7 @@ void main(void) Global_Option_Init(&DramConfig); - // DramC & PHY init for all channels + DDRPhyFreqSel(&DramConfig, LP4_DDR1600); @@ -3150,8 +3122,8 @@ void main(void) vSetPHY2ChannelMapping(&DramConfig, DramConfig.channel); #if SIMULATION_SW_IMPED - DramcImpedanceCal(&DramConfig, 1, LOW_FREQ); //for DRVN/P and ODTN - //DramcImpedanceCal(&DramConfig, 1, HIGH_FREQ); //for DRVN/P and ODTN + DramcImpedanceCal(&DramConfig, 1, LOW_FREQ); + //DramcImpedanceCal(&DramConfig, 1, HIGH_FREQ); #endif @@ -3171,10 +3143,10 @@ void main(void) #endif #if SIMULATION_GATING - // Gating calibration of single rank + DramcRxdqsGatingCal(&DramConfig); - // Gating calibration of both rank + //DualRankDramcRxdqsGatingCal(&DramConfig); #endif @@ -3183,10 +3155,10 @@ void main(void) #endif #if SIMULATION_DATLAT - // RX Datlat calibration of single rank + DramcRxdatlatCal(&DramConfig); - // RX Datlat calibration of two rank + //DramcDualRankRxdatlatCal(&DramConfig); #endif @@ -3200,12 +3172,12 @@ void main(void) #endif #if ENABLE_READ_DBI - //Read DBI ON + SetDramModeRegForReadDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_R_onoff[DramConfig.dram_fsp]); #endif #if ENABLE_WRITE_DBI - //Write DBI ON + DramcWriteShiftMCKForWriteDBI(&DramConfig, -1); SetDramModeRegForWriteDBIOnOff(&DramConfig, DramConfig.dram_fsp, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); #endif @@ -3218,8 +3190,7 @@ void main(void) DramcWriteDBIOnOff(&DramConfig, DramConfig.DBI_W_onoff[DramConfig.dram_fsp]); #endif } -#endif //SW_CHANGE_FOR_SIMULATION -#endif // __A60868_TO_BE_PORTING__ -///TODO: wait for porting --- +#endif +#endif #endif diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c index 56624129f4..e5e3b19b09 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c @@ -210,12 +210,12 @@ void mdl_setting(DRAMC_CTX_T *p) emi_init(); enable_infra_emi_broadcast(1); - //The following is MDL settings + set_cen_emi_cona(emi_set->EMI_CONA_VAL); set_cen_emi_conf(emi_set->EMI_CONF_VAL); set_cen_emi_conh(emi_set->EMI_CONH_VAL); - // CHNA and CHNB uses the same CH0 setting + set_chn_emi_cona(emi_set->CHN0_EMI_CONA_VAL); //set_chn_emi_conc(0x4); enable_infra_emi_broadcast(0); @@ -466,13 +466,13 @@ unsigned int is_discrete_lpddr4(void) #if DRAM_AUXADC_CONFIG return dram_type_auxadc; #else - return TRUE; /* for 4ch DSC */ + return TRUE; #endif } unsigned int mt_get_dram_type_from_hw_trap(void) { - #if 1 //for bring up use + #if 1 return TYPE_LPDDR4X; #else unsigned int trap = get_dram_type() & 0x7; @@ -643,7 +643,7 @@ static void restore_pmic_setting(void) return; } -#if 0 //for bring-up +#if 0 dramc_set_vmdd_voltage(TYPE_LPDDR4, 1125000); dramc_set_vmddq_voltage(TYPE_LPDDR4, 600000); dramc_set_vmddr_voltage(750000); @@ -693,28 +693,28 @@ void release_dram(void) int i; int counter = TIMEOUT; - // scy: restore pmic setting (VCORE, VDRAM, VSRAM, VDDQ) + restore_pmic_setting(); - drm_release_rg_dramc_conf_iso();//Release DRAMC/PHY conf ISO + drm_release_rg_dramc_conf_iso(); -#if DDR_RESERVE_NEW_MODE //new modw +#if DDR_RESERVE_NEW_MODE ASVA5_8_New_Mode_1(); Dramc_DDR_Reserved_Mode_setting(); - drm_release_rg_dramc_iso();//Release PHY IO ISO + drm_release_rg_dramc_iso(); ASVA5_8_New_Mode_2(); -#else //old mode +#else Dramc_DDR_Reserved_Mode_setting(); ASVA5_8_CSCA_Pull_Down_EN(); - drm_release_rg_dramc_iso();//Release PHY IO ISO + drm_release_rg_dramc_iso(); ASVA5_8_CSCA_Pull_Down_DIS(); #endif - drm_release_rg_dramc_sref();//Let DRAM Leave SR + drm_release_rg_dramc_sref(); while(counter) { - if(is_dramc_exit_slf() == 1) /* expect to exit dram-self-refresh */ + if(is_dramc_exit_slf() == 1) break; counter--; } @@ -733,15 +733,11 @@ void release_dram(void) } Dramc_DDR_Reserved_Mode_AfterSR(); -#if DDR_RESERVE_NEW_MODE //new modw +#if DDR_RESERVE_NEW_MODE ASVA5_8_New_Mode_3(); #endif - //Expect to Use LPDDR3200 and PHYPLL as output, so no need to handle - //shuffle status since the status will be reset by system reset - //There is an PLLL_SHU_GP in SPM which will reset by system reset - // setup for EMI: touch center EMI and channel EMI to enable CLK dramc_crit("[DDR reserve] EMI CEN CONA: %x\n", get_cen_emi_cona()); dramc_crit("[DDR reserve] EMI CHN CONA: %x\n", get_chn_emi_cona()); for (i=0;i<10;i++); @@ -777,8 +773,8 @@ static int check_qvl(DRAM_INFO_BY_MRR_T *dram_info, unsigned int dram_type) mr5 = dram_info->u2MR5VendorID & 0xFF; - rank_size[0] = dram_info->u8MR8Density[0]; //now only K CHA to save time - rank_size[1] = dram_info->u8MR8Density[1]; //now only K CHA to save time + rank_size[0] = dram_info->u8MR8Density[0]; + rank_size[1] = dram_info->u8MR8Density[1]; result = platform_get_mcp_id(id, emmc_nand_id_len,&fw_id_len); for (i = 0; i < num_of_emi_records; i++) { @@ -786,23 +782,23 @@ static int check_qvl(DRAM_INFO_BY_MRR_T *dram_info, unsigned int dram_type) "qvl", i, "type", qvl_list[i].type, "mr5", qvl_list[i].iLPDDR3_MODE_REG_5, - "rank0_size", qvl_list[i].DRAM_RANK_SIZE[0], //DA need (unsigned int) (qvl_list[i].DRAM_RANK_SIZE[0] & 0xFFFFFFFF), (unsigned int)(qvl_list[i].DRAM_RANK_SIZE[0] >> 32), - "rank1_size", qvl_list[i].DRAM_RANK_SIZE[1]);//DA need (unsigned int) (qvl_list[i].DRAM_RANK_SIZE[1] & 0xFFFFFFFF), (unsigned int)(qvl_list[i].DRAM_RANK_SIZE[1] >> 32)); - /* check DRAM type */ + "rank0_size", qvl_list[i].DRAM_RANK_SIZE[0], + "rank1_size", qvl_list[i].DRAM_RANK_SIZE[1]); + if ((qvl_list[i].type & 0xF) != (dram_type & 0xF)) continue; - /* check MR5 */ + if (qvl_list[i].iLPDDR3_MODE_REG_5 != mr5) continue; - /* check rank size */ + if (qvl_list[i].DRAM_RANK_SIZE[0] != rank_size[0]) continue; if (qvl_list[i].DRAM_RANK_SIZE[1] != rank_size[1]) continue; - /* check storage ID if MCP */ + if (qvl_list[i].type & 0xF00) { if (!result) { if (memcmp(id, qvl_list[i].ID, qvl_list[i].id_length)) { @@ -845,8 +841,8 @@ int get_dram_rank_nr(void) cen_emi_cona = g_default_emi_setting.EMI_CONA_VAL; - if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0 - (cen_emi_cona & (1 << 16)) != 0 ) //for channel 1 + if ((cen_emi_cona & (1 << 17)) != 0 || + (cen_emi_cona & (1 << 16)) != 0 ) return 2; else return 1; @@ -864,9 +860,7 @@ int get_dram_freq_cnt(void) #if (FOR_DV_SIMULATION_USED==0) #if !__FLASH_TOOL_DA__ && !__ETT__ -/* - * setup block - */ + void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK]) { @@ -1403,14 +1397,14 @@ static int update_dram_setting(EMI_SETTINGS *default_emi_setting, unsigned int d default_emi_setting->iLPDDR3_MODE_REG_5 = dram_info->u2MR5VendorID; - if (dram_info->u4RankNum == 1) { // single rank + if (dram_info->u4RankNum == 1) { if (dram_info->u1DieNum[RANK_0] == 1) default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL; else if (dram_info->u1DieNum[RANK_0] == 2) default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_BYTE; else return -1; - } else if (dram_info->u4RankNum == 2) { // dual rank + } else if (dram_info->u4RankNum == 2) { if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 1)) default_emi_setting->dram_cbt_mode_extern = CBT_R0_R1_NORMAL; else if ((dram_info->u1DieNum[RANK_0] == 1) && (dram_info->u1DieNum[RANK_1] == 2)) @@ -1435,7 +1429,7 @@ static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_IN unsigned long long die_size; emi_info->dram_type = dram_type; - emi_info->ch_num = 2; //2; //FIXME use GPIO + emi_info->ch_num = 2; emi_info->bank_width[0] = 3; emi_info->bank_width[1] = 3; emi_info->col_width[0] = 10; @@ -1451,37 +1445,30 @@ static int decode_emi_info(EMI_INFO_T *emi_info, unsigned int dram_type, DRAM_IN //emi_info->rank_size[1] /= emi_info->ch_num; emi_info->rk_num = dram_info->u4RankNum; - /** - * ranksize row width - * 4Gb -> 15 - * 8Gb -> 16 - * 16Gb -> 17 - * 32Gb -> 18 - **/ for (i = 0; i < emi_info->rk_num; i++) { die_size = emi_info->rank_size[i] / dram_info->u1DieNum[i]; switch (die_size | (dram_info->u1DieNum[i] << 4) | u1IsLP4Family(dram_type)) { - case 0x20000011ULL: // 4Gb, x16, LP4 - case 0x20000021ULL: // 4Gb, x8, LP4 - case 0x40000021ULL: // 8Gb, x8, LP4 - case 0x30000011ULL: // 6Gb, x16, LP4 - case 0x40000011ULL: // 8Gb, x16, LP4 + case 0x20000011ULL: + case 0x20000021ULL: + case 0x40000021ULL: + case 0x30000011ULL: + case 0x40000011ULL: emi_info->row_width[i] = 15; break; - case 0x30000021ULL: // 6Gb, x8, LP4 - case 0x60000011ULL: // 12Gb, x16, LP4 - case 0x80000011ULL: // 16Gb, x16, LP4 + case 0x30000021ULL: + case 0x60000011ULL: + case 0x80000011ULL: emi_info->row_width[i] = 16; break; - case 0x060000021ULL: // 12Gb, x8, LP4 - case 0x080000021ULL: // 16Gb, x8, LP4 - case 0x0C0000011ULL: // 24Gb, x16, LP4 - case 0x100000011ULL: // 32Gb, x16, LP4 + case 0x060000021ULL: + case 0x080000021ULL: + case 0x0C0000011ULL: + case 0x100000011ULL: emi_info->row_width[i] = 17; break; - case 0x0C0000021ULL: // 24Gb, x8, LP4 - case 0x100000021ULL: // 32Gb, x8, LP4 + case 0x0C0000021ULL: + case 0x100000021ULL: emi_info->row_width[i] = 18; break; default: @@ -1542,7 +1529,7 @@ void dram_auto_detection(void) DRAMC_ASSERT(0); } - // different files for mt6880 and 6890 (different folder) + ret = update_emi_setting(&g_default_emi_setting, &emi_info); if (ret) { dramc_crit("[DRAMC] update_emi_setting err %d\n", ret); @@ -1566,20 +1553,9 @@ void mt_set_emi(struct dramc_param *dparam) EMI_rank_swap_handle(); #endif - // set voltage and hw trapping before mdl + setup_dramc_voltage_by_pmic(); -/* - if ((doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_all_3094_0725"))) - freq_table_are_all_3094(); - else if (doe_get_config("dram_all_1534_0725")) - freq_table_are_all_1534(); - else if (doe_get_config("dram_opp0_3733_others_3094_0825")) - freq_table_opp0_3733_others_3094(); - else if (doe_get_config("dram_opp0_3094_others_1534_0725")) - freq_table_opp0_3094_others_1534(); - else if (doe_get_config("dram_opp0_2400_others_1534_0725")) - freq_table_opp0_2400_others_1534(); -*/ + #if DRAM_AUXADC_CONFIG get_ch_num_by_auxadc(); #endif @@ -1690,7 +1666,7 @@ unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset) unsigned int get_dummy_read_addr(dram_addr_t *dram_addr) { - return get_dramc_addr(dram_addr, 0x20); // 32-byte align for dummy RW pattern + return get_dramc_addr(dram_addr, 0x20); } static unsigned int get_ta2_addr(dram_addr_t *dram_addr) @@ -1705,20 +1681,20 @@ void init_ta2_single_channel(unsigned int channel) DRAMC_CTX_T *p = psCurrDramCtx; int test_cnt; - // disable self test engine1 and self test engine2 + temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel)) & 0x1FFFFFFF; vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), temp); - // set rank address for test agent to auto + temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel)) & 0x8FFFFFFF; temp |= (0x4 << 28); vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A4, channel), temp); - // set test for both rank0 and rank1 + temp = u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel)) & 0xFFFFFFF0; vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), temp | 0x1); - // set base address for test agent to reserved space + dram_addr.ch = channel; dram_addr.rk = 0; temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1, channel)) & 0x00000007); @@ -1727,11 +1703,11 @@ void init_ta2_single_channel(unsigned int channel) temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1+0x200, channel)) & 0x00000007); vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_RK_TEST2_A1+0x200, channel), temp | get_ta2_addr(&dram_addr)); - // set test length (offset) to 0x20 + temp = (u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A2, channel)) & 0x0000000F) | (0x20 << 4); vIO32Write4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A2, channel), temp); - // set TA2 pattern to the worst case + test_cnt = (get_dram_rank_nr() > 1) ? 1 : 0; vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), 0, TEST2_A3_TESTAUDPAT); vIO32WriteFldAlign(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3, channel), test_cnt, TEST2_A3_TESTCNT); @@ -1759,7 +1735,7 @@ void update_last_dramc_info(void) unsigned int *curr; DRAMC_CTX_T *p = psCurrDramCtx; - // init checksum and magic pattern + if(last_dramc_info_ptr->ta2_result_magic != LAST_DRAMC_MAGIC_PATTERN) { last_dramc_info_ptr->ta2_result_magic = LAST_DRAMC_MAGIC_PATTERN; last_dramc_info_ptr->ta2_result_last = 0; @@ -1776,9 +1752,9 @@ void update_last_dramc_info(void) last_dramc_info_ptr->ta2_result_checksum ^= last_dramc_info_ptr->reboot_count; } - // TODO: check DCS status - // read data from latch register and reset + + for (chn = 0; chn < CHANNEL_NUM; ++chn) { //dramc_crit("[LastDRAMC] latch result before RST: %x\n", u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn))); latch_result = (latch_result << 16) | u4IO32Read4B(DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_WDT_DBG_SIGNAL, chn)) & 0xFFFF; @@ -1806,11 +1782,11 @@ void init_ta2_all_channel(void) update_last_dramc_info(); - //cache flush after update dramc info + #if CFG_ENABLE_DCACHE plat_clean_invalidate_dcache(); #endif - // TODO: consider DCS + for (chn = 0; chn < CHANNEL_NUM; ++chn) init_ta2_single_channel(chn); } @@ -1845,7 +1821,7 @@ void dram_fatal_exception_detection_start(void) last_dramc_info_ptr = (LAST_DRAMC_INFO_T *) get_dbg_info_base(KEY_LAST_DRAMC); #if SUPPORT_SAVE_TIME_FOR_CALIBRATION - part_dram_data_addr = get_part_addr("boot_para") + 0x100000; // addr = 0x108000 + part_dram_data_addr = get_part_addr("boot_para") + 0x100000; if (part_dram_data_addr != 0x0) dramc_crit("[dramc] init partition address is 0x%llx\n", part_dram_data_addr); else { @@ -1859,7 +1835,7 @@ void dram_fatal_exception_detection_start(void) if ((g_boot_reason == BR_POWER_KEY) || (g_boot_reason == BR_USB) || mtk_wdt_is_pmic_full_reset() || (is_last_dramc_initialized() == 0)){ - /* cold boot: initialize last_dram_fatal_err_flag and dram_fatal_err_flag */ + dramc_crit("[dramc] init SRAM region for DRAM exception detection\n"); last_dramc_info_ptr->last_fatal_err_flag = 0x0; last_dramc_info_ptr->storage_api_err_flag = 0x0; @@ -1968,7 +1944,7 @@ void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int o #endif -#if (FOR_DV_SIMULATION_USED==0) // for DV sim build pass +#if (FOR_DV_SIMULATION_USED==0) int doe_get_config(const char* feature) { #if defined(ENABLE_DOE) @@ -2000,9 +1976,9 @@ void log_to_storage(const char c) if (log_start && (!logen)) { logen = 1; logcount = 0; - part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000; // addr = 0x1f300000, the first 1MB for debug + part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000; memset(&logbuf, 0, sizeof(logbuf)); - for (clr_count = 0; clr_count < 3072 ; clr_count++) //3M + for (clr_count = 0; clr_count < 3072 ; clr_count++) ret = blkdev_write(bootdev, (part_dram_data_addr_uart + (1024 * clr_count)), 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER)); } @@ -2012,7 +1988,7 @@ void log_to_storage(const char c) // else logbuf[logcount] = (char) c; logcount = logcount + 1; - //write to storage + if (logcount==1024) { logcount = 0; ret = blkdev_write(bootdev, part_dram_data_addr_uart, 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER)); @@ -2048,7 +2024,7 @@ static u16 crc16(const u8* data, u32 length){ static void assign_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data) { - /* need to initialize checksum to 0 before calculation */ + shu_data->checksum = 0; shu_data->checksum = crc16((u8*)shu_data, sizeof(*shu_data)); } @@ -2065,7 +2041,7 @@ static int check_checksum_for_dram_data(DRAM_CALIBRATION_SHU_DATA_T *shu_data) #if !__ETT__ static void assign_checksum_for_mdl_data(DRAM_CALIBRATION_MRR_DATA_T *mrr_info) { - /* need to initialize checksum to 0 before calculation */ + mrr_info->checksum = 0; mrr_info->checksum = crc16((u8*)mrr_info, sizeof(*mrr_info)); } @@ -2118,7 +2094,7 @@ int read_offline_dram_calibration_data(DRAM_DFS_SRAM_SHU_T shuffle, SAVE_TIME_FO dramc_info("read calibration data from shuffle %d(For verify: WL B0:%u, B1: %u)\n", shuffle, params->wr_level[CHANNEL_A][RANK_0][0], params->wr_level[CHANNEL_B][RANK_0][0]); - /* copy the data stored in storage to the data structure for calibration */ + memcpy(offLine_SaveData, params, sizeof(*offLine_SaveData)); fastk_data_dump(params, shuffle); @@ -2137,7 +2113,7 @@ int clean_dram_calibration_data(void) #else #if 0 -DRAM_CALIBRATION_DATA_T dram_data; // using global variable to avoid stack overflow +DRAM_CALIBRATION_DATA_T dram_data; static int read_offline_dram_mdl_data(DRAM_INFO_BY_MRR_T *DramInfo) { @@ -2273,24 +2249,24 @@ unsigned int get_mr8_by_mrr(U8 channel, U8 rank) } #endif -/* Get Channel Number from AUXADC */ + #if DRAM_AUXADC_CONFIG static unsigned int get_ch_num_by_auxadc(void) { - unsigned int ret = 0, voltage = 0;//, u1ch_num = 0; + unsigned int ret = 0, voltage = 0; ret = iio_read_channel_processed(5, &voltage); if (ret == 0) { - if (voltage < 700) /* 4CH with DSC */ + if (voltage < 700) { channel_num_auxadc = CHANNEL_FOURTH; dram_type_auxadc = PINMUX_DSC; } - else if (voltage >= 700 && voltage < 1200) /* 2CH with eMCP */ + else if (voltage >= 700 && voltage < 1200) { channel_num_auxadc = CHANNEL_DUAL; dram_type_auxadc = PINMUX_EMCP; } - else /* 2CH with DSC*/ + else { channel_num_auxadc = CHANNEL_DUAL; dram_type_auxadc = PINMUX_DSC; diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c index d0a7f2073e..5f5b7a2bc9 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c @@ -14,20 +14,20 @@ // Global variables //----------------------------------------------------------------------------- -//U8 gu1MR23Done = FALSE; /* Not used starting from Vinson (all freqs use MR23=0x3F) */ +//U8 gu1MR23Done = FALSE; U8 gu1MR23[CHANNEL_NUM][RANK_MAX]; -/* DQSOSCTHRD_INC & _DEC are 12 bits (Starting from Vinson) */ + U16 gu2DQSOSCTHRD_INC[CHANNEL_NUM][RANK_MAX]; U16 gu2DQSOSCTHRD_DEC[CHANNEL_NUM][RANK_MAX]; -U16 gu2MR18[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR18 (DQS ocillator count - MSB) */ -U16 gu2MR19[CHANNEL_NUM][RANK_MAX]; /* Stores MRR MR19 (DQS ocillator count - LSB) */ -U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX]; /* Stores tDQSOSC results */ +U16 gu2MR18[CHANNEL_NUM][RANK_MAX]; +U16 gu2MR19[CHANNEL_NUM][RANK_MAX]; +U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX]; U16 gu2DQSOscCnt[CHANNEL_NUM][RANK_MAX][2]; void DramcDQSOSCInit(void) { - memset(gu1MR23, 0x3F, sizeof(gu1MR23)); /* MR23 should be 0x3F for all freqs (Starting from Vinson) */ + memset(gu1MR23, 0x3F, sizeof(gu1MR23)); memset(gu2DQSOSCTHRD_INC, 0x6, sizeof(gu2DQSOSCTHRD_INC)); memset(gu2DQSOSCTHRD_DEC, 0x4, sizeof(gu2DQSOSCTHRD_DEC)); } @@ -44,14 +44,12 @@ static DRAM_STATUS_T DramcStartDQSOSC_SCSM(DRAMC_CTX_T *p) u4MRSRKBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); - //!!R_DMMRSRK(R_DMMPCRKEN=1) specify rank0 or rank1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSC2RK); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN); - //R_DMDQSOSCENEN, 0x1E4[10]=1 for DQSOSC Start - //Wait dqsoscen_response=1 (dramc_conf_nao, 0x3b8[29]) - //R_DMDQSOSCENEN, 0x1E4[10]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_DQSOSCENEN); do @@ -65,7 +63,7 @@ static DRAM_STATUS_T DramcStartDQSOSC_SCSM(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4MRSRKBak, SWCMD_CTRL0_MRSRK); - if (u4TimeCnt == 0)//time out + if (u4TimeCnt == 0) { mcSHOW_ERR_MSG(("Start fail (time out)\n")); return DRAM_FAIL; @@ -106,7 +104,7 @@ static DRAM_STATUS_T DramcStartDQSOSC_RTSWCMD(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_RTSWCMD_HPRI_EN); - if (u4TimeCnt == 0)//time out + if (u4TimeCnt == 0) { mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out)\n")); return DRAM_FAIL; @@ -123,27 +121,27 @@ static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p) U32 u4TimeCnt = TIME_OUT_CNT; U32 u4RegBackupAddress[] = {DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)}; - // Backup rank, CKE fix on/off, HW MIOCK control settings + DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); - // Disable HW MIOCK control to make CLK always on + DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL); mcDELAY_US(1); - //if CKE2RANK=1, only need to set CKEFIXON, it will apply to both rank. + CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL); - //ZQCAL Start + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_WCK2DQI_START_SWTRIG); do { u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE); u4TimeCnt --; - mcDELAY_US(1); // Wait tZQCAL(min) 1us or wait next polling + mcDELAY_US(1); mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); @@ -158,7 +156,7 @@ static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p) return DRAM_FAIL; } - // Restore rank, CKE fix on, HW MIOCK control settings + DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n")); @@ -174,7 +172,7 @@ static DRAM_STATUS_T DramcStartDQSOSC(DRAMC_CTX_T *p) return DramcStartDQSOSC_SCSM(p); #elif DQSOSC_RTSWCMD return DramcStartDQSOSC_RTSWCMD(p); -#else //DQSOSC_SWCMD +#else return DramcStartDQSOSC_SWCMD(p); #endif } @@ -194,16 +192,14 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p) u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); u4RegBak[1] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); - //LPDDR4-3200, PI resolution = tCK/64 =9.76ps - //Only if MR23>=16, then error < PI resolution. - //Set MR23 == 0x3f, stop after 63*16 clock + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1GetRank(p), MRS_MRSRK); DramcModeRegWriteByRank(p, p->rank, 23, u1MR23); - //SW mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS); - // Disable HW MIOCK control to make CLK always on + DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL); CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); @@ -215,17 +211,17 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p) DramcModeRegReadByRank(p, p->rank, 19, &u2MR19); #if (SW_CHANGE_FOR_SIMULATION == 0) - //B0 + u2DQSCnt = (u2MR18 & 0x00FF) | ((u2MR19 & 0x00FF) << 8); if (u2DQSCnt != 0) - u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); //tDQSOSC = 16*MR23*tCK/2*count + u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); else u2DQSOsc[0] = 0; - //B1 + u2DQSCnt = (u2MR18 >> 8) | ((u2MR19 & 0xFF00)); if (u2DQSCnt != 0) - u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); //tDQSOSC = 16*MR23*tCK/2*count + u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p)); else u2DQSOsc[1] = 0; mcSHOW_DBG_MSG2(("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1])); @@ -246,14 +242,11 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p) #if ENABLE_TX_TRACKING -/* Using gu2DQSOSC results calculated from DramcDQSOSCAuto - * -> calculate DQSOSCTHRD_INC, DQSOSCTHRD_DEC - * _INC, _DEC formulas are extracted from "Verification plan of Vinson LPDDR4 HW TX Tracking" doc - */ + DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p) { #if (SW_CHANGE_FOR_SIMULATION == 0) - /* Preloader doesn't support floating point numbers -> Manually expand/simpify _INC, _DEC formula */ + U8 u1MR23 = gu1MR23[p->channel][p->rank]; U16 u2DQSOSC = gu2DQSOSC[p->channel][p->rank]; U32 u4tCK = 1000000 / DDRPhyGetRealFreq(p); @@ -272,16 +265,16 @@ DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p) } -/* Sets DQSOSC_BASE for specified rank/byte */ + DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p) { U16 u2DQSOscCnt[2]; DramcDQSOSCAuto(p); - //B0 + gu2DQSOscCnt[p->channel][p->rank][0] = u2DQSOscCnt[0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8); - //B1 + gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00)); if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && (gu2DQSOscCnt[p->channel][p->rank][1] == 0)) @@ -359,7 +352,7 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p) u1FILT_PITHRD = 0x12; u1W2R_SEL = 0x2; } - else //4266 + else { u1FILT_PITHRD = 0x17; u1W2R_SEL = 0x2; @@ -372,7 +365,7 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p) } u1DQSOSCRCNT = ((p->frequency<< u1IsDiv4))/100; - if ((p->frequency%100) != 0) // @Darren, Round up for tOSCO timing (40ns) + if ((p->frequency%100) != 0) u1DQSOSCRCNT++; if (gu1MR23[p->channel][RANK_1] > gu1MR23[p->channel][RANK_0]) @@ -385,16 +378,15 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p) if (u1RoundUp != 0) u2PRDCNT++; - //Don't power down dram during DQS interval timer run time, (MR23[7:0] /4) + (tOSCO/MCK unit/16) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT); //@Darren, unit: 16MCK and tOSCO=40ns/MCK - //set tOSCO constraint to read MR18/MR19, should be > 40ns/MCK - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);//@Darren, unit: MCK to meet spec. tOSCO=40ns/MCK + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT); + + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), (u1FILT_PITHRD>>1), SHU_TX_SET0_DQS2DQ_FILT_PITHRD); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(u1W2R_SEL, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL)); - /* Starting from Vinson, DQSOSCTHRD_INC & _DEC is split into RK0 and RK1 */ - //Rank 0/1 + for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) { vSetRank(p, u1RankIdx); @@ -403,8 +395,7 @@ DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p) } vSetRank(p, u1RankIdxBak); - //set interval to do MPC(start DQSOSC) command, and dramc send DQSOSC start to rank0/1/2 at the same time - //TX tracking period unit: 3.9us + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2DQSOSCENCNT, SHU_DQSOSC_SET0_DQSOSCENCNT); return DRAM_OK; @@ -415,22 +406,22 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p) DRAM_RANK_T rank_bak = u1GetRank(p); DRAM_CHANNEL_T ch_bak = p->channel; - //Enable TX tracking new mode + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), 1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); - //Enable Freq_RATIO update + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0), P_Fld(1, TX_TRACKING_SET0_SHU_PRELOAD_TX_HW) | P_Fld(0, TX_TRACKING_SET0_SHU_PRELOAD_TX_START) | P_Fld(0, TX_TRACKING_SET0_SW_UP_TX_NOW_CASE)); - //DQSOSC MPC command violation + #if ENABLE_TMRRI_NEW_MODE vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 1, MPC_CTRL_MPC_BLOCKALE_OPT); #else vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_MPC_BLOCKALE_OPT); #endif - //DQS2DQ UI/PI setting controlled by HW + #if ENABLE_SW_TX_TRACKING vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW); #else @@ -441,15 +432,14 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p) #endif vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW); - //Set dqsosc oscillator run time by MRW - //write RK0 MR23 + #if 0 vSetRank(p, RANK_0); vSetPHY2ChannelMapping(p, CHANNEL_A); DramcModeRegWrite(p, 23, u1MR23); vSetPHY2ChannelMapping(p, CHANNEL_B); DramcModeRegWrite(p, 23, u1MR23); - //write RK1 MR23 + vSetRank(p, RANK_1); vSetPHY2ChannelMapping(p, CHANNEL_A); DramcModeRegWrite(p, 23, u1MR23); @@ -457,7 +447,7 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p) DramcModeRegWrite(p, 23, u1MR23); #endif - //Enable HW read MR18/MR19 for each rank + #if ENABLE_SW_TX_TRACKING vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSCRDIS); #else @@ -472,8 +462,8 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN); } - //@Jouling, Update MP setting - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN); //Set as 1 to fix issue of RANK_SINGLE, dual rank can also be enable + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSC_CALEN); @@ -483,7 +473,7 @@ void DramcHwDQSOSC(DRAMC_CTX_T *p) void Enable_TX_Tracking(DRAMC_CTX_T *p) { - //open loop mode and semi-open do not enable tracking + if (u1IsPhaseMode(p) == TRUE) { vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS); @@ -498,8 +488,8 @@ void Enable_TX_Tracking(DRAMC_CTX_T *p) #if RDSEL_TRACKING_EN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq) { - //Only enable at DDR4266 - if (u2Freq >= RDSEL_TRACKING_TH) //add if(u1ShuffleIdx==DRAM_DFS_SRAM_MAX) to avoid enable tx-tracking when running DDR800 as RG-SHU0 + + if (u2Freq >= RDSEL_TRACKING_TH) { vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN); vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) @@ -515,7 +505,7 @@ void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq) #ifdef HW_GATING void Enable_Gating_Tracking(DRAMC_CTX_T *p) { - //open loop mode and semi-open do not enable tracking + if (u1IsPhaseMode(p) == TRUE) { vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL, @@ -552,14 +542,14 @@ void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p) else vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); - // Set 1 to be make TX DQS/DQ/DQM PI take effect when TX OE low, for new cross rank mode. + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0); if (!isLP4_DSC) vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1); else vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD2, 1, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA); - // Default settings before init + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, 1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, 1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, 1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA); @@ -578,7 +568,7 @@ void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p) } } -#if ENABLE_TX_WDQS // @Darren, To avoid unexpected DQS toggle during calibration +#if ENABLE_TX_WDQS void Enable_TxWDQS(DRAMC_CTX_T *p) { BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; @@ -609,8 +599,8 @@ static void Enable_and_Trigger_TX_Retry(DRAMC_CTX_T *p) | P_Fld(0, TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT) | P_Fld(1, TX_RETRY_SET0_XSR_TX_RETRY_OPT) | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_EN) - | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN)); //If using SW mode, don;t have to set this field - //open loop mode and semi-open do not enable tracking + | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN)); + if (u1IsPhaseMode(p) == TRUE) { vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS); @@ -722,8 +712,7 @@ void DramcSWTxTracking(DRAMC_CTX_T *p) u2MR1819_Runtime[p->rank][1] = u2MR1819_Runtime[p->rank][0]; } - //INC : MR1819>base. PI- - //DEC : MR1819<base. PI+ + for (byteIdx = 0; byteIdx < 2; byteIdx++) { U16 deltaMR1819 = 0; @@ -828,16 +817,8 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) U32 u4WbrBackup = GetDramcBroadcast(); DramcBroadcastOnOff(DRAMC_BROADCAST_ON); - //Monitor window size setting - //DDRPHY.SHU*_B*_DQ5.RG_RX_ARDQS0_DVS_DLY_B* (suggested value from A-PHY owner) -//WHITNEY_TO_BE_PORTING + #if (fcFOR_CHIP_ID == fc8195) - // 6400 5500 4266 3733 3200 2400 1600 1200 800 - //UI 156p 181p 234p 268p 312p 417p 625p 833p 1250p - //DVS_EN O O O O O O X X X - //INI 1 2 3 N=5 N=5 N=7 N=12 N=15 N=15 - //DVS delay O O O X X X X X X - //calibration if(p->frequency >= 3200) { @@ -874,12 +855,12 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) #if RX_DVS_NOT_SHU_WA if (isLP4_DSC) { - //CA_CMD5_RG_RX_ARCLK_DVS_EN is not shu RG, so always enable. Fixed in IPMv2 + u1DVS_En =1; } #endif - //Note that DVS DLY is _DQS_ and DVS_EN is _DQ_ + vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ5), u1DVS_Delay, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0); if (!isLP4_DSC) { @@ -890,13 +871,12 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD5), u1DVS_Delay, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY); } - /* Bian_co HW design issue: run-time PBYTE flag will lose it's function and become per-bit -> set to 0 */ + vIO32WriteFldMulti((DDRPHY_REG_SHU_B0_DQ7), P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)); vIO32WriteFldMulti((DDRPHY_REG_SHU_B1_DQ7), P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)); - //Note that DVS DLY is _DQS_ and DVS_EN is _DQ_ - //Enable A-PHY DVS LEAD/LAG + vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ11), u1DVS_En, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); if (!isLP4_DSC) { @@ -911,13 +891,12 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p) } #endif -///TODO: wait for porting +++ + #if __A60868_TO_BE_PORTING__ #if RX_DLY_TRACK_ONLY_FOR_DEBUG void DramcRxDlyTrackDebug(DRAMC_CTX_T *p) { - /* indicate ROW_ADR = 2 for dummy write & read for Rx dly track debug feature, avoid pattern overwrite by MEM_TEST - * pattern(0xAAAA5555) locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */ + vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(2, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR) | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR) @@ -937,16 +916,16 @@ void DramcRxDlyTrackDebug(DRAMC_CTX_T *p) vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA2, 0xAAAA5555); vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA3, 0xAAAA5555); - //disable Rx dly track debug and clear status lock + vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN) | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR) | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN)); - //trigger dummy write pattern 0xAAAA5555 + vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG); vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG); - // enable Rx dly track debug feature + vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN) | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR) | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN)); @@ -955,7 +934,7 @@ void DramcRxDlyTrackDebug(DRAMC_CTX_T *p) void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p) { U32 backup_rank, u1ChannelBak, u4value; - U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;//channel A/B ... + U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num; u1ChannelBak = p->channel; backup_rank = u1GetRank(p); @@ -1025,7 +1004,7 @@ void DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T *p, bool bEn) { if (bEn == 1) { - vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)//Retry once + vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM) | P_Fld(1, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE) | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN) | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN) @@ -1049,7 +1028,7 @@ void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn) if (bEn == 1) { - vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent + vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL); vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM) | P_Fld(1, DUMMY_RD_DUMMY_RD_SW)); @@ -1079,7 +1058,7 @@ void DramcImpedanceHWSaving(DRAMC_CTX_T *p) void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p) { U8 u1CHAB_en = DISABLE; - #if 0 //Impedance tracking offset for DRVP+2 + #if 0 vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL1, P_Fld(2, IMPEDAMCE_CTRL1_DQS1_OFF) | P_Fld(2, IMPEDAMCE_CTRL1_DOS2_OFF)); vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL2, P_Fld(2, IMPEDAMCE_CTRL2_DQ1_OFF) | P_Fld(2, IMPEDAMCE_CTRL2_DQ2_OFF)); #endif @@ -1098,39 +1077,35 @@ void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMP_CTRL1, 1, MISC_IMP_CTRL1_IMP_ABN_LAT_EN); #endif - //Write (DRAMC _BASE+ 0x8B) [31:0] = 32'he4000000//enable impedance tracking + //u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE; - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);//Set CHA this bit to enable dual channel tracking + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN); + - //During shuffle, after CH_A IMP update done, CH_B has no enough time to update (IMPCAL_IMPCAL_DRVUPDOPT=1) - //enable ECO function for impedance load last tracking result of previous shuffle level (IMPCAL_IMPCAL_CHGDRV_ECO_OPT=1) - //enable ECO function for impcal_sm hange when DRVP>=0x1D (IMPCAL_IMPCAL_SM_ECO_OPT=1) vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_HW) | P_Fld(0, MISC_IMPCAL_IMPCAL_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_SWVALUE_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_NEW_OLD_SL) | P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_SM_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPBINARY) | P_Fld(1, MISC_IMPCAL_DRV_ECO_OPT)); - //dual channel continuously tracking @ system busy, self-refresh, Hhbrid-S1 - //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, 0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT); - //@tg.Only CHA do Impcal tracking, CHB sync CHA result value + vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE)); vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE)); - // no update imp CA, because CA is unterm now + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV); - // CH_A set 1, CH_B set 0 (mp setting) + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV) | - P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting - P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting + P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | + P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV) | - P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | //Update mp setting - P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); //Update mp setting + P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | + P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); #if (CHANNEL_NUM > 2) if (channel_num_auxadc > 2) { vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV)); @@ -1142,8 +1117,8 @@ void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p) } #endif - //Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode) - vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF); //@Maoauo, Wait AB refresh to avoid IO drive via logic design + + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF); vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DQDRVSWUPD); } #endif @@ -1164,9 +1139,9 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel) mcSHOW_DBG_MSG3(("[IMPTrackingStatus] CH=%d\n", p->channel)); // if (u1Channel == CHANNEL_A) - {//460 464: ODTN DRVP, 468 46C: DRVN DRVP + { + - //DQS DQS_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2); DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2); DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2); @@ -1174,7 +1149,7 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel) DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1); DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1); - //DQ + DQ_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2); DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2); DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2); @@ -1182,7 +1157,7 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel) DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1); DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1); - //CMD + CMD_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2); CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2); CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2); @@ -1195,23 +1170,23 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel) { U8 shu_level; - //Channel B is workaround + shu_level = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHUSTATUS), SHUSTATUS_SHUFFLE_LEVEL); mcSHOW_DBG_MSG(("shu_level=%d\n", shu_level)); - //DQ + DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQDRV2_DRVP); DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_DQDRV1_DRVP); DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQODT2_ODTN); DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_DQODT1_ODTN); - //DQS + DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV2_DRVP); DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV1_DRVP); DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT2_ODTN); DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT1_ODTN); - //CMD + CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV2_DRVP); CMD_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV1_DRVP); CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_CMDODT2_ODTN); @@ -1232,9 +1207,7 @@ void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel) #endif } #endif -/* divRoundClosest() - to round up to the nearest integer - * discard four, but treat five as whole (of decimal points) - */ + int divRoundClosest(const int n, const int d) { return ((n < 0) ^ (d < 0))? ((n - d / 2) / d): ((n + d / 2) / d); @@ -1245,10 +1218,10 @@ int divRoundClosest(const int n, const int d) void FreqJumpRatioCalculation(DRAMC_CTX_T *p) { U32 shuffle_src_freq, shuffle_dst_index, jump_ratio_index; - U16 u2JumpRatio[12] = {0}; /* Used to record __DBQUOTE_ANCHOR__ calulation results */ + U16 u2JumpRatio[12] = {0}; U16 u2Freq = 0; - /* Calculate jump ratios and save to u2JumpRatio array */ + jump_ratio_index = 0; if (vGet_DDR_Loop_Mode(p) == CLOSE_LOOP_MODE) @@ -1264,7 +1237,7 @@ void FreqJumpRatioCalculation(DRAMC_CTX_T *p) while (1); #endif } - #if 0 //cc mark since been removed in new flow + #if 0 if (pDstFreqTbl->freq_sel == LP4_DDR800) { u2JumpRatio[jump_ratio_index] = 0; @@ -1287,7 +1260,7 @@ void FreqJumpRatioCalculation(DRAMC_CTX_T *p) } } - /* Save jumpRatios into corresponding register fields */ + vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(u2JumpRatio[0], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) | P_Fld(u2JumpRatio[1], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) | P_Fld(u2JumpRatio[2], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) @@ -1318,13 +1291,13 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p) #if 1//(fcFOR_CHIP_ID == fc8195) mck2ui = 4; #else - ///TODO: use vGet_Div_Mode() instead later + if (vGet_Div_Mode(p) == DIV16_MODE) - mck2ui = 4; /* 1:16 mode */ + mck2ui = 4; else if (vGet_Div_Mode(p) == DIV8_MODE) - mck2ui = 3; /* 1: 8 mode */ + mck2ui = 3; else - mck2ui = 2; /* 1: 4 mode */ + mck2ui = 2; #endif mcSHOW_DBG_MSG2(("Pre-setting of DQS Precalculation\n")); @@ -1381,7 +1354,7 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p) vSetRank(p, backup_rank); - /* Disable DDR800semi and DDR400open precal */ + if (vGet_DDR_Loop_Mode(p) != CLOSE_LOOP_MODE) { set_value = 1; @@ -1401,7 +1374,7 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p) } #if 0 -void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calculation +void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p) { U8 u1ByteIdx, u1RankNum, u1RankBackup = p->rank; U8 u1ShuLevel = vGet_Current_SRAMIdx(p); @@ -1414,28 +1387,28 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula mcDUMP_REG_MSG(("Pre-setting of DQS Precalculation\n")); if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7)) - { //SHU4, 5, 6, 7 - u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30; //Offset of phase0 UI register - u1Delay_Addr[1] = 0x38; //Offset of phase1 UI register + { + u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30; + u1Delay_Addr[1] = 0x38; u2Byte_offset = 0xc; } else if (u1ShuLevel >= SRAM_SHU8) - { //SHU8, 9 - u1Delay_Addr[0] = 0x260; //Offset of phase0 UI register - u1Delay_Addr[1] = 0x268; //Offset of phase1 UI register + { + u1Delay_Addr[0] = 0x260; + u1Delay_Addr[1] = 0x268; u2Byte_offset = 0x4; } - else //SHU0, 1, 2, 3 + else { - u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4); //Offset of phase0 UI register - u1Delay_Addr[1] = 0x8; //Offset of phase1 UI register + u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4); + u1Delay_Addr[1] = 0x8; u2Byte_offset = 0xc; } - u1Delay_Fld[0] = u1ShuLevel % 2; //Field of phase0 PI and UI - u1Delay_Fld[1] = u1ShuLevel % 4; //Field of phase1 UI + u1Delay_Fld[0] = u1ShuLevel % 2; + u1Delay_Fld[1] = u1ShuLevel % 4; - switch (u1Delay_Fld[0]) //Phase0 UI and PI + switch (u1Delay_Fld[0]) { case 0: TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0; @@ -1451,17 +1424,17 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula if (u1ShuLevel == SRAM_SHU8) { - TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0; //Byte0 - TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0; //Byte1 + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0; + TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0; } else if (u1ShuLevel == SRAM_SHU9) { - TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0; //Byte0 - TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0; //Byte1 + TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0; + TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0; } - else //(u1ShuLevel < SRAM_SHU8) + else { - switch (u1Delay_Fld[1]) //Phase1 UI + switch (u1Delay_Fld[1]) { case 0: TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0; @@ -1492,31 +1465,31 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED); u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS0IEN); } - else //Byte1 + else { u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED); u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED); u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS1IEN); } - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);//UI - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld); //PI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld); if (u1ByteIdx == 0) { u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1); u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1); } - else //Byte1 + else { u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1); u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1); } if ((u1ShuLevel == SRAM_SHU8) || (u1ShuLevel == SRAM_SHU9)) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]); //phase1 UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]); else - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]); //phase1 UI + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]); } } vSetRank(p, u1RankBackup); @@ -1527,18 +1500,16 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p) { - //DQS pre-K new mode - //cc mark removed vIO32WriteFldAlign_All(DRAMC_REG_RK0_PRE_TDQSCK15, 0x1, RK0_PRE_TDQSCK15_SHUFFLE_LEVEL_MODE_SELECT); - //Enable pre-K HW + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW); - //Select HW flow + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS); - //Set Auto save to RG + vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL); } #endif -#if 0 /* CC mark to use DV initial setting */ +#if 0 void DramcHWGatingInit(DRAMC_CTX_T *p) { #ifdef HW_GATING @@ -1546,7 +1517,7 @@ void DramcHWGatingInit(DRAMC_CTX_T *p) 0, MISC_SHU_STBCAL_STBCALEN); vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(0, MISC_STBCAL_STBCAL2R) | - //cc mark P_Fld(0,STBCAL_STB_SELPHYCALEN) | + //P_Fld(0,STBCAL_STB_SELPHYCALEN) | P_Fld(0, MISC_STBCAL_STBSTATE_OPT) | P_Fld(0, MISC_STBCAL_RKCHGMASKDIS) | P_Fld(0, MISC_STBCAL_REFUICHG) | @@ -1585,7 +1556,7 @@ void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff) { #ifdef HW_GATING - // STBCAL2_STB_DBG_EN = 0x3, byte0/1 enable + U8 u1EnB0B1 = (u1OnOff == ENABLE)? 0x3: 0x0; vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2, @@ -1605,7 +1576,7 @@ void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff) #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) #if (__ETT__ || CPU_RW_TEST_AFTER_K) -#if 0 // Please use memeset to initail value, due to different CHANNEL_NUM +#if 0 U16 u2MaxGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; U16 u2MinGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; #endif @@ -1692,7 +1663,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel) else u1RankMax = RANK_1; - //Run Time HW Gating Debug Information + //for(u1RankIdx=0; u1RankIdx<u1RankMax; u1RankIdx++) for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) { @@ -1707,11 +1678,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel) for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++) { - //DFS_ST(Shuffle Level): bit[15:14] - //Shift_R(Lead): bit[13] - //Shift_L(Lag) : bit[12] - //UI_DLY : bit[11:06] - //PI_DLY : bit[05:00] + u4DBG_Dqs01_Info = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B01_STB_DBG_INFO_00 + 0x4 * u1Info_NUM)); u4DBG_Dqs0_Info = (u4DBG_Dqs01_Info >> 0) & 0xffff; u4DBG_Dqs1_Info = (u4DBG_Dqs01_Info >> 16) & 0xffff; @@ -1742,11 +1709,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel) u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI)); } - //Run Time HW Gating Max and Min Value Record - //Run Time HW Gating MAX_DLY UI : bit[27:22] - //Run Time HW Gating MAX_DLY PI : bit[21:16] - //Run Time HW Gating MIN_DLY UI : bit[11:06] - //Run Time HW Gating MIN_DLY PI : bit[05:00] + u4Dqs0_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY)); u2Dqs0_UI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 22) & 0x3f; u2Dqs0_PI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 16) & 0x3f; @@ -1779,8 +1742,7 @@ static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel) void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p) { #if RX_PICG_NEW_MODE - //RX FIFO debug feature, MP setting should enable debug function for Gating error information - //APHY control new mode + U32 u1ChannelBak, u4value; U8 u1ChannelIdx; @@ -1790,7 +1752,7 @@ void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p) { p->channel = u1ChannelIdx; - u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); //DDRPHY NAO bit24~27 + u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); if (u4value) { mcSHOW_DBG_MSG2(("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value)); diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c index 63384cf4f8..9f57ce4713 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c @@ -68,14 +68,14 @@ void DramcBroadcastOnOff(U32 bOnOff) #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) #if (fcFOR_CHIP_ID == fcA60868) - return; //disable broadcast in A60868 + return; #endif #if __Petrus_TO_BE_PORTING__ U8 u1BroadcastStatus = 0; - // INFRA_RSVD3[9:8] = protect_set_clr_mask + u1BroadcastStatus = (*((volatile unsigned int *)(INFRA_RSVD3)) >> 8) & 0x3; - if (u1BroadcastStatus & 0x1) // Enable new infra access by Preloader + if (u1BroadcastStatus & 0x1) { if (bOnOff == DRAMC_BROADCAST_ON) *((volatile unsigned int *)(DRAMC_WBR_SET)) = DRAMC_BROADCAST_SET; @@ -170,7 +170,7 @@ void CheckDramcWBR(U32 u4address) if (channel_num_auxadc > 2) { channel_and_value = 0x3; } - #else //for channel number = 1 or 2 + #else channel_and_value = 0x1; #endif if ((((u4address - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & channel_and_value) != CHANNEL_A) @@ -209,7 +209,7 @@ static U8 GetChannelInfoToConf(DRAMC_CTX_T *p) emi_set = &g_default_emi_setting; - u4value = (emi_set->EMI_CONA_VAL >> 8) & 0x3;//CONA 8,9th 0:1ch, 1:2ch, 2:4ch + u4value = (emi_set->EMI_CONA_VAL >> 8) & 0x3; if (u4value == 0) u1ch_num = CHANNEL_SINGLE; @@ -267,48 +267,45 @@ void vSetFSPNumber(DRAMC_CTX_T *p) static void setFreqGroup(DRAMC_CTX_T *p) { - /* Below listed conditions represent freqs that exist in ACTimingTable - * -> Should cover freqGroup settings for all real freq values - */ { - if (p->frequency <= 200) // DDR400 + if (p->frequency <= 200) { p->freqGroup = 200; } - else if (p->frequency <= 400) // DDR800 + else if (p->frequency <= 400) { p->freqGroup = 400; } - else if (p->frequency <= 600) // DDR1200 + else if (p->frequency <= 600) { p->freqGroup = 600; } - else if (p->frequency <= 800) // DDR1600 + else if (p->frequency <= 800) { p->freqGroup = 800; } - else if (p->frequency <= 933) //DDR1866 + else if (p->frequency <= 933) { p->freqGroup = 933; } - else if (p->frequency <= 1200) //DDR2400, DDR2280 + else if (p->frequency <= 1200) { p->freqGroup = 1200; } - else if (p->frequency <= 1333) // DDR2667 + else if (p->frequency <= 1333) { p->freqGroup = 1333; } - else if (p->frequency <= 1600) // DDR3200 + else if (p->frequency <= 1600) { p->freqGroup = 1600; } - else if (p->frequency <= 1866) // DDR3733 + else if (p->frequency <= 1866) { p->freqGroup = 1866; } - else // DDR4266 + else { p->freqGroup = 2133; } @@ -328,7 +325,7 @@ U16 DDRPhyGetRealFreq(DRAMC_CTX_T *p) { U8 u1SRAMShuLevel = vGet_Current_SRAMIdx(p); - /* The result may be used as divisor, so need to avoid 0 returned */ + if(gddrphyfmeter_value[u1SRAMShuLevel]) { return gddrphyfmeter_value[u1SRAMShuLevel]; @@ -341,28 +338,27 @@ U16 DDRPhyGetRealFreq(DRAMC_CTX_T *p) #if __ETT__ || defined(SLT) void GetPhyPllFrequency(DRAMC_CTX_T *p) { - //U8 u1ShuLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL); + U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP); U32 u4PLL5_ADDR = DDRPHY_REG_SHU_PHYPLL1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; U32 u4PLL8_ADDR = DDRPHY_REG_SHU_PHYPLL2 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; U32 u4B0_DQ = DDRPHY_REG_SHU_B0_DQ1 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; U32 u4PLL3_ADDR = DDRPHY_REG_SHU_PHYPLL3 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; - //Darren-U32 u4PLL4 = DDRPHY_SHU_PLL4 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; // for DDR4266 + U32 u4B0_DQ6 = DDRPHY_REG_SHU_B0_DQ6 + SHU_GRP_DDRPHY_OFFSET * u1ShuLevel; - /* VCOFreq = FREQ_XTAL x ((RG_RCLRPLL_SDM_PCW) / 2^(RG_*_RCLRPLL_PREDIV)) / 2^(RG_*_RCLRPLL_POSDIV) */ U32 u4SDM_PCW = u4IO32ReadFldAlign(u4PLL5_ADDR, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW); U32 u4PREDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_PREDIV); U32 u4POSDIV = u4IO32ReadFldAlign(u4PLL8_ADDR, SHU_PHYPLL2_RG_RPHYPLL_POSDIV); U32 u4CKDIV4 = u4IO32ReadFldAlign(u4B0_DQ, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0); U8 u1FBKSEL = u4IO32ReadFldAlign(u4PLL3_ADDR, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL); - //Darren-U16 u2CKMUL2 = u4IO32ReadFldAlign(u4PLL4, SHU_PLL4_RG_RPHYPLL_RESERVED); + U8 u1SopenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0); U8 u1OpenDQ = u4IO32ReadFldAlign(u4B0_DQ6, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0); U32 u4VCOFreq = (((52>>u4PREDIV)*(u4SDM_PCW>>8))>>u4POSDIV) << u1FBKSEL; U32 u4DataRate = u4VCOFreq>>u4CKDIV4; - if ((u1SopenDQ == ENABLE)||(u1OpenDQ == ENABLE)) // for 1:4 mode DDR800 (3.2G/DIV4) and DDR400 (1.6G/DIV4) + if ((u1SopenDQ == ENABLE)||(u1OpenDQ == ENABLE)) u4DataRate >>= 2; //mcSHOW_DBG_MSG(("PCW=0x%X, u4PREDIV=%d, u4POSDIV=%d, CKDIV4=%d, DataRate=%d\n", u4SDM_PCW, u4PREDIV, u4POSDIV, u4CKDIV4, u4DataRate)); @@ -420,19 +416,13 @@ DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p) VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p) { #if FOR_DV_SIMULATION_USED - return VREF_CALI_OFF; //@ tg add for simulation speed up + return VREF_CALI_OFF; #else return p->pDFSTable->vref_calibartion_enable; #endif } -/* vGet_Dram_CBT_Mode - * Due to current HW design (both ranks share the same set of ACTiming regs), mixed - * mode LP4 now uses byte mode ACTiming settings. This means most calibration steps - * should use byte mode code flow. - * Note: The below items must have per-rank settings (Don't use this function) - * 1. CBT training 2. TX tracking - */ + DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p) { if (p->support_rank_num == RANK_DUAL) @@ -466,7 +456,7 @@ void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p) "fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n" "===============================================================================\n", p->dram_type, - p->frequency /*DDRPhyFMeter()*/, + p->frequency, p->channel, p->rank, p->dram_fsp, @@ -641,9 +631,8 @@ void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel) if (p->dram_type == TYPE_LPDDR4P) p->odt_onoff = ODT_OFF; - setFreqGroup(p); /* Set p->freqGroup to support freqs not in ACTimingTable */ + setFreqGroup(p); - ///TODO: add DBI_onoff by condition //p->DBI_onoff = p->odt_onoff; } @@ -672,45 +661,45 @@ U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p) U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type) { #if ENABLE_EYESCAN_GRAPH -#if (fcFOR_CHIP_ID == fcA60868) //need check unterm highest freq is saved at SRAM_SHU4?? - //CBT +#if (fcFOR_CHIP_ID == fcA60868) + if (get_type == EYESCAN_TYPE_CBT) - if (ENABLE_EYESCAN_CBT==1) return ENABLE; //TO DO :Temp Force open EYESCAN + if (ENABLE_EYESCAN_CBT==1) return ENABLE; + - //RX if (get_type == EYESCAN_TYPE_RX) - if (ENABLE_EYESCAN_RX==1) return ENABLE; //TO DO :Temp Force open EYESCAN + if (ENABLE_EYESCAN_RX==1) return ENABLE; + - //TX if (get_type == EYESCAN_TYPE_TX) - if (ENABLE_EYESCAN_TX==1) return ENABLE; //TO DO :Temp Force open EYESCAN + if (ENABLE_EYESCAN_TX==1) return ENABLE; #else - //CBT + if (get_type == EYESCAN_TYPE_CBT) { if (gCBT_EYE_Scan_flag==DISABLE) return DISABLE; - if (gCBT_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE; //K All freq - if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; // K highest freq - if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE; // K unterm highest freq + if (gCBT_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE; + if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; + if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE; } - //RX + if (get_type == EYESCAN_TYPE_RX) { if (gRX_EYE_Scan_flag==DISABLE) return DISABLE; - if (gRX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE; //K All freq - if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; // K highest freq - if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE; // K unterm highest freq + if (gRX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE; + if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; + if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE; } - //TX + if (get_type == EYESCAN_TYPE_TX) { if (gTX_EYE_Scan_flag==DISABLE) return DISABLE; - if (gTX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE; //K All freq - if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; // K highest freq - if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE; // K unterm highest freq + if (gTX_EYE_Scan_only_higheset_freq_flag == DISABLE) return ENABLE; + if (p->frequency == u2DFSGetHighestFreq(p)) return ENABLE; + if (gEye_Scan_unterm_highest_flag==ENABLE && vGet_Current_SRAMIdx(p)==SRAM_SHU2) return ENABLE; } #endif @@ -721,14 +710,14 @@ U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type) void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff) { - // DRAMC Write-DBI On/Off + vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, onoff, SHU_TX_SET0_DBIWR); mcSHOW_DBG_MSG2(("DramC Write-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off"))); } void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff) { - // DRAMC Read-DBI On/Off + vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, onoff, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, onoff, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); mcSHOW_DBG_MSG2(("DramC Read-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off"))); @@ -741,7 +730,7 @@ void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff) #endif //mcSHOW_DBG_MSG(("--Fsp%d --\n", p->dram_fsp)); - //DRAM MR3[6] read-DBI On/Off + u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0xbf) | (onoff << 6)); DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]); } @@ -753,7 +742,7 @@ void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff) #if MRW_CHECK_ONLY mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); #endif - //DRAM MR3[7] write-DBI On/Off + u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0x7F) | (onoff << 7)); DramcModeRegWriteByRank(p, p->rank, 3, u1MR03Value[u1fsp]); } @@ -775,7 +764,7 @@ static void AutoRefreshCKEOff(DRAMC_CTX_T *p) mcDELAY_US(1); - //restore broadcast on/off + DramcBroadcastOnOff(u4backup_broadcast); } #endif @@ -796,17 +785,17 @@ void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, CHANNEL_RA { U8 u1CKEOn, u1CKEOff; - if (option == CKE_DYNAMIC) //if CKE is dynamic, set both CKE fix On and Off as 0 - { //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) + if (option == CKE_DYNAMIC) + { u1CKEOn = u1CKEOff = 0; } - else //if CKE fix on is set as 1, CKE fix off should also be set as 0; vice versa + else { u1CKEOn = option; u1CKEOff = (1 - option); } - if (WriteChannelNUM == TO_ALL_CHANNEL) //write register to all channel + if (WriteChannelNUM == TO_ALL_CHANNEL) { if((u1RankIdx == RANK_0)||(u1RankIdx == TO_ALL_RANK)) { @@ -841,31 +830,23 @@ void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option) { if (option == ENABLE) { - //enable autorefresh - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_REFDIS); //REFDIS=0, enable auto refresh + + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_REFDIS); } - else // DISABLE + else { - //disable autorefresh - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS); //REFDIS=1, disable auto refresh - //because HW will actually disable autorefresh after refresh_queue empty, so we need to wait quene empty. - mcDELAY_US(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_QUEUE_CNT) * 4); //wait refresh_queue_cnt * 3.9us + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 1, REFCTRL0_REFDIS); + + + mcDELAY_US(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_QUEUE_CNT) * 4); } } -//------------------------------------------------------------------------- -/** vCKERankCtrl - * Control CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT)) - * Note: Sets CKE toggle mode for all channels - * @param p Pointer of context created by DramcCtxCreate. - * @param CKECtrlMode Indicates - */ -//------------------------------------------------------------------------- void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode) { - /* Struct indicating all register fields mentioned in "multi rank CKE control" */ + typedef struct { U8 u1CKE2Rank: Fld_wid(RKCFG_CKE2RANK); @@ -884,7 +865,7 @@ void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode) U8 u1ClkWiTrfc: Fld_wid(ACTIMING_CTRL_CLKWITRFC); } CKE_CTRL_T; - /* CKE_Rank dependent/independent mode register setting values */ + CKE_CTRL_T CKE_Mode, CKE_Rank_Independent = { .u1CKE2Rank = 0, .u1CKE2Rank_Opt3 = 0, .u1CKE2Rank_Opt2 = 1, .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 1, .u1CKE2Rank_Opt8 = 0, .u1CKETimer_Sel = 0, .u1FASTWake = 1, .u1FASTWake2 = 1, .u1FastWake_Sel = 1, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0 @@ -893,10 +874,10 @@ void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode) .u1CKE2Rank_Opt5 = 0, .u1CKE2Rank_Opt6 = 0, .u1CKE2Rank_Opt7 = 0, .u1CKE2Rank_Opt8 = 0, .u1CKETimer_Sel = 1, .u1FASTWake = 1, .u1FASTWake2 = 0, .u1FastWake_Sel = 0, .u1CKEWake_Sel = 0, .u1ClkWiTrfc = 0 }; - //Select CKE control mode + CKE_Mode = (CKECtrlMode == CKE_RANK_INDEPENDENT)? CKE_Rank_Independent: CKE_Rank_Dependent; - //Apply CKE control mode register settings + vIO32WriteFldAlign_All(DRAMC_REG_RKCFG, CKE_Mode.u1CKE2Rank, RKCFG_CKE2RANK); vIO32WriteFldMulti_All(DRAMC_REG_CKECTRL, P_Fld(CKE_Mode.u1CKE2Rank_Opt3, CKECTRL_CKE2RANK_OPT3) | P_Fld(CKE_Mode.u1CKE2Rank_Opt, CKECTRL_CKE2RANK_OPT) @@ -915,7 +896,7 @@ void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode) } -#define MAX_CMP_CPT_WAIT_LOOP 100000 // max loop +#define MAX_CMP_CPT_WAIT_LOOP 100000 static void DramcSetRWOFOEN(DRAMC_CTX_T *p, U8 u1onoff) { U32 u4loop_count = 0; @@ -950,7 +931,7 @@ static void DramcSetRWOFOEN(DRAMC_CTX_T *p, U8 u1onoff) //} -static void DramcEngine2SetUiShift(DRAMC_CTX_T *p, U8 option)//UI shift function +static void DramcEngine2SetUiShift(DRAMC_CTX_T *p, U8 option) { if(option == ENABLE) { @@ -974,47 +955,34 @@ static void DramcEngine2SetUiShift(DRAMC_CTX_T *p, U8 option)//UI shift function void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel) { - //LPDDR2_3_ADRDECEN_TARKMODE =0, always rank0 - /* ADRDECEN_TARKMODE: rank input selection - * 1'b1 select CTO_AGENT1_RANK, 1'b0 rank by address decode - */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), 1, TEST2_A3_ADRDECEN_TARKMODE); - // DUMMY_TESTAGENTRKSEL =0, select rank according to CATRAIN_TESTAGENTRK - /* TESTAGENTRKSEL: Test agent access rank mode selection - * 2'b00: rank selection by TESTAGENTRK, 2'b01: rank selection by CTO_AGENT_1_BK_ADR[0] - * 2'b10: rank selection by CTO_AGENT1_COL_ADR[3], 2'b11: rank selection by CTO_AGENT1_COL_ADR[4] - */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAGENTRKSEL); - //CATRAIN_TESTAGENTRK = u1RankSel - /* TESTAGENTRK: Specify test agent rank - * 2'b00 rank 0, 2'b01 rank 1, 2'b10 rank 2 - */ + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), u1RankSel, TEST2_A4_TESTAGENTRK); } -void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift) //u1LoopCnt is related to rank +void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift) { - if ((u1TestPat == TEST_XTALK_PATTERN) || (u1TestPat == TEST_SSOXTALK_PATTERN)) //xtalk or SSO+XTALK + if ((u1TestPat == TEST_XTALK_PATTERN) || (u1TestPat == TEST_SSOXTALK_PATTERN)) { - //TEST_REQ_LEN1=1 is new feature, hope to make dq bus continously. - //but DV simulation will got problem of compare err - //so go back to use old way - //TEST_REQ_LEN1=0, R_DMRWOFOEN=1 + if (u1Len1Flag != 0) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), - P_Fld(1, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0, LEN1 of 256bits data - DramcSetRWOFOEN(p, 0); //@IPM will fix for LEN1=1 issue + P_Fld(1, TEST2_A4_TEST_REQ_LEN1)); + DramcSetRWOFOEN(p, 0); } else { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), - P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); DramcSetRWOFOEN(p, 1); } @@ -1023,40 +991,40 @@ void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Fla P_Fld(0, TEST2_A3_HFIDPAT) | P_Fld(0, TEST2_A3_TEST_AID_EN) | P_Fld(0, TEST2_A3_TESTAUDPAT) | - P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); //dont use audio pattern + P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); if (u1TestPat == TEST_SSOXTALK_PATTERN) { - //set addr 0x48[16] to 1, TESTXTALKPAT = 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), P_Fld(1, TEST2_A4_TESTXTALKPAT) | P_Fld(0, TEST2_A4_TESTAUDMODE) | - P_Fld(0, TEST2_A4_TESTAUDBITINV)); //use XTALK pattern, dont use audio pattern + P_Fld(0, TEST2_A4_TESTAUDBITINV)); + - //R_DMTESTSSOPAT=0, R_DMTESTSSOXTALKPAT=0 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), P_Fld(1, TEST2_A4_TESTSSOPAT) | - P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); //dont use sso, sso+xtalk pattern + P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); } - else //select XTALK pattern + else { - //set addr 0x48[16] to 1, TESTXTALKPAT = 1 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), P_Fld(1, TEST2_A4_TESTXTALKPAT) | P_Fld(0, TEST2_A4_TESTAUDMODE) | - P_Fld(0, TEST2_A4_TESTAUDBITINV)); //use XTALK pattern, dont use audio pattern + P_Fld(0, TEST2_A4_TESTAUDBITINV)); + - //R_DMTESTSSOPAT=0, R_DMTESTSSOXTALKPAT=0 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), P_Fld(0, TEST2_A4_TESTSSOPAT) | - P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); //dont use sso, sso+xtalk pattern + P_Fld(0, TEST2_A4_TESTSSOXTALKPAT)); } } - else if (u1TestPat == TEST_AUDIO_PATTERN) //AUDIO + else if (u1TestPat == TEST_AUDIO_PATTERN) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), - P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 - // set AUDINIT=0x11 AUDINC=0x0d AUDBITINV=1 AUDMODE=1(1:read only(address fix), 0: write/read address change) + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), P_Fld(0x00000011, TEST2_A4_TESTAUDINIT) | P_Fld(0x0000000d, TEST2_A4_TESTAUDINC) | @@ -1064,7 +1032,7 @@ void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Fla P_Fld(0, TEST2_A4_TESTAUDMODE) | P_Fld(1, TEST2_A4_TESTAUDBITINV)); - // set addr 0x044 [7] to 1 ,select audio pattern + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_AUTO_GEN_PAT) | P_Fld(0, TEST2_A3_HFIDPAT) | @@ -1072,7 +1040,7 @@ void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Fla P_Fld(1, TEST2_A3_TESTAUDPAT) | P_Fld(u1LoopCnt, TEST2_A3_TESTCNT)); } - else if (u1TestPat == TEST_WORST_SI_PATTERN) //TEST2_OFF > 'h56 + else if (u1TestPat == TEST_WORST_SI_PATTERN) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), P_Fld(u1Len1Flag, TEST2_A4_TEST_REQ_LEN1)| @@ -1088,12 +1056,12 @@ void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Fla P_Fld(1, TEST2_A3_TEST_AID_EN) | P_Fld(u1LoopCnt, TEST2_A3_TESTCNT) ); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x56, TEST2_A2_TEST2_OFF);//Set to min value to save time; + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x56, TEST2_A2_TEST2_OFF); } - else //ISI + else { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), - P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_AUTO_GEN_PAT) | @@ -1104,16 +1072,16 @@ void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Fla vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTXTALKPAT); } - DramcEngine2SetUiShift(p, u1EnableUiShift); //Enalbe/Disable UI shift + DramcEngine2SetUiShift(p, u1EnableUiShift); } -#define CMP_CPT_POLLING_PERIOD 1 // timeout for TE2: (CMP_CPT_POLLING_PERIOD X MAX_CMP_CPT_WAIT_LOOP) -#define MAX_CMP_CPT_WAIT_LOOP 100000 // max loop +#define CMP_CPT_POLLING_PERIOD 1 +#define MAX_CMP_CPT_WAIT_LOOP 100000 static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status) { U32 u4loop_count = 0; U32 u4Ta2_loop_count = 0; - U32 u4ShiftUiFlag = 0;//Use TEST_WORST_SI_PATTERN_UI_SHIFT + U32 u4ShiftUiFlag = 0; while ((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status) { @@ -1125,7 +1093,7 @@ static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status) } else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP) { - /*TINFO="fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count*/ + mcSHOW_ERR_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT))); //mcFPRINTF((fp_A60501, "fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count)); @@ -1136,7 +1104,7 @@ static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status) u4loop_count = 0; u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT); - if(u4ShiftUiFlag)//Use TEST_WORST_SI_PATTERN_UI_SHIFT + if(u4ShiftUiFlag) { while ((u4Ta2_loop_count = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT))) != 8) { @@ -1154,23 +1122,23 @@ static U32 DramcEngine2Compare(DRAMC_CTX_T *p, DRAM_TE_OP_T wr) { U32 u4result = 0xffffffff; U32 u4loopcount; - U8 u1status = 1; //RK0 + U8 u1status = 1; U32 u4ShiftUiFlag = 0; u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT); if (u4loopcount == 1) - u1status = 3; //RK0/1 + u1status = 3; u4ShiftUiFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TEST2_PAT_SHIFT); if (wr == TE_OP_WRITE_READ_CHECK) { - if(!u4ShiftUiFlag)//Could not use while UI shift is open + if(!u4ShiftUiFlag) { - // read data compare ready check + DramcEngine2CheckComplete(p, u1status); - // disable write + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | @@ -1178,7 +1146,7 @@ static U32 DramcEngine2Compare(DRAMC_CTX_T *p, DRAM_TE_OP_T wr) mcDELAY_US(1); - // enable read + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(1, TEST2_A3_TEST2R) | @@ -1186,49 +1154,31 @@ static U32 DramcEngine2Compare(DRAMC_CTX_T *p, DRAM_TE_OP_T wr) } } - // 5 - // read data compare ready check + DramcEngine2CheckComplete(p, u1status); - // delay 10ns after ready check from DE suggestion (1ms here) //mcDELAY_US(1); - u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & u1status; //CMP_ERR_RK0/1 + u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & u1status; return u4result; } -//------------------------------------------------------------------------- -/** DramcEngine2 - * start the self test engine 2 inside dramc to test dram w/r. - * @param p Pointer of context created by DramcCtxCreate. - * @param wr (DRAM_TE_OP_T): TE operation - * @param test2_1 (U32): 28bits,base address[27:0]. - * @param test2_2 (U32): 28bits,offset address[27:0]. (unit is 16-byte, i.e: 0x100 is 0x1000). - * @param loopforever (S16): 0 read\write one time ,then exit - * >0 enable eingie2, after "loopforever" second ,write log and exit - * -1 loop forever to read\write, every "period" seconds ,check result ,only when we find error,write log and exit - * -2 loop forever to read\write, every "period" seconds ,write log ,only when we find error,write log and exit - * -3 just enable loop forever ,then exit - * @param period (U8): it is valid only when loopforever <0; period should greater than 0 - * @param u1LoopCnt (U8): test loop number of test agent2 loop number =2^(u1LoopCnt) ,0 one time - * @retval status (U32): return the value of DM_CMP_ERR ,0 is ok ,others mean error - */ -//------------------------------------------------------------------------- + static U32 uiReg0D0h; DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift) { U8 u1Len1Flag; - // error handling + if (!p) { mcSHOW_ERR_MSG(("context is NULL\n")); return DRAM_FAIL; } - // check loop number validness -// if ((u1LoopCnt > 15) || (u1LoopCnt < 0)) // U8 >=0 always. + +// if ((u1LoopCnt > 15) || (u1LoopCnt < 0)) if (u1LoopCnt > 15) { mcSHOW_ERR_MSG(("wrong param: u1LoopCnt > 15\n")); @@ -1247,31 +1197,21 @@ DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1Te P_Fld(0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0, DUMMY_RD_DMY_RD_DBG) | - P_Fld(0, DUMMY_RD_DMY_WR_DBG)); //must close dummy read when do test agent + P_Fld(0, DUMMY_RD_DMY_WR_DBG)); - //fixme-zj vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT); - // disable self test engine1 and self test engine2 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1)); - // 1.set pattern ,base address ,offset address - // 2.select ISI pattern or audio pattern or xtalk pattern - // 3.set loop number - // 4.enable read or write - // 5.loop to check DM_CMP_CPT - // 6.return CMP_ERR - // currently only implement ucengine_status = 1, others are left for future extension - // 1 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), P_Fld(test2_1 >> 24, TEST2_A0_TEST2_PAT0) | P_Fld(test2_2 >> 24, TEST2_A0_TEST2_PAT1)); { - // LP4 TA2 base: 0x10000. It's only TBA constrain, but not HW. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), (test2_1 + 0x10000) & 0x00ffffff, RK_TEST2_A1_TEST2_BASE); } @@ -1279,8 +1219,7 @@ DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1Te vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), test2_2 & 0x00ffffff, TEST2_A2_TEST2_OFF); - // 2 & 3 - // (TESTXTALKPAT, TESTAUDPAT) = 00 (ISI), 01 (AUD), 10 (XTALK), 11 (UNKNOWN) + DramcEngine2SetPat(p, u1TestPat, u1LoopCnt, u1Len1Flag, u1EnableUiShift); return DRAM_OK; @@ -1291,16 +1230,16 @@ U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat) { U32 u4result = 0xffffffff; - // 4 + if (wr == TE_OP_READ_CHECK) { if ((u1TestPat == 1) || (u1TestPat == 2)) { - //if audio pattern, enable read only (disable write after read), AUDMODE=0x48[15]=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), 0, TEST2_A4_TESTAUDMODE); } - // enable read, 0x008[31:29] + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(1, TEST2_A3_TEST2R) | @@ -1308,7 +1247,7 @@ U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat) } else if (wr == TE_OP_WRITE_READ_CHECK) { - // enable write + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(1, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | @@ -1316,16 +1255,13 @@ U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat) } DramcEngine2Compare(p, wr); - // delay 10ns after ready check from DE suggestion (1ms here) + mcDELAY_US(1); - // 6 - // return CMP_ERR, 0 is ok ,others are fail,diable test2w or test2r - // get result - // or all result + u4result = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))); - // disable read + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | @@ -1337,13 +1273,12 @@ U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 u1TestPat) void DramcEngine2End(DRAMC_CTX_T *p) { vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), - P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); //test agent 2 with cmd length = 0 + P_Fld(0, TEST2_A4_TEST_REQ_LEN1)); DramcSetRWOFOEN(p, 1); vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), uiReg0D0h); } #if 0 -// Full set of usage test engine 2, including of DramcEngine2Init->DramcEngine2Run->DramcEngine2End -// if you don't care the performance, and just for convinent, you may use this API (TestEngineCompare) + static U32 TestEngineCompare(DRAMC_CTX_T *p) { U8 jj; @@ -1378,13 +1313,12 @@ static U32 TestEngineCompare(DRAMC_CTX_T *p) #if (fcFOR_CHIP_ID == fcA60868) #define EMI_APB_BASE 0x10219000 #elif (fcFOR_CHIP_ID == fc8195) - #define EMI_APB_BASE 0x10219000///TODO:Darren confirm + #define EMI_APB_BASE 0x10219000 //#define SUB_EMI_APB_BASE 0x1021D000 - // 0x10219000 for CH0/1 - // 0x1021D000 for CH2/3 + #endif -U8 u1MaType = 0x2; // for DV sim +U8 u1MaType = 0x2; void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p) { U8 u1ChannelIdx = 0; @@ -1404,15 +1338,15 @@ void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p) if (channel_num_auxadc > 2) { if (u1ChannelIdx >= CHANNEL_C) { - u4EmiOffset = 0x4000; // 0x1021D000 for CH2/3 + u4EmiOffset = 0x4000; u1EmiChIdx = u1ChannelIdx-2; } } #endif u4matype = u4IO32Read4B(EMI_APB_BASE + u4EmiOffset); - u4matypeR0 = ((u4matype >> (4 + u1EmiChIdx * 16)) & 0x3) + 1; //refer to init_ta2_single_channel() - u4matypeR1 = ((u4matype >> (6 + u1EmiChIdx * 16)) & 0x3) + 1; //refer to init_ta2_single_channel() + u4matypeR0 = ((u4matype >> (4 + u1EmiChIdx * 16)) & 0x3) + 1; + u4matypeR1 = ((u4matype >> (6 + u1EmiChIdx * 16)) & 0x3) + 1; if(p->support_rank_num==RANK_SINGLE) { @@ -1420,7 +1354,7 @@ void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p) } else { - u4matype = (u4matypeR0 > u4matypeR1) ? u4matypeR1 : u4matypeR0; //get min value + u4matype = (u4matypeR0 > u4matypeR1) ? u4matypeR1 : u4matypeR0; } //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MATYPE), u4matype, MATYPE_MATYPE); } @@ -1430,30 +1364,17 @@ void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p) return; } -/* ---------------------------------------------------------------------- - * LP4 RG Address - * bit: 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * --------------------------------------------------------------- - * RG: - - R R R R R R R R R R R R R R R R R R|B B B|C C C C C C - - - - * 2_BASE 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0|A A A|9 8 7 6 5 4 - * 7 6 5 4 3 2 1 0 |2 1 0| - * AXI --------------------------------------------------------------- - * Addr: R R R R R R R R R R R R R R R R|B B B|C C C|C|C C C C C C C - - * 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0|A A A|9 8 7|H|6 5 4 3 2 1 0 - * 5 4 3 2 1 0 |2 1 0| | | - * ---------------------------------------------------------------------- - */ + #define TA2_RANK0_ADDRESS (0x40200000) -#define AXI_CHAN_BIT_WIDTH 1 //2: 4_channel 1: 2_channel +#define AXI_CHAN_BIT_WIDTH 1 #define OFFSET_OF_RG_BASE_AND_AXI 2 #define LEN1_INTRINSIC_OFFSET 2 #if FOR_DV_SIMULATION_USED -#define TRANSFER_DRAM_ADDR_BY_EMI_API 0 // @ tg add to fix simulation compile error +#define TRANSFER_DRAM_ADDR_BY_EMI_API 0 #else -#define TRANSFER_DRAM_ADDR_BY_EMI_API 1 //1: by emi API 0: by above table +#define TRANSFER_DRAM_ADDR_BY_EMI_API 1 #endif -void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode)/* Should call after TA2_Test_Run_Time_Pat_Setting() */ +void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode) { DRAM_CHANNEL_T eOriChannel = p->channel; DRAM_RANK_T eOriRank = p->rank; @@ -1470,40 +1391,40 @@ void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T unsigned long long ull_axi_addr = TA2_RANK0_ADDRESS; memset(&dram_addr, 0, sizeof(dram_addr)); - phy_addr_to_dram_addr(&dram_addr, ull_axi_addr); //Make sure row. bank. column are correct - u4BaseR0 = ((dram_addr.row << 12) | (dram_addr.bk << 9) | (dram_addr.col >> 1)) >> 3;// >>1: RG C4 @3th bit >>3: RG start with bit 3 + phy_addr_to_dram_addr(&dram_addr, ull_axi_addr); + u4BaseR0 = ((dram_addr.row << 12) | (dram_addr.bk << 9) | (dram_addr.col >> 1)) >> 3; } #else - // >>AXI_CHAN_BIT_WIDTH: drop bit8; >>OFFSET_OF_RG_BASE_AND_AXI: align with RG row; >>3: RG start with bit 3 + u4BaseR0 = (((u4Addr & ~0x1ff) >> AXI_CHAN_BIT_WIDTH) | (u4Addr & 0xff)) >> (OFFSET_OF_RG_BASE_AND_AXI + 3); #endif //mcSHOW_DBG_MSG(("===u4BaseR0 = 0x%x\n", u4BaseR0)); - u4Offset = len >> (AXI_CHAN_BIT_WIDTH + 5);//5:0x20 bytes(256 bits) address coverage per pattern(128 bits data + 128 bits bubble); offset should bigger than 0xFF + u4Offset = len >> (AXI_CHAN_BIT_WIDTH + 5); } else { u4BaseR0 = u4Addr >> 4; if (rksel_mode == TA2_RKSEL_XRT) { - u4Offset = len >> 4;//16B per pattern + u4Offset = len >> 4; } else { - u4Offset = (len >> 4) >> 1;//16B per pattern //len should be >>2 or test engine will time out + u4Offset = (len >> 4) >> 1; } } u4BaseR1 = u4BaseR0; u4matypeR0 = ((u4IO32Read4B(EMI_APB_BASE) >> 4) & 0x3) + 1; u4matypeR1 = ((u4IO32Read4B(EMI_APB_BASE) >> 6) & 0x3) + 1; - if (u4matypeR0 != u4matypeR1)//R0 R1 mix mode + if (u4matypeR0 != u4matypeR1) { - (u4matypeR0 > u4matypeR1)? (u4BaseR0 >>= 1): (u4BaseR1 >>= 1);//set the correct start address, refer to mapping table - u4Offset >>= 1;//set min value + (u4matypeR0 > u4matypeR1)? (u4BaseR0 >>= 1): (u4BaseR1 >>= 1); + u4Offset >>= 1; } - u4Offset = (u4Offset == 0) ? 1 : u4Offset; //halt if u4Offset = 0 + u4Offset = (u4Offset == 0) ? 1 : u4Offset; u4LEN1 = u4IO32ReadFldAlign(DRAMC_REG_TEST2_A4, TEST2_A4_TEST_REQ_LEN1); if(u4LEN1) @@ -1517,13 +1438,13 @@ void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T u4matypeR0 = 2; u4matypeR1 = 2; u4Offset = 3; - //u4Offset = 6;//3; //6: for emilpbk_dq_dvs_leadlag_toggle_ringcnt + //u4Offset = 6; } #endif if (TA2_RKSEL_XRT == rksel_mode) { - // In order to enhance XRT R2R/W2W probability, use TEST2_4_TESTAGENTRKSEL=3, PERFCTL0_RWOFOEN=0 mode + uiRWOFOEN = 0; mcSHOW_DBG_MSG2(("=== TA2 XRT R2R/W2W\n")); } @@ -1544,9 +1465,9 @@ void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T for(u1RkIdx = 0; u1RkIdx < p->support_rank_num; u1RkIdx++) { p->rank = (DRAM_RANK_T)u1RkIdx; - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), u4BaseR0, RK_TEST2_A1_TEST2_BASE);//fill based on RG table for Rank 0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), u4BaseR0, RK_TEST2_A1_TEST2_BASE); } - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), u4Offset, TEST2_A2_TEST2_OFF);//128 bits data length per offest + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), u4Offset, TEST2_A2_TEST2_OFF); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), rksel_mode, TEST2_A4_TESTAGENTRKSEL); DramcSetRWOFOEN(p, uiRWOFOEN); } @@ -1581,7 +1502,7 @@ void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch) #if !ETT_MINI_STRESS_USE_TA2_LOOP_MODE { U32 u4Value = 0; - u4Value = (u1Pat == TEST_WORST_SI_PATTERN) ? 1 : 0; //Worst SI pattern + loop mode + LEN1 + u4Value = (u1Pat == TEST_WORST_SI_PATTERN) ? 1 : 0; vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_TA2_LOOP_EN); vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_LOOP_NV_END); vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A0, u4Value, TEST2_A0_ERR_BREAK_EN); @@ -1658,7 +1579,7 @@ static void TA2_Show_Cnt(DRAMC_CTX_T * p, U32 u4ErrorValue) static void TA2_Test_Run_Time_Stop_Loop_Mode(DRAMC_CTX_T * p) { U8 u1ChannelIdx = 0; - U8 u1status = (p->support_rank_num == 2) ? 3 : 1; //3: 2 ranks; 1: 1 rank + U8 u1status = (p->support_rank_num == 2) ? 3 : 1; U32 u4loop_count = 0; DRAM_CHANNEL_T eOriChannel = p->channel; @@ -1666,10 +1587,10 @@ static void TA2_Test_Run_Time_Stop_Loop_Mode(DRAMC_CTX_T * p) { vSetPHY2ChannelMapping(p, u1ChannelIdx); - //Step 1: set LOOP_NV_END=0 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END); - //Step 2: check TA2 status + while (((u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) & u1status) != u1status) || (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT))) { mcDELAY_US(CMP_CPT_POLLING_PERIOD); @@ -1685,7 +1606,7 @@ static void TA2_Test_Run_Time_Stop_Loop_Mode(DRAMC_CTX_T * p) } } - //Step 3: set TEST2W/TEST2R=0 and RG_TA2_LOOP_EN=0 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1)); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_TA2_LOOP_EN); } @@ -1713,12 +1634,12 @@ static U32 TA2_Test_Run_Time_Err_Status(DRAMC_CTX_T *p) for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++) { vSetPHY2ChannelMapping(p, u1ChannelIdx); - u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //CMP_ERR_RK0/1 + u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //mcSHOW_DBG_MSG(("CMP_ERR_RK0/1:0x%x ", u4ErrorValue)); TA2_Show_Cnt(p, u4ErrorValue); u4AllErrorValue |= u4ErrorValue; - u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT)); //loop counter + u4Value = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TEST_LOOP_CNT)); mcSHOW_DBG_MSG2(("CH[%d] LOOP_CNT:0x%x \n", u1ChannelIdx, u4Value)); } vSetPHY2ChannelMapping(p, bkchannel); @@ -1737,7 +1658,7 @@ U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p) vSetPHY2ChannelMapping(p, u1ChannelIdx); u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK); - if (u4ErrorValue & 0x3) //RK0 or RK1 test fail + if (u4ErrorValue & 0x3) { mcSHOW_DBG_MSG2(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)))); #if defined(SLT) @@ -1777,17 +1698,17 @@ U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p) { u4loopcount = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), TEST2_A3_TESTCNT); if (u4loopcount == 1) - u1status = 3; //RK0/1 + u1status = 3; - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);//cancel NV_END - DramcEngine2CheckComplete(p, u1status);//Wait for complete - //mcSHOW_DBG_MSG(("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));//check TESTRPT_TESTSTAT - u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //CMP_ERR_RK0/1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END); + DramcEngine2CheckComplete(p, u1status); + //mcSHOW_DBG_MSG(("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT))); + u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; } else u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK); - if (u4ErrorValue & 0x3) //RK0 or RK1 test fail + if (u4ErrorValue & 0x3) { mcSHOW_DBG_MSG2(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)))); #if defined(SLT) @@ -1816,7 +1737,7 @@ void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p) DRAM_CHANNEL_T channel_bak = p->channel; DRAM_RANK_T rank_bak = p->rank; - TA2_Test_Run_Time_HW_Presetting(p, 0x10000, TA2_RKSEL_HW); //TEST2_2_TEST2_OFF = 0x400 + TA2_Test_Run_Time_HW_Presetting(p, 0x10000, TA2_RKSEL_HW); TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_OFF); TA2_Test_Run_Time_HW_Write(p, ENABLE); //mcDELAY_MS(1); @@ -1835,7 +1756,7 @@ void Temp_TA2_Test_After_K(DRAMC_CTX_T * p) do { TA2_Test_Run_Time_Pat_Setting(p, TA2_PAT_SWITCH_ON); TA2_Test_Run_Time_HW_Presetting(p, 0x200000, TA2_RKSEL_HW); - TA2_Test_Run_Time_HW_Write(p, ENABLE);//TA2 trigger W + TA2_Test_Run_Time_HW_Write(p, ENABLE); TA2_Test_Run_Time_HW_Status(p); }while(1); @@ -1890,7 +1811,7 @@ U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank) } } - if (u1Fsp == FSP_0) /* All MR */ + if (u1Fsp == FSP_0) { switch (u1MRIdx) { @@ -2048,7 +1969,7 @@ U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank) break; } } - else if (u1MRIdx == 21 || u1MRIdx == 22) /* MR only in FSP0/FSP1 */ + else if (u1MRIdx == 21 || u1MRIdx == 22) { if (u1MRIdx == 21) { @@ -2061,7 +1982,7 @@ U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank) TransferReg.u4Fld = MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22; } } - else /* MR in FSP0/FSP1/FSP2 */ + else { if (u1MRIdx <= 20) { @@ -2155,28 +2076,27 @@ void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u2pValue) //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), p->rank, SWCMD_CTRL0_MRRRK); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA); - // MRR command will be fired when MRREN 0->1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN); - // wait MRR command fired. + while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) == 0) { mcDELAY_US(1); } - // Since LP3 does not support CG condition, LP3 can not use MRR_STATUS_MRR_SW_REG to do sw mrr. - // After fix HW CG condition, LP3 will use MRR_STATUS_MRR_SW_REG to do sw mrr. + U32 u4MRRReg; if (u1IsLP4Family(p->dram_type)) u4MRRReg = MRR_STATUS_MRR_SW_REG; else u4MRRReg = MRR_STATUS_MRR_REG; - // Read out mode register value + u4MRValue = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), u4MRRReg); *u2pValue = (U16)u4MRValue; - // Set MRREN =0 for next time MRR. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN); #ifdef DUMP_INIT_RG_LOG_TO_DE @@ -2192,21 +2112,15 @@ void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue U16 u2Value = 0; U8 u1RankBak; - /* Since, TMRRI design changed (2 kinds of modes depending on value of R_DMRK_SCINPUT_OPT) - * DE: Jouling, Berson - * To specify SW_MRR rank -> new mode(scinput_opt == 0): MRSRK - * old mode(scinput_opt == 1): MRRRK - * Note: MPCRK is not used by SW to control rank anymore - */ - //Backup & set rank - u1RankBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); //backup rank - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); //set rank - - //Mode reg read + + u1RankBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); + + DramcModeRegRead(p, u1MRIdx, &u2Value); *u2pValue = u2Value; - //Restore rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1RankBak, SWCMD_CTRL0_MRSRK); } @@ -2266,7 +2180,7 @@ void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 * mcDELAY_US(5); } while ((u4Response == 0) && (u4TimeCnt > 0)); - if (u4TimeCnt == 0)//time out + if (u4TimeCnt == 0) { mcSHOW_ERR_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0])); } @@ -2281,25 +2195,25 @@ static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U32 u4RabnkBackup; U32 u4register_024; - // backup rank + u4RabnkBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK); - //backup register of CKE fix on/off + u4register_024 = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); - // set rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Rank, SWCMD_CTRL0_MRSRK); - //CKE must be fix on when doing MRW + CKEFixOnOff(p, u1Rank, CKE_FIXON, TO_ONE_CHANNEL); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1MRIdx, SWCMD_CTRL0_MRSMA); vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1Value, SWCMD_CTRL0_MRSOP); - // MRW command will be fired when MRWEN 0->1 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRWEN); - // wait MRW command fired. + while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) == 0) { counter++; @@ -2307,13 +2221,13 @@ static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, mcDELAY_US(1); } - // Set MRWEN =0 for next time MRW. + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRWEN); - // restore CKEFIXON value + vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4register_024); - // restore rank + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4RabnkBackup, SWCMD_CTRL0_MRSRK); } @@ -2322,7 +2236,7 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value) mcSHOW_DBG_MSG2(("MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value)); #if (fcFOR_CHIP_ID == fcA60868) - // RTMRW & RTSWCMD-MRW can not be used in runtime + if (u1EnterRuntime) { @@ -2466,20 +2380,20 @@ void DramcConfInfraReset(DRAMC_CTX_T *p) vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL) | P_Fld(1, MISC_CG_CTRL0_W_CHG_MEM)); - mcDELAY_XNS(100);//reserve 100ns period for clock mute and latch the rising edge sync condition for BCLK + mcDELAY_XNS(100); vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), 0, MISC_CG_CTRL0_W_CHG_MEM); #if (fcFOR_CHIP_ID == fcLafite) - // 26M - vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX) //move CKMUX_SEL_R_PHYCTRLMUX to here (it was originally between MISC_CG_CTRL0_CLK_MEM_SEL and MISC_CTRL0_R_DMRDSEL_DIV2_OPT) - | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); // PHYCTRLDCM 1: follow DDRPHY_conf DCM settings, 0: follow infra DCM settings + + vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX) + | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM)); vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL0, P_Fld(0, MISC_CG_CTRL0_W_CHG_MEM) - | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL));//[5:4] mem_ck mux: 2'b00: 26MHz, [0]: change memory clock - vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);//change clock freq + | P_Fld(0, MISC_CG_CTRL0_CLK_MEM_SEL)); + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM); mcDELAY_US(1); - vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM); + - // dramc conf reset //mcSHOW_TIME_MSG(("Before infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148))); *(volatile unsigned *)(0x10001140) = (0x1 << 15); //mcSHOW_TIME_MSG(("After infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148))); @@ -2497,14 +2411,14 @@ void DramcConfInfraReset(DRAMC_CTX_T *p) mcDELAY_US(200); #endif - //DDRPHY Reset + vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_ARDQ_RESETB_B0); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); vIO32WriteFldAlign_All(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_ARDQ_RESETB_B1); vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x0, CA_CMD3_RG_ARCMD_RESETB); vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); - vIO32WriteFldAlign(DDRPHY_PLL4, 0x0, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA + vIO32WriteFldAlign(DDRPHY_PLL4, 0x0, PLL4_RG_RPHYPLL_RESETB); mcDELAY_US(200); vIO32WriteFldAlign_All(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0); vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); @@ -2512,12 +2426,12 @@ void DramcConfInfraReset(DRAMC_CTX_T *p) vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); vIO32WriteFldAlign_All(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_ARCMD_RESETB); vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); - vIO32WriteFldAlign(DDRPHY_PLL4, 0x1, PLL4_RG_RPHYPLL_RESETB);//Since there is only 1 PLL, only control CHA + vIO32WriteFldAlign(DDRPHY_PLL4, 0x1, PLL4_RG_RPHYPLL_RESETB); + - //Disable SPM control vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(0, POWERON_CONFIG_EN_BCLK_CG_EN)); - //For FMeter after dcm enable + vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN); vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL2, 0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON); #endif @@ -2541,7 +2455,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) size = len >> 2; - /* === Verify the tied bits (tied high) === */ + for (i = 0; i < size; i++) { MEM32_BASE[i] = 0; @@ -2559,7 +2473,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Verify the tied bits (tied low) === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xffffffff) @@ -2570,7 +2484,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) MEM32_BASE[i] = 0x00; } - /* === Verify pattern 1 (0x00~0xff) === */ + pattern8 = 0x00; for (i = 0; i < len; i++) MEM8_BASE[i] = pattern8++; @@ -2583,7 +2497,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Verify pattern 2 (0x00~0xff) === */ + pattern8 = 0x00; for (i = j = 0; i < len; i += 2, j++) { @@ -2596,7 +2510,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) pattern8 += 2; } - /* === Verify pattern 3 (0x00~0xffff) === */ + pattern16 = 0x00; for (i = 0; i < (len >> 1); i++) MEM16_BASE[i] = pattern16++; @@ -2609,7 +2523,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Verify pattern 4 (0x00~0xffffffff) === */ + pattern32 = 0x00; for (i = 0; i < (len >> 2); i++) MEM32_BASE[i] = pattern32++; @@ -2622,11 +2536,11 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Pattern 5: Filling memory range with 0x44332211 === */ + for (i = 0; i < size; i++) MEM32_BASE[i] = 0x44332211; - /* === Read Check then Fill Memory with a5a5a5a5 Pattern === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0x44332211) @@ -2639,7 +2553,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Read Check then Fill Memory with 00 Byte Pattern at offset 0h === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xa5a5a5a5) @@ -2652,7 +2566,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Read Check then Fill Memory with 00 Byte Pattern at offset 2h === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xa5a5a500) @@ -2665,7 +2579,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Read Check then Fill Memory with 00 Byte Pattern at offset 1h === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xa500a500) @@ -2678,7 +2592,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Read Check then Fill Memory with 00 Byte Pattern at offset 3h === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xa5000000) @@ -2691,7 +2605,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Read Check then Fill Memory with ffff Word Pattern at offset 1h == */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0x00000000) @@ -2704,7 +2618,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /* === Read Check then Fill Memory with ffff Word Pattern at offset 0h == */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xffff0000) @@ -2717,7 +2631,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /*=== Read Check === */ + for (i = 0; i < size; i++) { if (MEM32_BASE[i] != 0xffffffff) @@ -2726,17 +2640,14 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } } - /************************************************ - * Additional verification - ************************************************/ - /* === stage 1 => write 0 === */ + for (i = 0; i < size; i++) { MEM_BASE[i] = PATTERN1; } - /* === stage 2 => read 0, write 0xF === */ + for (i = 0; i < size; i++) { value = MEM_BASE[i]; @@ -2748,7 +2659,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) MEM_BASE[i] = PATTERN2; } - /* === stage 3 => read 0xF, write 0 === */ + for (i = 0; i < size; i++) { value = MEM_BASE[i]; @@ -2760,7 +2671,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } - /* === stage 4 => read 0, write 0xF === */ + for (i = 0; i < size; i++) { value = MEM_BASE[i]; @@ -2771,7 +2682,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) MEM_BASE[i] = PATTERN2; } - /* === stage 5 => read 0xF, write 0 === */ + for (i = 0; i < size; i++) { value = MEM_BASE[i]; @@ -2782,7 +2693,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) MEM_BASE[i] = PATTERN1; } - /* === stage 6 => read 0 === */ + for (i = 0; i < size; i++) { value = MEM_BASE[i]; @@ -2793,7 +2704,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } #if 1 - /* === 1/2/4-byte combination test === */ + i = (unsigned int) MEM_BASE; while (i < (unsigned int) MEM_BASE + (size << 2)) @@ -2841,7 +2752,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) } #endif - /* === Verify pattern 1 (0x00~0xff) === */ + pattern8 = 0x00; MEM8_BASE[0] = pattern8; for (i = 0; i < size * 4; i++) @@ -2858,7 +2769,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) pattern8++; } - /* === Verify pattern 2 (0x00~0xffff) === */ + pattern16 = 0x00; MEM16_BASE[0] = pattern16; for (i = 0; i < size * 2; i++) @@ -2872,7 +2783,7 @@ int dramc_complex_mem_test (unsigned int start, unsigned int len) pattern16++; } - /* === Verify pattern 3 (0x00~0xffffffff) === */ + pattern32 = 0x00; MEM32_BASE[0] = pattern32; for (i = 0; i < size; i++) @@ -2916,7 +2827,7 @@ U32 TimeProfileDiffUS(PROFILING_TIME_T *base) u4Acc = 0; TimeProfileGetTick(&end); - /* temporary patch for overflow */ + u4Diff = end.u4TickLow - base->u4TickLow; if (end.u4TickLow > base->u4TickLow) { @@ -2965,29 +2876,21 @@ void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0, DUMMY_RD_DQSG_DMYWR_EN) | P_Fld(0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0, DUMMY_RD_SREF_DMYRD_EN) | P_Fld(0, DUMMY_RD_DMY_RD_DBG) | P_Fld(0, DUMMY_RD_DMY_WR_DBG)); //must close dummy read when do test agent //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTCHIP_DMA1), 0, TESTCHIP_DMA1_DMA_LP4MATAB_OPT);//Eddie - // disable self test engine1 and self test engine2 + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3), P_Fld(0, TEST2_A3_TEST2W) | P_Fld(0, TEST2_A3_TEST2R) | P_Fld(0, TEST2_A3_TEST1)); - // 1.set pattern ,base address ,offset address - // 2.select ISI pattern or audio pattern or xtalk pattern - // 3.set loop number - // 4.enable read or write - // 5.loop to check DM_CMP_CPT - // 6.return CMP_ERR - // currently only implement ucengine_status = 1, others are left for future extension - // 1 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), P_Fld(test2_1>>24,TEST2_A0_TEST2_PAT0)|P_Fld(test2_2>>24,TEST2_A0_TEST2_PAT1)); #if (FOR_DV_SIMULATION_USED==1 || SW_CHANGE_FOR_SIMULATION==1) - //DV sim memory 0~0x100 has values, can't used + //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A1), (test2_1+0x100) & 0x00ffffff, TEST2_A1_TEST2_BASE); - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x10000, RK_TEST2_A1_TEST2_BASE); //LPDDR4 Setting - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x0, RK_TEST2_A1_TEST2_BASE); //Eddie Change to 0 for LP5 + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x10000, RK_TEST2_A1_TEST2_BASE); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0x0, RK_TEST2_A1_TEST2_BASE); #else vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1), 0, RK_TEST2_A1_TEST2_BASE); #endif - vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x2, TEST2_A2_TEST2_OFF);//Eddie + vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2), 0x2, TEST2_A2_TEST2_OFF); return; } diff --git a/src/vendorcode/mediatek/mt8195/dramc/emi.c b/src/vendorcode/mediatek/mt8195/dramc/emi.c index 6649e82b97..5a1f09de50 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/emi.c +++ b/src/vendorcode/mediatek/mt8195/dramc/emi.c @@ -39,12 +39,12 @@ static inline unsigned int mt_emi_sync_read(unsigned long long addr) static void emi_cen_config(void) { #ifndef ONE_CH - #ifdef RANK_512MB // => 2channel , dual rank , total=2G + #ifdef RANK_512MB mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154); #else - #ifdef RANK_1GB //RANK_1G => 2channel , dual rank , total=4G + #ifdef RANK_1GB mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154); - #else // RANK_2G => 2channel , dual rank , total=8G + #else #ifdef RANK_2GB mt_emi_sync_write(EMI_APB_BASE+0x00000000,0x00530154); #endif @@ -58,58 +58,58 @@ static void emi_cen_config(void) { #endif #endif - // overhead: 20190821 item1 - synced - mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4 - r1 overhead // TBD - change to 4266 - mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8 - r5 overhead // TBD - change to 4266 - mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9 overhead // TBD - change to 4266 - mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead // TBD - change to 4266 - mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8 - r5 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8 - r5 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8 - r5 overhead - mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8 - r5 overhead - mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8 - r5 overhead - mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800 (1:4) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800 (1:4) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800 (1:4) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800 (1:4) r8 - r5 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800 (1:4) r12 - r9 overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800 (1:4) r4 - r1 overhead - mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800 (1:4) r16 - r13 overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800 (1:4) r8 - r5 overhead - - mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead // TBD - change to 4266 - mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead // TBD - change to 4266 - mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800 (1:4) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800 (1:4) r16 - r10 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800 (1:4) r8 - r2 non-align overhead - mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800 (1:4) r16 - r10 non-align overhead - - // + + mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); + mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); + mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); + mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); + mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); + mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); + mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); + mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); + mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); + mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); + mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); + mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); + mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); + mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); + mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); + mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); + mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); + mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); + mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); + mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); + mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); + mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); + mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); + mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); + mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); + mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); + mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); + mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); + mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); + mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); + mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); + mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); + + mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); + mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); + mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); + mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); + mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); + mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); + mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); + mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); + mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); + mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); + mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); + mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); + mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); + mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); + mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); + mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); + + mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a); mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042); mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000); @@ -121,17 +121,17 @@ static void emi_cen_config(void) { mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210); mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802); mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000); - mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7 + mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000); - mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1 - mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1 + mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); + mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123); mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123); mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8); mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525); mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8); mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525); - mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1 + mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014); mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000); mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244); @@ -146,38 +146,38 @@ static void emi_cen_config(void) { mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108); mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a0000); mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00); - mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor + mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008); mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101); mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424); mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101); mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050); - mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT, + mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003); mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff); - mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update + mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8); mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b); mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290); mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200); mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000); mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000); - mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold - mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); //disable internal MD latency urgent mask + mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); + mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5); - mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d); mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59); mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff); mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff); mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b); - mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185); - mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185); - mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update + mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff); @@ -209,7 +209,7 @@ static void emi_cen_config(void) { mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64); mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101); mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101); - mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025); //ignore wff threshold + mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025); mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8); mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b); mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290); @@ -223,47 +223,47 @@ static void emi_cen_config(void) { mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101); mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101); - mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0 - mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1 - mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0 - mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1 - mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1 - mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0 - mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1 - mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet - mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0 - mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1 - mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh - mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR - mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select - mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB - mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control + mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); + mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); + mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); + mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); + mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); + mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); + mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); + mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); + mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); + mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); + mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); + mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); + mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); + mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); + mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); + mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); + mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); + mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); + mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); + mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); + mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166); mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff); @@ -277,51 +277,50 @@ static void emi_cen_config(void) { mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff); - // Added by Wei-Lun - START - // prtcl chker - golden setting - mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc - mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl - mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk + + mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); + mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); + mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85); - mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk + mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); + + + mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); - //weilun for new feature - mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_emi rw switching shf - // cen_emi timeout value mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060); mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060); - // fine-grained qos + mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000); - // ostd->bw + mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff); mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c); mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff); @@ -330,16 +329,16 @@ static void emi_cen_config(void) { mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff); mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000); - // hash rule + //mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000); } static void emi_chn_config(void) { -#ifdef RANK_512MB // => 2channel , dual rank , total=2G +#ifdef RANK_512MB mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400a051); #else - #ifdef RANK_1GB //RANK_1G => 2channel , dual rank , total=4G + #ifdef RANK_1GB mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051); #else #ifdef RANK_2GB @@ -350,26 +349,26 @@ static void emi_chn_config(void) { mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000) - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2 - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111); //mw2 + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e); // chuan - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e); // chuan + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e); + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3ff79); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79); // update timeout setting: bit 12~15 + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222); // Stop urgent read first when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27: 24] wr_rsv_thr_h, + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0 + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f); + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa6168ff); mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa516cff); @@ -385,10 +384,10 @@ static void emi_sw_setting(void) enable_infra_emi_broadcast(1); - /* mpu irq settings. separate emi mpu and devmpu irq */ + *((volatile unsigned int *) EMI_CONH) = *((volatile unsigned int *) EMI_CONH) | 0xC0; - /* for DVFS BW monitor */ + *((volatile unsigned int *) EMI_BWCT0) = 0x05000305; *((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF0705; *((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF0A05; @@ -423,10 +422,10 @@ static void emi_sw_setting(void) } #endif - /* align urgent monitor countrol to bus monitor */ + *((volatile unsigned int *)0x10219858) |= 0x1 << 11; - /* EMI doeapp for DCM */ + emi_dcm = 0; emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm); if (emi_dcm == 1) { @@ -446,9 +445,9 @@ void emi_init(void) //unsigned int domain = 0; //char *str; - mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000); // config emi for 2+2CH + mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000); #ifdef SUB_EMI_BASE - mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000); // config sub emi for 2+2CH + mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000); #endif enable_infra_emi_broadcast(1); @@ -465,27 +464,26 @@ void emi_init2(void) enable_infra_emi_broadcast(1); - mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001); // [0] EMI enable - mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400); //[10] EMI enable + mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001); + mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400); #ifdef REAL_CHIP_EMI_GOLDEN_SETTING - mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg interrupt + mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); + - // Clear rank_arb_en - emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0); // read ch0 + emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0); emi_temp_data = emi_temp_data & ~(0x1); - mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel - // auto-config rank_arb_en according to dual_rank_en setting - // assume all channel with same configuration - emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000); // read ch0 + mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); + + emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000); emi_temp_data = emi_temp_data & 0x1; - mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel + mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); enable_infra_emi_broadcast(0); - // ----- from dcm_setting.c ----- + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF); mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF); mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF); @@ -546,13 +544,13 @@ void emi_init2(void) mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0xA00001FF); - mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg + mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); #ifdef EMI_MP_SETTING - // Enable rdata_prty_gen & wdata_prty_chk - mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000); // enable cen_emi parity (w) - // emi bus parity workaround + mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000); + + emi_temp_data = mt_emi_sync_read(0x40000000); mt_emi_sync_write(0x40000000, emi_temp_data); emi_temp_data = mt_emi_sync_read(0x40000100); @@ -562,61 +560,20 @@ void emi_init2(void) emi_temp_data = mt_emi_sync_read(0x40000300); mt_emi_sync_write(0x40000300, emi_temp_data); - mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004); // enable chn_emi parity - - //// Enable APMCU Early CKE - //// set reg_chn_en - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data >> 6) & (0x1<<2); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_chn_pos - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data << 2) & (0x3<<4); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_chn_loc - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data >> 4) & (0x1<<6); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_dual_rank_en - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data >> 10) & (0x1<<7); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_cas_size[1:0] - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data >> 9) & (0x3<<9); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_cas_size[2] - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data << 11) & (0x1<<11); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_cas_size[3] - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000); - //emi_temp_data = (emi_temp_data >> 14) & (0x1<<12); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_remap_shift - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000); - //// set reg_rank_dec0 - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000038); - //emi_temp_data = (emi_temp_data << 2) & (0x1f<<18); - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data); - //// set reg_rank_cke_ext and reg_enable - //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x11000001); - //// set to mcusys - //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4); - //mt_emi_sync_write(MCUSYS_PAR_WRAP_BASE+0x0000a490, emi_temp_data); - - /*TINFO="program hash rule"*/ + mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004); + + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021); - mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1 + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); + - /*TINFO="read emi_reg_pd then write apmcu config reg"*/ emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050); emi_temp_data = emi_temp_data & 0xf; mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data); - /*TINFO="Enable EMI wdata bus encode function"*/ - mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus encode // *EMI_CONN |= (0x1 << 21); - mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010); // enable chn_emi wdata bus encode // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4); + + mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); + mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010); #else // MP_dsim_v02 test (from v01) - all fr //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000); @@ -626,27 +583,27 @@ void emi_init2(void) #endif - /*TINFO="program hash rule"*/ + if (channel_num_auxadc == CHANNEL_FOURTH) { mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021); - mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1 + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); } - else /* CHANNEL_DUAL */ + else { mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007); - mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1 + mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); } - /*TINFO="read emi_reg_pd then write apmcu config reg"*/ + emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050); emi_temp_data = emi_temp_data & 0xf; enable_infra_emi_broadcast(1); mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data); - mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG + mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); enable_infra_emi_broadcast(0); emi_sw_setting(); @@ -809,7 +766,7 @@ unsigned int get_cen_emi_cona(void) return mt_emi_sync_read(EMI_CONA); } -/* assume all chn emi setting are the same */ + unsigned int get_chn_emi_cona(void) { unsigned int ch0_emi_cona; @@ -897,7 +854,7 @@ void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr) static unsigned int cen_emi_conh_backup = 0; static unsigned int chn_emi_cona_backup = 0; -/* return the start address of rank1 */ + unsigned int set_emi_before_rank1_mem_test(void) { cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH); @@ -905,13 +862,13 @@ unsigned int set_emi_before_rank1_mem_test(void) enable_infra_emi_broadcast(1); if (get_rank_nr_by_emi() == 2) { - /* set the rank size to 1GB for 2 channels */ + mt_emi_sync_write(EMI_CONH, (cen_emi_conh_backup & 0x0000ffff) | 0x22220000); set_chn_emi_cona( (chn_emi_cona_backup & 0xff00ffff) | 0x00220000); } else { - /* set the rank size to 1GB for 1 channel */ + mt_emi_sync_write(EMI_CONH, (cen_emi_conh_backup & 0x0000ffff) | 0x44440000); set_chn_emi_cona( @@ -1053,7 +1010,7 @@ void record_emi_snst(void) last_emi_info_ptr->snst_last = mt_emi_sync_read(EMI_SNST); emi_log("[EMI] SNST: 0x%x\n", last_emi_info_ptr->snst_last); - /* clear EMI_SNST and set target master to M5 */ + mt_emi_sync_write(EMI_SNST, 0x85000000); #endif } diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h b/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h index 356c8176c7..982209345c 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h @@ -12,24 +12,20 @@ #define ENABLE_EMI_LPBK_TEST 0 #endif -#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST // 0: EMI LPBK test, 1: normal K, dram used +#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST -#define EMI_LPBK_USE_THROUGH_IO 0 //test through IO -#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window -#define EMI_LPBK_ADDRESS_DEFECT 0 //test address defect, MUST use CPU WRITE mode +#define EMI_LPBK_USE_THROUGH_IO 0 +#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 +#define EMI_LPBK_ADDRESS_DEFECT 0 #if ENABLE_EMI_LPBK_TEST -#define EMI_USE_TA2 0 // 0:CPU write, 1:TA2, DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode) +#define EMI_USE_TA2 0 #else #define EMI_USE_TA2 0 #endif -/**************************** -Summary: -1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode -8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode) -****************************/ -#define EMI_LPBK_1W1R 0 //CPU mode 0:8W1R, 1:1W1R + +#define EMI_LPBK_1W1R 0 #define EMI_LPBK_S1 0 @@ -40,12 +36,12 @@ Summary: #define ADJUST_TXDLY_SCAN_RX_WIN 0 #define EMI_LPBK_K_TX 0 -#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write +#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 -#define EMI_LPBK_DFS_32 0 //DFS 32<->32<->32 -#define EMI_LPBK_DFS_24 0 //DFS 24<->24<->24 -#define EMI_LPBK_DFS_16 0 //DFS 16<->16<->16 +#define EMI_LPBK_DFS_32 0 +#define EMI_LPBK_DFS_24 0 +#define EMI_LPBK_DFS_16 0 #define EMI_LPBK_USE_LP3_PINMUX 0 #define EMI_LPBK_8W1R 1 #if EMI_LPBK_1W1R @@ -60,13 +56,13 @@ Summary: #endif //#define K_TX_DQS_DLY 0 -#define LP4_4266_freq_meter 533 // //shu0 533 -#define LP4_3733_freq_meter 464 // //shu0 464 -#define LP4_3200_freq_meter 386 // //shu8 386 //shu9 386 -#define LP4_2400_freq_meter 299 //shu6 299 shu5 299 -#define LP4_1600_freq_meter 191 //199 //shu4 383 shu3 191 -#define LP4_1200_freq_meter 299 //shu2 299 shu1 299 -#define LP4_800_freq_meter 199 //shu7 199 +#define LP4_4266_freq_meter 533 +#define LP4_3733_freq_meter 464 +#define LP4_3200_freq_meter 386 +#define LP4_2400_freq_meter 299 +#define LP4_1600_freq_meter 191 +#define LP4_1200_freq_meter 299 +#define LP4_800_freq_meter 199 #if ENABLE_EMI_LPBK_TEST //EMI_LPBK_DRAM_USED==0 diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h index d27d7ea96f..3e5c421799 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h @@ -16,9 +16,9 @@ #include <soc/dramc_soc.h> #include <soc/dramc_param.h> -#define SW_CHANGE_FOR_SIMULATION 0 //calibration funciton for whole chip simulation. Code changed due to different compiler +#define SW_CHANGE_FOR_SIMULATION 0 #ifndef FOR_DV_SIMULATION_USED -#define FOR_DV_SIMULATION_USED (FALSE) ////calibration funciton for DV simulation. Code changed due to different compiler#define FT_DSIM_USED 0 +#define FOR_DV_SIMULATION_USED (FALSE) #endif #define DV_SIMULATION_LP4 1 #define BYPASS_CALIBRATION 0 @@ -52,13 +52,13 @@ #define EYESCAN_K (0) -//Read Chip QT Tool + #ifndef QT_GUI_Tool -#define QT_GUI_Tool 0 //Setting 1 when using QT GUI Tool Compiler. -#define HAPS_FPFG_A60868 0 //Setting 1 when testing HAPS FPGA +#define QT_GUI_Tool 0 +#define HAPS_FPFG_A60868 0 #endif -//DRAMC Chip + #define fcA60868 1 #define fcPetrus 2 #define fcIPM 3 @@ -78,7 +78,7 @@ #define __LP5_COMBO__ (FALSE) -#define FEATURE_RDDQC_K_DMI (FALSE) // This feature is not supported at A60868 test chip +#define FEATURE_RDDQC_K_DMI (FALSE) #if FOR_DV_SIMULATION_USED #undef __ETT__ @@ -97,41 +97,41 @@ #endif #if FOR_DV_SIMULATION_USED -#define CHANNEL_NUM 2 // 1 single channel, 2 dual channel, 4 channel +#define CHANNEL_NUM 2 #else -#define CHANNEL_NUM 4 // 1 single channel, 2 dual channel, 4 channel +#define CHANNEL_NUM 4 #endif -#define DPM_CH_NUM 2 // CH0/1 is Master, CH2/3 is Slave +#define DPM_CH_NUM 2 + -//ZQ calibration #define ENABLE_LP4_ZQ_CAL 1 -#if ENABLE_LP4_ZQ_CAL //choose one mode to do ZQ calibration -#define ZQ_SWCMD_MODE 1 //suggested SW CMD mode -#define ZQ_RTSWCMD_MODE 0 //run time SW mode -#define ZQ_SCSM_MODE 0 //old mode +#if ENABLE_LP4_ZQ_CAL +#define ZQ_SWCMD_MODE 1 +#define ZQ_RTSWCMD_MODE 0 +#define ZQ_SCSM_MODE 0 #endif #define CODE_SIZE_REDUCE 0 #define CALIBRATION_SPEED_UP_DEBUG 0 #define VENDER_JV_LOG 0 -//SW option -#define DUAL_FREQ_K 1 //0 : only K 1 freq(1600), 1: K multi freq + +#define DUAL_FREQ_K 1 #define SCRAMBLE_EN 1 #if 1 //[FOR_CHROMEOS] #define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem. #else #define ENABLE_EYESCAN_GRAPH 1 #endif -#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 +#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U #define EYESCAN_GRAPH_RX_VREF_STEP 2 -#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 +#define EYESCAN_RX_VREF_RANGE_END 128 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10 #if (fcFOR_CHIP_ID == fcA60868) -#define ENABLE_EYESCAN_CBT 0 //TO DO:Forece to draw CBT eye diagram after calibration -#define ENABLE_EYESCAN_RX 0 //TO DO:Forece to draw RX eye diagram after calibration -#define ENABLE_EYESCAN_TX 0 //TO DO:Forece to draw TX eye diagram after calibration -#define ENABLE_VREFSCAN 0 //TO DO:Forece to Vref Scan for calibration +#define ENABLE_EYESCAN_CBT 0 +#define ENABLE_EYESCAN_RX 0 +#define ENABLE_EYESCAN_TX 0 +#define ENABLE_VREFSCAN 0 #endif #define CHECK_HQA_CRITERIA 0 @@ -148,7 +148,7 @@ #define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1 #define DUMP_TA2_WINDOW_SIZE_RX_TX 0 #if ENABLE_TX_TRACKING - #define ENABLE_SW_TX_TRACKING 0 //if SW_TX_TRACKING is 0, using HW_TX_TRACKING + #define ENABLE_SW_TX_TRACKING 0 //can only choose 1 to set as 1 in the following 3 define #define DQSOSC_SWCMD 1 #define DQSOSC_RTSWCMD 0 @@ -164,15 +164,15 @@ #define ENABLE_TMRRI_NEW_MODE 1 #define ENABLE_8PHASE_CALIBRATION 1 #define ENABLE_DUTY_SCAN_V2 1 -#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 //0: K all Freq 1: K highest Freq +#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 #define APPLY_DQDQM_DUTY_CALIBRATION 1 -#define IMPEDANCE_TRACKING_ENABLE //Impendence tracking +#define IMPEDANCE_TRACKING_ENABLE #ifdef IMPEDANCE_TRACKING_ENABLE #define IMPEDANCE_HW_CALIBRATION 0 #else #define IMPEDANCE_HW_CALIBRATION 0 #endif -#define IMPEDANCE_HW_SAVING //mask because function fail, it lets clk swing change larger before DVFS occurs +#define IMPEDANCE_HW_SAVING #define IMP_DEBUG_ENABLE #define ENABLE_MIOCK_JMETER #define MIOCK_JMETER_CNT_WA 1 @@ -182,8 +182,8 @@ #define TDQSCK_PRECALCULATION_FOR_DVFS 1 #define HW_GATING #define ENABLE_RX_FIFO_MISMATCH_DEBUG 1 -#define VERIFY_CKE_PWR_DOWN_FLOW 0 //Lewis add for DVT -#define CBT_MOVE_CA_INSTEAD_OF_CLK 1 // need to check on LP5 +#define VERIFY_CKE_PWR_DOWN_FLOW 0 +#define CBT_MOVE_CA_INSTEAD_OF_CLK 1 #define MRW_CHECK_ONLY 0 #define MRW_BACKUP 0 #define ENABLE_SAMSUNG_NT_ODT 0 @@ -196,31 +196,31 @@ #define DUMP_ALLSUH_RG 0 #define PIN_CHECK_TOOL 0 #define ENABLE_DATLAT_BY_FORMULA 1 -#define ENABLE_RX_AUTOK_MISS_FIRSTPASS_WA 1 //TOBE remove at IPMv2.2 +#define ENABLE_RX_AUTOK_MISS_FIRSTPASS_WA 1 //Debug option #define GATING_ONLY_FOR_DEBUG 0 #define ENABLE_RX_AUTOK_DEBUG_MODE 0 -#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 // LP4 only, LP3 not support +#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 #if CODE_SIZE_REDUCE || FOR_DV_SIMULATION_USED -#define CPU_RW_TEST_AFTER_K 0 // need to enable GATING_ONLY_FOR_DEBUG at the same time for gating debug log +#define CPU_RW_TEST_AFTER_K 0 #define TA2_RW_TEST_AFTER_K 0 #else -#define CPU_RW_TEST_AFTER_K 1 // need to enable GATING_ONLY_FOR_DEBUG at the same time for gating debug log +#define CPU_RW_TEST_AFTER_K 1 #define TA2_RW_TEST_AFTER_K 1 #endif -//PINMUX auto test per bit related + #define PINMUX_AUTO_TEST_PER_BIT_CA 0 #define PINMUX_AUTO_TEST_PER_BIT_RX 0 #define PINMUX_AUTO_TEST_PER_BIT_TX 0 -#define CA_PER_BIT_DELAY_CELL 1//LP4 +#define CA_PER_BIT_DELAY_CELL 1 #if PINMUX_AUTO_TEST_PER_BIT_CA #undef CA_PER_BIT_DELAY_CELL #define CA_PER_BIT_DELAY_CELL 0 #endif -//Gating calibration + #define GATING_LEADLAG_LOW_LEVEL_CHECK 0 #if CODE_SIZE_REDUCE @@ -258,7 +258,7 @@ #define EYESCAN_LOG 0 #define FSP1_CLKCA_TERM 1 #define CBT_FSP1_MATCH_FSP0_UNTERM_WA 1 -#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED //@Darren, Wait DFS ready +#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED #define FT_DSIM_USED 0 #define GATING_ONLY_FOR_DEBUG 0 #define MEASURE_DRAM_POWER_INDEX 0 @@ -274,11 +274,11 @@ #define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 #define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0 #define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 -//Run time config -#define TEMP_SENSOR_ENABLE // Enable rumtime HMR4 + +#define TEMP_SENSOR_ENABLE #define ENABLE_REFRESH_RATE_DEBOUNCE 1 #define ENABLE_PER_BANK_REFRESH 1 -#define PER_BANK_REFRESH_USE_MODE 1 // 0: original mode, 1: hybrid mode, 2: always pb mode +#define PER_BANK_REFRESH_USE_MODE 1 #define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1 #define DRAMC_MODIFIED_REFRESH_MODE 1 #define DRAMC_CKE_DEBOUNCE 1 @@ -286,14 +286,14 @@ #define SAMSUNG_LP4_NWR_WORKAROUND 1 #define AC_TIMING_DERATE_ENABLE 1 -#define ENABLE_EARLY_BG_CMD 0 // 0: Disable 1: Enable, Reduce the CMD latency by CTO_EBG request +#define ENABLE_EARLY_BG_CMD 0 //////////////////////////////////// DVFS ////////////////////////////// -#define ENABLE_DVS 1 //DVS need tracking enable -#define DRAMC_DFS_MODE 1 // 0:Legacy, 1:DPM RG, 2: PHY RG +#define ENABLE_DVS 1 +#define DRAMC_DFS_MODE 1 #define ENABLE_RTMRW_DEBUG_LOG 0 -#define ENABLE_TX_REBASE_ODT_WA 0 // for Pexxxs/xxx868 -#define ENABLE_DDR800_SOPEN_DSC_WA 1 //Paxxer +#define ENABLE_TX_REBASE_ODT_WA 0 +#define ENABLE_DDR800_SOPEN_DSC_WA 1 #if ENABLE_TX_WDQS #define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0 #endif @@ -306,18 +306,18 @@ #define ENABLE_DFS_TIMING_ENLARGE 0 #define ENABLE_DFS_208M_CLOCK 0 #define ENABLE_DFS_HW_SAVE_MASK 0 -#define REPLACE_DFS_RG_MODE 1 //Trial run Remove DFS PHY RG mode +#define REPLACE_DFS_RG_MODE 1 #define ENABLE_LP4Y_DFS 0 #if ENABLE_LP4Y_DFS -#define LP4Y_BACKUP_SOLUTION 0 // 0: Set SE after calibration, 1: Set SE before calibration -#define ENABLE_LP4Y_WA 1 //no que flush actiming extend and CBT can't train in SE +#define LP4Y_BACKUP_SOLUTION 0 +#define ENABLE_LP4Y_WA 1 #define ENABLE_DFS_RUNTIME_MRW 1 #else #define LP4Y_BACKUP_SOLUTION 0 #define ENABLE_LP4Y_WA 0 -#define ENABLE_DFS_RUNTIME_MRW 0 // for LP4x +#define ENABLE_DFS_RUNTIME_MRW 0 #endif -#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION // Wait overhead refresh enable, @Darren, Entry SREF -> EXIT SREF -> PDE Command violates tXSR time +#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION #define ENABLE_RANK_NUMBER_AUTO_DETECTION 1 #define DDR_HW_AUTOK_POLLING_CNT 100000 @@ -325,9 +325,9 @@ //////////////////////////////////// FIXME end///////////////////////// #if (fcFOR_CHIP_ID == fcA60868) -#define WORKAROUND_LP5_HEFF 1 //High efficiency mode +#define WORKAROUND_LP5_HEFF 1 #undef ENABLE_RUNTIME_MRW_FOR_LP5 -#define ENABLE_RUNTIME_MRW_FOR_LP5 0 // DV fail in 868, use RTSWCMD_MRW +#define ENABLE_RUNTIME_MRW_FOR_LP5 0 #endif #if ENABLE_RODT_TRACKING @@ -337,10 +337,10 @@ #endif #define CHECK_GOLDEN_SETTING (FALSE) -#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 //0: DCM Off, 1: DCM On -#define LP5_GOLDEN_SETTING_CHECKER (FALSE) //FALSE: enable LP4 checker +#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 +#define LP5_GOLDEN_SETTING_CHECKER (FALSE) //#define CMD_PICG_NEW_MODE 1 -//#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error (Remove the flag, the setting will be 1) +//#define ENABLE_RX_DCM_DPHY 1 //#define CLK_FREE_FUN_FOR_DRAMC_PSEL //#define HW_SAVE_FOR_SR @@ -352,10 +352,8 @@ #define RX_PICG_NEW_MODE 0 #endif -#define DDR_RESERVE_NEW_MODE 1 //0: old mode 1: new mode -//============================================================================= -// for D Sim sumulation used -//============================================================================= +#define DDR_RESERVE_NEW_MODE 1 + #if QT_GUI_Tool || !FOR_DV_SIMULATION_USED #define DV_SIMULATION_INIT_C 1 #define SIMULATION_LP4_ZQ 1 @@ -370,7 +368,7 @@ #define SIMULATION_DATLAT 1 #define SIMULATION_RX_RDDQC 1 #define SIMULATION_RX_PERBIT 1 -#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling +#define SIMULATION_TX_PERBIT 1 #define SIMULATION_RX_DVS 0 #define SIMULATION_RUNTIME_CONFIG 0 #else @@ -387,11 +385,11 @@ #define SIMULATION_DATLAT 1 #define SIMULATION_RX_RDDQC 1 #define SIMULATION_RX_PERBIT 1 -#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling +#define SIMULATION_TX_PERBIT 1 #define SIMULATION_RX_DVS 0 -#define SIMULATION_RUNTIME_CONFIG 1 // @Darren for DV sim +#define SIMULATION_RUNTIME_CONFIG 1 #endif -//Used to keep original VREF when doing Rx calibration for RX DVS + #define DVS_CAL_KEEP_VREF 0xf //#define DDR_INIT_TIME_PROFILING @@ -405,9 +403,9 @@ // common #define DQS_BYTE_NUMBER 2 #define DQS_BIT_NUMBER 8 -#define DQ_DATA_WIDTH 16 // define max support bus width in the system (to allocate array size) +#define DQ_DATA_WIDTH 16 #define DQM_BYTE_NUM 2 -#define TIME_OUT_CNT 100 //100us +#define TIME_OUT_CNT 100 #define HW_REG_SHUFFLE_MAX 4 typedef enum @@ -417,16 +415,16 @@ typedef enum ALL_BYTES } BYTES_T; -//Should be removed after A60868 + #define LP5_DDR4266_RDBI_WORKAROUND 0 #define CBT_O1_PINMUX_WORKAROUND 0 #define WLEV_O1_PINMUX_WORKAROUND 0 #define WCK_LEVELING_FM_WORKAROUND 0 -//RX input buffer offset calibration + #define ENABLE_RX_INPUT_BUFF_OFF_K 1 -/* Gating window */ + #define DQS_GW_COARSE_STEP 1 #define DQS_GW_FINE_START 0 #define DQS_GW_FINE_END 32 @@ -435,23 +433,23 @@ typedef enum #define DQS_GW_UI_PER_MCK 16 #define DQS_GW_PI_PER_UI 32 -// DATLAT + #define DATLAT_TAP_NUMBER 32 -// RX DQ/DQS -#define MAX_RX_DQSDLY_TAPS 511 // 0x018, May set back to 64 if no need. + +#define MAX_RX_DQSDLY_TAPS 511 #define MAX_RX_DQDLY_TAPS 252 #define RX_VREF_NOT_SPECIFY 0xff -#define RX_VREF_DUAL_RANK_K_FREQ 1866 // if freq >=RX_VREF_DUAL_RANK_K_FREQ, Rank1 rx vref K will be enable. +#define RX_VREF_DUAL_RANK_K_FREQ 1866 #define RX_VREF_RANGE_BEGIN 0 #define RX_VREF_RANGE_BEGIN_ODT_OFF 32 #define RX_VREF_RANGE_BEGIN_ODT_ON 24 -#define RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63 +#define RX_VREF_RANGE_END 128 #define RX_VREF_RANGE_STEP 1 #define RX_PASS_WIN_CRITERIA 30 #define RDDQC_PINMUX_WORKAROUND 1 -// TX DQ/DQS + #if CODE_SIZE_REDUCE #define TX_AUTO_K_SUPPORT 0 #else @@ -462,8 +460,8 @@ typedef enum #define TX_AUTO_K_WORKAROUND 1 #define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1 #endif -#define MAX_TX_DQDLY_TAPS 31 // max DQ TAP number -#define MAX_TX_DQSDLY_TAPS 31 // max DQS TAP number +#define MAX_TX_DQDLY_TAPS 31 +#define MAX_TX_DQSDLY_TAPS 31 #define TX_OE_EXTEND 0 #define TX_DQ_OE_SHIFT_LP5 5 #if TX_OE_EXTEND @@ -483,13 +481,12 @@ typedef enum #define TX_RETRY_CONTROL_BY_SPM 0 #endif -// Sw work around options. -#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 // work around for clock multi phase problem(cannot move clk or the clk will be bad) + +#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 #define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1 #define DramcHWDQSGatingTracking_FIFO_MODE 1 -#define DONT_MOVE_CLK_DELAY // don't move clk delay -/* If defined for gFreqTbl and fastK - */ +#define DONT_MOVE_CLK_DELAY + #define LP4_SHU0_FREQ (1866) #define LP4_SHU8_FREQ (1600) #define LP4_SHU9_FREQ (1600) @@ -514,14 +511,14 @@ typedef enum #define LP4_SHU7_FREQSEL (LP4_DDR800) #if FOR_DV_SIMULATION_USED -#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration -#define DEFAULT_TEST2_2_CAL 0xaa000020 // pattern1 and offset address for test engine when we do calibraion +#define DEFAULT_TEST2_1_CAL 0x55000000 +#define DEFAULT_TEST2_2_CAL 0xaa000020 #else -#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration -#define DEFAULT_TEST2_2_CAL 0xaa000100 // pattern1 and offset address for test engine when we do calibraion +#define DEFAULT_TEST2_1_CAL 0x55000000 +#define DEFAULT_TEST2_2_CAL 0xaa000100 #endif -//CBT/CA training + #if CODE_SIZE_REDUCE #define CBT_AUTO_K_SUPPORT 0 #define CBT_OLDMODE_SUPPORT 0 @@ -535,13 +532,13 @@ typedef enum #define LP4_MRFSP_TERM_FREQ 1333 #define LP5_MRFSP_TERM_FREQ 1866 -//Calibration Summary + #define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION) #define PRINT_CALIBRATION_SUMMARY_DETAIL 1 #define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0 -#if 1 //(FOR_DV_SIMULATION_USED==0) -#define ETT_PRINT_FORMAT // Apply for both preloader and ETT +#if 1 +#define ETT_PRINT_FORMAT #endif #if !CODE_SIZE_REDUCE @@ -553,7 +550,7 @@ typedef enum //Run Time Config //#define DUMMY_READ_FOR_TRACKING #define ZQCS_ENABLE_LP4 -#if ENABLE_LP4Y_DFS // @Darren, RT-mrw to HW-zqcal tMRD Violation Report - SW workaround from Robert +#if ENABLE_LP4Y_DFS #undef ZQCS_ENABLE_LP4 #endif #ifndef ZQCS_ENABLE_LP4 @@ -565,7 +562,7 @@ typedef enum #define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1 #define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1 #define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1 -#define RDSEL_TRACKING_EN 1 // @Darren, for SHU0 only (DDR3733 or DDR4266) +#define RDSEL_TRACKING_EN 1 #define RDSEL_TRACKING_TH 2133 #define ENABLE_DFS_SSC_WA 0 #define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1 @@ -587,12 +584,12 @@ typedef enum #if !__ETT__ -// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify + #if (FOR_DV_SIMULATION_USED==0) && !defined(SLT) -// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify + #define SUPPORT_SAVE_TIME_FOR_CALIBRATION CFG_DRAM_CALIB_OPTIMIZATION #else -// DV simulation, use full calibration flow + #define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 #endif #define EMMC_READY CFG_DRAM_CALIB_OPTIMIZATION @@ -632,16 +629,16 @@ typedef enum //#define USE_CLK26M #undef DUAL_FREQ_K -#define DUAL_FREQ_K 0 //0 : only K 1 freq(1600), 1: K multi freq +#define DUAL_FREQ_K 0 #undef TDQSCK_PRECALCULATION_FOR_DVFS -#define TDQSCK_PRECALCULATION_FOR_DVFS 0//DQS pre-calculation +#define TDQSCK_PRECALCULATION_FOR_DVFS 0 //#undef CHANNEL_NUM //#define CHANNEL_NUM 4 #undef REPLACE_DFS_RG_MODE -#define REPLACE_DFS_RG_MODE 1 //Trial run Remove DFS PHY RG mode +#define REPLACE_DFS_RG_MODE 1 #undef ENABLE_DUTY_SCAN_V2 #define ENABLE_DUTY_SCAN_V2 0 @@ -664,7 +661,7 @@ typedef enum #define REDUCE_CALIBRATION_OLYMPUS_ONLY 0 #undef APPLY_LOWPOWER_GOLDEN_SETTINGS -#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //Should open APPLY_LOWPOWER_GOLDEN_SETTINGS before SB + 3 +#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3 @@ -689,13 +686,13 @@ typedef enum #define GATING_ADJUST_TXDLY_FOR_TRACKING 0 #undef ENABLE_PER_BANK_REFRESH -#define ENABLE_PER_BANK_REFRESH 1 //align bringup setting, Derping +#define ENABLE_PER_BANK_REFRESH 1 #undef ENABLE_TPBR2PBR_REFRESH_TIMING -#define ENABLE_TPBR2PBR_REFRESH_TIMING 1 //align bringup setting, Robert +#define ENABLE_TPBR2PBR_REFRESH_TIMING 1 #undef REFRESH_OVERHEAD_REDUCTION -#define REFRESH_OVERHEAD_REDUCTION 1 //align bringup setting, Derping +#define REFRESH_OVERHEAD_REDUCTION 1 #undef AC_TIMING_DERATE_ENABLE #define AC_TIMING_DERATE_ENABLE 1 @@ -745,18 +742,18 @@ typedef enum #undef XRTW2W_PERFORM_ENHANCE_TX #undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY #ifdef XRTR2W_PERFORM_ENHANCE_RODTEN -#undef XRTR2W_PERFORM_ENHANCE_RODTEN //conflict with ENABLE_RODT_TRACKING, LP4 support only +#undef XRTR2W_PERFORM_ENHANCE_RODTEN +#endif #endif #endif -#endif //FIRST_BRING_UP //======================== RSHMOO Definition ===================================== #define RUNTIME_SHMOO_RELEATED_FUNCTION CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO #define RUNTIME_SHMOO_RG_BACKUP_NUM (100) -#define RUNTIME_SHMOO_TX 0 //TX RX can't be opened simultaneously +#define RUNTIME_SHMOO_TX 0 #define RUNTIME_SHMOO_RX 0 -#if RUNTIME_SHMOO_RELEATED_FUNCTION //if enable rshmoo, close TX OE calibration +#if RUNTIME_SHMOO_RELEATED_FUNCTION #undef TX_OE_EXTEND #define TX_OE_EXTEND 1 #undef TX_DQ_OE_SHIFT_LP4 @@ -775,19 +772,19 @@ typedef enum #define RUNTIME_SHMOO_FAST_K 1 -#define RUNTIME_SHMOO_TEST_CHANNEL 0 // 0: CHA, 1: CHB -#define RUNTIME_SHMOO_TEST_RANK 0 // 0: RK0, 1: RK1 -#define RUNTIME_SHMOO_TEST_BYTE 0 // 0: Byte0, 1: Byte1 +#define RUNTIME_SHMOO_TEST_CHANNEL 0 +#define RUNTIME_SHMOO_TEST_RANK 0 +#define RUNTIME_SHMOO_TEST_BYTE 0 -#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 // 0~63 -#define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 // 0~63 +#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 +#define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 #define RUNTIME_SHMOO_TEST_PI_DELAY_STEP 1 -#define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 //La_fite: 63 -#define RUNTIME_SHMOO_RX_TEST_MARGIN 2 //for RX Delay (start:first_pass-margin, end:last_pass +margin) +#define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 +#define RUNTIME_SHMOO_RX_TEST_MARGIN 2 -#define RUNTIME_SHMOO_TEST_VREF_START 0 // 0~81 : 0~50 is range 0, 51~81 is range 1 -#define RUNTIME_SHMOO_TEST_VREF_END 81 // 0~81 : 0~50 is range 0, 51~81 is range 1 +#define RUNTIME_SHMOO_TEST_VREF_START 0 +#define RUNTIME_SHMOO_TEST_VREF_END 81 #define RUNTIME_SHMOO_TEST_VREF_STEP 1 #endif //============================================================================= @@ -850,7 +847,7 @@ typedef enum { IMP_LOW_FREQ = 0, IMP_HIGH_FREQ, - IMP_NT_ODTN, // Samsung support only for LP4X + IMP_NT_ODTN, IMP_VREF_MAX } DRAMC_IMP_T; @@ -869,11 +866,11 @@ typedef enum typedef enum { - DRAM_OK = 0, // OK - DRAM_FAIL, // FAIL + DRAM_OK = 0, + DRAM_FAIL, DRAM_FAST_K, DRAM_NO_K, -} DRAM_STATUS_T; // DRAM status type +} DRAM_STATUS_T; typedef enum { @@ -888,7 +885,7 @@ typedef enum { CKE_FIXOFF = 0, CKE_FIXON, - CKE_DYNAMIC //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) + CKE_DYNAMIC } CKE_FIX_OPTION; typedef enum @@ -930,7 +927,7 @@ typedef enum LP4_DDR400, PLL_FREQ_SEL_MAX -} DRAM_PLL_FREQ_SEL_T; // DRAM DFS type +} DRAM_PLL_FREQ_SEL_T; typedef enum { @@ -974,14 +971,14 @@ typedef enum SRAM_SHU7, #endif DRAM_DFS_SRAM_MAX -} DRAM_DFS_SRAM_SHU_T; // DRAM SRAM RG type +} DRAM_DFS_SRAM_SHU_T; typedef enum { SHUFFLE_RG = 0, NONSHUFFLE_RG, BOTH_SHU_NONSHU_RG, -} RG_SHU_TYPE_T; // RG SHUFFLE type +} RG_SHU_TYPE_T; typedef enum { @@ -1037,7 +1034,7 @@ typedef struct _DRAM_DFS_FREQUENCY_TABLE_T DIV_MODE_T divmode; DRAM_DFS_SRAM_SHU_T SRAMIdx; DUTY_CALIBRATION_T duty_calibration_mode; - VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; // CBT/RX/TX vref calibration enable or not + VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; DDR800_MODE_T ddr_loop_mode; } DRAM_DFS_FREQUENCY_TABLE_T; @@ -1060,13 +1057,7 @@ typedef enum RANK_MAX } DRAM_RANK_T; -/* - * Internal CBT mode enum - * 1. Calibration flow uses vGet_Dram_CBT_Mode to - * differentiate between mixed vs non-mixed LP4 - * 2. Declared as dram_cbt_mode[RANK_MAX] internally to - * store each rank's CBT mode type - */ + typedef enum { CBT_NORMAL_MODE = 0, @@ -1112,10 +1103,7 @@ typedef enum PINMUX_MAX } DRAM_PINMUX; -/* For faster switching between term and un-term operation - * FSP_0: For un-terminated freq. - * FSP_1: For terminated freq. - */ + typedef enum { FSP_0 = 0, @@ -1151,17 +1139,13 @@ typedef enum CBT_PHASE_FALLING } lp5_cbt_phase_t; -/* - * External CBT mode enum - * Due to MDL structure compatibility (single field for dram CBT mode), - * the below enum is used in preloader to differentiate between dram cbt modes - */ + typedef enum { - CBT_R0_R1_NORMAL = 0, // Normal mode - CBT_R0_R1_BYTE, // Byte mode - CBT_R0_NORMAL_R1_BYTE, // Mixed mode R0: Normal R1: Byte - CBT_R0_BYTE_R1_NORMAL // Mixed mode R0: Byte R1: Normal + CBT_R0_R1_NORMAL = 0, + CBT_R0_R1_BYTE, + CBT_R0_NORMAL_R1_BYTE, + CBT_R0_BYTE_R1_NORMAL } DRAM_CBT_MODE_EXTERN_T; typedef enum @@ -1197,9 +1181,9 @@ typedef enum typedef enum { - TEST_ISI_PATTERN = 0, //don't change - TEST_AUDIO_PATTERN = 1, //don't change - TEST_XTALK_PATTERN = 2, //don't change + TEST_ISI_PATTERN = 0, + TEST_AUDIO_PATTERN = 1, + TEST_XTALK_PATTERN = 2, TEST_WORST_SI_PATTERN, TEST_TA1_SIMPLE, TEST_TESTPAT4, @@ -1228,7 +1212,7 @@ typedef enum TX_DQM_WINDOW_SPEC_OUT = 0xff } DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T; -// enum for CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT)) + typedef enum { CKE_RANK_INDEPENDENT = 0, @@ -1274,7 +1258,7 @@ enum lpddr5_rpre_mode { LPDDR5_RPRE_4S_0T = 0, LPDDR5_RPRE_2S_2T, LPDDR5_RPRE_0S_4T, - LPDDR5_RPRE_XS_4T, /* X = 2~4tWCK */ + LPDDR5_RPRE_XS_4T, }; enum rxdqs_autok_burst_len { @@ -1313,7 +1297,7 @@ typedef enum Deviation_RX, Deviation_TX, Deviation_MAX -} DRAM_DEVIATION_TYPE_T; // DRAM SHUFFLE RG type +} DRAM_DEVIATION_TYPE_T; #endif #if SUPPORT_SAVE_TIME_FOR_CALIBRATION @@ -1367,7 +1351,7 @@ typedef struct _SAVE_TIME_FOR_CALIBRATION_T #endif // Write leveling - U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; //for bypass writeleveling + U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; // Gating U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_BYTE_NUMBER]; @@ -1399,15 +1383,15 @@ typedef struct _SAVE_TIME_FOR_CALIBRATION_T #if RUNTIME_SHMOO_RELEATED_FUNCTION - S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; //for bypass rxwindow - U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; //for bypass rxwindow + S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; + U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; U8 u1SwImpedanceResule[2][4]; U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM]; RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para; #endif }SAVE_TIME_FOR_CALIBRATION_T; -#endif // SUPPORT_SAVE_TIME_FOR_CALIBRATION +#endif #if MRW_CHECK_ONLY #define MR_NUM 64 @@ -1423,18 +1407,18 @@ typedef struct _DRAMC_CTX_T DRAM_RANK_T rank; DRAM_PLL_FREQ_SEL_T freq_sel; DRAM_DRAM_TYPE_T dram_type; - DRAM_FAST_SWITH_POINT_T dram_fsp; // only for LP4, uesless in LP3 - DRAM_FAST_SWITH_POINT_T boot_fsp; // for RTMRW DFS - DRAM_ODT_MODE_T odt_onoff;/// only for LP4, uesless in LP3 - DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; //only for LP4, useless in LP3 - DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; // only for LP4, uesless in LP3 - DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; // only for LP4, uesless in LP3 + DRAM_FAST_SWITH_POINT_T dram_fsp; + DRAM_FAST_SWITH_POINT_T boot_fsp; + DRAM_ODT_MODE_T odt_onoff; + DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; + DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; + DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; DRAM_DATA_WIDTH_T data_width; U32 test2_1; U32 test2_2; DRAM_TEST_PATTERN_T test_pattern; U16 frequency; - U16 freqGroup; /* Used to support freq's that are not in ACTimingTable */ + U16 freqGroup; U16 vendor_id; U16 revision_id; U16 density; @@ -1445,13 +1429,13 @@ typedef struct _DRAMC_CTX_T //U8 enable_tx_scan_vref; #if PRINT_CALIBRATION_SUMMARY - U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail - U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done + U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX]; + U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; U32 SWImpCalResult; U32 SWImpCalExecute; #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK - U32 FastKResultFlag[2][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail - U32 FastKExecuteFlag[2][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done + U32 FastKResultFlag[2][RANK_MAX]; + U32 FastKExecuteFlag[2][RANK_MAX]; #endif #endif @@ -1467,8 +1451,8 @@ typedef struct _DRAMC_CTX_T #endif DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable; DRAM_DFS_REG_SHU_T ShuRGAccessIdx; - lp5_training_mode_t lp5_training_mode; //only for LP5 - lp5_cbt_phase_t lp5_cbt_phase; //only for LP5 + lp5_training_mode_t lp5_training_mode; + lp5_cbt_phase_t lp5_cbt_phase; u8 new_cbt_mode; U8 u1PLLMode; DRAM_DBI_MODE_T curDBIState; @@ -1524,9 +1508,9 @@ typedef struct _JMETER_DELAYCELL_T #if PIN_CHECK_TOOL typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T { - U16 TOTAL_ERR;//DQ,CA + U16 TOTAL_ERR; U16 IMP_ERR_FLAG; - U8 WL_ERR_FLAG;//DQS + U8 WL_ERR_FLAG; U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX]; U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4]; U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_BYTE_NUMBER]; @@ -1610,11 +1594,11 @@ typedef struct _PROFILING_TIME_T #define JUST_TO_GLOBAL_VALUE (0) #define TO_MR (1) -// LP5 MR30 -#define MR30_DCAU (Fld(4, 4)) // DCA for upper byte -#define MR30_DCAL (Fld(4, 0)) // DCA for lower byte -// LP5 MR26 +#define MR30_DCAU (Fld(4, 4)) +#define MR30_DCAL (Fld(4, 0)) + + #define MR26_DCMU1 (Fld(1, 5)) #define MR26_DCMU0 (Fld(1, 4)) #define MR26_DCML1 (Fld(1, 3)) @@ -1622,7 +1606,7 @@ typedef struct _PROFILING_TIME_T #define MR26_DCM_FLIP (Fld(1, 1)) #define MR26_DCM_START_STOP (Fld(1, 0)) -// LP4 MR13 + #define MR13_FSP_OP (Fld(1, 7)) #define MR13_FSP_WR (Fld(1, 6)) #define MR13_DMD (Fld(1, 5)) diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_register.h b/src/vendorcode/mediatek/mt8195/include/dramc_register.h index e5a68bcf98..36ebd052fb 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_register.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_register.h @@ -189,7 +189,7 @@ #define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS -#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 #elif(HAPS_FPFG_A60868 ==0) #undef Channel_A_DRAMC_AO_BASE_ADDRESS #define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000 diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_top.h b/src/vendorcode/mediatek/mt8195/include/dramc_top.h index cbeb6930a1..bddbbd613a 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_top.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_top.h @@ -96,16 +96,16 @@ typedef struct _AC_TIMING_EXTERNAL_T U32 AC_TIME_EMI_TRTW_ODT_ON :4; // U 04 - U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0) - U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1) + U32 AC_TIME_EMI_REFCNT :8; + U32 AC_TIME_EMI_REFCNT_FR_CLK :8; U32 AC_TIME_EMI_TXREFCNT :8; U32 AC_TIME_EMI_TZQCS :8; // U 05 - U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new - U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new - U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new - U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new + U32 AC_TIME_EMI_TRTPD :8; + U32 AC_TIME_EMI_TWTPD :8; + U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; + U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // U 06 // Byte0 @@ -121,19 +121,19 @@ typedef struct _AC_TIMING_EXTERNAL_T // Byte2 U32 AC_TIME_EMI_TRCD_05T :2; U32 AC_TIME_EMI_TWR_05T :2; - U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified + U32 AC_TIME_EMI_TWTR_05T :2; U32 AC_TIME_EMI_TRRD_05T :2; // Byte3 U32 AC_TIME_EMI_TFAW_05T :2; U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2; U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2; - U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new + U32 AC_TIME_EMI_TRTPD_05T :2; // U 07 // Byte0 - U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new - U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us - U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us + U32 AC_TIME_EMI_TWTPD_05T :2; + U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; + U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; }AC_TIMING_EXTERNAL_T; @@ -171,8 +171,8 @@ typedef struct { typedef struct { unsigned int type; - unsigned int id_length; /* storage ID lengty */ - unsigned char ID[16]; /* storage ID */ + unsigned int id_length; + unsigned char ID[16]; u64 DRAM_RANK_SIZE[4]; unsigned int reserved[6]; unsigned int iLPDDR3_MODE_REG_5; @@ -183,7 +183,7 @@ typedef struct { void setup_dramc_voltage_by_pmic(void); void switch_dramc_voltage_to_auto_mode(void); #if ! __ETT__ -uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting. +uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); #endif #endif @@ -210,8 +210,8 @@ typedef struct { volatile unsigned int last_fatal_err_flag; volatile unsigned int fatal_err_flag; volatile unsigned int storage_api_err_flag; - volatile unsigned int last_gating_err[4][2]; // [channel][rank] - volatile unsigned int gating_err[4][2]; // [channel][rank] + volatile unsigned int last_gating_err[4][2]; + volatile unsigned int gating_err[4][2]; unsigned short mr5; unsigned short mr6; unsigned short mr7; @@ -240,7 +240,7 @@ typedef struct { #define ERR_CPU_RW_RK0 (1 << 0) #define ERR_CPU_RW_RK1 (1 << 1) -/* 0x1f -> bit[4:0] is for DDR reserve mode */ + #define DDR_RSV_MODE_ERR_MASK (0x1f) unsigned int check_last_dram_fatal_exception(void); @@ -254,7 +254,7 @@ void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_c void dram_fatal_backup_stberr(void); void dram_fatal_init_stberr(void); void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset); -#if 0//DRAM_AUXADC_CONFIG +#if 0 unsigned int get_ch_num_by_auxadc(void); #endif @@ -288,7 +288,7 @@ unsigned int get_ch_num_by_auxadc(void); dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\ } while(0) -#endif //LAST_DRAMC +#endif typedef enum { KSHU0 = 0, @@ -517,13 +517,7 @@ typedef struct _DRAM_CALIBRATION_DATA_T DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SRAM_MAX]; } DRAM_CALIBRATION_DATA_T; -/* - * g_dram_storage_api_err_code: - * bit[0:3] -> read api - * bit[4:7] -> write api - * bit[8:11] -> clean api - * bit[12:12] -> data formatted due to fatal exception - */ + #define ERR_NULL_POINTER (0x1) #define ERR_MAGIC_NUMBER (0x2) #define ERR_CHECKSUM (0x3) diff --git a/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h b/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h index dc17370baa..0b7a1ea571 100644 --- a/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h +++ b/src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h @@ -15,18 +15,14 @@ mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \ }) -/* - * channel type from sv's view - */ + enum { SV_CHN_A = 0, SV_CHN_B }; -/* - * dram type from sv's view - */ + enum { SV_LPDDR = 0, SV_LPDDR2, @@ -36,9 +32,7 @@ enum { SV_LPDDR5 }; -/* - * data rate from sv's view - */ + enum { SV_DDR4266 = 0, SV_DDR3200, @@ -59,208 +53,96 @@ enum { SV_DDR2133 }; -/* - * cal_sv_rand_args is data traffic from sv to c. - * sv randomizes these arguments for c to control - * calibration. - */ + typedef struct cal_sv_rand_args { -/* >>>>>>>>>> common part begin>>>>>>>>>> */ - /* - * 0x4C503435 - * "LP45" - */ + int magic; - /* - * 0: channel-a - * 1: channel-b - */ + int calibration_channel; - /* - * 0: rank0 - * 1: rank1 - */ + int calibration_rank; - /* - * 0: LPDDR - * 1: LPDDR2 - * 2: PCDDR3 - * 3: LPDDR3 - * 4: LPDDR4 - * 5: LPDDR5 - */ + int dram_type; - /* - * 0: DDR4266 - * 1: DDR3200 - * 2: DDR1600 - * 3: DDR3733 - * 4: DDR2400 - * 5: DDR1866 - * 6: DDR1200 - * 7: DDR1333 - * 8: DDR800 - * 9: DDR1066 - * 10: DDR2667 - * 11: DDR4800 - * 12: DDR5500 - * 13: DDR6000 - * 14: DDR6400 - * 15: DDR2750 - * 16: DDR2133 - */ + int datarate; - /* - * Data Mask Disable - * 0: enable - * 1: disable - */ + int dmd; - int mr2_value; /* for lp4-wirteleveling*/ + int mr2_value; int mr3_value; int mr13_value; int mr12_value; int mr16_value; - int mr18_value; /* lp5 writeleveling */ - int mr20_value; /* lp5 rddqc */ -/* ============================= */ + int mr18_value; + int mr20_value; - -/* >>>>>>>>>> cbt part begin>>>>>>>>>> */ - /* - * 0: doesn't run cbt calibration - * 1: run cbt calibration - */ int cbt; - /* - * 0: rising phase - * 1: falling phase - */ + int cbt_phase; - /* - * 0: training mode1 - * 1: training mode2 - */ + int cbt_training_mode; - /* - * 0: normal mode - * 1: byte mode - */ + int rk0_cbt_mode; - /* - * 0: normal mode - * 1: byte mode - */ + int rk1_cbt_mode; - /* - * 0: cbt does NOT use autok - * 1: cbt use autok - */ + int cbt_autok; - /* - * autok respi - * 0/1/2/3 - */ + int cbt_atk_respi; - /* - * 0: cbt does NOT use new cbt mode - * 1: cbt use new cbt mode - */ + int new_cbt_mode; - /* - * cbt pat0~7v - */ + int pat_v[8]; - /* - * cbt pat0~7a - */ + int pat_a[8]; - /* - * cbt pat_dmv - */ + int pat_dmv; - /* - * cbt pat_dma - */ + int pat_dma; - /* - * cbt pat_cs - */ + int pat_cs; - /* - * new cbt cagolden sel - */ + int cagolden_sel; - /* - * new cbt invert num - */ + int invert_num; -/* ============================= */ -/* >>>>>>>>>> wl part begin>>>>>>>>>> */ - /* - * 0: doesn't run wl calibration - * 1: run wl calibration - */ int wl; - /* - * 0: wl does NOT use autok - * 1: wl use autok - */ + int wl_autok; - /* - * autok respi - * 0/1/2/3 - */ + int wl_atk_respi; -/* ============================= */ -/* >>>>>>>>>> Gating part begin >>>>>> */ - /* - * 0: does not run gating calibration - * 1: run gating calibration - */ int gating; - /* - * 0: SW mode calibration - * 1: HW AUTO calibration - */ + int gating_autok; int dqsien_autok_pi_offset; int dqsien_autok_early_break_en; int dqsien_autok_dbg_mode_en; -/* ============================= */ -/* >>>>>>>>>> RDDQC part begin >>>>>> */ - /* - * 0: does not run rddq calibration - * 1: run rddq calibration - */ int rddqc; int low_byte_invert_golden; @@ -269,42 +151,24 @@ typedef struct cal_sv_rand_args { int mr_dq_b_golden; int lp5_mr20_6_golden; int lp5_mr20_7_golden; -/* ============================= */ -/* >>>>>>>>>> TX perbit part begin >>>>>> */ - /* - * 0: does not run txperbit calibration - * 1: run txperbit calibration - */ int tx_perbit; - /* - * 0: does not run txperbit auto calibration - * 1: run txperbit auto calibration - */ + int tx_auto_cal; int tx_atk_pass_pi_thrd; int tx_atk_early_break; -/* ============================= */ -/* >>>>>>>>>> TX perbit part begin >>>>>> */ - /* - * 0: does not run rxperbit calibration - * 1: run rxperbit calibration - */ int rx_perbit; - /* - * 0: does not run rxperbit auto calibration - * 1: run rxperbit auto calibration - */ + int rx_auto_cal; int rx_atk_cal_step; int rx_atk_cal_out_dbg_en; int rx_atk_cal_out_dbg_sel; -/* ============================= */ + } cal_sv_rand_args_t; void set_psra(cal_sv_rand_args_t *psra); |