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authorRyan Chuang <ryan.chuang@mediatek.corp-partner.google.com>2021-09-23 20:35:22 +0800
committerHung-Te Lin <hungte@chromium.org>2021-09-29 06:57:06 +0000
commit98affb68f04d74eebd4ce98a64b21935caf63562 (patch)
tree99b2cfbb7d9e19d08e433df3e6d19ebb9a3a2ac5 /src/vendorcode/mediatek
parent9af3de12f6fafa6c0ea67bed33952fc9b43c2bcc (diff)
vc/mediatek/mt8195: Remove unused code
Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/mediatek')
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c10
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c139
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c31
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c287
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c1628
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c16
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c9194
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c160
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c1807
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c21
-rw-r--r--src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c245
-rw-r--r--src/vendorcode/mediatek/mt8195/include/dramc_actiming.h42
-rw-r--r--src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h3
13 files changed, 6 insertions, 13577 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c b/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
index 9cf8f93414..95581e9e81 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
@@ -839,16 +839,6 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7), 0xFFFFFFFF);
}
-#if 0
-void DVFS_config(DRAMC_CTX_T *p)
-{
- U8 DVFS_NO_QUEUE_FLASH = 0;
-
- //1. DVFS flow control
-
- //2. Relationship among groups -- Save & Restore
-}
-#endif
static void IO_Release(DRAMC_CTX_T *p)
{
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c b/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
index 7f7c2c82e7..1dfd9676b2 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
@@ -441,17 +441,6 @@ static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
RD_DBI_EN = LP4_temp.DBI_RD;
WR_DBI_EN = LP4_temp.DBI_WR;
}
-#if __LP5_COMBO__
- else
- {//TODO LPDDR5 and other dram type not ready
- LP5_DRAM_CONFIG_T LP5_temp;
- memset((void *)&LP5_temp, 0, sizeof(LP5_temp));
-
- LP5_DRAM_config(DFS(group_id),&LP5_temp);
- RD_DBI_EN = LP5_temp.DBI_RD;
- WR_DBI_EN = LP5_temp.DBI_WR;
- }
-#endif
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
@@ -504,134 +493,6 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
mcSHOW_DBG_MSG6(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id));
}
-#if __LP5_COMBO__
-void DIG_CONFG_SHU_LP5_WCK(DRAMC_CTX_T *p, int ch_id, int group_id)
-{
- U8 backup_ch_id = p->channel;
- u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
-
- U8 BYTEMODE_EN=0;//TODO
- U8 READ_DBI=0;
- U8 DVFSC_DIS=0;
- U8 WCK_offset_by_UI=0;
- U8 tWCKENL_WR=0;
- U8 tWCKPRE_WR_Static=0;
- U8 tWCKENL_RD_DBION=0;
- U8 tWCKENL_RD_DBIOFF=0;
- U8 tWCKPRE_RD_Static=0;
- U8 tWCKENL_FS=0;
- U8 tWCKPRE_FS_Static=0;
-
- U8 WCK_WR_MCK=0;
- U8 WCK_RD_MCK=0;
- U8 WCK_FS_MCK=0;
- U8 WCK_WR_UI=0;
- U8 WCK_RD_UI=0;
- U8 WCK_FS_UI=0;
-
- U8 irank = 0;
- U8 ui_ratio = 2;
- //write and FS
- if(DFS(group_id)->CKR==2) {
- if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
- else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =2;tWCKENL_FS =0;tWCKPRE_FS_Static =2;}
- else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
- else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
- else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =4;tWCKENL_FS =1;tWCKPRE_FS_Static =4;}
- else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
- } else if (DFS(group_id)->CKR==4){
- if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
- else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
- else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =1;tWCKPRE_FS_Static =1;}
- else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
- else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
- else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =2;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
- else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
- else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
- else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_WR =3;tWCKPRE_WR_Static =3;tWCKENL_FS =2;tWCKPRE_FS_Static =3;}
- else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
- else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
- else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
- } else {
- mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
- }
-
- //read
- if(DVFSC_DIS == 1)
- {
- if(DFS(group_id)->CKR==2) {
- if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =2;}
- else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?3:1;tWCKPRE_RD_Static =2;}
- else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:2;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =3;}
- else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =4;}
- else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:5;tWCKENL_RD_DBION =7;tWCKPRE_RD_Static =4;}
- } else if (DFS(group_id)->CKR==4){
- if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?2:1;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:1;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
- else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =2;}
- else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =2;}
- else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =BYTEMODE_EN?5:4;tWCKPRE_RD_Static =3;}
- else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?5:4;tWCKENL_RD_DBION =BYTEMODE_EN?6:5;tWCKPRE_RD_Static =3;}
- else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?6:5;tWCKENL_RD_DBION =BYTEMODE_EN?7:6;tWCKPRE_RD_Static =3;}
- else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?8:7;tWCKPRE_RD_Static =4;}
- else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?9:7;tWCKPRE_RD_Static =4;}
- else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?8:7;tWCKENL_RD_DBION =BYTEMODE_EN?10:8;tWCKPRE_RD_Static=4;}
- } else {
- mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
- }
-
- } else {
- if(DFS(group_id)->CKR==2) {
- if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:0;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
- else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =2;}
- } else if (DFS(group_id)->CKR==4){
- if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?1:0;tWCKENL_RD_DBION =1;tWCKPRE_RD_Static =1;}
- else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =1;}
- } else {
- mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
- }
- }
- //=====================================
- //Algrithm
- //=====================================
- WCK_offset_by_UI = (DFS(group_id)->DQ_P2S_RATIO==4) ? 0 :
- (DFS(group_id)->DQ_P2S_RATIO==8) ? ((DFS(group_id)->CKR==4) ? 1 : -5) :
- (DFS(group_id)->DQ_P2S_RATIO==16) ? -5 : 0;
-
- WCK_WR_UI = ((tWCKENL_WR + tWCKPRE_WR_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
- WCK_RD_UI = (((READ_DBI?tWCKENL_RD_DBION:tWCKENL_RD_DBIOFF) + tWCKPRE_RD_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
- WCK_FS_UI = ((tWCKENL_FS + tWCKPRE_FS_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
-
-
- //=====================================
- //setting
- //=====================================
- p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
-
- for(irank = RANK_0; irank < RANK_MAX; irank++)
- {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK), P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) \
- | P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_MCK), P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) \
- | P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_MCK), P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) \
- | P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI) , P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B0_UI ) \
- | P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B1_UI ));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_UI) , P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B0_UI ) \
- | P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B1_UI ));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_UI) , P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B0_UI ) \
- | P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B1_UI ));
- }
- vSetPHY2ChannelMapping(p, backup_ch_id);
- p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
-}
-#endif
//=================================================
//Jump ratio calculate and setting
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c b/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
index 0ddeaee8c9..98cd138125 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
@@ -278,37 +278,6 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
//[3733:6400] 4
//[400 :3733) 2
-#if __LP5_COMBO__
- else if (MEM_TYPE == LPDDR5)
- {
- #if SA_CONFIG_EN
- if(p->freq_sel==LP5_DDR4266)
- {
- (tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
- }
- else if(p->freq_sel==LP5_DDR5500)
- {
- (tr->DFS_GP[0])->data_rate = 5500; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
- }
- else
- {
- (tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 2;tr->DFS_GP[0]->DQSIEN_MODE = 1;
- }
- #else
- (tr->DFS_GP[0])->data_rate = 6400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 1;
- #endif
- (tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[1]->CKR = 2;tr->DFS_GP[1]->DQSIEN_MODE = 1;
- (tr->DFS_GP[2])->data_rate = 1600; (tr->DFS_GP[2])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[2]->CKR = 2;tr->DFS_GP[2]->DQSIEN_MODE = 1;
- (tr->DFS_GP[3])->data_rate = 4266; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[3]->CKR = 4;tr->DFS_GP[3]->DQSIEN_MODE = 1;
- (tr->DFS_GP[4])->data_rate = 3733; (tr->DFS_GP[4])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[4]->CKR = 4;tr->DFS_GP[4]->DQSIEN_MODE = 1;
- (tr->DFS_GP[5])->data_rate = 1600; (tr->DFS_GP[5])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[5]->CKR = 2;tr->DFS_GP[5]->DQSIEN_MODE = 1;
- (tr->DFS_GP[6])->data_rate = 1200; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[6]->CKR = 2;tr->DFS_GP[6]->DQSIEN_MODE = 1;
- (tr->DFS_GP[7])->data_rate = 800 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[7]->CKR = 2;tr->DFS_GP[7]->DQSIEN_MODE = 1;
- (tr->DFS_GP[8])->data_rate = 400 ; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[8]->CKR = 2;tr->DFS_GP[8]->DQSIEN_MODE = 1;
- (tr->DFS_GP[9])->data_rate = 5500; (tr->DFS_GP[9])->DQ_P2S_RATIO = 16; tr->DFS_GP[9]->CKR = 4;tr->DFS_GP[9]->DQSIEN_MODE = 1;
- LP5_DRAM_config(tr->DFS_GP[0],tr->lp5_init);
- }
-#endif
ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);
mcSHOW_DBG_MSG6(("=================================== \n"));
diff --git a/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c b/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
index e390052ec7..a537e87952 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
@@ -126,291 +126,4 @@ U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value)
return WL;
}
-#if __LP5_COMBO__
-U32 Get_RL_LP5_DVFSC_DIS( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
-{
- U32 RL=0;
-
- if(CKR == 2)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {RL = 6; break;}
- case 1 : {RL = 8; break;}
- case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 10 ) : 10); break;}
- case 3 : {RL = ((BYTE_MODE_EN == 1) ? ( 14 ) : ((DBI_EN == 1) ? 14 : 12 )); break;}
- case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ( 16 )); break;}
- case 5 : {RL = ((BYTE_MODE_EN == 1) ? ( 20 ) : ((DBI_EN == 1) ? 20 : 18 )); break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else if (CKR == 4)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {RL = 3; break;}
- case 1 : {RL = 4; break;}
- case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 6 : 5 ) : ( 5 )); break;}
- case 3 : {RL = ((BYTE_MODE_EN == 1) ? 7 : ((DBI_EN == 1) ? 7 : 6 )); break;}
- case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 9 : 8 ) : ( 8 )); break;}
- case 5 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 9 )); break;}
- case 6 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 11 ) : ((DBI_EN == 1) ? 11 : 10)); break;}
- case 7 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 13 ) : ((DBI_EN == 1) ? 13 : 12)); break;}
- case 8 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 15 : 14 ) : ((DBI_EN == 1) ? 14 : 13)); break;}
- case 9 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 17 : 16 ) : ((DBI_EN == 1) ? 16 : 15)); break;}
- case 10: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 19 : 17 ) : ((DBI_EN == 1) ? 17 : 16)); break;}
- case 11: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 20 : 18 ) : ((DBI_EN == 1) ? 18 : 17)); break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else
- {
- mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
- }
-
- mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
-
- return RL;
-}
-
-U32 Get_RL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
-{
- U32 RL=0;
-
- if(CKR == 2)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {RL = 6; break;}
- case 1 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 8 )); break;}
- case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 12 ) : 12); break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else if (CKR == 4)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {RL = 3; break;}
- case 1 : {RL = ((BYTE_MODE_EN == 1) ? 5 : ((DBI_EN == 1) ? 4 : 5 )); break;}
- case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 7 : 6 ) : 6); break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else
- {
- mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
- }
-
- mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
-
- return RL;
-}
-
-
-
-//LPDDR5 write Latency Version B not implemented --TODO
-U32 Get_WL_LP5_DVFSC_DIS( U8 MR_RL_field_value,U8 BYTE_MODE_EN,U8 CKR)
-{
- U32 WL=0;
-
- if(CKR == 2)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {WL = 4; break;}
- case 1 : {WL = 4; break;}
- case 2 : {WL = 6; break;}
- case 3 : {WL = 8; break;}
- case 4 : {WL = 8; break;}
- case 5 : {WL = 10; break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else if (CKR == 4)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {WL = 2; break;}
- case 1 : {WL = 2; break;}
- case 2 : {WL = 3; break;}
- case 3 : {WL = 4; break;}
- case 4 : {WL = 4; break;}
- case 5 : {WL = 5; break;}
- case 6 : {WL = 6; break;}
- case 7 : {WL = 6; break;}
- case 8 : {WL = 7; break;}
- case 9 : {WL = 8; break;}
- case 10: {WL = 9; break;}
- case 11: {WL = 9; break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else
- {
- mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
- }
-
- mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
-
- return WL;
-}
-
-//LPDDR5 write Latency Version B not implemented --TODO
-U32 Get_WL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 BYTE_MODE_EN,U8 CKR)
-{
- U32 WL=0;
-
- if(CKR == 2)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {WL = 4; break;}
- case 1 : {WL = 4; break;}
- case 2 : {WL = 6; break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else if (CKR == 4)
- {
- switch(MR_RL_field_value)
- {
- case 0 : {WL = 2; break;}
- case 1 : {WL = 2; break;}
- case 2 : {WL = 3; break;}
- default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
- }
- }
- else
- {
- mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
- }
-
- mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
-
- return WL;
-}
-
-//LP5 dram initial ModeRegister setting
-U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
-{
- U8 MR2_RLWL=0;
-
- if ((data_rate<=6400) && (data_rate > 6000)) {MR2_RLWL = 11 ;}
- else if ((data_rate<=6400) && (data_rate > 5500)) {MR2_RLWL = 10 ;}
- else if ((data_rate<=5500) && (data_rate > 4800)) {MR2_RLWL = 9 ;}
- else if ((data_rate<=4800) && (data_rate > 4266)) {MR2_RLWL = 8 ;}
- else if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
- else if ((data_rate<=3700) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
- else if ((data_rate<=3200) && (data_rate > 2400)) {MR2_RLWL = 5 ;}
- else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
- else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
- else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2 ;}
- else {mcSHOW_ERR_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;}
-
- mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
- return MR2_RLWL;
-}
-
-void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr)
-{
- tr->BYTE_MODE[0] = 0 ;
- tr->BYTE_MODE[1] = 0 ;
- tr->EX_ROW_EN[0] = 0 ;
- tr->EX_ROW_EN[1] = 0 ;
- tr->MR_WL = LP5_DRAM_INIT_RLWL_MRfield_config(dfs_tr->data_rate);
- tr->MR_RL = tr->MR_WL;
- tr->BL = 2;
- tr->CK_Mode = (dfs_tr->data_rate>=2133)?0:1; //0:diff 1:SE
- tr->RPST = 0;
- tr->RD_PRE = 0;
- tr->WR_PRE = 1;
- tr->WR_PST = (dfs_tr->data_rate>=3200)?1:0 ;
-#if SA_CONFIG_EN
- tr->DBI_WR = 0;
- #if LP5_DDR4266_RDBI_WORKAROUND
- tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
- #else
- tr->DBI_RD = 0;
- #endif
-#else
- tr->DBI_WR = (dfs_tr->data_rate>=3733)?1:0 ;
- tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
-#endif
- tr->DMI = 1;
- tr->OTF = 1;
- tr->WCK_PST = (dfs_tr->data_rate>=3733)?1:0 ;
- tr->RDQS_PST = 0;
- tr->CA_ODT = 0;
- tr->DQ_ODT = (dfs_tr->data_rate>=3733)?3:0 ;
- tr->CKR = (dfs_tr->CKR==4)?0:1;
- tr->WCK_ON = 0; //TODO
-#if SA_CONFIG_EN
- #if WCK_LEVELING_FM_WORKAROUND
- tr->WCK_FM = 0;
- #else
- tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
- #endif
-#else
- tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
-#endif
- tr->WCK_ODT = (dfs_tr->CKR==4)?3:0;
- tr->DVFSQ = (dfs_tr->data_rate>=3733)?0:1;
- tr->DVFSC = (dfs_tr->data_rate>=2133)?0:1;
- tr->RDQSmode[0] = EN_both;//TODO --RK0 have to EN_t if SE enable
- tr->RDQSmode[1] = EN_both;//TODO --RK1 have to EN_c if SE enable
- tr->WCKmode[0] = (dfs_tr->data_rate>=1600)?0:1;
- tr->WCKmode[1] = (dfs_tr->data_rate>=1600)?0:2;
- tr->RECC = 0;//TODO
- tr->WECC = 0;//TODO
- tr->BankMode = (dfs_tr->data_rate>=3733)?BG4BK4:BK16;
- tr->WORK_FSP = 0;//TODO
-
- switch (dfs_tr->DQSIEN_MODE)
- {
- case 1: {tr->RDQS_PRE = 0;break;}
- case 2: {tr->RDQS_PRE = 1;break;}
- case 3: {tr->RDQS_PRE = 3;break;}
- case 6: {tr->RDQS_PRE = 1;break;}
- case 7: {tr->RDQS_PRE = 3;break;}
- default : {mcSHOW_ERR_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);};
- }
-
- mcSHOW_DBG_MSG2(("=================================== \n"));
- mcSHOW_DBG_MSG2(("LPDDR5 DRAM CONFIGURATION\n" ));
- mcSHOW_DBG_MSG2(("=================================== \n"));
- mcSHOW_DBG_MSG2(("MR_WL = 0x%1x\n",tr->MR_WL ));
- mcSHOW_DBG_MSG2(("MR_RL = 0x%1x\n",tr->MR_RL ));
- mcSHOW_DBG_MSG2(("BL = 0x%1x\n",tr->BL ));
- mcSHOW_DBG_MSG2(("CK_Mode = 0x%1x\n",tr->CK_Mode ));
- mcSHOW_DBG_MSG2(("RPST = 0x%1x\n",tr->RPST ));
- mcSHOW_DBG_MSG2(("RD_PRE = 0x%1x\n",tr->RD_PRE ));
- mcSHOW_DBG_MSG2(("RDQS_PRE = 0x%1x\n",tr->RDQS_PRE ));
- mcSHOW_DBG_MSG2(("WR_PRE = 0x%1x\n",tr->WR_PRE ));
- mcSHOW_DBG_MSG2(("WR_PST = 0x%1x\n",tr->WR_PST ));
- mcSHOW_DBG_MSG2(("DBI_WR = 0x%1x\n",tr->DBI_WR ));
- mcSHOW_DBG_MSG2(("DBI_RD = 0x%1x\n",tr->DBI_RD ));
- mcSHOW_DBG_MSG2(("DMI = 0x%1x\n",tr->DMI ));
- mcSHOW_DBG_MSG2(("OTF = 0x%1x\n",tr->OTF ));
- mcSHOW_DBG_MSG2(("WCK_PST = 0x%1x\n",tr->WCK_PST ));
- mcSHOW_DBG_MSG2(("RDQS_PST = 0x%1x\n",tr->RDQS_PST ));
- mcSHOW_DBG_MSG2(("CA_ODT = 0x%1x\n",tr->CA_ODT ));
- mcSHOW_DBG_MSG2(("DQ_ODT = 0x%1x\n",tr->DQ_ODT ));
- mcSHOW_DBG_MSG2(("CKR = 0x%1x\n",tr->CKR ));
- mcSHOW_DBG_MSG2(("WCK_ON = 0x%1x\n",tr->WCK_ON ));
- mcSHOW_DBG_MSG2(("WCK_FM = 0x%1x\n",tr->WCK_FM ));
- mcSHOW_DBG_MSG2(("WCK_ODT = 0x%1x\n",tr->WCK_ODT ));
- mcSHOW_DBG_MSG2(("DVFSQ = 0x%1x\n",tr->DVFSQ ));
- mcSHOW_DBG_MSG2(("DVFSC = 0x%1x\n",tr->DVFSC ));
- mcSHOW_DBG_MSG2(("RDQSmode[0] = 0x%1x\n",tr->RDQSmode[0] ));
- mcSHOW_DBG_MSG2(("RDQSmode[1] = 0x%1x\n",tr->RDQSmode[1] ));
- mcSHOW_DBG_MSG2(("WCKmode[0] = 0x%1x\n",tr->WCKmode[0] ));
- mcSHOW_DBG_MSG2(("WCKmode[1] = 0x%1x\n",tr->WCKmode[1] ));
- mcSHOW_DBG_MSG2(("RECC = 0x%1x\n",tr->RECC ));
- mcSHOW_DBG_MSG2(("WECC = 0x%1x\n",tr->WECC ));
- mcSHOW_DBG_MSG2(("BankMode = 0x%1x\n",tr->BankMode ));
- mcSHOW_DBG_MSG2(("WORK_FSP = 0x%1x\n",tr->WORK_FSP ));
- mcSHOW_DBG_MSG2(("=================================== \n"));
-}
-#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
index 7e83c16cf2..5ab06f5f75 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
@@ -28,41 +28,12 @@ static U8 u1GetACTimingIdx(DRAMC_CTX_T *p)
U8 u1TimingIdx = 0xff, u1TmpIdx;
U8 u1TmpDramType = p->dram_type;
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- u1TmpDramType = TYPE_LPDDR5;
- }
- else
-#endif
{
// LP4/LP4P/LP4X use same table
if (u1TmpDramType == TYPE_LPDDR4X || u1TmpDramType == TYPE_LPDDR4P)
u1TmpDramType = TYPE_LPDDR4;
}
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP5; u1TmpIdx++)
- {
- if ((ACTimingTbl_LP5[u1TmpIdx].dramType == u1TmpDramType) &&
- /* p->frequency may not be in ACTimingTable, use p->freqGroup */
- (ACTimingTbl_LP5[u1TmpIdx].freq == p->freqGroup) &&
- (ACTimingTbl_LP5[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) &&
- (ACTimingTbl_LP5[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode
- (ACTimingTbl_LP5[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming
- )
- {
- u1TimingIdx = u1TmpIdx;
- //Also for Dump_REG
- mcSHOW_DBG_MSG2(("match AC timing %d\n", u1TimingIdx));
- break;
- }
- }
- }
- else
-#endif
{
for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP4; u1TmpIdx++)
{
@@ -235,354 +206,6 @@ static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p)
* @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
*/
//-------------------------------------------------------------------------
-#if __LP5_COMBO__
-static DRAM_STATUS_T DdrUpdateACTimingReg_LP5(DRAMC_CTX_T *p, const ACTime_T_LP5 *ACTbl)
-{
- ACTime_T_LP5 ACTblFinal;
- U8 backup_rank = p->rank;
- DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming)
- // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value
- // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field
-#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
- U8 u1RANKINCTL = 0;
-#endif
- U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values
-
-#if SAMSUNG_LP4_NWR_WORKAROUND
- U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0;
-#endif
- // ACTiming regs that aren't currently in ACTime_T struct
- U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF)
- U8 u1TFAW_05T=0, u1TRRD_05T=0;
- U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0;
- U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0;
-
-#if XRTRTR_NEW_CROSS_RK_MODE
- U16 u2PHSINCTL = 0;
-#endif
-
- U32 u4RankINCTL_ROOT;
-
- if(ACTbl == NULL)
- return DRAM_FAIL;
- ACTblFinal = *ACTbl;
-
- u4Datlat = ACTblFinal.datlat;
-
- // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios--------------------------
-#if ENABLE_TX_WDQS
- r2w_odt_onoff = ODT_ON;
-#else
- r2w_odt_onoff = p->odt_onoff;
-#endif
-
- // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable
- if (r2w_odt_onoff == ODT_ON) //odt_on
- {
- u2TRTW = ACTblFinal.tr2w_odt_on;
- u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T;
- u2XRTW2R = ACTblFinal.xrtw2r_odt_on_otf_off;
- u2XRTR2W = ACTblFinal.xrtr2w_odt_on;
- }
- else //odt_off
- {
- u2TRTW = ACTblFinal.tr2w_odt_off;
- u2TRTW_05T = ACTblFinal.tr2w_odt_off_05T;
- u2XRTW2R = ACTblFinal.xrtw2r_odt_off_otf_off;
- u2XRTR2W = ACTblFinal.xrtr2w_odt_off;
- }
-
- // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW)
- if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY)
- {
- u2TRTW = ACTblFinal.tr2w_odt_on;
- u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T;
- }
-
- if (r2w_odt_onoff == ODT_ON)
- {
- u2XTRTRT = ACTblFinal.xrtr2r_odt_on;
- u2XRTWTW = ACTblFinal.xrtw2w_odt_on;
- }
- else
- {
- u2XTRTRT = ACTblFinal.xrtr2r_odt_off;
- u2XRTWTW = ACTblFinal.xrtw2w_odt_off;
- }
-
-#if ENABLE_RODT_TRACKING_SAVE_MCK
- // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN)
- u1ODT_ON = p->odt_onoff;
- u1RODT_TRACK = ENABLE_RODT_TRACKING;
- u1ROEN = u1WDQS_ON | u1ODT_ON;
- u1ModeSel = u1RODT_TRACK & u1ROEN;
-
- // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting
- // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team)
- //if (u1RODT_TRACK && (u1ROEN==1))
- // RODT_TRACKING_SAVEING_MCK = 1;
-#endif
-
-#if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN))
- /* yr: same code
- // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided
- if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK
- else RODT_TRACKING_SAVEING_MCK = 0;
- */
- RODT_TRACKING_SAVEING_MCK = 0;
-#endif
-
- // Update values that are used by RODT_TRACKING_SAVEING_MCK
- u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK;
- u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK;
-
-#if SAMSUNG_LP4_NWR_WORKAROUND
- // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung DRAM internal IO precharge time
- if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency == 800)) //LP4X, Samsung, DDR1600
- {
- u1TWTR_TMP = (ACTblFinal.twtr * 4 - ACTblFinal.twtr_05T * 2) + 2; //Convert TWTR to tCK, and add 2tCK
- if ((u1TWTR_TMP % 4) == 0) //TWTR can be transferred to TWTR directly
- {
- u1TWTR = u1TWTR_TMP >> 2;
- u1TWTR_05T = 0;
- }
- else //Can't be transfered to TWTR directly
- {
- u1TWTR = (u1TWTR_TMP + 2) >> 2; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T)
- u1TWTR_05T = 1; //05T means minus 2tCK
- }
-
- ACTblFinal.twtr = u1TWTR;
- ACTblFinal.twtr_05T = u1TWTR_05T;
- }
-#endif
-
- //DATLAT related
- if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
- u1DATLAT_DSEL = u4Datlat;
- else
- u1DATLAT_DSEL = u4Datlat - 1;
-
-#if TX_OE_EXTEND
- u2XRTWTW += 1;
- u2XRTW2R += 1;
-#endif
-
-#if 0//(!CMD_CKE_WORKAROUND_FIX)
- U8 u1Txp = 0, u1Txp0p5 = 0;
-
- if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)))
- {
- u1Txp = 1;
- }
- else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600))))
- {
- u1Txp = 2;
- }
-
- if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200)))
- {
- u1Txp0p5 = 1;
- }
-
- ACTblFinal.txp = u1Txp;
- ACTblFinal.txp_05T = u1Txp0p5;
- ACTblFinal.ckelckcnt = 4;
- ACTblFinal.earlyckecnt = 0;
- ACTblFinal.ckeprd -= 1;
-#endif
-
- // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)-------
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS)
- | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP)
- | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB)
- | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL)
- | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC));
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC)
- | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR)
- | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB));
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP)
- | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI)
- | P_Fld(ACTblFinal.tfaw, SHU_ACTIM2_TFAW)
- | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW
- | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP));
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD)
- | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR)
- | P_Fld(ACTblFinal.trrd, SHU_ACTIM0_TRRD));
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR)
- | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD)
- | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT));
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW)
- | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW)
- | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD)
- | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2)
- | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW));
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW)
- | P_Fld(ACTblFinal.tmrr2w, SHU_ACTIM4_TMRR2W)
- | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS)
- | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT));
-
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD);
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W)
- | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R)
- | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W)
- | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R));
-
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
-// vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)
-// | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP));
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP);
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP);
-
- // AC timing 0.5T
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T)
- | P_Fld(ACTblFinal.twtr_l_05T, SHU_AC_TIME_05T_BGTWTR_M05T)
- | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW
- | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T)
- | P_Fld(ACTblFinal.tfaw_05T, SHU_AC_TIME_05T_TFAW_05T)
- | P_Fld(ACTblFinal.trrd_05T, SHU_AC_TIME_05T_TRRD_05T)
- | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T)
- | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T)
- | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T)
- | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T)
- | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T)
- | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T)
- | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T)
- | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T)
- | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T)
- | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T)
- | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T)
- | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T)
- | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T)
- | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T)
- | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T)
- | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T)
- | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T)
- | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T)
- | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T));
-
- {
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr_l, SHU_ACTIM0_TWTR_L);
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM7, P_Fld(ACTblFinal.tcsh_cscal, SHU_ACTIM7_TCSH_CSCAL)
- | P_Fld(ACTblFinal.tcacsh, SHU_ACTIM7_TCACSH));
- }
- {
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR);
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE)
- | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX)
- | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T)
- | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T));
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_WCKCTRL, P_Fld(ACTblFinal.wckrdoff, SHU_WCKCTRL_WCKRDOFF)
- | P_Fld(ACTblFinal.wckrdoff_05T, SHU_WCKCTRL_WCKRDOFF_05T)
- | P_Fld(ACTblFinal.wckwroff, SHU_WCKCTRL_WCKWROFF)
- | P_Fld(ACTblFinal.wckwroff_05T, SHU_WCKCTRL_WCKWROFF_05T));
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD);
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T);
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_LP5_CMD, ACTblFinal.tcsh, SHU_LP5_CMD_TCSH);
- }
-
-#if AC_TIMING_DERATE_ENABLE
- if (u1IsLP4Family(p->dram_type))
- {
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE)
- | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE));
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE)
- | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE)
- | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE)
- | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE));
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_05T_derate, SHU_AC_DERATING_05T_TRRD_05T_DERATE)
- | P_Fld(ACTblFinal.tras_05T_derate, SHU_AC_DERATING_05T_TRAS_05T_DERATE)
- | P_Fld(ACTblFinal.trpab_05T_derate, SHU_AC_DERATING_05T_TRPAB_05T_DERATE)
- | P_Fld(ACTblFinal.trp_05T_derate, SHU_AC_DERATING_05T_TRP_05T_DERATE)
- | P_Fld(ACTblFinal.trcd_05T_derate, SHU_AC_DERATING_05T_TRCD_05T_DERATE)
- | P_Fld(ACTblFinal.trc_05T_derate, SHU_AC_DERATING_05T_TRC_05T_DERATE));
- vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN);
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing
- }
-#endif
-
- // DQSINCTL related
- vSetRank(p, RANK_0);
- vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL
- vSetRank(p, RANK_1);
- vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL
- vSetRank(p, backup_rank);
- vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT);
-
- if (ACTblFinal.dqsinctl >= 2)
- {
- u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2;
- }
- else
- {
- mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
- u4RankINCTL_ROOT = 0;
- }
-
- vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY)
- | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1)
- | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL));
-
-#if XRTRTR_NEW_CROSS_RK_MODE
- u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1);
- vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL);
-#endif
-
- // DATLAT related, tREFBW
- vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(u4Datlat, MISC_SHU_RDAT_DATLAT)
- | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL)
- | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
-
- vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR);
-
- // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------
-#ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
- //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1
- //XRTR2R setting will be updated in RxdqsGatingPostProcess
- u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL);
- vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY);
-#endif
-
- //Update releated RG of XRTW2W
- if (p->frequency <= 800)
- {
- if (vGet_Div_Mode(p) == DIV4_MODE)
- {
- u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2;
- }
- else
- {
- u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1;
- }
- }
- else
- {
- u1ROOT = (p->frequency == 1866)? 1: 0;
- u1TXRANKINCTL = 1; u1TXDLY = 2;
- }
- #if TX_OE_EXTEND
- if (p->frequency >= 1333)
- {
- u1TXRANKINCTL += 1;
- u1TXDLY += 1;
- }
- #endif
-
- vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
- | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
- | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
-
- return DRAM_OK;
-}
-#endif
#if ENABLE_WDQS_MODE_2
static void WDQSMode2AcTimingEnlarge(DRAMC_CTX_T *p, U16 *u2_XRTW2W, U16 *u2_XRTR2W, U16 *u2_XRTW2R, U16 *u2_TRTW)
@@ -1035,128 +658,12 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p)
}
//Set ACTiming registers
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- DdrUpdateACTimingReg_LP5(p, &ACTimingTbl_LP5[u1TimingIdx]);
- }
- else
-#endif
{
DdrUpdateACTimingReg_LP4(p, &ACTimingTbl_LP4[u1TimingIdx]);
}
return DRAM_OK;
}
-#if 0
-#if ((!SW_CHANGE_FOR_SIMULATION) && (!FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0) && (!__ETT__))
-DRAM_STATUS_T DdrUpdateACTiming_EMI(DRAMC_CTX_T *p, AC_TIMING_EXTERNAL_T *ACRegFromEmi)
-{
- U8 u1TimingIdx = 0;
- #if (__LP5_COMBO__ == TRUE)
- ACTime_T_LP5 ACTime_LP5;
- #endif
- ACTime_T_LP4 ACTime_LP4;
- mcSHOW_DBG_MSG3(("[DdrUpdateACTiming_EMI]\n"));
-
- if (ACRegFromEmi == NULL)
- return DRAM_FAIL;
-
- //Retrieve ACTimingTable's corresponding index
- u1TimingIdx = u1GetACTimingIdx(p);
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- ACTime_LP5 = ACTimingTbl_LP5[u1TimingIdx];
- }
-#endif
- ACTime_LP4 = ACTimingTbl_LP4[u1TimingIdx];
-
- //Overwrite AC timing from emi settings
- ACTime.dramType = p->dram_type;
-#if 1 // Will use MDL ac timing, Others from internal ac timing
- ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP;
- ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB;
- ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC;
- ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD;
-
- ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T;
- ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T;
- ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T;
- ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T;
-#else
- ACTime.freq = ACRegFromEmi->AC_TIME_EMI_FREQUENCY;
- ACTime.tras = ACRegFromEmi->AC_TIME_EMI_TRAS;
- ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP;
-
- ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB;
- ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC;
- ACTime.trfc = ACRegFromEmi->AC_TIME_EMI_TRFC;
- ACTime.trfcpb = ACRegFromEmi->AC_TIME_EMI_TRFCPB;
-
- ACTime.txp = ACRegFromEmi->AC_TIME_EMI_TXP;
- ACTime.trtp = ACRegFromEmi->AC_TIME_EMI_TRTP;
- ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD;
- ACTime.twr = ACRegFromEmi->AC_TIME_EMI_TWR;
-
- ACTime.twtr = ACRegFromEmi->AC_TIME_EMI_TWTR;
- ACTime.trrd = ACRegFromEmi->AC_TIME_EMI_TRRD;
- ACTime.tfaw = ACRegFromEmi->AC_TIME_EMI_TFAW;
- ACTime.trtw_ODT_off = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF;
- ACTime.trtw_ODT_on = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON;
-
- ACTime.refcnt = ACRegFromEmi->AC_TIME_EMI_REFCNT; //(REFFRERUN = 0)
- ACTime.refcnt_fr_clk = ACRegFromEmi->AC_TIME_EMI_REFCNT_FR_CLK; //(REFFRERUN = 1)
- ACTime.txrefcnt = ACRegFromEmi->AC_TIME_EMI_TXREFCNT;
- ACTime.tzqcs = ACRegFromEmi->AC_TIME_EMI_TZQCS;
-
- ACTime.trtpd = ACRegFromEmi->AC_TIME_EMI_TRTPD;
- ACTime.twtpd = ACRegFromEmi->AC_TIME_EMI_TWTPD;
- ACTime.tmrr2w_ODT_off = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_OFF;
- ACTime.tmrr2w_ODT_on = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_ON;
-
- ACTime.tras_05T = ACRegFromEmi->AC_TIME_EMI_TRAS_05T;
- ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T;
- ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T;
- ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T;
- ACTime.trfc_05T = ACRegFromEmi->AC_TIME_EMI_TRFC_05T;
- ACTime.trfcpb_05T = ACRegFromEmi->AC_TIME_EMI_TRFCPB_05T;
- ACTime.txp_05T = ACRegFromEmi->AC_TIME_EMI_TXP_05T;
- ACTime.trtp_05T = ACRegFromEmi->AC_TIME_EMI_TRTP_05T;
- ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T;
- ACTime.twr_05T = ACRegFromEmi->AC_TIME_EMI_TWR_05T;
- ACTime.twtr_05T = ACRegFromEmi->AC_TIME_EMI_TWTR_05T;
- ACTime.trrd_05T = ACRegFromEmi->AC_TIME_EMI_TRRD_05T;
- ACTime.tfaw_05T = ACRegFromEmi->AC_TIME_EMI_TFAW_05T;
- ACTime.trtw_ODT_off_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF_05T;
- ACTime.trtw_ODT_on_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON_05T;
- ACTime.trtpd_05T = ACRegFromEmi->AC_TIME_EMI_TRTPD_05T;
- ACTime.twtpd_05T = ACRegFromEmi->AC_TIME_EMI_TWTPD_05T;
-#endif
-
- //Set ACTiming registers
- DdrUpdateACTimingReg(p, &ACTime);
-
- return DRAM_OK;
-}
-#endif
-#endif
-///TODO: wait for porting +++
-#if __A60868_TO_BE_PORTING__
-
-U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p)
-{
- U8 u1TimingIdx = u1GetACTimingIdx(p);
-#if (__LP5_COMBO__ == TRUE)
- ACTime_T_LP5 ACTime = ACTimingTbl_LP5[u1TimingIdx];
-#else
- ACTime_T_LP4 ACTime = ACTimingTbl_LP4[u1TimingIdx];
-#endif
-
- return ACTime.datlat;
-}
-#endif // __A60868_TO_BE_PORTING__
-///TODO: wait for porting +++
/* Optimize all-bank refresh parameters (by density) for LP4 */
void vDramcACTimingOptimize(DRAMC_CTX_T *p)
@@ -3787,1138 +3294,3 @@ static const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = {
#endif
};
-#if (__LP5_COMBO__)
- static const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5] = {
- //----------LPDDR5---------------------------
- #if SUPPORT_LP5_DDR6400_ACTIM
- //LP5_DDR6400 ACTiming---------------------------------
- #if (ENABLE_READ_DBI == 1)
- //LPDDR5_6400_Div 16_DBI1.csv Read 1
- {
- .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
-
- //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
- .readLat = 20, .writeLat = 9, .DivMode = DIV16_MODE,
-
- .tras = 8, .tras_05T = 0,
- .trp = 7, .trp_05T = 1,
- .trpab = 8, .trpab_05T = 1,
- .trc = 16, .trc_05T = 1,
- .trfc = 100, .trfc_05T = 0,
- .trfcpb = 44, .trfcpb_05T = 0,
- .txp = 2, .txp_05T = 1,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 7, .trcd_05T = 1,
- .twr = 19, .twr_05T = 0,
- .twtr = 6, .twtr_05T = 0,
- .twtr_l = 10, .twtr_l_05T = 0,
- .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 15, .tr2mrw_05T = 0,
- .tw2mrw = 8, .tw2mrw_05T = 1,
- .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
- .tmrw = 4, .tmrw_05T = 0,
- .tmrd = 6, .tmrd_05T = 1,
- .tmrwckel = 8, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 12, .tmrri_05T = 0,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 5, .tr2w_odt_off_05T = 1,
- .tr2w_odt_on = 7, .tr2w_odt_on_05T = 0,
- .txrefcnt = 115,
- .wckrdoff = 13, .wckrdoff_05T = 0,
- .wckwroff = 7, .wckwroff_05T = 1,
- .tzqcs = 34,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 8,
- .xrtr2w_odt_on = 9,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 3,
- .xrtw2r_odt_on_wck = 4,
- .xrtr2w_odt_off_wck = 11,
- .xrtr2w_odt_on_wck = 11,
- .xrtr2r_wck = 8,
- .tr2mrr = 4,
- .hwset_mr2_op = 187,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 176,
- .vrcgdis_prdcnt = 40,
- .lp5_cmd1to2en = 0,
- .trtpd = 13, .trtpd_05T = 1,
- .twtpd = 21, .twtpd_05T = 1,
- .tmrr2w = 16,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 8, .trcd_derate_05T = 0,
- .trc_derate = 17, .trc_derate_05T = 0,
- .tras_derate = 10, .tras_derate_05T = 0,
- .trpab_derate = 7, .trpab_derate_05T = 1,
- .trp_derate = 6, .trp_derate_05T = 0,
- .trrd_derate = 2, .trrd_derate_05T = 0,
- .zqlat2 = 12,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 7, .datlat = 10
- },
- //LPDDR5_6400_BT_Div 16_DBI1.csv Read 1
- {
- .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
- //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
- .readLat = 18, .writeLat = 9, .DivMode = DIV16_MODE,
-
- .tras = 8, .tras_05T = 0,
- .trp = 7, .trp_05T = 1,
- .trpab = 8, .trpab_05T = 1,
- .trc = 16, .trc_05T = 1,
- .trfc = 100, .trfc_05T = 0,
- .trfcpb = 44, .trfcpb_05T = 0,
- .txp = 2, .txp_05T = 1,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 7, .trcd_05T = 1,
- .twr = 18, .twr_05T = 1,
- .twtr = 5, .twtr_05T = 0,
- .twtr_l = 9, .twtr_l_05T = 0,
- .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 14, .tr2mrw_05T = 0,
- .tw2mrw = 8, .tw2mrw_05T = 1,
- .tmrr2mrw = 12, .tmrr2mrw_05T = 0,
- .tmrw = 4, .tmrw_05T = 0,
- .tmrd = 6, .tmrd_05T = 1,
- .tmrwckel = 8, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 12, .tmrri_05T = 0,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1,
- .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
- .txrefcnt = 115,
- .wckrdoff = 12, .wckrdoff_05T = 0,
- .wckwroff = 7, .wckwroff_05T = 1,
- .tzqcs = 34,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 7,
- .xrtr2w_odt_on = 8,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 4,
- .xrtw2r_odt_on_wck = 5,
- .xrtr2w_odt_off_wck = 10,
- .xrtr2w_odt_on_wck = 10,
- .xrtr2r_wck = 8,
- .tr2mrr = 3,
- .hwset_mr2_op = 187,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 176,
- .vrcgdis_prdcnt = 40,
- .lp5_cmd1to2en = 0,
- .trtpd = 12, .trtpd_05T = 1,
- .twtpd = 21, .twtpd_05T = 0,
- .tmrr2w = 15,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 8, .trcd_derate_05T = 0,
- .trc_derate = 17, .trc_derate_05T = 0,
- .tras_derate = 10, .tras_derate_05T = 0,
- .trpab_derate = 7, .trpab_derate_05T = 1,
- .trp_derate = 6, .trp_derate_05T = 0,
- .trrd_derate = 2, .trrd_derate_05T = 0,
- .zqlat2 = 12,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 7, .datlat = 10
- },
- #else //ENABLE_READ_DBI == 0)
- //LPDDR5_6400_Div 16_DBI0.csv Read 0
- {
- .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
- .readLat = 18, .writeLat = 9, .DivMode = DIV16_MODE,
-
- .tras = 8, .tras_05T = 0,
- .trp = 7, .trp_05T = 1,
- .trpab = 8, .trpab_05T = 1,
- .trc = 16, .trc_05T = 1,
- .trfc = 100, .trfc_05T = 0,
- .trfcpb = 44, .trfcpb_05T = 0,
- .txp = 2, .txp_05T = 1,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 7, .trcd_05T = 1,
- .twr = 19, .twr_05T = 0,
- .twtr = 6, .twtr_05T = 0,
- .twtr_l = 10, .twtr_l_05T = 0,
- .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 14, .tr2mrw_05T = 0,
- .tw2mrw = 8, .tw2mrw_05T = 1,
- .tmrr2mrw = 12, .tmrr2mrw_05T = 0,
- .tmrw = 4, .tmrw_05T = 0,
- .tmrd = 6, .tmrd_05T = 1,
- .tmrwckel = 8, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 12, .tmrri_05T = 0,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1,
- .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
- .txrefcnt = 115,
- .wckrdoff = 12, .wckrdoff_05T = 0,
- .wckwroff = 7, .wckwroff_05T = 1,
- .tzqcs = 34,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 7,
- .xrtr2w_odt_on = 8,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 4,
- .xrtw2r_odt_on_wck = 5,
- .xrtr2w_odt_off_wck = 10,
- .xrtr2w_odt_on_wck = 10,
- .xrtr2r_wck = 8,
- .tr2mrr = 3,
- .hwset_mr2_op = 187,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 176,
- .vrcgdis_prdcnt = 40,
- .lp5_cmd1to2en = 0,
- .trtpd = 12, .trtpd_05T = 1,
- .twtpd = 21, .twtpd_05T = 1,
- .tmrr2w = 15,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 8, .trcd_derate_05T = 0,
- .trc_derate = 17, .trc_derate_05T = 0,
- .tras_derate = 10, .tras_derate_05T = 0,
- .trpab_derate = 7, .trpab_derate_05T = 1,
- .trp_derate = 6, .trp_derate_05T = 0,
- .trrd_derate = 2, .trrd_derate_05T = 0,
- .zqlat2 = 12,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 7, .datlat = 10
- },
- //LPDDR5_6400_BT_Div 16_DBI0.csv Read 0
- {
- .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
- .readLat = 17, .writeLat = 9, .DivMode = DIV16_MODE,
-
- .tras = 8, .tras_05T = 0,
- .trp = 7, .trp_05T = 1,
- .trpab = 8, .trpab_05T = 1,
- .trc = 16, .trc_05T = 1,
- .trfc = 100, .trfc_05T = 0,
- .trfcpb = 44, .trfcpb_05T = 0,
- .txp = 2, .txp_05T = 1,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 7, .trcd_05T = 1,
- .twr = 18, .twr_05T = 1,
- .twtr = 5, .twtr_05T = 0,
- .twtr_l = 9, .twtr_l_05T = 0,
- .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 13, .tr2mrw_05T = 1,
- .tw2mrw = 8, .tw2mrw_05T = 1,
- .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
- .tmrw = 4, .tmrw_05T = 0,
- .tmrd = 6, .tmrd_05T = 1,
- .tmrwckel = 8, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 12, .tmrri_05T = 0,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1,
- .txrefcnt = 115,
- .wckrdoff = 11, .wckrdoff_05T = 1,
- .wckwroff = 7, .wckwroff_05T = 1,
- .tzqcs = 34,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 7,
- .xrtr2w_odt_on = 7,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 4,
- .xrtw2r_odt_on_wck = 5,
- .xrtr2w_odt_off_wck = 10,
- .xrtr2w_odt_on_wck = 10,
- .xrtr2r_wck = 8,
- .tr2mrr = 2,
- .hwset_mr2_op = 187,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 176,
- .vrcgdis_prdcnt = 40,
- .lp5_cmd1to2en = 0,
- .trtpd = 12, .trtpd_05T = 0,
- .twtpd = 21, .twtpd_05T = 0,
- .tmrr2w = 15,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 8, .trcd_derate_05T = 0,
- .trc_derate = 17, .trc_derate_05T = 0,
- .tras_derate = 10, .tras_derate_05T = 0,
- .trpab_derate = 7, .trpab_derate_05T = 1,
- .trp_derate = 6, .trp_derate_05T = 0,
- .trrd_derate = 2, .trrd_derate_05T = 0,
- .zqlat2 = 12,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 7, .datlat = 10
- },
- #endif
- #endif
- #if SUPPORT_LP5_DDR5500_ACTIM
- //LP5_DDR5500 ACTiming---------------------------------
- #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1))
- //F5500_Div16_DB1_NT0_RG0_EC0.csv Read 1
- {
- .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
-
- //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
- .readLat = 17, .writeLat = 8, .DivMode = DIV16_MODE,
-
- .tras = 5, .tras_05T = 1,
- .trp = 6, .trp_05T = 1,
- .trpab = 7, .trpab_05T = 1,
- .trc = 13, .trc_05T = 0,
- .trfc = 84, .trfc_05T = 1,
- .trfcpb = 36, .trfcpb_05T = 1,
- .txp = 2, .txp_05T = 0,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 6, .trcd_05T = 1,
- .twr = 16, .twr_05T = 1,
- .twtr = 5, .twtr_05T = 0,
- .twtr_l = 8, .twtr_l_05T = 1,
- .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 13, .tr2mrw_05T = 1,
- .tw2mrw = 8, .tw2mrw_05T = 0,
- .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
- .tmrw = 3, .tmrw_05T = 1,
- .tmrd = 5, .tmrd_05T = 1,
- .tmrwckel = 7, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 10, .tmrri_05T = 1,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1,
- .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
- .txrefcnt = 99,
- .wckrdoff = 11, .wckrdoff_05T = 1,
- .wckwroff = 7, .wckwroff_05T = 0,
- .tzqcs = 29,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 7,
- .xrtr2w_odt_on = 8,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 3,
- .xrtw2r_odt_on_wck = 4,
- .xrtr2w_odt_off_wck = 10,
- .xrtr2w_odt_on_wck = 10,
- .xrtr2r_wck = 8,
- .tr2mrr = 2,
- .hwset_mr2_op = 153,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 144,
- .vrcgdis_prdcnt = 35,
- .lp5_cmd1to2en = 0,
- .trtpd = 12, .trtpd_05T = 0,
- .twtpd = 19, .twtpd_05T = 0,
- .tmrr2w = 15,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 7, .trcd_derate_05T = 0,
- .trc_derate = 13, .trc_derate_05T = 1,
- .tras_derate = 7, .tras_derate_05T = 0,
- .trpab_derate = 6, .trpab_derate_05T = 0,
- .trp_derate = 5, .trp_derate_05T = 0,
- .trrd_derate = 1, .trrd_derate_05T = 1,
- .zqlat2 = 11,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 6, .datlat = 19
- },
- //LPDDR5_DDR5500_Div 16_RDBI_ON_CBT_NORMAL_MODE
- {
- .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
- //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
- .readLat = 16, .writeLat = 8, .DivMode = DIV16_MODE,
-
- .tras = 5, .tras_05T = 1,
- .trp = 6, .trp_05T = 1,
- .trpab = 7, .trpab_05T = 1,
- .trc = 13, .trc_05T = 0,
- .trfc = 84, .trfc_05T = 1,
- .trfcpb = 36, .trfcpb_05T = 1,
- .txp = 2, .txp_05T = 0,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 6, .trcd_05T = 1,
- .twr = 16, .twr_05T = 0,
- .twtr = 4, .twtr_05T = 1,
- .twtr_l = 8, .twtr_l_05T = 0,
- .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 13, .tr2mrw_05T = 0,
- .tw2mrw = 8, .tw2mrw_05T = 0,
- .tmrr2mrw = 11, .tmrr2mrw_05T = 0,
- .tmrw = 3, .tmrw_05T = 1,
- .tmrd = 5, .tmrd_05T = 1,
- .tmrwckel = 7, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 10, .tmrri_05T = 1,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1,
- .txrefcnt = 99,
- .wckrdoff = 11, .wckrdoff_05T = 0,
- .wckwroff = 7, .wckwroff_05T = 0,
- .tzqcs = 29,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 7,
- .xrtr2w_odt_on = 7,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 4,
- .xrtw2r_odt_on_wck = 5,
- .xrtr2w_odt_off_wck = 10,
- .xrtr2w_odt_on_wck = 10,
- .xrtr2r_wck = 8,
- .tr2mrr = 2,
- .hwset_mr2_op = 153,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 144,
- .vrcgdis_prdcnt = 35,
- .lp5_cmd1to2en = 0,
- .trtpd = 11, .trtpd_05T = 1,
- .twtpd = 18, .twtpd_05T = 1,
- .tmrr2w = 14,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 7, .trcd_derate_05T = 0,
- .trc_derate = 13, .trc_derate_05T = 1,
- .tras_derate = 7, .tras_derate_05T = 0,
- .trpab_derate = 6, .trpab_derate_05T = 0,
- .trp_derate = 5, .trp_derate_05T = 0,
- .trrd_derate = 1, .trrd_derate_05T = 1,
- .zqlat2 = 11,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 6, .datlat = 19
- },
- #else //ENABLE_READ_DBI == 0
- //LPDDR5_DDR5500_Div 16_RDBI_OFF_CBT_BYTE_MODE1
- {
- .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
- .readLat = 16, .writeLat = 8, .DivMode = DIV16_MODE,
-
- .tras = 5, .tras_05T = 1,
- .trp = 6, .trp_05T = 1,
- .trpab = 7, .trpab_05T = 1,
- .trc = 13, .trc_05T = 0,
- .trfc = 84, .trfc_05T = 1,
- .trfcpb = 36, .trfcpb_05T = 1,
- .txp = 2, .txp_05T = 0,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 6, .trcd_05T = 1,
- .twr = 16, .twr_05T = 1,
- .twtr = 5, .twtr_05T = 0,
- .twtr_l = 8, .twtr_l_05T = 1,
- .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 13, .tr2mrw_05T = 0,
- .tw2mrw = 8, .tw2mrw_05T = 0,
- .tmrr2mrw = 11, .tmrr2mrw_05T = 0,
- .tmrw = 3, .tmrw_05T = 1,
- .tmrd = 5, .tmrd_05T = 1,
- .tmrwckel = 7, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 10, .tmrri_05T = 1,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1,
- .txrefcnt = 99,
- .wckrdoff = 11, .wckrdoff_05T = 0,
- .wckwroff = 7, .wckwroff_05T = 0,
- .tzqcs = 29,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 7,
- .xrtr2w_odt_on = 7,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 4,
- .xrtw2r_odt_on_wck = 5,
- .xrtr2w_odt_off_wck = 10,
- .xrtr2w_odt_on_wck = 10,
- .xrtr2r_wck = 8,
- .tr2mrr = 2,
- .hwset_mr2_op = 153,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 144,
- .vrcgdis_prdcnt = 35,
- .lp5_cmd1to2en = 0,
- .trtpd = 11, .trtpd_05T = 1,
- .twtpd = 19, .twtpd_05T = 0,
- .tmrr2w = 14,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 7, .trcd_derate_05T = 0,
- .trc_derate = 13, .trc_derate_05T = 1,
- .tras_derate = 7, .tras_derate_05T = 0,
- .trpab_derate = 6, .trpab_derate_05T = 0,
- .trp_derate = 5, .trp_derate_05T = 0,
- .trrd_derate = 1, .trrd_derate_05T = 1,
- .zqlat2 = 11,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 6, .datlat = 19
- },
- {
- .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
- .readLat = 15, .writeLat = 8, .DivMode = DIV16_MODE,
-
- .tras = 5, .tras_05T = 1,
- .trp = 6, .trp_05T = 1,
- .trpab = 7, .trpab_05T = 1,
- .trc = 13, .trc_05T = 0,
- .trfc = 84, .trfc_05T = 1,
- .trfcpb = 36, .trfcpb_05T = 1,
- .txp = 2, .txp_05T = 0,
- .trtp = 1, .trtp_05T = 1,
- .trcd = 6, .trcd_05T = 1,
- .twr = 16, .twr_05T = 0,
- .twtr = 4, .twtr_05T = 1,
- .twtr_l = 8, .twtr_l_05T = 0,
- .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
- .tpbr2act = 2, .tpbr2act_05T = 0,
- .tr2mrw = 12, .tr2mrw_05T = 1,
- .tw2mrw = 8, .tw2mrw_05T = 0,
- .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
- .tmrw = 3, .tmrw_05T = 1,
- .tmrd = 5, .tmrd_05T = 1,
- .tmrwckel = 7, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 10, .tmrri_05T = 1,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 3, .tr2w_odt_off_05T = 1,
- .tr2w_odt_on = 5, .tr2w_odt_on_05T = 0,
- .txrefcnt = 99,
- .wckrdoff = 10, .wckrdoff_05T = 1,
- .wckwroff = 7, .wckwroff_05T = 0,
- .tzqcs = 29,
- .xrtw2w_odt_off = 2,
- .xrtw2w_odt_on = 3,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 1,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 6,
- .xrtr2w_odt_on = 7,
- .xrtr2r_odt_off = 6,
- .xrtr2r_odt_on = 6,
- .xrtw2w_odt_off_wck = 6,
- .xrtw2w_odt_on_wck = 8,
- .xrtw2r_odt_off_wck = 4,
- .xrtw2r_odt_on_wck = 5,
- .xrtr2w_odt_off_wck = 9,
- .xrtr2w_odt_on_wck = 9,
- .xrtr2r_wck = 8,
- .tr2mrr = 1,
- .hwset_mr2_op = 153,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 144,
- .vrcgdis_prdcnt = 35,
- .lp5_cmd1to2en = 0,
- .trtpd = 11, .trtpd_05T = 0,
- .twtpd = 18, .twtpd_05T = 1,
- .tmrr2w = 14,
- .ckeprd = 2,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 7, .trcd_derate_05T = 0,
- .trc_derate = 13, .trc_derate_05T = 1,
- .tras_derate = 7, .tras_derate_05T = 0,
- .trpab_derate = 6, .trpab_derate_05T = 0,
- .trp_derate = 5, .trp_derate_05T = 0,
- .trrd_derate = 1, .trrd_derate_05T = 1,
- .zqlat2 = 11,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 6, .datlat = 19
- },
- #endif
- #endif
- #if SUPPORT_LP5_DDR4266_ACTIM
- //LP5_DDR4266 ACTiming---------------------------------
- #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1))
- //LPDDR5_4266_Div 8_CKR4_DBI1.csv Read 1
- {
- .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
-
- //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
- .readLat = 14, .writeLat = 6, .DivMode = DIV8_MODE,
-
- .tras = 14, .tras_05T = 0,
- .trp = 10, .trp_05T = 0,
- .trpab = 12, .trpab_05T = 0,
- .trc = 25, .trc_05T = 0,
- .trfc = 138, .trfc_05T = 0,
- .trfcpb = 63, .trfcpb_05T = 0,
- .txp = 5, .txp_05T = 0,
- .trtp = 4, .trtp_05T = 0,
- .trcd = 10, .trcd_05T = 0,
- .twr = 27, .twr_05T = 0,
- .twtr = 10, .twtr_05T = 0,
- .twtr_l = 16, .twtr_l_05T = 0,
- .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
- .tpbr2act = 3, .tpbr2act_05T = 0,
- .tr2mrw = 23, .tr2mrw_05T = 0,
- .tw2mrw = 14, .tw2mrw_05T = 0,
- .tmrr2mrw = 21, .tmrr2mrw_05T = 0,
- .tmrw = 6, .tmrw_05T = 0,
- .tmrd = 9, .tmrd_05T = 0,
- .tmrwckel = 13, .tmrwckel_05T = 0,
- .tpde = 5, .tpde_05T = 0,
- .tpdx = 3, .tpdx_05T = 0,
- .tmrri = 17, .tmrri_05T = 0,
- .trrd = 3, .trrd_05T = 0,
- .tfaw = 3, .tfaw_05T = 0,
- .tr2w_odt_off = 11, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 15, .tr2w_odt_on_05T = 0,
- .txrefcnt = 154,
- .wckrdoff = 20, .wckrdoff_05T = 0,
- .wckwroff = 12, .wckwroff_05T = 0,
- .tzqcs = 46,
- .xrtw2w_odt_off = 5,
- .xrtw2w_odt_on = 7,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 12,
- .xrtr2w_odt_on = 14,
- .xrtr2r_odt_off = 9,
- .xrtr2r_odt_on = 9,
- .xrtw2w_odt_off_wck = 10,
- .xrtw2w_odt_on_wck = 12,
- .xrtw2r_odt_off_wck = 6,
- .xrtw2r_odt_on_wck = 7,
- .xrtr2w_odt_off_wck = 18,
- .xrtr2w_odt_on_wck = 18,
- .xrtr2r_wck = 14,
- .tr2mrr = 13,
- .hwset_mr2_op = 119,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 112,
- .vrcgdis_prdcnt = 54,
- .lp5_cmd1to2en = 1,
- .trtpd = 19, .trtpd_05T = 0,
- .twtpd = 31, .twtpd_05T = 0,
- .tmrr2w = 23,
- .ckeprd = 3,
- .ckelckcnt = 5,
- .tcsh_cscal = 5,
- .tcacsh = 3,
- .tcsh = 4,
- .trcd_derate = 11, .trcd_derate_05T = 0,
- .trc_derate = 26, .trc_derate_05T = 0,
- .tras_derate = 17, .tras_derate_05T = 0,
- .trpab_derate = 10, .trpab_derate_05T = 0,
- .trp_derate = 8, .trp_derate_05T = 0,
- .trrd_derate = 3, .trrd_derate_05T = 0,
- .zqlat2 = 16,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 10, .datlat = 19
- },
- //LPDDR5_4266_BT_Div 8_CKR4_DBI1.csv Read 1
- {
- .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
- //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
- .readLat = 13, .writeLat = 6, .DivMode = DIV8_MODE,
-
- .tras = 14, .tras_05T = 0,
- .trp = 10, .trp_05T = 0,
- .trpab = 12, .trpab_05T = 0,
- .trc = 25, .trc_05T = 0,
- .trfc = 138, .trfc_05T = 0,
- .trfcpb = 63, .trfcpb_05T = 0,
- .txp = 5, .txp_05T = 0,
- .trtp = 4, .trtp_05T = 0,
- .trcd = 10, .trcd_05T = 0,
- .twr = 26, .twr_05T = 0,
- .twtr = 9, .twtr_05T = 0,
- .twtr_l = 15, .twtr_l_05T = 0,
- .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
- .tpbr2act = 3, .tpbr2act_05T = 0,
- .tr2mrw = 22, .tr2mrw_05T = 0,
- .tw2mrw = 14, .tw2mrw_05T = 0,
- .tmrr2mrw = 20, .tmrr2mrw_05T = 0,
- .tmrw = 6, .tmrw_05T = 0,
- .tmrd = 9, .tmrd_05T = 0,
- .tmrwckel = 13, .tmrwckel_05T = 0,
- .tpde = 5, .tpde_05T = 0,
- .tpdx = 3, .tpdx_05T = 0,
- .tmrri = 17, .tmrri_05T = 0,
- .trrd = 3, .trrd_05T = 0,
- .tfaw = 3, .tfaw_05T = 0,
- .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 14, .tr2w_odt_on_05T = 0,
- .txrefcnt = 154,
- .wckrdoff = 19, .wckrdoff_05T = 0,
- .wckwroff = 12, .wckwroff_05T = 0,
- .tzqcs = 46,
- .xrtw2w_odt_off = 5,
- .xrtw2w_odt_on = 7,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 11,
- .xrtr2w_odt_on = 13,
- .xrtr2r_odt_off = 9,
- .xrtr2r_odt_on = 9,
- .xrtw2w_odt_off_wck = 10,
- .xrtw2w_odt_on_wck = 12,
- .xrtw2r_odt_off_wck = 7,
- .xrtw2r_odt_on_wck = 8,
- .xrtr2w_odt_off_wck = 17,
- .xrtr2w_odt_on_wck = 17,
- .xrtr2r_wck = 14,
- .tr2mrr = 12,
- .hwset_mr2_op = 119,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 112,
- .vrcgdis_prdcnt = 54,
- .lp5_cmd1to2en = 1,
- .trtpd = 18, .trtpd_05T = 0,
- .twtpd = 30, .twtpd_05T = 0,
- .tmrr2w = 22,
- .ckeprd = 3,
- .ckelckcnt = 5,
- .tcsh_cscal = 5,
- .tcacsh = 3,
- .tcsh = 4,
- .trcd_derate = 11, .trcd_derate_05T = 0,
- .trc_derate = 26, .trc_derate_05T = 0,
- .tras_derate = 17, .tras_derate_05T = 0,
- .trpab_derate = 10, .trpab_derate_05T = 0,
- .trp_derate = 8, .trp_derate_05T = 0,
- .trrd_derate = 3, .trrd_derate_05T = 0,
- .zqlat2 = 16,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 10, .datlat = 19
- },
- #else //ENABLE_READ_DBI == 0)
- //LPDDR5_4266_Div 8_CKR4_DBI0.csv Read 0
- {
- .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
- .readLat = 13, .writeLat = 6, .DivMode = DIV8_MODE,
-
- .tras = 14, .tras_05T = 0,
- .trp = 10, .trp_05T = 0,
- .trpab = 12, .trpab_05T = 0,
- .trc = 25, .trc_05T = 0,
- .trfc = 138, .trfc_05T = 0,
- .trfcpb = 63, .trfcpb_05T = 0,
- .txp = 5, .txp_05T = 0,
- .trtp = 4, .trtp_05T = 0,
- .trcd = 10, .trcd_05T = 0,
- .twr = 27, .twr_05T = 0,
- .twtr = 10, .twtr_05T = 0,
- .twtr_l = 16, .twtr_l_05T = 0,
- .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
- .tpbr2act = 3, .tpbr2act_05T = 0,
- .tr2mrw = 22, .tr2mrw_05T = 0,
- .tw2mrw = 14, .tw2mrw_05T = 0,
- .tmrr2mrw = 20, .tmrr2mrw_05T = 0,
- .tmrw = 6, .tmrw_05T = 0,
- .tmrd = 9, .tmrd_05T = 0,
- .tmrwckel = 13, .tmrwckel_05T = 0,
- .tpde = 5, .tpde_05T = 0,
- .tpdx = 3, .tpdx_05T = 0,
- .tmrri = 17, .tmrri_05T = 0,
- .trrd = 3, .trrd_05T = 0,
- .tfaw = 3, .tfaw_05T = 0,
- .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 14, .tr2w_odt_on_05T = 0,
- .txrefcnt = 154,
- .wckrdoff = 19, .wckrdoff_05T = 0,
- .wckwroff = 12, .wckwroff_05T = 0,
- .tzqcs = 46,
- .xrtw2w_odt_off = 5,
- .xrtw2w_odt_on = 7,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 0,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 11,
- .xrtr2w_odt_on = 13,
- .xrtr2r_odt_off = 9,
- .xrtr2r_odt_on = 9,
- .xrtw2w_odt_off_wck = 10,
- .xrtw2w_odt_on_wck = 12,
- .xrtw2r_odt_off_wck = 7,
- .xrtw2r_odt_on_wck = 8,
- .xrtr2w_odt_off_wck = 17,
- .xrtr2w_odt_on_wck = 17,
- .xrtr2r_wck = 14,
- .tr2mrr = 12,
- .hwset_mr2_op = 119,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 112,
- .vrcgdis_prdcnt = 54,
- .lp5_cmd1to2en = 1,
- .trtpd = 18, .trtpd_05T = 0,
- .twtpd = 31, .twtpd_05T = 0,
- .tmrr2w = 22,
- .ckeprd = 3,
- .ckelckcnt = 5,
- .tcsh_cscal = 5,
- .tcacsh = 3,
- .tcsh = 4,
- .trcd_derate = 11, .trcd_derate_05T = 0,
- .trc_derate = 26, .trc_derate_05T = 0,
- .tras_derate = 17, .tras_derate_05T = 0,
- .trpab_derate = 10, .trpab_derate_05T = 0,
- .trp_derate = 8, .trp_derate_05T = 0,
- .trrd_derate = 3, .trrd_derate_05T = 0,
- .zqlat2 = 16,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 10, .datlat = 19
- },
- //LPDDR5_4266_BT_Div 8_CKR4_DBI0.csv Read 0
- {
- .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
- .readLat = 12, .writeLat = 6, .DivMode = DIV8_MODE,
-
- .tras = 14, .tras_05T = 0,
- .trp = 10, .trp_05T = 0,
- .trpab = 12, .trpab_05T = 0,
- .trc = 25, .trc_05T = 0,
- .trfc = 138, .trfc_05T = 0,
- .trfcpb = 63, .trfcpb_05T = 0,
- .txp = 5, .txp_05T = 0,
- .trtp = 4, .trtp_05T = 0,
- .trcd = 10, .trcd_05T = 0,
- .twr = 26, .twr_05T = 0,
- .twtr = 9, .twtr_05T = 0,
- .twtr_l = 15, .twtr_l_05T = 0,
- .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
- .tpbr2act = 3, .tpbr2act_05T = 0,
- .tr2mrw = 21, .tr2mrw_05T = 0,
- .tw2mrw = 14, .tw2mrw_05T = 0,
- .tmrr2mrw = 19, .tmrr2mrw_05T = 0,
- .tmrw = 6, .tmrw_05T = 0,
- .tmrd = 9, .tmrd_05T = 0,
- .tmrwckel = 13, .tmrwckel_05T = 0,
- .tpde = 5, .tpde_05T = 0,
- .tpdx = 3, .tpdx_05T = 0,
- .tmrri = 17, .tmrri_05T = 0,
- .trrd = 3, .trrd_05T = 0,
- .tfaw = 3, .tfaw_05T = 0,
- .tr2w_odt_off = 9, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 13, .tr2w_odt_on_05T = 0,
- .txrefcnt = 154,
- .wckrdoff = 18, .wckrdoff_05T = 0,
- .wckwroff = 12, .wckwroff_05T = 0,
- .tzqcs = 46,
- .xrtw2w_odt_off = 5,
- .xrtw2w_odt_on = 7,
- .xrtw2r_odt_off_otf_off = 0,
- .xrtw2r_odt_on_otf_off = 1,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 10,
- .xrtr2w_odt_on = 12,
- .xrtr2r_odt_off = 9,
- .xrtr2r_odt_on = 9,
- .xrtw2w_odt_off_wck = 10,
- .xrtw2w_odt_on_wck = 12,
- .xrtw2r_odt_off_wck = 8,
- .xrtw2r_odt_on_wck = 9,
- .xrtr2w_odt_off_wck = 16,
- .xrtr2w_odt_on_wck = 16,
- .xrtr2r_wck = 14,
- .tr2mrr = 11,
- .hwset_mr2_op = 119,
- .hwset_mr13_op = 74,
- .hwset_vrcg_op = 112,
- .vrcgdis_prdcnt = 54,
- .lp5_cmd1to2en = 1,
- .trtpd = 17, .trtpd_05T = 0,
- .twtpd = 30, .twtpd_05T = 0,
- .tmrr2w = 21,
- .ckeprd = 3,
- .ckelckcnt = 5,
- .tcsh_cscal = 5,
- .tcacsh = 3,
- .tcsh = 4,
- .trcd_derate = 11, .trcd_derate_05T = 0,
- .trc_derate = 26, .trc_derate_05T = 0,
- .tras_derate = 17, .tras_derate_05T = 0,
- .trpab_derate = 10, .trpab_derate_05T = 0,
- .trp_derate = 8, .trp_derate_05T = 0,
- .trrd_derate = 3, .trrd_derate_05T = 0,
- .zqlat2 = 16,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 10, .datlat = 19
- },
- #endif
- #endif
- #if SUPPORT_LP5_DDR3200_ACTIM
- //LP5_DDR3200 ACTiming---------------------------------
- //LPDDR5_3200_Div 8_CKR2_DBI1.csv Read 0
- {
- .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
-
- //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
- .readLat = 20, .writeLat = 10, .DivMode = DIV8_MODE,
-
- .tras = 8, .tras_05T = 0,
- .trp = 7, .trp_05T = 1,
- .trpab = 8, .trpab_05T = 1,
- .trc = 16, .trc_05T = 1,
- .trfc = 140, .trfc_05T = 0,
- .trfcpb = 64, .trfcpb_05T = 0,
- .txp = 2, .txp_05T = 1,
- .trtp = 2, .trtp_05T = 0,
- .trcd = 7, .trcd_05T = 1,
- .twr = 19, .twr_05T = 0,
- .twtr = 10, .twtr_05T = 0,
- .twtr_l = 10, .twtr_l_05T = 0,
- .tpbr2pbr = 36, .tpbr2pbr_05T = 0,
- .tpbr2act = 3, .tpbr2act_05T = 0,
- .tr2mrw = 15, .tr2mrw_05T = 0,
- .tw2mrw = 10, .tw2mrw_05T = 0,
- .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
- .tmrw = 4, .tmrw_05T = 0,
- .tmrd = 6, .tmrd_05T = 1,
- .tmrwckel = 8, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 12, .tmrri_05T = 0,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
- .txrefcnt = 115,
- .wckrdoff = 13, .wckrdoff_05T = 0,
- .wckwroff = 8, .wckwroff_05T = 0,
- .tzqcs = 34,
- .xrtw2w_odt_off = 6,
- .xrtw2w_odt_on = 9,
- .xrtw2r_odt_off_otf_off = 3,
- .xrtw2r_odt_on_otf_off = 3,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 9,
- .xrtr2w_odt_on = 10,
- .xrtr2r_odt_off = 8,
- .xrtr2r_odt_on = 8,
- .xrtw2w_odt_off_wck = 7,
- .xrtw2w_odt_on_wck = 9,
- .xrtw2r_odt_off_wck = 5,
- .xrtw2r_odt_on_wck = 6,
- .xrtr2w_odt_off_wck = 12,
- .xrtr2w_odt_on_wck = 12,
- .xrtr2r_wck = 10,
- .tr2mrr = 3,
- .hwset_mr2_op = 45,
- .hwset_mr13_op = 216,
- .hwset_vrcg_op = 208,
- .vrcgdis_prdcnt = 40,
- .lp5_cmd1to2en = 0,
- .trtpd = 13, .trtpd_05T = 1,
- .twtpd = 13, .twtpd_05T = 0,
- .tmrr2w = 16,
- .ckeprd = 4,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 8, .trcd_derate_05T = 0,
- .trc_derate = 17, .trc_derate_05T = 0,
- .tras_derate = 10, .tras_derate_05T = 0,
- .trpab_derate = 7, .trpab_derate_05T = 1,
- .trp_derate = 6, .trp_derate_05T = 0,
- .trrd_derate = 2, .trrd_derate_05T = 0,
- .zqlat2 = 12,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 7, .datlat = 15
- },
- //LPDDR5_3200_BT_Div 8_CKR2_DBI1.csv Read 0
- {
- .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
- //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
- .readLat = 18, .writeLat = 10, .DivMode = DIV8_MODE,
-
- .tras = 8, .tras_05T = 0,
- .trp = 7, .trp_05T = 1,
- .trpab = 8, .trpab_05T = 1,
- .trc = 16, .trc_05T = 1,
- .trfc = 140, .trfc_05T = 0,
- .trfcpb = 64, .trfcpb_05T = 0,
- .txp = 2, .txp_05T = 1,
- .trtp = 2, .trtp_05T = 0,
- .trcd = 7, .trcd_05T = 1,
- .twr = 19, .twr_05T = -2,
- .twtr = 9, .twtr_05T = 0,
- .twtr_l = 9, .twtr_l_05T = 0,
- .tpbr2pbr = 36, .tpbr2pbr_05T = 0,
- .tpbr2act = 3, .tpbr2act_05T = 0,
- .tr2mrw = 14, .tr2mrw_05T = 0,
- .tw2mrw = 10, .tw2mrw_05T = 0,
- .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
- .tmrw = 4, .tmrw_05T = 0,
- .tmrd = 6, .tmrd_05T = 1,
- .tmrwckel = 8, .tmrwckel_05T = 1,
- .tpde = 2, .tpde_05T = 1,
- .tpdx = 1, .tpdx_05T = 1,
- .tmrri = 12, .tmrri_05T = 0,
- .trrd = 2, .trrd_05T = 0,
- .tfaw = 0, .tfaw_05T = 0,
- .tr2w_odt_off = 3, .tr2w_odt_off_05T = 0,
- .tr2w_odt_on = 5, .tr2w_odt_on_05T = 0,
- .txrefcnt = 115,
- .wckrdoff = 12, .wckrdoff_05T = 0,
- .wckwroff = 8, .wckwroff_05T = 0,
- .tzqcs = 34,
- .xrtw2w_odt_off = 6,
- .xrtw2w_odt_on = 9,
- .xrtw2r_odt_off_otf_off = 3,
- .xrtw2r_odt_on_otf_off = 3,
- .xrtw2r_odt_off_otf_on = 3,
- .xrtw2r_odt_on_otf_on = 3,
- .xrtr2w_odt_off = 8,
- .xrtr2w_odt_on = 9,
- .xrtr2r_odt_off = 8,
- .xrtr2r_odt_on = 8,
- .xrtw2w_odt_off_wck = 7,
- .xrtw2w_odt_on_wck = 9,
- .xrtw2r_odt_off_wck = 6,
- .xrtw2r_odt_on_wck = 7,
- .xrtr2w_odt_off_wck = 11,
- .xrtr2w_odt_on_wck = 11,
- .xrtr2r_wck = 10,
- .tr2mrr = 2,
- .hwset_mr2_op = 45,
- .hwset_mr13_op = 216,
- .hwset_vrcg_op = 208,
- .vrcgdis_prdcnt = 40,
- .lp5_cmd1to2en = 0,
- .trtpd = 12, .trtpd_05T = 1,
- .twtpd = 12, .twtpd_05T = 0,
- .tmrr2w = 15,
- .ckeprd = 4,
- .ckelckcnt = 3,
- .tcsh_cscal = 3,
- .tcacsh = 2,
- .tcsh = 5,
- .trcd_derate = 8, .trcd_derate_05T = 0,
- .trc_derate = 17, .trc_derate_05T = 0,
- .tras_derate = 10, .tras_derate_05T = 0,
- .trpab_derate = 7, .trpab_derate_05T = 1,
- .trp_derate = 6, .trp_derate_05T = 0,
- .trrd_derate = 2, .trrd_derate_05T = 0,
- .zqlat2 = 12,
-
- //DQSINCTL, DATLAT aren't in ACTiming excel file
- .dqsinctl = 7, .datlat = 15
- },
- #endif
- };
-#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
index e3f4c55460..6684c291c4 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
@@ -3387,14 +3387,6 @@ void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)
mcSHOW_MRW_MSG(("[MR Dump] CH%d Rank%d Fsp%d MR%d =0x%x\n", p->channel, p->rank, gFSPWR_Flag[p->rank], u1MRIdx, u2MRValue));
#if MRW_BACKUP
//MR13(LP4) work around, two RG is not synchronized
- #if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- if (u1MRIdx==16)
- gFSPWR_Flag[p->rank]=u1Backup_Fsp;
- }
- else
- #endif
{
if (u1MRIdx==13)
gFSPWR_Flag[p->rank]=u1Backup_Fsp;
@@ -3402,14 +3394,6 @@ void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)
DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
- #if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- if (u1MRIdx==16)
- gFSPWR_Flag[p->rank]=u1FSPIdx;
- }
- else
- #endif
{
if (u1MRIdx==13)
gFSPWR_Flag[p->rank]=u1FSPIdx;
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
index f659dcd443..1af3490a64 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
@@ -15635,9199 +15635,5 @@ vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RAN
}
-#if __LP5_COMBO__
-void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p)
-{
- // Enter body
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634
- DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)
- DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)
- DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00)
- DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00)
- DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00)
- DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00)
- DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0
- DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
- P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645
- CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)
- CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)
- CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00)
- CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00)
- DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00)
- DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00)
- DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655
- DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
- DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
- DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
- DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
- DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
- DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664
- CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
- CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
- CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
- CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
- DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
- DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682
- IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h09 (Mirror: 6'h01)
- DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00
- DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x09, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
- P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625
- IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h5 (Mirror: 3'h4)
- IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
- IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
- IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
- IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
- IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x5, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
- P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
- P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
- P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734
- DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0e (Mirror: 5'h00)
- RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
- RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
- SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfd7 (Mirror: 12'h000)
- SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h029 (Mirror: 12'h000)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0e, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
- P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
- P_Fld(0xfd7, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x029, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604
- DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0e (Mirror: 5'h00)
- DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0e (Mirror: 5'h00)
- DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0e (Mirror: 5'h00)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0e, MISC_SHU_RDAT_DATLAT) |
- P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540
- RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
- RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
- RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
- RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)
- RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
- RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)
- RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
- P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
- P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
- P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530
- RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h4 (Mirror: 4'h0)
- RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1
- RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0
- RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h7 (Mirror: 4'h0)
- RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h5 (Mirror: 4'h0)
- RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h5 (Mirror: 4'h0)
- RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h8 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
- P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
- P_Fld(0x7, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL) |
- P_Fld(0x5, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_PHY));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757
- RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)
- RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)
- RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
- P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352
- DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h7 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356
- DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h7 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x7, MISC_SHU_RK_DQSCTL_DQSINCTL);
- /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624
- DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'ha (Mirror: 4'h0)
- DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'he (Mirror: 4'h0)
- DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
- DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0xe, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
- /*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638
- DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00)
- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0f, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631
- DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)
- DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0
- DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
- DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642
- DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027
- DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'ha (Mirror: 4'h0)
- DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'he (Mirror: 4'h0)
- DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
- DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0xe, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041
- DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0f (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0f, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034
- DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hc (Mirror: 4'h0)
- DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h0
- DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
- DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xc, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045
- DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h11 (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x11, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550
- RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
- RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h6 (Mirror: 4'h0)
- RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
- RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
- FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
- RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
- RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
- RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x6, MISC_SHU_ODTCTRL_RODT_LAT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
- P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_RX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_RX_PIPE_CTRL_0 - @12704
- RX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_RX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x1, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646
- RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h5 (Mirror: 3'h0)
- RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h5 (Mirror: 3'h0)
- RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
- RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653
- RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)
- RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)
- RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0
- RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x7, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049
- RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h5 (Mirror: 3'h0)
- RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h5 (Mirror: 3'h0)
- RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
- RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056
- RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h7 (Mirror: 3'h0)
- RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h7 (Mirror: 3'h0)
- RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h0
- RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x7, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323
- DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0
- READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0
- DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)
- READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)
- DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
- READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
- P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720
- RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
- RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
- RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
- RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
- RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
- RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
- RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h8 (Mirror: 4'h0)
- RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
- RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
- RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0)
- RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x8, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370
- DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
- DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
- DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
- DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377
- DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
- DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
- DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
- DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602
- CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
- CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x0a, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005
- CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
- CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x0a, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607
- CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
- CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x0c, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010
- CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
- CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x0c, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612
- NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
- NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
- NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0e (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x0a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015
- NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0f (Mirror: 7'h00)
- NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h0a (Mirror: 8'h00)
- NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0e (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x0a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618
- NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
- NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
- NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x0c, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x10, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021
- NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h11 (Mirror: 7'h00)
- NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0c (Mirror: 8'h00)
- NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h10 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x0c, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x10, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10426
- RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0
- RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0
- RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00
- RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h10 (Mirror: 6'h00)
- RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582
- RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
- RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
- SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h0f (Mirror: 6'h00)
- SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h0f (Mirror: 6'h00)
- ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0f, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x0f, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985
- RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
- RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
- SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h18 (Mirror: 6'h00)
- SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h18 (Mirror: 6'h00)
- ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x18, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10436
- RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0
- RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0
- RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00
- RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h10 (Mirror: 6'h00)
- RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592
- RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
- RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
- SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h0e (Mirror: 6'h00)
- SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h0e (Mirror: 6'h00)
- ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x0e, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x0e, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995
- RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
- RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
- SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h15 (Mirror: 6'h00)
- SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h15 (Mirror: 6'h00)
- ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x15, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027
- DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
- DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4
- DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
- CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0
- FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0
- FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377
- DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0)
- DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h3 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
- P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
- P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h3 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h3 (Mirror: 3'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h3 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h3 (Mirror: 3'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371
- TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h3 (Mirror: 3'h0)
- TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)
- TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
- P_Fld(0x3, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271
- TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h4 (Mirror: 3'h1)
- TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h4 (Mirror: 3'h1)
- TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1
- TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1
- TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1
- TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
- P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
- P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282
- dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h6 (Mirror: 4'h1)
- dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h7 (Mirror: 4'h1)
- dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1
- dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1
- dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h3 (Mirror: 4'h1)
- dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h4 (Mirror: 4'h1)
- dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1
- dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_DQS0) |
- P_Fld(0x7, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
- P_Fld(0x4, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746
- TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h4 (Mirror: 3'h1)
- TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h4 (Mirror: 3'h1)
- TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
- TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
- TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
- TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768
- TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h4 (Mirror: 3'h1)
- TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h4 (Mirror: 3'h1)
- TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
- TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
- TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
- TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790
- dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h5 (Mirror: 4'h1)
- dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h5 (Mirror: 4'h1)
- dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
- dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
- dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h1
- dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h1
- dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
- dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x5, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0x5, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812
- dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h5 (Mirror: 4'h1)
- dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h5 (Mirror: 4'h1)
- dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
- dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
- dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h1
- dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h1
- dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
- dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x5, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0x5, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757
- TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h4 (Mirror: 3'h1)
- TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h4 (Mirror: 3'h1)
- TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
- TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
- TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
- TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779
- TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h4 (Mirror: 3'h1)
- TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h4 (Mirror: 3'h1)
- TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
- TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
- TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
- TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801
- dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h6 (Mirror: 4'h1)
- dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h6 (Mirror: 4'h1)
- dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
- dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
- dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h2 (Mirror: 4'h1)
- dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h2 (Mirror: 4'h1)
- dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
- dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0x6, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823
- dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h6 (Mirror: 4'h1)
- dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h6 (Mirror: 4'h1)
- dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
- dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
- dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h2 (Mirror: 4'h1)
- dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h2 (Mirror: 4'h1)
- dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
- dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0x6, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834
- BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h00f (Mirror: 11'h000)
- BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h018 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x00f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x018, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844
- BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h00f (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h018 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x00f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x018, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882
- BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h00f (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h018 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x00f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x018, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839
- BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h00e (Mirror: 11'h000)
- BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h015 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x015, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849
- BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h00e (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h015 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x015, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887
- BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h00e (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h015 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x00e, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x015, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892
- RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h18 (Mirror: 6'h00)
- RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h0f (Mirror: 6'h00)
- RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h18 (Mirror: 6'h00)
- RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h0f (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x18, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x0f, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x18, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x0f, SHURK_PI_RK0_ARPI_DQM_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899
- RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h15 (Mirror: 6'h00)
- RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h0e (Mirror: 6'h00)
- RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h15 (Mirror: 6'h00)
- RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h0e (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x15, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x0e, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x15, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x0e, SHURK_PI_RK0_ARPI_DQM_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428
- TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h2c (Mirror: 8'h00)
- TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h2c (Mirror: 8'h00)
- TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h2c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442
- TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h2c (Mirror: 8'h00)
- TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h2c (Mirror: 8'h00)
- TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h2c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470
- TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
- TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435
- TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h2c (Mirror: 8'h00)
- TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h2c (Mirror: 8'h00)
- TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h2c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449
- TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h2c (Mirror: 8'h00)
- TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h2c (Mirror: 8'h00)
- TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h2c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476
- TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
- TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838
- TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h08 (Mirror: 8'h00)
- TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h08 (Mirror: 8'h00)
- TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h08 (Mirror: 8'h00)
- TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h08 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
- P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
- P_Fld(0x08, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852
- TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h08 (Mirror: 8'h00)
- TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h08 (Mirror: 8'h00)
- TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h08 (Mirror: 8'h00)
- TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h08 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
- P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
- P_Fld(0x08, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879
- TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h08 (Mirror: 8'h00)
- TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00
- TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x08, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
- P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345
- TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h2 (Mirror: 4'h0)
- TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h2 (Mirror: 4'h0)
- TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
- P_Fld(0x2, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_WR_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0 - @4936
- WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h3 (Mirror: 4'h1)
- WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_WR_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1 - @4941
- WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h3 (Mirror: 4'h1)
- WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_RD_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0 - @4946
- WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h4 (Mirror: 4'h1)
- WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h4 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_RD_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1 - @4951
- WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h4 (Mirror: 4'h1)
- WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h4 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0 - @4956
- WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h2 (Mirror: 4'h1)
- WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h2 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1 - @4961
- WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h2 (Mirror: 4'h1)
- WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h2 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_0 - @4986
- WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[3:0]=4'h5 (Mirror: 4'h1)
- WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[7:4]=4'h5 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI, P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
- P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_1 - @4991
- WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[3:0]=4'h5 (Mirror: 4'h1)
- WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[7:4]=4'h5 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
- P_Fld(0x5, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041
- TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052
- TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01
- TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
- P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
- P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060
- TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071
- TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082
- dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1
- dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1
- dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
- dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1
- dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1
- dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1
- dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1
- dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018
- CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3
- SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
- P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036
- FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h64 (Mirror: 8'h00)
- REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x64, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199
- TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h1 (Mirror: 1'h0)
- TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0
- TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0
- TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0
- TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0)
- TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0
- TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0)
- TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h1 (Mirror: 1'h0)
- TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h1 (Mirror: 1'h0)
- TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0
- TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)
- TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0
- TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0
- TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0
- TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0
- TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)
- TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0)
- TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0
- BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0
- BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0
- BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0
- TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h1 (Mirror: 1'h0)
- TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0
- XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0
- TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0
- TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0
- TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0
- TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0
- TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0
- TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0
- XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRPAB_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192
- XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h09 (Mirror: 5'h01)
- XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0b (Mirror: 6'h01)
- XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h6 (Mirror: 4'h1)
- XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h06 (Mirror: 5'h01)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x09, SHU_ACTIM_XRT_XRTR2R) |
- P_Fld(0x0b, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x6, SHU_ACTIM_XRT_XRTW2R) |
- P_Fld(0x06, SHU_ACTIM_XRT_XRTW2W));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138
- TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h9 (Mirror: 4'h1)
- CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0)
- TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h13 (Mirror: 8'h06)
- TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h2 (Mirror: 3'h0)
- TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'h7 (Mirror: 4'h2)
- TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'h9 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x9, SHU_ACTIM0_TWTR) |
- P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x13, SHU_ACTIM0_TWR) |
- P_Fld(0x2, SHU_ACTIM0_TRRD) | P_Fld(0x7, SHU_ACTIM0_TRCD) |
- P_Fld(0x9, SHU_ACTIM0_TWTR_L));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147
- TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'h8 (Mirror: 4'ha)
- TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h8
- TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h7 (Mirror: 4'h2)
- TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h08 (Mirror: 6'h04)
- TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h10 (Mirror: 5'h05)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0x8, SHU_ACTIM1_TRPAB) |
- P_Fld(0x8, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x7, SHU_ACTIM1_TRP) |
- P_Fld(0x08, SHU_ACTIM1_TRAS) | P_Fld(0x10, SHU_ACTIM1_TRC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155
- TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h2 (Mirror: 4'h0)
- TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0b (Mirror: 5'h0e)
- TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h2 (Mirror: 3'h0)
- TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h06 (Mirror: 6'h00)
- TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h00 (Mirror: 5'h05)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x2, SHU_ACTIM2_TXP) |
- P_Fld(0x0b, SHU_ACTIM2_TMRRI) | P_Fld(0x2, SHU_ACTIM2_TRTP) |
- P_Fld(0x06, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163
- TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h2c (Mirror: 8'h00)
- MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
- TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
- TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h64 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x2c, SHU_ACTIM3_TRFCPB) |
- P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
- P_Fld(0x64, SHU_ACTIM3_TRFC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170
- TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h073 (Mirror: 10'h028)
- TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0f (Mirror: 6'h00)
- TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h0c (Mirror: 6'h00)
- TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h22 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x073, SHU_ACTIM4_TXREFCNT) |
- P_Fld(0x0f, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x0c, SHU_ACTIM4_TMRR2W) |
- P_Fld(0x22, SHU_ACTIM4_TZQCS));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177
- TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h11 (Mirror: 7'h00)
- TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h16 (Mirror: 7'h00)
- TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h24 (Mirror: 8'h00)
- TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h3 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x11, SHU_ACTIM5_TR2PD) |
- P_Fld(0x16, SHU_ACTIM5_TWTPD) | P_Fld(0x24, SHU_ACTIM5_TPBR2PBR) |
- P_Fld(0x3, SHU_ACTIM5_TPBR2ACT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184
- TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h0c (Mirror: 5'h1f)
- TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h6 (Mirror: 4'h0)
- TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h5 (Mirror: 4'h0)
- TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h0a (Mirror: 6'h00)
- TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h0f (Mirror: 6'h13)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x0c, SHU_ACTIM6_TZQLAT2) |
- P_Fld(0x6, SHU_ACTIM6_TMRD) | P_Fld(0x5, SHU_ACTIM6_TMRW) |
- P_Fld(0x0a, SHU_ACTIM6_TW2MRW) | P_Fld(0x0f, SHU_ACTIM6_TR2MRW));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262
- TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h1 (Mirror: 1'h0)
- TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h2 (Mirror: 3'h1)
- TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1
- TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2)
- TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
- P_Fld(0x1, SHU_CKECTRL_TPDX_05T) | P_Fld(0x2, SHU_CKECTRL_TPDE) |
- P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) |
- P_Fld(0x3, SHU_CKECTRL_TCKESRX));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365
- REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2
- DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
- DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
- P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427
- LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h0
- TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'h5 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
- P_Fld(0x5, SHU_LP5_CMD_TCSH));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM7_0 ral_reg_DRAMC_blk_SHU_ACTIM7_0 - @5436
- TCSH_CSCAL uvm_reg_field ... RW SHU_ACTIM7_0[3:0]=4'h3 (Mirror: 4'h0)
- TCACSH uvm_reg_field ... RW SHU_ACTIM7_0[7:4]=4'h1 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0x3, SHU_ACTIM7_TCSH_CSCAL) |
- P_Fld(0x1, SHU_ACTIM7_TCACSH));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_WCKCTRL_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_0 - @5407
- WCKRDOFF uvm_reg_field ... RW SHU_WCKCTRL_0[5:0]=6'h0c (Mirror: 6'h00)
- WCKRDOFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[7:7]=1'h0
- WCKWROFF uvm_reg_field ... RW SHU_WCKCTRL_0[13:8]=6'h08 (Mirror: 6'h00)
- WCKWROFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[15:15]=1'h0
- WCKDUAL uvm_reg_field ... RW SHU_WCKCTRL_0[16:16]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x0c, SHU_WCKCTRL_WCKRDOFF) |
- P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x08, SHU_WCKCTRL_WCKWROFF) |
- P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828
- R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h00c4 (Mirror: 15'h0000)
- R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0
- R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x00c4, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231
- R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h00c4 (Mirror: 15'h0000)
- R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0
- R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x00c4, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728
- RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e
- RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0
- RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00
- RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0
- RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0
- RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h4 (Mirror: 4'h0)
- RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
- P_Fld(0x4, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131
- RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e
- RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0
- RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00
- RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0
- RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0
- RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h4 (Mirror: 4'h0)
- RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
- P_Fld(0x4, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490
- RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504
- RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518
- RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532
- RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546
- RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x76, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x76, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556
- RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h047 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h047 (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x047, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x047, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497
- RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511
- RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525
- RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539
- RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551
- RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x75, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561
- RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h046 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h046 (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x046, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x046, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893
- RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907
- RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921
- RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935
- RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h76 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h76 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949
- RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h76 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h76 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x76, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x76, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959
- RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h047 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h047 (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x047, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x047, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900
- RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914
- RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928
- RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942
- RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h75 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h75 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954
- RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h75 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h75 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x75, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964
- RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h046 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h046 (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x046, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x046, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384
- RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
- RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
- P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
- P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
- P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787
- RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
- RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
- P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
- P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
- P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384
- RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
- P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
- P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
- P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787
- RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
- P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
- P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
- P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313
- RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h7e (Mirror: 7'h00)
- RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h7e (Mirror: 7'h00)
- RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h36 (Mirror: 6'h00)
- RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h36 (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x7e, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
- P_Fld(0x7e, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x36, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
- P_Fld(0x36, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716
- RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h7e (Mirror: 7'h00)
- RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h7e (Mirror: 7'h00)
- RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h36 (Mirror: 6'h00)
- RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h36 (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x7e, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
- P_Fld(0x7e, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x36, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
- P_Fld(0x36, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320
- RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10
- RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1
- RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1
- RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0
- RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1
- RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
- P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
- P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
- P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723
- RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10
- RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1
- RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1
- RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0
- RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1
- RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
- P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
- P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
- P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001
- FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0)
- FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0
- FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0
- DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0)
- DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0
- LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h0
- LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h0
- CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0
- BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0
- BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
- LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0
- BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1
- LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h0
- SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) |
- P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
- P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
- P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x0, SHU_COMMON0_LP5WCKON) |
- P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
- P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
- P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x0, SHU_COMMON0_LP5HEFF_MODE) |
- P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_WCKCTRL_1_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_1_0 - @5415
- WCKSYNC_PRE_MODE uvm_reg_field ... RW SHU_WCKCTRL_1_0[0:0]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DRAMC_REG_SHU_WCKCTRL_1, 0x1, SHU_WCKCTRL_1_WCKSYNC_PRE_MODE);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255
- SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
- TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0
- REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000
- TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
- P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
- P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027
- DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1
- DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4
- DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5
- CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0
- FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
- FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356
- DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
- ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0
- ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
- PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
- REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
- REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
- P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
- P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
- P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996
- MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
- NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
- P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023
- DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899
- TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0
- TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0
- DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0
- TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1
- DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0
- OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0
- DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0
- WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
- DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0
- DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0
- ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0
- TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0
- DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0
- DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0
- RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0
- DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
- P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
- P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
- P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
- P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
- P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
- P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
- P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
- P_Fld(0x0, TX_SET0_DRAMOEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0)
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514
- DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0
- DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0
- r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0
- STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
- STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
- DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
- P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
- P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
- P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499
- DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)
- PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
- DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
- DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
- DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h1
- DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1
- DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0
- STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
- STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
- DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0
- DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0
- DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
- P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
- P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562
- RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
- RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
- RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
- RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
- RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
- RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
- RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
- RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
- RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
- P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751
- DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0)
- RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0)
- RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
- P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HWSET_MR13_0 ral_reg_DRAMC_blk_SHU_HWSET_MR13_0 - @5127
- HWSET_MR13_MRSMA uvm_reg_field ... RW SHU_HWSET_MR13_0[12:0]=13'h000d
- HWSET_MR13_OP uvm_reg_field ... RW SHU_HWSET_MR13_0[23:16]=8'h08 (Mirror: 8'hc8)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13, P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) |
- P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HWSET_VRCG_0 ral_reg_DRAMC_blk_SHU_HWSET_VRCG_0 - @5132
- HWSET_VRCG_MRSMA uvm_reg_field ... RW SHU_HWSET_VRCG_0[12:0]=13'h000d
- HWSET_VRCG_OP uvm_reg_field ... RW SHU_HWSET_VRCG_0[23:16]=8'h00 (Mirror: 8'hc0)
- VRCGDIS_PRDCNT uvm_reg_field ... RW SHU_HWSET_VRCG_0[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) |
- P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122
- HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002
- HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h2d (Mirror: 8'h12)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
- P_Fld(0x2d, SHU_HWSET_MR2_HWSET_MR2_OP));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384
- tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h55 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h0c (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
- P_Fld(0x55, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x0c, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
- P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523
- r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0
- r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
- r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
- r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
- P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
- P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- /*TINFO=---===BROADCAST OFF!===---*/
- DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- /*TINFO=---===BROADCAST ON!===---*/
- DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338
- DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h10 (Mirror: 8'h00)
- DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0
- DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0
- DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x10, SHU_DQSOSCR_DQSOSCRCNT) |
- P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
- P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332
- DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1
- DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h011 (Mirror: 10'h00f)
- DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
- P_Fld(0x011, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906
- DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h0317 (Mirror: 16'h0000)
- DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h0317 (Mirror: 16'h0000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x0317, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x0317, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911
- DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h01c4 (Mirror: 16'h0000)
- DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h01c4 (Mirror: 16'h0000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x01c4, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x01c4, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916
- DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h017 (Mirror: 12'h001)
- DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h00f (Mirror: 12'h001)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x017, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x00f, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921
- DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h007 (Mirror: 12'h001)
- DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h005 (Mirror: 12'h001)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x007, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x005, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0d (Mirror: 6'h0e)
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0d, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351
- ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
- TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1b
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
- P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036
- FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h64
- REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x64, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
- // Exit body
- }
-
-void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p)
-{
- // Enter body
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Enter:
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING1_DQDRVN2) |
- P_Fld(0x07, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN1) |
- P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x09, SHU_MISC_DRVING1_DQSDRVN2) |
- P_Fld(0x07, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
- P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN1) |
- P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x09, SHU_MISC_DRVING2_CMDDRVN2) |
- P_Fld(0x07, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x09, SHU_MISC_DRVING2_DQDRVN1) |
- P_Fld(0x07, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x1, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x07, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
- P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
- P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
- P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
- P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, IMP golden setting Exit:
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) |
- P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) |
- P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) |
- P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) |
- P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) |
- P_Fld(0x09, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) |
- P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) |
- P_Fld(0x1f, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) |
- P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x1, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) |
- P_Fld(0x1b, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) |
- P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) |
- P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) |
- P_Fld(0x00, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA) |
- P_Fld(0x1, SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) |
- P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) |
- P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x59, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) |
- P_Fld(0x3, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) |
- P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) |
- P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x7d, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) |
- P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) |
- P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) |
- P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) |
- P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) |
- P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) |
- P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) |
- P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) |
- P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) |
- P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) |
- P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) |
- P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) |
- P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x947a, SHU_PLL0_RG_RPHYPLL_TOP_REV) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) |
- P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) |
- P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) |
- P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) |
- P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) |
- P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) |
- P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) |
- P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) |
- P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) |
- P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) |
- P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) |
- P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) |
- P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) |
- P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) |
- P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) |
- P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) |
- P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) |
- P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) |
- P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) |
- P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) |
- P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) |
- P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) |
- P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET), 0x3338ac63, SHU_CA_CMD9_RG_ARPI_RESERVE_CA);
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) |
- P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) |
- P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) |
- P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x2, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x7f8d04df, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xa40fc3b2, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) |
- P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) |
- P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) |
- P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) |
- P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) |
- P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x3f6e1851, SHU_CA_DLL2_RG_ARCMD_REV);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) |
- P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) |
- P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) |
- P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) |
- P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) |
- P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) |
- P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) |
- P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) |
- P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0x8461c1a1, SHU_B0_DLL2_RG_ARDQ_REV_B0);
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET), 0xad90b805, SHU_B1_DLL2_RG_ARDQ_REV_B1);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) |
- P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
- P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
- P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) |
- P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) |
- P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) |
- P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) |
- P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) |
- P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) |
- P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) |
- P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) |
- P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) |
- P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) |
- P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA) |
- P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA) | P_Fld(0x00, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA) | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA) |
- P_Fld(0x1, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0) |
- P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0) | P_Fld(0x00, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0) | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ6+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1) |
- P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1) | P_Fld(0x00, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1) | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA) |
- P_Fld(0x10, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA) |
- P_Fld(0x3, SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0) |
- P_Fld(0x08, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0) |
- P_Fld(0x3, SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1) |
- P_Fld(0x02, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1) |
- P_Fld(0x3, SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x2, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA) |
- P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA) |
- P_Fld(0x00, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA) |
- P_Fld(0x1, SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA) | P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0) | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0) | P_Fld(0x0, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0) |
- P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0) | P_Fld(0x0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0) |
- P_Fld(0x1, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0) | P_Fld(0x76, SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ10+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1) | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1) | P_Fld(0x0, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ14+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1) |
- P_Fld(0x3, SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1) |
- P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1) | P_Fld(0x0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1) |
- P_Fld(0x1, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1) | P_Fld(0x4c, SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA) |
- P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA) |
- P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA) | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA) |
- P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA) |
- P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0) |
- P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0) |
- P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0) | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0) |
- P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0) |
- P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0) | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1) |
- P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1) |
- P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1) | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1) |
- P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1) |
- P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1) | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1d17, SHU_PLL0_RG_RPHYPLL_TOP_REV) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_SOPEN_EN) | P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV) | P_Fld(0x00, SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY) |
- P_Fld(0x0, SHU_PLL0_RG_RPLLGP_DLINE_MON_EN));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PLL1_RG_RPHYPLLGP_CK_SEL) |
- P_Fld(0x0, SHU_PLL1_RG_RPLLGP_PLLCK_VSEL) | P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX) |
- P_Fld(0x0, SHU_PLL1_RG_RPHYPLL_DDR400_EN));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_PLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x1, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_PHYPLL0_RG_RPHYPLL_RESERVED) |
- P_Fld(0x2, SHU_PHYPLL0_RG_RPHYPLL_FS) | P_Fld(0x7, SHU_PHYPLL0_RG_RPHYPLL_BW) |
- P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_IBIAS) |
- P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BLP) | P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BR) |
- P_Fld(0x1, SHU_PHYPLL0_RG_RPHYPLL_BP));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN) |
- P_Fld(0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_PHYPLL2_RG_RPHYPLL_POSDIV) |
- P_Fld(0x1, SHU_PHYPLL2_RG_RPHYPLL_PREDIV));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_PHYPLL3+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL) |
- P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL) |
- P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN) | P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_FS_EN) |
- P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_FBKSEL) | P_Fld(0x2, SHU_PHYPLL3_RG_RPHYPLL_RST_DLY) |
- P_Fld(0x1, SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN) |
- P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN) | P_Fld(0x0, SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL0+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00fe, SHU_CLRPLL0_RG_RCLRPLL_RESERVED) |
- P_Fld(0x2, SHU_CLRPLL0_RG_RCLRPLL_FS) | P_Fld(0x7, SHU_CLRPLL0_RG_RCLRPLL_BW) |
- P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_IBIAS) |
- P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BLP) | P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BR) |
- P_Fld(0x1, SHU_CLRPLL0_RG_RCLRPLL_BP));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN) |
- P_Fld(0x1, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG) | P_Fld(0x5b00, SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CLRPLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CLRPLL2_RG_RCLRPLL_POSDIV) |
- P_Fld(0x1, SHU_CLRPLL2_RG_RCLRPLL_PREDIV));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD5+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x00, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL) |
- P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS) | P_Fld(0x00, SHU_CA_CMD5_RG_ARPI_FB_CA) |
- P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY) |
- P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY) | P_Fld(0x0, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xd084ae4a, SHU_CA_CMD9_RG_ARPI_RESERVE_CA);
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_MIDPI_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE) |
- P_Fld(0x1, MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT) |
- P_Fld(0x1, MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT) | P_Fld(0x0, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT) |
- P_Fld(0x0, MISC_SHU_RDAT1_RDATDIV2) | P_Fld(0x1, MISC_SHU_RDAT1_RDATDIV4));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x3, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x2, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x27759cf9, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x5a41c75f, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD7+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD7_R_DMRANKRXDVS_CA) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA) | P_Fld(0x0, SHU_CA_CMD7_R_DMRODTEN_CA) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA) | P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW) |
- P_Fld(0x1, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) | P_Fld(0x0, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CMD_LAT) |
- P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_EN) | P_Fld(0x0, SHU_CA_CMD7_R_DMRXRANK_CLK_LAT));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA) |
- P_Fld(0x3, SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA) | P_Fld(0x2, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA) |
- P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PS_EN_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA) |
- P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDIV_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA) |
- P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PGAIN_CA) |
- P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x249e9d9e, SHU_CA_DLL2_RG_ARCMD_REV);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0) |
- P_Fld(0x3, SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0) | P_Fld(0x2, SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0) |
- P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PS_EN_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0) |
- P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDIV_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0) |
- P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0) | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PGAIN_B0) |
- P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL1+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1) |
- P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1) | P_Fld(0x3, SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1) |
- P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PS_EN_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1) |
- P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDIV_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1) |
- P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1) | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PGAIN_B1) |
- P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0x23566f78, SHU_B0_DLL2_RG_ARDQ_REV_B0);
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DLL2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), 0xaec2cdcb, SHU_B1_DLL2_RG_ARDQ_REV_B1);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA) |
- P_Fld(0x2, SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA) | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
- P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
- P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA) |
- P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA) |
- P_Fld(0x1, SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA) | P_Fld(0x1, SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA) | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA) |
- P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0) |
- P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0) |
- P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0) | P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0) |
- P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU) |
- P_Fld(0x0, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0) | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ2+(1*SHU_GRP_DDRPHY_OFFSET)+((U32)CHANNEL_B<<POS_BANK_NUM), P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1) |
- P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1) |
- P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1) | P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1) |
- P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU) |
- P_Fld(0x0, SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1) | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Exit
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, APHY clock related setting Enter
- vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN) |
- P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN) |
- P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN) | P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA) |
- P_Fld(0x1, SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0) |
- P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0) |
- P_Fld(0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DLL_ARPI3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1) |
- P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1) |
- P_Fld(0x1, SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX_MODE_SET related setting Enter
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0) | P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0) | P_Fld(0x2, SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0) | P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1) | P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1) | P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Enter:
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0f, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
- P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
- P_Fld(0xff0, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x010, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0f, MISC_SHU_RDAT_DATLAT) |
- P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0e, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
- P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
- P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
- P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
- P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
- P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL) |
- P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x6, MISC_SHU_RANKCTL_RANKINCTL_PHY));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
- P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x4, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
- vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL);
- vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x6, MISC_SHU_RK_DQSCTL_DQSINCTL);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0x6, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x1e, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x17, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x4, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0x6, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), 0x1e, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), 0x17, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x3, MISC_SHU_ODTCTRL_RODT_LAT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
- P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
- vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
- P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x7, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
- P_Fld(0x2, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x04, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x04, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x04, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x06, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x04, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x06, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x07, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x17, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x07, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX data path setting Exit:
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Enter:
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x1d, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x09, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x09, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x09, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x09, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
- vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
- vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xa, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
- P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x2, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
- P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x3, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
- vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
- P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0) |
- P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
- P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0x0, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0x0, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x4, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x4, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x2, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x2, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x01d, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x009, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x009, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x009, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x009, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x1d, SHURK_PI_RK0_ARPI_DQM_B0));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x09, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x09, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x09, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x09, SHURK_PI_RK0_ARPI_DQM_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
- P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
- P_Fld(0x14, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
- P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
- P_Fld(0x14, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x14, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
- P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
- P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0x7f8904df, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9+(1*SHU_GRP_DDRPHY_OFFSET), 0xa409c3b2, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX data path setting Exit:
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX WCK auto-generation set Enter
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x0, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
- P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
- P_Fld(0x0, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
- P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
- P_Fld(0x0, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
- P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
- P_Fld(0x0, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX WCK auto-generation set Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Enter:
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
- P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
- P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, TX CA golden setting Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Enter:
- vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
- P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
- vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
- vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0d, SHU_ACTIM_XRT_XRTR2R) |
- P_Fld(0x03, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x4, SHU_ACTIM_XRT_XRTW2R) |
- P_Fld(0x04, SHU_ACTIM_XRT_XRTW2W));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x4, SHU_ACTIM0_TWTR) |
- P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x06, SHU_ACTIM0_TWR) |
- P_Fld(0x0, SHU_ACTIM0_TRRD) | P_Fld(0x3, SHU_ACTIM0_TRCD) |
- P_Fld(0xe, SHU_ACTIM0_TWTR_L));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_ACTIM1_TRPAB) |
- P_Fld(0x3, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x1, SHU_ACTIM1_TRP) |
- P_Fld(0x00, SHU_ACTIM1_TRAS) | P_Fld(0x00, SHU_ACTIM1_TRC));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_ACTIM2_TXP) |
- P_Fld(0x05, SHU_ACTIM2_TMRRI) | P_Fld(0x1, SHU_ACTIM2_TRTP) |
- P_Fld(0x04, SHU_ACTIM2_TR2W) | P_Fld(0x00, SHU_ACTIM2_TFAW));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x09, SHU_ACTIM3_TRFCPB) |
- P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
- P_Fld(0x1e, SHU_ACTIM3_TRFC));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x02b, SHU_ACTIM4_TXREFCNT) |
- P_Fld(0x38, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x05, SHU_ACTIM4_TMRR2W) |
- P_Fld(0x0c, SHU_ACTIM4_TZQCS));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x08, SHU_ACTIM5_TR2PD) |
- P_Fld(0x08, SHU_ACTIM5_TWTPD) | P_Fld(0x0e, SHU_ACTIM5_TPBR2PBR) |
- P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x05, SHU_ACTIM6_TZQLAT2) |
- P_Fld(0x2, SHU_ACTIM6_TMRD) | P_Fld(0x0, SHU_ACTIM6_TMRW) |
- P_Fld(0x22, SHU_ACTIM6_TW2MRW) | P_Fld(0x13, SHU_ACTIM6_TR2MRW));
- vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
- P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
- P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x3, SHU_CKECTRL_TCKEPRD) |
- P_Fld(0x3, SHU_CKECTRL_TCKESRX));
- vIO32WriteFldMulti(DRAMC_REG_SHU_MISC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
- P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
- vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
- P_Fld(0xb, SHU_LP5_CMD_TCSH));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0xb, SHU_ACTIM7_TCSH_CSCAL) |
- P_Fld(0xb, SHU_ACTIM7_TCACSH));
- vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2b, SHU_WCKCTRL_WCKRDOFF) |
- P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x2b, SHU_WCKCTRL_WCKWROFF) |
- P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) |
- P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) |
- P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, AC timing Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Enter.
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX cross-rank improve setting Exit.
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x004a, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
- P_Fld(0x6, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
- P_Fld(0x6, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x17, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0be, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x0be, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x16, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0bd, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x0bd, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x17, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x17, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0be, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x0be, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x16, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x16, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x0bd, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, RX input delay line set EXIT
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Enter
- vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_COMMON0_FREQDIV4) |
- P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x1, SHU_COMMON0_FREQDIV8) |
- P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
- P_Fld(0x0, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) |
- P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
- P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
- P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) |
- P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
- vIO32WriteFldAlign(DRAMC_REG_SHU_WCKCTRL_1+(1*SHU_GRP_DRAMC_OFFSET), 0x1, SHU_WCKCTRL_1_WCKSYNC_PRE_MODE);
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
- P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
- P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
- vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x6, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
- vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
- P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
- P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
- P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
- vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x2, SHU_MATYPE_MATYPE) |
- P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
- vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER+(1*SHU_GRP_DRAMC_OFFSET), 0x1, SHU_SCHEDULER_DUALSCHEN);
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
- P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
- P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
- P_Fld(0x0, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_STBCAL_DMSTBLAT) |
- P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
- P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) |
- P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL+(1*SHU_GRP_DDRPHY_OFFSET)+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) |
- P_Fld(0x1, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
- P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
- P_Fld(0x2, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
- P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x0, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, DRAMC other fixed register Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Enter
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, DBI gen by frequency Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Enter
- vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR13+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_MR13_HWSET_MR13_MRSMA) |
- P_Fld(0x08, SHU_HWSET_MR13_HWSET_MR13_OP));
- vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_VRCG+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x000d, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA) |
- P_Fld(0x00, SHU_HWSET_VRCG_HWSET_VRCG_OP) | P_Fld(0x00, SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, DVFS_WLRL_setting Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Enter
- vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
- P_Fld(0x00, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
- P_Fld(0x55, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, jump_ratio_setting_txrx_SHU_8_group Exit
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Enter
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL+(1*SHU_GRP_DDRPHY_OFFSET), P_Fld(0x1, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
- P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
- P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, dvfs_config_shuffle_registers Exit
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Enter
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
- // ========>SHUFFLE GROUP: 1, need_fifo: 1, sram_read_timing_option Exit
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0c, SHU_DQSOSCR_DQSOSCRCNT) |
- P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
- P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
- P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0844, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x0844, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x04b9, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0a6, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x06f, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*SHU_GRP_DRAMC_OFFSET)+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x036, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x024, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x0, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x0, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x06, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0, SHU_DQSOSC_SET0_DQSOSCENDIS) |
- P_Fld(0x021, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
- vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
- P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
- vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0+(1*SHU_GRP_DRAMC_OFFSET), P_Fld(0x26, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
- // Exit body
-}
-
-void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p)
-{
-// Enter body
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634
- DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)
- DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)
- DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00)
- DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00)
- DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00)
- DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00)
- DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0
- DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
- P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645
- CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)
- CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)
- CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00)
- CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00)
- DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00)
- DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00)
- DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655
- DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
- DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
- DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
- DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
- DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
- DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664
- CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
- CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
- CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
- CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
- DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
- DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682
- IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h0d (Mirror: 6'h01)
- DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00
- DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x0d, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
- P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625
- IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h7 (Mirror: 3'h4)
- IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
- IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
- IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
- IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
- IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x7, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
- P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
- P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
- P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734
- DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h13 (Mirror: 5'h00)
- RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
- RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
- SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfcb (Mirror: 12'h000)
- SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h035 (Mirror: 12'h000)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x13, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
- P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
- P_Fld(0xfcb, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x035, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604
- DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h13 (Mirror: 5'h00)
- DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h12 (Mirror: 5'h00)
- DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h12 (Mirror: 5'h00)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x13, MISC_SHU_RDAT_DATLAT) |
- P_Fld(0x12, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x12, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540
- RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
- RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
- RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
- RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h1 (Mirror: 3'h0)
- RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
- RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h3 (Mirror: 3'h0)
- RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
- P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
- P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
- P_Fld(0x3, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530
- RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'h8 (Mirror: 4'h0)
- RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1
- RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0
- RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'hb (Mirror: 4'h0)
- RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h9 (Mirror: 4'h0)
- RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h9 (Mirror: 4'h0)
- RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'hc (Mirror: 4'h0)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0x8, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
- P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
- P_Fld(0xb, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL) |
- P_Fld(0x9, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0xc, MISC_SHU_RANKCTL_RANKINCTL_PHY));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757
- RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h2 (Mirror: 4'h0)
- RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h2 (Mirror: 4'h0)
- RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h2 (Mirror: 4'h0)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
- P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x2, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352
- DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'hb (Mirror: 4'h0)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0xb, MISC_SHU_RK_DQSCTL_DQSINCTL);
-/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356
- DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'hb (Mirror: 4'h0)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0xb, MISC_SHU_RK_DQSCTL_DQSINCTL);
-/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624
- DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hb (Mirror: 4'h0)
- DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hf (Mirror: 4'h0)
- DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
- DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xb, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
-/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638
- DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h05 (Mirror: 7'h00)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x05, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631
- DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hd (Mirror: 4'h0)
- DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h1 (Mirror: 4'h0)
- DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
- DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642
- DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1b (Mirror: 7'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027
- DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hb (Mirror: 4'h0)
- DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'hf (Mirror: 4'h0)
- DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h0
- DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xb, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041
- DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h05 (Mirror: 7'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x05, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034
- DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'hd (Mirror: 4'h0)
- DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'h1 (Mirror: 4'h0)
- DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h0
- DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h1 (Mirror: 4'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0xd, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045
- DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1b (Mirror: 7'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550
- RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
- RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'ha (Mirror: 4'h0)
- RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
- RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
- FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
- RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
- RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
- RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0xa, MISC_SHU_ODTCTRL_RODT_LAT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
- P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2 (Mirror: 3'h0)
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1 (Mirror: 3'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646
- RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h6 (Mirror: 3'h0)
- RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h6 (Mirror: 3'h0)
- RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
- RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x6, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653
- RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h0
- RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h0
- RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
- RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049
- RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h6 (Mirror: 3'h0)
- RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h6 (Mirror: 3'h0)
- RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h0
- RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x6, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x6, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056
- RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h0
- RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h0
- RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h1 (Mirror: 3'h0)
- RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323
- DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h1 (Mirror: 1'h0)
- READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h1 (Mirror: 1'h0)
- DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h1 (Mirror: 1'h0)
- READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h1 (Mirror: 1'h0)
- DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
- READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720
- RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
- RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
- RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
- RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
- RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
- RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
- RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'hc (Mirror: 4'h0)
- RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
- RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
- RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h1 (Mirror: 4'h0)
- RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0xc, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370
- DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
- DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
- DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
- DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377
- DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
- DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
- DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
- DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602
- CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
- CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x05, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005
- CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
- CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x05, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607
- CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
- CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x0d, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010
- CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
- CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x0d, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612
- NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
- NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
- NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h0f (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x05, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x0f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015
- NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h05 (Mirror: 7'h00)
- NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h0b (Mirror: 8'h00)
- NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h0f (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x05, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x0f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618
- NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
- NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
- NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h11 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x0d, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x11, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021
- NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1b (Mirror: 7'h00)
- NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h0d (Mirror: 8'h00)
- NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h11 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x0d, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x11, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10426
- RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0
- RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0
- RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00
- RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h20 (Mirror: 6'h00)
- RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582
- RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
- RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
- SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h1f (Mirror: 6'h00)
- SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h1f (Mirror: 6'h00)
- ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x1f, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985
- RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
- RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
- SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h25 (Mirror: 6'h00)
- SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h25 (Mirror: 6'h00)
- ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x25, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x25, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10436
- RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0
- RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0
- RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00
- RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h20 (Mirror: 6'h00)
- RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x20, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592
- RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
- RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
- SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h2c (Mirror: 6'h00)
- SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h2c (Mirror: 6'h00)
- ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x2c, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x2c, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995
- RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
- RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
- SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h1f (Mirror: 6'h00)
- SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h1f (Mirror: 6'h00)
- ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x1f, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027
- DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
- DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4
- DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
- CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0
- FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0
- FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377
- DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0)
- DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h4 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h3 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
- P_Fld(0x4, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x3, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
- P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h5 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h4 (Mirror: 3'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x5, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h5 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h4 (Mirror: 3'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x4, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371
- TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h4 (Mirror: 3'h0)
- TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h4 (Mirror: 3'h0)
- TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x4, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
- P_Fld(0x4, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271
- TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h5 (Mirror: 3'h1)
- TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h5 (Mirror: 3'h1)
- TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1
- TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1
- TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h4 (Mirror: 3'h1)
- TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1
- TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_DQS0) |
- P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
- P_Fld(0x5, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282
- dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'h2 (Mirror: 4'h1)
- dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'h3 (Mirror: 4'h1)
- dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1
- dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1
- dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'h7 (Mirror: 4'h1)
- dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'h0 (Mirror: 4'h1)
- dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1
- dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_DQS0) |
- P_Fld(0x3, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0x7, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
- P_Fld(0x0, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746
- TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h5 (Mirror: 3'h1)
- TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h5 (Mirror: 3'h1)
- TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
- TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
- TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
- TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768
- TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h5 (Mirror: 3'h1)
- TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h5 (Mirror: 3'h1)
- TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
- TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
- TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
- TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790
- dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'h1
- dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'h1
- dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
- dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
- dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h5 (Mirror: 4'h1)
- dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h5 (Mirror: 4'h1)
- dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
- dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x5, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812
- dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'h1
- dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'h1
- dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
- dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
- dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h5 (Mirror: 4'h1)
- dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h5 (Mirror: 4'h1)
- dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
- dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x5, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757
- TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h5 (Mirror: 3'h1)
- TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h5 (Mirror: 3'h1)
- TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
- TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
- TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
- TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x5, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779
- TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h5 (Mirror: 3'h1)
- TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h5 (Mirror: 3'h1)
- TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
- TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
- TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h5 (Mirror: 3'h1)
- TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
- TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x5, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801
- dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'h2 (Mirror: 4'h1)
- dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'h2 (Mirror: 4'h1)
- dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
- dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
- dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h6 (Mirror: 4'h1)
- dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h6 (Mirror: 4'h1)
- dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
- dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0x2, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x6, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823
- dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'h2 (Mirror: 4'h1)
- dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'h2 (Mirror: 4'h1)
- dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
- dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
- dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h6 (Mirror: 4'h1)
- dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h6 (Mirror: 4'h1)
- dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
- dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0x2, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x6, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834
- BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h01f (Mirror: 11'h000)
- BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h025 (Mirror: 11'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x025, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844
- BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h01f (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h025 (Mirror: 11'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x025, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882
- BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h01f (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h025 (Mirror: 11'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x025, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839
- BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h02c (Mirror: 11'h000)
- BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h01f (Mirror: 11'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x01f, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849
- BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h02c (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h01f (Mirror: 11'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x01f, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887
- BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h02c (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h01f (Mirror: 11'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x02c, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x01f, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892
- RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h25 (Mirror: 6'h00)
- RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h1f (Mirror: 6'h00)
- RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h25 (Mirror: 6'h00)
- RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h1f (Mirror: 6'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x25, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x25, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899
- RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h1f (Mirror: 6'h00)
- RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h2c (Mirror: 6'h00)
- RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h1f (Mirror: 6'h00)
- RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h2c (Mirror: 6'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x2c, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x1f, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x2c, SHURK_PI_RK0_ARPI_DQM_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428
- TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h14 (Mirror: 8'h00)
- TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h14 (Mirror: 8'h00)
- TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h14 (Mirror: 8'h00)
- TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h14 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442
- TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h14 (Mirror: 8'h00)
- TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h14 (Mirror: 8'h00)
- TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h14 (Mirror: 8'h00)
- TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h14 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x14, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470
- TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h14 (Mirror: 8'h00)
- TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
- TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x14, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435
- TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h04 (Mirror: 8'h00)
- TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h04 (Mirror: 8'h00)
- TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h04 (Mirror: 8'h00)
- TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h04 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x04, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449
- TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h04 (Mirror: 8'h00)
- TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h04 (Mirror: 8'h00)
- TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h04 (Mirror: 8'h00)
- TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h04 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x04, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476
- TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h04 (Mirror: 8'h00)
- TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
- TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x04, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838
- TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h34 (Mirror: 8'h00)
- TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h34 (Mirror: 8'h00)
- TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h34 (Mirror: 8'h00)
- TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h34 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
- P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
- P_Fld(0x34, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852
- TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h34 (Mirror: 8'h00)
- TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h34 (Mirror: 8'h00)
- TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h34 (Mirror: 8'h00)
- TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h34 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
- P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
- P_Fld(0x34, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879
- TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h34 (Mirror: 8'h00)
- TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00
- TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x34, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
- P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345
- TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h3 (Mirror: 4'h0)
- TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h3 (Mirror: 4'h0)
- TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x3, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
- P_Fld(0x3, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ9_0 ral_reg_DDRPHY_blk_SHU_B1_DQ9_0 - @9248
- RG_ARPI_RESERVE_B1 uvm_reg_field ... RW SHU_B1_DQ9_0[31:0]=32'hce301f15 (Mirror: 32'hce341f15)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xce301f15, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_WCK_WR_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0 - @4936
- WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h5 (Mirror: 4'h1)
- WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h5 (Mirror: 4'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_WCK_WR_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1 - @4941
- WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h5 (Mirror: 4'h1)
- WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h5 (Mirror: 4'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x5, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_WCK_RD_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0 - @4946
- WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h8 (Mirror: 4'h1)
- WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h8 (Mirror: 4'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-#if LP5_DDR4266_RDBI_WORKAROUND
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
-#else
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x7, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x7, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
-#endif
-
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_WCK_RD_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1 - @4951
- WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h8 (Mirror: 4'h1)
- WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h8 (Mirror: 4'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x8, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_WCK_FS_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0 - @4956
- WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h4 (Mirror: 4'h1)
- WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h4 (Mirror: 4'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_WCK_FS_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1 - @4961
- WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h4 (Mirror: 4'h1)
- WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h4 (Mirror: 4'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x4, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041
- TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052
- TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01
- TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
- P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
- P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060
- TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071
- TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082
- dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1
- dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1
- dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
- dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1
- dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1
- dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1
- dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1
- dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018
- CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h3
- SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h3 (Mirror: 2'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x3, SHU_SREF_CTRL_CKEHCMD) |
- P_Fld(0x3, SHU_SREF_CTRL_SREF_CK_DLY));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036
- FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86 (Mirror: 8'h00)
- REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199
- TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h0
- TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0
- TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h0
- TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h0
- TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h0
- TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0
- TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h0
- TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0
- TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0
- TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0
- TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)
- TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h0
- TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h0
- TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0
- TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0
- TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h1 (Mirror: 1'h0)
- TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h0
- TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h0
- BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0
- BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0
- BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h1 (Mirror: 1'h0)
- TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h0
- TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h1 (Mirror: 1'h0)
- XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h1 (Mirror: 1'h0)
- TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h0
- TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0
- TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h0
- TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h0
- TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0
- TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h0
- XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x0, SHU_AC_TIME_05T_TRC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRFC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TXP_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRCD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TFAW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRRI_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_BGTWTR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWTR_M05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TMRR2MRW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x0, SHU_AC_TIME_05T_XRTW2R_M05T));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192
- XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h09 (Mirror: 5'h01)
- XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h0e (Mirror: 6'h01)
- XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h0 (Mirror: 4'h1)
- XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h0d (Mirror: 5'h01)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x09, SHU_ACTIM_XRT_XRTR2R) |
- P_Fld(0x0e, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x0, SHU_ACTIM_XRT_XRTW2R) |
- P_Fld(0x0d, SHU_ACTIM_XRT_XRTW2W));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138
- TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h9 (Mirror: 4'h1)
- CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h3 (Mirror: 3'h0)
- TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'h25 (Mirror: 8'h06)
- TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h3 (Mirror: 3'h0)
- TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2)
- TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'hf (Mirror: 4'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x9, SHU_ACTIM0_TWTR) |
- P_Fld(0x3, SHU_ACTIM0_CKELCKCNT) | P_Fld(0x25, SHU_ACTIM0_TWR) |
- P_Fld(0x3, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) |
- P_Fld(0xf, SHU_ACTIM0_TWTR_L));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147
- TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'hc (Mirror: 4'ha)
- TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'he (Mirror: 4'h8)
- TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'ha (Mirror: 4'h2)
- TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h0e (Mirror: 6'h04)
- TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h19 (Mirror: 5'h05)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xc, SHU_ACTIM1_TRPAB) |
- P_Fld(0xe, SHU_ACTIM1_TMRWCKEL) | P_Fld(0xa, SHU_ACTIM1_TRP) |
- P_Fld(0x0e, SHU_ACTIM1_TRAS) | P_Fld(0x19, SHU_ACTIM1_TRC));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155
- TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'h3 (Mirror: 4'h0)
- TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h0f (Mirror: 5'h0e)
- TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h4 (Mirror: 3'h0)
- TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h12 (Mirror: 6'h00)
- TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h0d (Mirror: 5'h05)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0x3, SHU_ACTIM2_TXP) |
- P_Fld(0x0f, SHU_ACTIM2_TMRRI) | P_Fld(0x4, SHU_ACTIM2_TRTP) |
- P_Fld(0x12, SHU_ACTIM2_TR2W) | P_Fld(0x0d, SHU_ACTIM2_TFAW));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163
- TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h3f (Mirror: 8'h00)
- MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
- TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
- TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h8a (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x3f, SHU_ACTIM3_TRFCPB) |
- P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
- P_Fld(0x8a, SHU_ACTIM3_TRFC));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170
- TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h09a (Mirror: 10'h028)
- TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h1b (Mirror: 6'h00)
- TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h17 (Mirror: 6'h00)
- TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h2e (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x09a, SHU_ACTIM4_TXREFCNT) |
- P_Fld(0x1b, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x17, SHU_ACTIM4_TMRR2W) |
- P_Fld(0x2e, SHU_ACTIM4_TZQCS));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177
- TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h20 (Mirror: 7'h00)
- TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h23 (Mirror: 7'h00)
- TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h30 (Mirror: 8'h00)
- TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x20, SHU_ACTIM5_TR2PD) |
- P_Fld(0x23, SHU_ACTIM5_TWTPD) | P_Fld(0x30, SHU_ACTIM5_TPBR2PBR) |
- P_Fld(0x0, SHU_ACTIM5_TPBR2ACT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184
- TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h10 (Mirror: 5'h1f)
- TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'ha (Mirror: 4'h0)
- TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'ha (Mirror: 4'h0)
- TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h17 (Mirror: 6'h00)
- TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h20 (Mirror: 6'h13)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x10, SHU_ACTIM6_TZQLAT2) |
- P_Fld(0xa, SHU_ACTIM6_TMRD) | P_Fld(0xa, SHU_ACTIM6_TMRW) |
- P_Fld(0x17, SHU_ACTIM6_TW2MRW) | P_Fld(0x20, SHU_ACTIM6_TR2MRW));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262
- TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0
- TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h1
- TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h1
- TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h4 (Mirror: 3'h2)
- TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h3 (Mirror: 2'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
- P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x1, SHU_CKECTRL_TPDE) |
- P_Fld(0x1, SHU_CKECTRL_TPDX) | P_Fld(0x4, SHU_CKECTRL_TCKEPRD) |
- P_Fld(0x3, SHU_CKECTRL_TCKESRX));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365
- REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2
- DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h7 (Mirror: 3'h4)
- DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
- P_Fld(0x7, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427
- LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h0
- TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'h4 (Mirror: 4'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
- P_Fld(0x4, SHU_LP5_CMD_TCSH));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIM7_0 ral_reg_DRAMC_blk_SHU_ACTIM7_0 - @5436
- TCSH_CSCAL uvm_reg_field ... RW SHU_ACTIM7_0[3:0]=4'h4 (Mirror: 4'h0)
- TCACSH uvm_reg_field ... RW SHU_ACTIM7_0[7:4]=4'h3 (Mirror: 4'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0x4, SHU_ACTIM7_TCSH_CSCAL) |
- P_Fld(0x3, SHU_ACTIM7_TCACSH));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_WCKCTRL_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_0 - @5407
- WCKRDOFF uvm_reg_field ... RW SHU_WCKCTRL_0[5:0]=6'h13 (Mirror: 6'h00)
- WCKRDOFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[7:7]=1'h0
- WCKWROFF uvm_reg_field ... RW SHU_WCKCTRL_0[13:8]=6'h0c (Mirror: 6'h00)
- WCKWROFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[15:15]=1'h0
- WCKDUAL uvm_reg_field ... RW SHU_WCKCTRL_0[16:16]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x13, SHU_WCKCTRL_WCKRDOFF) |
- P_Fld(0x0, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x0c, SHU_WCKCTRL_WCKWROFF) |
- P_Fld(0x0, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MISC_TX_PIPE_CTRL_0 ral_reg_DDRPHY_blk_SHU_MISC_TX_PIPE_CTRL_0 - @12708
- CMD_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- CK_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[1:1]=1'h1 (Mirror: 1'h0)
- TX_PIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[2:2]=1'h0
- CS_TXPIPE_BYPASS_EN uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[3:3]=1'h0
- SKIP_TXPIPE_BYPASS uvm_reg_field ... RW SHU_MISC_TX_PIPE_CTRL_0[8:8]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL, P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN) |
- P_Fld(0x1, SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN) |
- P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN) | P_Fld(0x0, SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828
- R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)
- R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0
- R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231
- R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100 (Mirror: 15'h0000)
- R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0
- R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728
- RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e
- RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0
- RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00
- RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0
- RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0
- RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)
- RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
- P_Fld(0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131
- RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e
- RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0
- RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00
- RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0
- RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0
- RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h3 (Mirror: 4'h0)
- RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
- P_Fld(0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490
- RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504
- RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518
- RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532
- RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546
- RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x59, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x59, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556
- RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h016 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h016 (Mirror: 9'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x016, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x016, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497
- RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511
- RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525
- RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539
- RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551
- RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x58, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561
- RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h015 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h015 (Mirror: 9'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x015, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x015, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893
- RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907
- RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921
- RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935
- RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h59 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h59 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949
- RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h59 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h59 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x59, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x59, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959
- RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h016 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h016 (Mirror: 9'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x016, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x016, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900
- RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914
- RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928
- RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942
- RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h58 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h58 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954
- RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h58 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h58 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x58, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x58, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964
- RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h015 (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h015 (Mirror: 9'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x015, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x015, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384
- RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
- RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
- P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
- P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
- P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787
- RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
- RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
- P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
- P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
- P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384
- RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
- P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
- P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
- P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787
- RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
- P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
- P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
- P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313
- RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h5f (Mirror: 7'h00)
- RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h5f (Mirror: 7'h00)
- RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h19 (Mirror: 6'h00)
- RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h19 (Mirror: 6'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x5f, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
- P_Fld(0x5f, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x19, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
- P_Fld(0x19, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716
- RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h5f (Mirror: 7'h00)
- RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h5f (Mirror: 7'h00)
- RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h19 (Mirror: 6'h00)
- RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h19 (Mirror: 6'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x5f, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
- P_Fld(0x5f, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x19, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
- P_Fld(0x19, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320
- RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10
- RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1
- RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1
- RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0
- RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1
- RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
- P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
- P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
- P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723
- RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10
- RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1
- RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1
- RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0
- RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1
- RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
- P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
- P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
- P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001
- FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h1 (Mirror: 1'h0)
- FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0
- FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h0
- DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h1 (Mirror: 1'h0)
- DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h0
- LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h1 (Mirror: 1'h0)
- LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h1 (Mirror: 1'h0)
- CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0
- BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0
- BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
- LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0
- BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1
- LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h1 (Mirror: 1'h0)
- SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x1, SHU_COMMON0_FREQDIV4) |
- P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x0, SHU_COMMON0_FREQDIV8) |
- P_Fld(0x1, SHU_COMMON0_DM64BITEN) | P_Fld(0x0, SHU_COMMON0_DLE256EN) |
- P_Fld(0x1, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) |
- P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
- P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
- P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) |
- P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427
- LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h1 (Mirror: 1'h0)
- TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'h4
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x1, SHU_LP5_CMD_LP5_CMD1TO2EN) |
- P_Fld(0x4, SHU_LP5_CMD_TCSH));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255
- SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
- TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0
- REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000
- TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
- P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
- P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027
- DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1
- DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4
- DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5
- CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0
- FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
- FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356
- DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
- ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0
- ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
- PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
- REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
- REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
- P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
- P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
- P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996
- MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
- NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
- P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899
- TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0
- TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0
- DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0
- TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1
- DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0
- OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0
- DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0
- WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
- DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0
- DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0
- ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0
- TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0
- DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0
- DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0
- RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0
- DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
- P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
- P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
- P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
- P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
- P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
- P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
- P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
- P_Fld(0x0, TX_SET0_DRAMOEN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0)
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514
- DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0
- DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0
- r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0
- STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
- STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
- DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
- P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
- P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
- P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499
- DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)
- PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
- DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
- DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
- DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h2 (Mirror: 2'h1)
- DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1
- DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0
- STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
- STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
- DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0
- DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0
- DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
- P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x2, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
- P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562
- RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
- RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
- RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
- RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
- RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
- RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
- RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
- RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
- RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
- P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751
- DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h2 (Mirror: 2'h0)
- RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h1 (Mirror: 2'h0)
- RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h1 (Mirror: 2'h0)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
- P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x1, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0)
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122
- HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002
- HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h3f (Mirror: 8'h12)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
- P_Fld(0x3f, SHU_HWSET_MR2_HWSET_MR2_OP));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384
- tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h72 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h09 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
- P_Fld(0x72, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x09, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
- P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523
- r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0
- r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
- r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
- r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
- P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
- P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
-/*TINFO=---===BROADCAST OFF!===---*/
- DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
-/*TINFO=---===BROADCAST ON!===---*/
- DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
-// ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338
- DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h15 (Mirror: 8'h00)
- DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0
- DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0
- DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x15, SHU_DQSOSCR_DQSOSCRCNT) |
- P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
- P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332
- DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1
- DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h012 (Mirror: 10'h00f)
- DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
- P_Fld(0x012, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906
- DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h025c (Mirror: 16'h0000)
- DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h025c (Mirror: 16'h0000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x025c, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x025c, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911
- DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0159 (Mirror: 16'h0000)
- DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0159 (Mirror: 16'h0000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x0159, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916
- DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h00d (Mirror: 12'h001)
- DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h009 (Mirror: 12'h001)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x00d, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x009, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921
- DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h004 (Mirror: 12'h001)
- DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h002 (Mirror: 12'h001)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x004, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h17 (Mirror: 6'h0e)
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x17, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351
- ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0000
- TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1f (Mirror: 5'h1b)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0000, SHU_ZQ_SET0_ZQCSCNT) |
- P_Fld(0x1f, SHU_ZQ_SET0_TZQLAT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351
- ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
- TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1f
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
- P_Fld(0x1f, SHU_ZQ_SET0_TZQLAT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036
- FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h86
- REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x86, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828
- R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0100
- R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0100, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231
- R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0100
- R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0100, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'ha (Mirror: 4'h0)
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h1 (Mirror: 1'h0)
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h1 (Mirror: 1'h0)
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h2
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0xa, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x2, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'ha (Mirror: 4'h0)
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h1 (Mirror: 1'h0)
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h1 (Mirror: 1'h0)
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h2
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h1
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0xa, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x2, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794
- RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0
- RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0
- RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0
- RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0
- RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0
- RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0
- RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0
- RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0
- RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h2
- RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
- P_Fld(0x2, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
-/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Name Type Size Value
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197
- RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0
- RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0
- RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0
- RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0
- RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0
- RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0
- RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0
- RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0
- RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h2
- RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-*/
-vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
- P_Fld(0x2, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
-// Exit body
-}
-
-void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p)
-{
- // Enter body
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Enter:
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING1_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING1_0 - @12634
- DQDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[4:0]=5'h08 (Mirror: 5'h00)
- DQDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[9:5]=5'h06 (Mirror: 5'h00)
- DQSDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[14:10]=5'h08 (Mirror: 5'h00)
- DQSDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING1_0[19:15]=5'h06 (Mirror: 5'h00)
- DQSDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[24:20]=5'h08 (Mirror: 5'h00)
- DQSDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING1_0[29:25]=5'h06 (Mirror: 5'h00)
- DIS_IMP_ODTN_track uvm_reg_field ... RW SHU_MISC_DRVING1_0[30:30]=1'h0
- DIS_IMPCAL_HW uvm_reg_field ... RW SHU_MISC_DRVING1_0[31:31]=1'h0
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(0x08, SHU_MISC_DRVING1_DQDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQDRVP2) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(0x08, SHU_MISC_DRVING1_DQSDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK) |
- P_Fld(0x0, SHU_MISC_DRVING1_DIS_IMPCAL_HW));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING2_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING2_0 - @12645
- CMDDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[4:0]=5'h08 (Mirror: 5'h00)
- CMDDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[9:5]=5'h06 (Mirror: 5'h00)
- CMDDRVN2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[14:10]=5'h08 (Mirror: 5'h00)
- CMDDRVP2 uvm_reg_field ... RW SHU_MISC_DRVING2_0[19:15]=5'h06 (Mirror: 5'h00)
- DQDRVN1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[24:20]=5'h08 (Mirror: 5'h00)
- DQDRVP1 uvm_reg_field ... RW SHU_MISC_DRVING2_0[29:25]=5'h06 (Mirror: 5'h00)
- DIS_IMPCAL_ODT_EN uvm_reg_field ... RW SHU_MISC_DRVING2_0[31:31]=1'h0
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING2, P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(0x08, SHU_MISC_DRVING2_CMDDRVN2) |
- P_Fld(0x06, SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(0x08, SHU_MISC_DRVING2_DQDRVN1) |
- P_Fld(0x06, SHU_MISC_DRVING2_DQDRVP1) | P_Fld(0x0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING3_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING3_0 - @12655
- DQODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[4:0]=5'h0a (Mirror: 5'h00)
- DQODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[9:5]=5'h0a (Mirror: 5'h00)
- DQSODTN uvm_reg_field ... RW SHU_MISC_DRVING3_0[14:10]=5'h0a (Mirror: 5'h00)
- DQSODTP uvm_reg_field ... RW SHU_MISC_DRVING3_0[19:15]=5'h0a (Mirror: 5'h00)
- DQSODTN2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[24:20]=5'h0a (Mirror: 5'h00)
- DQSODTP2 uvm_reg_field ... RW SHU_MISC_DRVING3_0[29:25]=5'h0a (Mirror: 5'h00)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING3, P_Fld(0x0a, SHU_MISC_DRVING3_DQODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQODTP2) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP) | P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING3_DQSODTP2));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING4_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING4_0 - @12664
- CMDODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[4:0]=5'h0a (Mirror: 5'h00)
- CMDODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[9:5]=5'h0a (Mirror: 5'h00)
- CMDODTN2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[14:10]=5'h0a (Mirror: 5'h00)
- CMDODTP2 uvm_reg_field ... RW SHU_MISC_DRVING4_0[19:15]=5'h0a (Mirror: 5'h00)
- DQODTN1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[24:20]=5'h0a (Mirror: 5'h00)
- DQODTP1 uvm_reg_field ... RW SHU_MISC_DRVING4_0[29:25]=5'h0a (Mirror: 5'h00)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING4, P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP1) | P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTN2) |
- P_Fld(0x0a, SHU_MISC_DRVING4_CMDODTP2) | P_Fld(0x0a, SHU_MISC_DRVING4_DQODTN1) |
- P_Fld(0x0a, SHU_MISC_DRVING4_DQODTP1));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_DRVING6_0 ral_reg_DDRPHY_blk_SHU_MISC_DRVING6_0 - @12682
- IMP_TXDLY_CMD uvm_reg_field ... RW SHU_MISC_DRVING6_0[5:0]=6'h11 (Mirror: 6'h01)
- DQCODTN1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[24:20]=5'h00
- DQCODTP1 uvm_reg_field ... RW SHU_MISC_DRVING6_0[29:25]=5'h00
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING6, P_Fld(0x11, SHU_MISC_DRVING6_IMP_TXDLY_CMD) |
- P_Fld(0x00, SHU_MISC_DRVING6_DQCODTN1) | P_Fld(0x00, SHU_MISC_DRVING6_DQCODTP1));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_IMPCAL1_0 ral_reg_DDRPHY_blk_SHU_MISC_IMPCAL1_0 - @12625
- IMPCAL_CHKCYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[2:0]=3'h1 (Mirror: 3'h4)
- IMPDRVP uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[8:4]=5'h00
- IMPDRVN uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[16:12]=5'h00
- IMPCAL_CALEN_CYCLE uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[19:17]=3'h4
- IMPCALCNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[27:20]=8'h03 (Mirror: 8'h00)
- IMPCAL_CALICNT uvm_reg_field ... RW SHU_MISC_IMPCAL1_0[31:28]=4'h8
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_IMPCAL1, P_Fld(0x1, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE) |
- P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVP) | P_Fld(0x00, SHU_MISC_IMPCAL1_IMPDRVN) |
- P_Fld(0x4, SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(0x03, SHU_MISC_IMPCAL1_IMPCALCNT) |
- P_Fld(0x8, SHU_MISC_IMPCAL1_IMPCAL_CALICNT));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, IMP golden setting Exit:
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Enter:
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_RDSEL_TRACK_0 ral_reg_DDRPHY_blk_SHU_MISC_RDSEL_TRACK_0 - @12734
- DMDATLAT_i uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[4:0]=5'h0d (Mirror: 5'h00)
- RDSEL_HWSAVE_MSK uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[6:6]=1'h1 (Mirror: 1'h0)
- RDSEL_TRACK_EN uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[7:7]=1'h0
- SHU_GW_THRD_NEG uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[19:8]=12'hfb9 (Mirror: 12'h000)
- SHU_GW_THRD_POS uvm_reg_field ... RW SHU_MISC_RDSEL_TRACK_0[31:20]=12'h047 (Mirror: 12'h000)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x0d, SHU_MISC_RDSEL_TRACK_DMDATLAT_I) |
- P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK) | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN) |
- P_Fld(0xfb9, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG) | P_Fld(0x047, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RDAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RDAT_0 - @12604
- DATLAT uvm_reg_field ... RW MISC_SHU_RDAT_0[4:0]=5'h0d (Mirror: 5'h00)
- DATLAT_DSEL uvm_reg_field ... RW MISC_SHU_RDAT_0[12:8]=5'h0c (Mirror: 5'h00)
- DATLAT_DSEL_PHY uvm_reg_field ... RW MISC_SHU_RDAT_0[20:16]=5'h0c (Mirror: 5'h00)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(0x0d, MISC_SHU_RDAT_DATLAT) |
- P_Fld(0x0c, MISC_SHU_RDAT_DATLAT_DSEL) | P_Fld(0x0c, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_PHY_RX_CTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_PHY_RX_CTRL_0 - @12540
- RANK_RXDLY_UPDLAT_EN uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[8:8]=1'h1 (Mirror: 1'h0)
- RANK_RXDLY_UPD_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[11:9]=3'h2 (Mirror: 3'h0)
- RX_IN_GATE_EN_PRE_OFFSET uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[15:14]=2'h2 (Mirror: 2'h0)
- RX_IN_GATE_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[18:16]=3'h0
- RX_IN_GATE_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[22:20]=3'h1 (Mirror: 3'h0)
- RX_IN_BUFF_EN_HEAD uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[26:24]=3'h1 (Mirror: 3'h0)
- RX_IN_BUFF_EN_TAIL uvm_reg_field ... RW MISC_SHU_PHY_RX_CTRL_0[30:28]=3'h0
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN) |
- P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET) | P_Fld(0x2, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET) |
- P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD) | P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL) |
- P_Fld(0x1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD) | P_Fld(0x0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RANKCTL_0 ral_reg_DDRPHY_blk_MISC_SHU_RANKCTL_0 - @12530
- RANKINCTL_RXDLY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[3:0]=4'hf (Mirror: 4'h0)
- RANK_RXDLY_OPT uvm_reg_field ... RW MISC_SHU_RANKCTL_0[4:4]=1'h1
- RANKSEL_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_RANKCTL_0[15:15]=1'h0
- RANKINCTL_STB uvm_reg_field ... RW MISC_SHU_RANKCTL_0[19:16]=4'h2 (Mirror: 4'h0)
- RANKINCTL uvm_reg_field ... RW MISC_SHU_RANKCTL_0[23:20]=4'h0
- RANKINCTL_ROOT1 uvm_reg_field ... RW MISC_SHU_RANKCTL_0[27:24]=4'h0
- RANKINCTL_PHY uvm_reg_field ... RW MISC_SHU_RANKCTL_0[31:28]=4'h4 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(0xf, MISC_SHU_RANKCTL_RANKINCTL_RXDLY) |
- P_Fld(0x1, MISC_SHU_RANKCTL_RANK_RXDLY_OPT) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN) |
- P_Fld(0x2, MISC_SHU_RANKCTL_RANKINCTL_STB) | P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL) |
- P_Fld(0x0, MISC_SHU_RANKCTL_RANKINCTL_ROOT1) | P_Fld(0x4, MISC_SHU_RANKCTL_RANKINCTL_PHY));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RANK_SEL_LAT_0 ral_reg_DDRPHY_blk_MISC_SHU_RANK_SEL_LAT_0 - @12757
- RANK_SEL_LAT_B0 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[3:0]=4'h1 (Mirror: 4'h0)
- RANK_SEL_LAT_B1 uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[7:4]=4'h1 (Mirror: 4'h0)
- RANK_SEL_LAT_CA uvm_reg_field ... RW MISC_SHU_RANK_SEL_LAT_0[11:8]=4'h1 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
- P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x1, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCTL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_0 - @12352
- DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_0[3:0]=4'h2 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL, 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
- /*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCTL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCTL_0_1 - @12356
- DQSINCTL uvm_reg_field ... RW MISC_SHU_RK_DQSCTL_0_1[3:0]=4'h2 (Mirror: 4'h0)
- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_RK_DQSCTL+(1*DDRPHY_AO_RANK_OFFSET), 0x2, MISC_SHU_RK_DQSCTL_DQSINCTL);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0 - @7624
- DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hf (Mirror: 4'h0)
- DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h7 (Mirror: 4'h0)
- DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
- DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h2 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY, P_Fld(0xf, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0x7, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x1, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_0 - @7638
- DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY, 0x0b, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1 - @7631
- DQSIEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h2 (Mirror: 4'h0)
- DQSIEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'ha (Mirror: 4'h0)
- DQSIEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h2 (Mirror: 4'h0)
- DQSIEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h2 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) |
- P_Fld(0xa, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0) | P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) |
- P_Fld(0x2, SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_DQSIEN_PI_DLY_0_1 - @7642
- DQSIEN_PI_B0 uvm_reg_field ... RW SHU_RK_B0_DQSIEN_PI_DLY_0_1[6:0]=7'h1e (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1e, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0 - @9027
- DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[3:0]=4'hf (Mirror: 4'h0)
- DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[7:4]=4'h7 (Mirror: 4'h0)
- DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[19:16]=4'h1 (Mirror: 4'h0)
- DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_0[23:20]=4'h2 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY, P_Fld(0xf, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0x7, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x1, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_PI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_0 - @9041
- DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_0[6:0]=7'h0b (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY, 0x0b, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1 - @9034
- DQSIEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[3:0]=4'h2 (Mirror: 4'h0)
- DQSIEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[7:4]=4'ha (Mirror: 4'h0)
- DQSIEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[19:16]=4'h2 (Mirror: 4'h0)
- DQSIEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_MCK_UI_DLY_0_1[23:20]=4'h2 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) |
- P_Fld(0xa, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1) | P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) |
- P_Fld(0x2, SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_DQSIEN_PI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_DQSIEN_PI_DLY_0_1 - @9045
- DQSIEN_PI_B1 uvm_reg_field ... RW SHU_RK_B1_DQSIEN_PI_DLY_0_1[6:0]=7'h1e (Mirror: 7'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY+(1*DDRPHY_AO_RANK_OFFSET), 0x1e, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_ODTCTRL_0 ral_reg_DDRPHY_blk_MISC_SHU_ODTCTRL_0 - @12550
- RODTEN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- RODTENSTB_SELPH_CG_IG uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[1:1]=1'h0
- RODT_LAT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[7:4]=4'h0
- RODTEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[15:15]=1'h0
- RODTDLY_LAT_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[25:24]=2'h0
- FIXRODT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[27:27]=1'h0
- RODTEN_OPT uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[29:29]=1'h1
- RODTE2 uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[30:30]=1'h1 (Mirror: 1'h0)
- RODTE uvm_reg_field ... RW MISC_SHU_ODTCTRL_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_ODTCTRL, P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODT_LAT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN) | P_Fld(0x0, MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT) |
- P_Fld(0x0, MISC_SHU_ODTCTRL_FIXRODT) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTEN_OPT) |
- P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE2) | P_Fld(0x1, MISC_SHU_ODTCTRL_RODTE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h0
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h0
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h0
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h0
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1 (Mirror: 3'h0)
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1 (Mirror: 1'h0)
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0 - @7646
- RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h2 (Mirror: 3'h0)
- RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h2 (Mirror: 3'h0)
- RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h3 (Mirror: 3'h0)
- RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY, P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x2, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1 - @7653
- RODTEN_UI_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h5 (Mirror: 3'h0)
- RODTEN_UI_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h5 (Mirror: 3'h0)
- RODTEN_MCK_P0_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h3 (Mirror: 3'h0)
- RODTEN_MCK_P1_B0 uvm_reg_field ... RW SHU_RK_B0_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) |
- P_Fld(0x5, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0) | P_Fld(0x3, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) |
- P_Fld(0x0, SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0 - @9049
- RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[2:0]=3'h2 (Mirror: 3'h0)
- RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[6:4]=3'h2 (Mirror: 3'h0)
- RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[18:16]=3'h3 (Mirror: 3'h0)
- RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_0[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY, P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x2, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 ral_reg_DDRPHY_blk_SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1 - @9056
- RODTEN_UI_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[2:0]=3'h5 (Mirror: 3'h0)
- RODTEN_UI_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[6:4]=3'h5 (Mirror: 3'h0)
- RODTEN_MCK_P0_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[18:16]=3'h3 (Mirror: 3'h0)
- RODTEN_MCK_P1_B1 uvm_reg_field ... RW SHU_RK_B1_RODTEN_MCK_UI_DLY_0_1[22:20]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) |
- P_Fld(0x5, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1) | P_Fld(0x3, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) |
- P_Fld(0x0, SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_RX_CG_SET0_0 ral_reg_DRAMC_blk_SHU_RX_CG_SET0_0 - @5323
- DLE_LAST_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[0:0]=1'h0
- READ_START_EXTEND3 uvm_reg_field ... RW SHU_RX_CG_SET0_0[1:1]=1'h0
- DLE_LAST_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[2:2]=1'h0
- READ_START_EXTEND2 uvm_reg_field ... RW SHU_RX_CG_SET0_0[3:3]=1'h0
- DLE_LAST_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[4:4]=1'h1 (Mirror: 1'h0)
- READ_START_EXTEND1 uvm_reg_field ... RW SHU_RX_CG_SET0_0[5:5]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_RX_CG_SET0, P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND3) |
- P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND3) | P_Fld(0x0, SHU_RX_CG_SET0_DLE_LAST_EXTEND2) |
- P_Fld(0x0, SHU_RX_CG_SET0_READ_START_EXTEND2) | P_Fld(0x1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
- P_Fld(0x1, SHU_RX_CG_SET0_READ_START_EXTEND1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_RANK_SELPH_UI_DLY_0 ral_reg_DDRPHY_blk_SHU_B0_RANK_SELPH_UI_DLY_0 - @7890
- RANKSEL_UI_DLY_P0_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[2:0]=3'h0
- RANKSEL_UI_DLY_P1_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[6:4]=3'h0
- RANKSEL_MCK_DLY_P0_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[18:16]=3'h1 (Mirror: 3'h0)
- RANKSEL_MCK_DLY_P1_B0 uvm_reg_field ... RW SHU_B0_RANK_SELPH_UI_DLY_0[22:20]=3'h1 (Mirror: 3'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY, P_Fld(0x0, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B0) |
- P_Fld(0x0, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B0) | P_Fld(0x1, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0) |
- P_Fld(0x1, SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_RANK_SELPH_UI_DLY_0 ral_reg_DDRPHY_blk_SHU_B1_RANK_SELPH_UI_DLY_0 - @9293
- RANKSEL_UI_DLY_P0_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[2:0]=3'h0
- RANKSEL_UI_DLY_P1_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[6:4]=3'h0
- RANKSEL_MCK_DLY_P0_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[18:16]=3'h1 (Mirror: 3'h0)
- RANKSEL_MCK_DLY_P1_B1 uvm_reg_field ... RW SHU_B1_RANK_SELPH_UI_DLY_0[22:20]=3'h1 (Mirror: 3'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY, P_Fld(0x0, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B1) |
- P_Fld(0x0, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B1) | P_Fld(0x1, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1) |
- P_Fld(0x1, SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_RANK_SEL_STB_0 ral_reg_DDRPHY_blk_SHU_MISC_RANK_SEL_STB_0 - @12720
- RANK_SEL_STB_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[0:0]=1'h1 (Mirror: 1'h0)
- RANK_SEL_STB_EN_B23 uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[1:1]=1'h0
- RANK_SEL_STB_SERMODE uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[3:2]=2'h0
- RANK_SEL_STB_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[4:4]=1'h1 (Mirror: 1'h0)
- RANK_SEL_RXDLY_TRACK uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[5:5]=1'h0
- RANK_SEL_STB_PHASE_EN uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[7:7]=1'h1 (Mirror: 1'h0)
- RANK_SEL_PHSINCTL uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[11:8]=4'h3 (Mirror: 4'h0)
- RANK_SEL_STB_UI_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[19:16]=4'h0
- RANK_SEL_STB_MCK_PLUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[23:20]=4'h0
- RANK_SEL_STB_UI_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[27:24]=4'h0
- RANK_SEL_STB_MCK_MINUS uvm_reg_field ... RW SHU_MISC_RANK_SEL_STB_0[31:28]=4'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK) |
- P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN) | P_Fld(0x3, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS) |
- P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS) | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCAL_0_0 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_0 - @12370
- DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[6:0]=7'h60 (Mirror: 7'h00)
- DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[7:7]=1'h1 (Mirror: 1'h0)
- DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[14:8]=7'h3f (Mirror: 7'h00)
- DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_0[15:15]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RK_DQSCAL_0_1 ral_reg_DDRPHY_blk_MISC_SHU_RK_DQSCAL_0_1 - @12377
- DQSIENLLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[6:0]=7'h60 (Mirror: 7'h00)
- DQSIENLLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[7:7]=1'h1 (Mirror: 1'h0)
- DQSIENHLMT uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[14:8]=7'h3f (Mirror: 7'h00)
- DQSIENHLMTEN uvm_reg_field ... RW MISC_SHU_RK_DQSCAL_0_1[15:15]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSCAL+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN) | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT) |
- P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_0 - @7602
- CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
- CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x1f, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_0 - @9005
- CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
- CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x1f, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_INI_UIPI_0_1 - @7607
- CURR_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)
- CURR_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0) |
- P_Fld(0x22, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_INI_UIPI_0_1 - @9010
- CURR_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)
- CURR_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1) |
- P_Fld(0x22, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_0 - @7612
- NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
- NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)
- NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_0[31:24]=8'h27 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x1f, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x27, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_NEXT_INI_UIPI_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_0 - @9015
- NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[6:0]=7'h0b (Mirror: 7'h00)
- NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[15:8]=8'h1f (Mirror: 8'h00)
- NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_0[31:24]=8'h27 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI, P_Fld(0x0b, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x1f, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x27, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_NEXT_INI_UIPI_0_1 - @7618
- NEXT_INI_PI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)
- NEXT_INI_UI_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)
- NEXT_INI_UI_P1_B0 uvm_reg_field ... RW SHU_R0_B0_NEXT_INI_UIPI_0_1[31:24]=8'h2a (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0) |
- P_Fld(0x22, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) | P_Fld(0x2a, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_NEXT_INI_UIPI_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_NEXT_INI_UIPI_0_1 - @9021
- NEXT_INI_PI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[6:0]=7'h1e (Mirror: 7'h00)
- NEXT_INI_UI_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[15:8]=8'h22 (Mirror: 8'h00)
- NEXT_INI_UI_P1_B1 uvm_reg_field ... RW SHU_R0_B1_NEXT_INI_UIPI_0_1[31:24]=8'h2a (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1e, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1) |
- P_Fld(0x22, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) | P_Fld(0x2a, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX data path setting Exit:
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Enter:
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_CA_CMD0_0_0 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_0 - @10426
- RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[2:0]=3'h0
- RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[6:4]=3'h0
- RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[13:8]=6'h00
- RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[21:16]=6'h10 (Mirror: 6'h00)
- RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0, P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_0 - @7582
- RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[2:0]=3'h0
- RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[6:4]=3'h0
- SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[13:8]=6'h26 (Mirror: 6'h00)
- SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[21:16]=6'h26 (Mirror: 6'h00)
- ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0, P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x26, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x26, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_DQ0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_0 - @8985
- RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[2:0]=3'h0
- RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[6:4]=3'h0
- SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[13:8]=6'h21 (Mirror: 6'h00)
- SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[21:16]=6'h21 (Mirror: 6'h00)
- ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0, P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x21, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_CA_CMD0_0_1 ral_reg_DDRPHY_blk_SHU_R0_CA_CMD0_0_1 - @10436
- RG_RX_ARCLK_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[2:0]=3'h0
- RG_RX_ARCLK_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[6:4]=3'h0
- RG_ARPI_CS uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[13:8]=6'h00
- RG_ARPI_CMD uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[21:16]=6'h10 (Mirror: 6'h00)
- RG_ARPI_CLK uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_CA uvm_reg_field ... RW SHU_R0_CA_CMD0_0_1[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_CA_CMD0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CS) |
- P_Fld(0x10, SHU_R0_CA_CMD0_RG_ARPI_CMD) | P_Fld(0x00, SHU_R0_CA_CMD0_RG_ARPI_CLK) |
- P_Fld(0x0, SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA) | P_Fld(0x0, SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_DQ0_0_1 - @7592
- RG_RX_ARDQS0_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[2:0]=3'h0
- RG_RX_ARDQS0_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[6:4]=3'h0
- SW_ARPI_DQ_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[13:8]=6'h21 (Mirror: 6'h00)
- SW_ARPI_DQM_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[21:16]=6'h21 (Mirror: 6'h00)
- ARPI_PBYTE_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B0 uvm_reg_field ... RW SHU_R0_B0_DQ0_0_1[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY) | P_Fld(0x21, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
- P_Fld(0x21, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0) | P_Fld(0x00, SHU_R0_B0_DQ0_ARPI_PBYTE_B0) |
- P_Fld(0x0, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0) | P_Fld(0x0, SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_DQ0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_DQ0_0_1 - @8995
- RG_RX_ARDQS1_R_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[2:0]=3'h0
- RG_RX_ARDQS1_F_DLY_DUTY uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[6:4]=3'h0
- SW_ARPI_DQ_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[13:8]=6'h22 (Mirror: 6'h00)
- SW_ARPI_DQM_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[21:16]=6'h22 (Mirror: 6'h00)
- ARPI_PBYTE_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[29:24]=6'h00
- DA_ARPI_DDR400_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[30:30]=1'h0
- DA_RX_ARDQSIEN_0D5UI_RK0_B1 uvm_reg_field ... RW SHU_R0_B1_DQ0_0_1[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_DQ0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY) |
- P_Fld(0x0, SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY) | P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
- P_Fld(0x22, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1) | P_Fld(0x00, SHU_R0_B1_DQ0_ARPI_PBYTE_B1) |
- P_Fld(0x0, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1) | P_Fld(0x0, SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027
- DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1 (Mirror: 1'h0)
- DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4
- DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5 (Mirror: 4'h0)
- CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0
- FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h0
- FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x0, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_APHY_TX_PICG_CTRL_0 ral_reg_DRAMC_blk_SHU_APHY_TX_PICG_CTRL_0 - @5377
- DDRPHY_CLK_EN_COMB_TX_PICG_CNT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[3:0]=4'h8 (Mirror: 4'h0)
- DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[6:4]=3'h1 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[10:8]=3'h1 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_OPT uvm_reg_field ... RW SHU_APHY_TX_PICG_CTRL_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x8, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT) |
- P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1) | P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0) |
- P_Fld(0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_APHY_TX_PICG_CTRL_0_0 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_0 - @4926
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[2:0]=3'h2 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_0[6:4]=3'h2 (Mirror: 3'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL, P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_APHY_TX_PICG_CTRL_0_1 ral_reg_DRAMC_blk_SHURK_APHY_TX_PICG_CTRL_0_1 - @4931
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[2:0]=3'h2 (Mirror: 3'h0)
- DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 uvm_reg_field ... RW SHURK_APHY_TX_PICG_CTRL_0_1[6:4]=3'h2 (Mirror: 3'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1) |
- P_Fld(0x2, SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_NEW_XRW2W_CTRL_0 ral_reg_DRAMC_blk_SHU_NEW_XRW2W_CTRL_0 - @5371
- TX_PI_UPDCTL_B0 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[18:16]=3'h2 (Mirror: 3'h0)
- TX_PI_UPDCTL_B1 uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[26:24]=3'h2 (Mirror: 3'h0)
- TXPI_UPD_MODE uvm_reg_field ... RW SHU_NEW_XRW2W_CTRL_0[31:31]=1'h0 (Mirror: 1'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_NEW_XRW2W_CTRL, P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0) |
- P_Fld(0x2, SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1) | P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_DQS0_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS0_0 - @5271
- TXDLY_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[2:0]=3'h2 (Mirror: 3'h1)
- TXDLY_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[6:4]=3'h2 (Mirror: 3'h1)
- TXDLY_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[10:8]=3'h1
- TXDLY_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[14:12]=3'h1
- TXDLY_OEN_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS0_0[18:16]=3'h2 (Mirror: 3'h1)
- TXDLY_OEN_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS0_0[22:20]=3'h2 (Mirror: 3'h1)
- TXDLY_OEN_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS0_0[26:24]=3'h1
- TXDLY_OEN_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS0_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS0) |
- P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_DQS3) | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS0) |
- P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS0_TXDLY_OEN_DQS3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_DQS1_0 ral_reg_DRAMC_blk_SHU_SELPH_DQS1_0 - @5282
- dly_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[3:0]=4'hd (Mirror: 4'h1)
- dly_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[7:4]=4'he (Mirror: 4'h1)
- dly_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[11:8]=4'h1
- dly_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[15:12]=4'h1
- dly_oen_DQS0 uvm_reg_field ... RW SHU_SELPH_DQS1_0[19:16]=4'ha (Mirror: 4'h1)
- dly_oen_DQS1 uvm_reg_field ... RW SHU_SELPH_DQS1_0[23:20]=4'hb (Mirror: 4'h1)
- dly_oen_DQS2 uvm_reg_field ... RW SHU_SELPH_DQS1_0[27:24]=4'h1
- dly_oen_DQS3 uvm_reg_field ... RW SHU_SELPH_DQS1_0[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0xd, SHU_SELPH_DQS1_DLY_DQS0) |
- P_Fld(0xe, SHU_SELPH_DQS1_DLY_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3) | P_Fld(0xa, SHU_SELPH_DQS1_DLY_OEN_DQS0) |
- P_Fld(0xb, SHU_SELPH_DQS1_DLY_OEN_DQS1) | P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS2) |
- P_Fld(0x1, SHU_SELPH_DQS1_DLY_OEN_DQS3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ0_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_0 - @4746
- TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[2:0]=3'h2 (Mirror: 3'h1)
- TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[6:4]=3'h2 (Mirror: 3'h1)
- TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[10:8]=3'h1
- TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[14:12]=3'h1
- TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[18:16]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[22:20]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[26:24]=3'h1
- TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0, P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ1_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_0 - @4768
- TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[2:0]=3'h2 (Mirror: 3'h1)
- TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[6:4]=3'h2 (Mirror: 3'h1)
- TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[10:8]=3'h1
- TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[14:12]=3'h1
- TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[18:16]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[22:20]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[26:24]=3'h1
- TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1, P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ2_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_0 - @4790
- dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[3:0]=4'hb (Mirror: 4'h1)
- dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[7:4]=4'hb (Mirror: 4'h1)
- dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[11:8]=4'h1
- dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[15:12]=4'h1
- dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[19:16]=4'h7 (Mirror: 4'h1)
- dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[23:20]=4'h7 (Mirror: 4'h1)
- dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[27:24]=4'h1
- dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_0[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2, P_Fld(0xb, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0xb, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x7, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ3_0_0 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_0 - @4812
- dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[3:0]=4'hb (Mirror: 4'h1)
- dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[7:4]=4'hb (Mirror: 4'h1)
- dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[11:8]=4'h1
- dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[15:12]=4'h1
- dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[19:16]=4'h7 (Mirror: 4'h1)
- dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[23:20]=4'h7 (Mirror: 4'h1)
- dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[27:24]=4'h1
- dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_0[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3, P_Fld(0xb, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0xb, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x7, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ0_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ0_0_1 - @4757
- TXDLY_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[2:0]=3'h2 (Mirror: 3'h1)
- TXDLY_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[6:4]=3'h2 (Mirror: 3'h1)
- TXDLY_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[10:8]=3'h1
- TXDLY_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[14:12]=3'h1
- TXDLY_OEN_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[18:16]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[22:20]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[26:24]=3'h1
- TXDLY_OEN_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ0_0_1[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ0+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ0) |
- P_Fld(0x2, SHURK_SELPH_DQ0_TXDLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_DQ3) | P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) |
- P_Fld(0x3, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ0_TXDLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ1_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ1_0_1 - @4779
- TXDLY_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[2:0]=3'h2 (Mirror: 3'h1)
- TXDLY_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[6:4]=3'h2 (Mirror: 3'h1)
- TXDLY_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[10:8]=3'h1
- TXDLY_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[14:12]=3'h1
- TXDLY_OEN_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[18:16]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[22:20]=3'h3 (Mirror: 3'h1)
- TXDLY_OEN_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[26:24]=3'h1
- TXDLY_OEN_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ1_0_1[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM0) |
- P_Fld(0x2, SHURK_SELPH_DQ1_TXDLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_DQM3) | P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) |
- P_Fld(0x3, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ2_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ2_0_1 - @4801
- dly_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[3:0]=4'hd (Mirror: 4'h1)
- dly_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[7:4]=4'hd (Mirror: 4'h1)
- dly_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[11:8]=4'h1
- dly_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[15:12]=4'h1
- dly_oen_DQ0 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[19:16]=4'h9 (Mirror: 4'h1)
- dly_oen_DQ1 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[23:20]=4'h9 (Mirror: 4'h1)
- dly_oen_DQ2 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[27:24]=4'h1
- dly_oen_DQ3 uvm_reg_field ... RW SHURK_SELPH_DQ2_0_1[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xd, SHURK_SELPH_DQ2_DLY_DQ0) |
- P_Fld(0xd, SHURK_SELPH_DQ2_DLY_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_DQ3) | P_Fld(0x9, SHURK_SELPH_DQ2_DLY_OEN_DQ0) |
- P_Fld(0x9, SHURK_SELPH_DQ2_DLY_OEN_DQ1) | P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ2) |
- P_Fld(0x1, SHURK_SELPH_DQ2_DLY_OEN_DQ3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_SELPH_DQ3_0_1 ral_reg_DRAMC_blk_SHURK_SELPH_DQ3_0_1 - @4823
- dly_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[3:0]=4'hd (Mirror: 4'h1)
- dly_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[7:4]=4'hd (Mirror: 4'h1)
- dly_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[11:8]=4'h1
- dly_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[15:12]=4'h1
- dly_oen_DQM0 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[19:16]=4'h9 (Mirror: 4'h1)
- dly_oen_DQM1 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[23:20]=4'h9 (Mirror: 4'h1)
- dly_oen_DQM2 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[27:24]=4'h1
- dly_oen_DQM3 uvm_reg_field ... RW SHURK_SELPH_DQ3_0_1[31:28]=4'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_SELPH_DQ3+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xd, SHURK_SELPH_DQ3_DLY_DQM0) |
- P_Fld(0xd, SHURK_SELPH_DQ3_DLY_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_DQM3) | P_Fld(0x9, SHURK_SELPH_DQ3_DLY_OEN_DQM0) |
- P_Fld(0x9, SHURK_SELPH_DQ3_DLY_OEN_DQM1) | P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM2) |
- P_Fld(0x1, SHURK_SELPH_DQ3_DLY_OEN_DQM3));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL1_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_0 - @4834
- BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[10:0]=11'h026 (Mirror: 11'h000)
- BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_0[26:16]=11'h021 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1, P_Fld(0x026, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL2_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_0 - @4844
- BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[10:0]=11'h026 (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_0[26:16]=11'h021 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2, P_Fld(0x026, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL5_0_0 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_0 - @4882
- BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[10:0]=11'h026 (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_0[26:16]=11'h021 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5, P_Fld(0x026, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL1_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL1_0_1 - @4839
- BOOT_ORIG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[10:0]=11'h021 (Mirror: 11'h000)
- BOOT_ORIG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL1_0_1[26:16]=11'h022 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL1+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0) |
- P_Fld(0x022, SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL2_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL2_0_1 - @4849
- BOOT_TARG_UI_RK0_DQ0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[10:0]=11'h021 (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQ1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL2_0_1[26:16]=11'h022 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL2+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0) |
- P_Fld(0x022, SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQS2DQ_CAL5_0_1 ral_reg_DRAMC_blk_SHURK_DQS2DQ_CAL5_0_1 - @4887
- BOOT_TARG_UI_RK0_DQM0 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[10:0]=11'h021 (Mirror: 11'h000)
- BOOT_TARG_UI_RK0_DQM1 uvm_reg_field ... RW SHURK_DQS2DQ_CAL5_0_1[26:16]=11'h022 (Mirror: 11'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQS2DQ_CAL5+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x021, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0) |
- P_Fld(0x022, SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_PI_0_0 ral_reg_DRAMC_blk_SHURK_PI_0_0 - @4892
- RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_0[5:0]=6'h21 (Mirror: 6'h00)
- RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_0[13:8]=6'h26 (Mirror: 6'h00)
- RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_0[21:16]=6'h21 (Mirror: 6'h00)
- RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_0[29:24]=6'h26 (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_PI, P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x26, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x26, SHURK_PI_RK0_ARPI_DQM_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_PI_0_1 ral_reg_DRAMC_blk_SHURK_PI_0_1 - @4899
- RK0_ARPI_DQ_B1 uvm_reg_field ... RW SHURK_PI_0_1[5:0]=6'h22 (Mirror: 6'h00)
- RK0_ARPI_DQ_B0 uvm_reg_field ... RW SHURK_PI_0_1[13:8]=6'h21 (Mirror: 6'h00)
- RK0_ARPI_DQM_B1 uvm_reg_field ... RW SHURK_PI_0_1[21:16]=6'h22 (Mirror: 6'h00)
- RK0_ARPI_DQM_B0 uvm_reg_field ... RW SHURK_PI_0_1[29:24]=6'h21 (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_PI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x22, SHURK_PI_RK0_ARPI_DQ_B1) |
- P_Fld(0x21, SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(0x22, SHURK_PI_RK0_ARPI_DQM_B1) |
- P_Fld(0x21, SHURK_PI_RK0_ARPI_DQM_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_0 - @7428
- TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[15:8]=8'h2c (Mirror: 8'h00)
- TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[23:16]=8'h2c (Mirror: 8'h00)
- TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_0[31:24]=8'h2c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_0 - @7442
- TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[15:8]=8'h2c (Mirror: 8'h00)
- TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[23:16]=8'h2c (Mirror: 8'h00)
- TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_0[31:24]=8'h2c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x2c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_0 - @7470
- TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[7:0]=8'h2c (Mirror: 8'h00)
- TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[23:16]=8'h00
- TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_0[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3, P_Fld(0x2c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_0 - @8831
- TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[7:0]=8'h3c (Mirror: 8'h00)
- TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[15:8]=8'h3c (Mirror: 8'h00)
- TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[23:16]=8'h3c (Mirror: 8'h00)
- TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_0[31:24]=8'h3c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
- P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
- P_Fld(0x3c, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_0 - @8845
- TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[7:0]=8'h3c (Mirror: 8'h00)
- TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[15:8]=8'h3c (Mirror: 8'h00)
- TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[23:16]=8'h3c (Mirror: 8'h00)
- TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_0[31:24]=8'h3c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
- P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
- P_Fld(0x3c, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_0 - @8873
- TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[7:0]=8'h3c (Mirror: 8'h00)
- TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[23:16]=8'h00
- TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_0[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3, P_Fld(0x3c, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
- P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY0_0_1 - @7435
- TX_ARDQ0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[7:0]=8'h1c (Mirror: 8'h00)
- TX_ARDQ1_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[15:8]=8'h1c (Mirror: 8'h00)
- TX_ARDQ2_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[23:16]=8'h1c (Mirror: 8'h00)
- TX_ARDQ3_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY0_0_1[31:24]=8'h1c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY1_0_1 - @7449
- TX_ARDQ4_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[7:0]=8'h1c (Mirror: 8'h00)
- TX_ARDQ5_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[15:8]=8'h1c (Mirror: 8'h00)
- TX_ARDQ6_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[23:16]=8'h1c (Mirror: 8'h00)
- TX_ARDQ7_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY1_0_1[31:24]=8'h1c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) | P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
- P_Fld(0x1c, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_TXDLY3_0_1 - @7476
- TX_ARDQM0_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[7:0]=8'h1c (Mirror: 8'h00)
- TX_ARWCK_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[23:16]=8'h00
- TX_ARWCKB_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_TXDLY3_0_1[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x1c, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0) |
- P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0) | P_Fld(0x00, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY0_0_1 - @8838
- TX_ARDQ0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[7:0]=8'h18 (Mirror: 8'h00)
- TX_ARDQ1_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[15:8]=8'h18 (Mirror: 8'h00)
- TX_ARDQ2_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[23:16]=8'h18 (Mirror: 8'h00)
- TX_ARDQ3_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY0_0_1[31:24]=8'h18 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
- P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) | P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
- P_Fld(0x18, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY1_0_1 - @8852
- TX_ARDQ4_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[7:0]=8'h18 (Mirror: 8'h00)
- TX_ARDQ5_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[15:8]=8'h18 (Mirror: 8'h00)
- TX_ARDQ6_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[23:16]=8'h18 (Mirror: 8'h00)
- TX_ARDQ7_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY1_0_1[31:24]=8'h18 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
- P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) | P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
- P_Fld(0x18, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_TXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_TXDLY3_0_1 - @8879
- TX_ARDQM0_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[7:0]=8'h18 (Mirror: 8'h00)
- TX_ARWCK_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[23:16]=8'h00
- TX_ARWCKB_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_TXDLY3_0_1[31:24]=8'h00
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_TXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x18, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1) |
- P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1) | P_Fld(0x00, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_RANKCTL_0 ral_reg_DRAMC_blk_SHU_TX_RANKCTL_0 - @5345
- TXRANKINCTL_TXDLY uvm_reg_field ... RW SHU_TX_RANKCTL_0[3:0]=4'h1 (Mirror: 4'h0)
- TXRANKINCTL uvm_reg_field ... RW SHU_TX_RANKCTL_0[7:4]=4'h1 (Mirror: 4'h0)
- TXRANKINCTL_ROOT uvm_reg_field ... RW SHU_TX_RANKCTL_0[11:8]=4'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY) |
- P_Fld(0x1, SHU_TX_RANKCTL_TXRANKINCTL) | P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ9_0 ral_reg_DDRPHY_blk_SHU_B0_DQ9_0 - @7845
- RG_ARPI_RESERVE_B0 uvm_reg_field ... RW SHU_B0_DQ9_0[31:0]=32'h0c410eb3 (Mirror: 32'h0c430eb3)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ9, 0x0c410eb3, SHU_B0_DQ9_RG_ARPI_RESERVE_B0);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ9_0 ral_reg_DDRPHY_blk_SHU_B1_DQ9_0 - @9248
- RG_ARPI_RESERVE_B1 uvm_reg_field ... RW SHU_B1_DQ9_0[31:0]=32'hfa89b179 (Mirror: 32'hfa8bb179)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ9, 0xfa89b179, SHU_B1_DQ9_RG_ARPI_RESERVE_B1);
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX data path setting Exit:
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_WR_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_0 - @4936
- WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[3:0]=4'h3 (Mirror: 4'h1)
- WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_0[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK, P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_WR_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_MCK_0_1 - @4941
- WCK_WR_B0_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[3:0]=4'h3 (Mirror: 4'h1)
- WCK_WR_B1_MCK uvm_reg_field ... RW SHURK_WCK_WR_MCK_0_1[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) |
- P_Fld(0x3, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_RD_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_0 - @4946
- WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[3:0]=4'h5 (Mirror: 4'h1)
- WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_0[7:4]=4'h5 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- #if LP5_DDR4266_RDBI_WORKAROUND
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- #else
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK, P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- #endif
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_RD_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_MCK_0_1 - @4951
- WCK_RD_B0_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[3:0]=4'h5 (Mirror: 4'h1)
- WCK_RD_B1_MCK uvm_reg_field ... RW SHURK_WCK_RD_MCK_0_1[7:4]=4'h5 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- #if LP5_DDR4266_RDBI_WORKAROUND
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x5, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- #else
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) |
- P_Fld(0x4, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
- #endif
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_MCK_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_0 - @4956
- WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[3:0]=4'h2 (Mirror: 4'h1)
- WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_0[7:4]=4'h2 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK, P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_MCK_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_MCK_0_1 - @4961
- WCK_FS_B0_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[3:0]=4'h2 (Mirror: 4'h1)
- WCK_FS_B1_MCK uvm_reg_field ... RW SHURK_WCK_FS_MCK_0_1[7:4]=4'h2 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_MCK+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) |
- P_Fld(0x2, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_WR_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_WR_UI_0_0 - @4966
- WCK_WR_B0_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_0[3:0]=4'h3 (Mirror: 4'h1)
- WCK_WR_B1_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_0[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI, P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
- P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_WR_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_WR_UI_0_1 - @4971
- WCK_WR_B0_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_1[3:0]=4'h3 (Mirror: 4'h1)
- WCK_WR_B1_UI uvm_reg_field ... RW SHURK_WCK_WR_UI_0_1[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_WR_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B0_UI) |
- P_Fld(0x3, SHURK_WCK_WR_UI_WCK_WR_B1_UI));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_RD_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_RD_UI_0_0 - @4976
- WCK_RD_B0_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_0[3:0]=4'h3 (Mirror: 4'h1)
- WCK_RD_B1_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_0[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- #if LP5_DDR4266_RDBI_WORKAROUND
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI, P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
- P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
- #else
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI, P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
- P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
- #endif
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_RD_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_RD_UI_0_1 - @4981
- WCK_RD_B0_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_1[3:0]=4'h3 (Mirror: 4'h1)
- WCK_RD_B1_UI uvm_reg_field ... RW SHURK_WCK_RD_UI_0_1[7:4]=4'h3 (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- #if LP5_DDR4266_RDBI_WORKAROUND
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
- P_Fld(0x3, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
- #else
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_RD_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B0_UI) |
- P_Fld(0xb, SHURK_WCK_RD_UI_WCK_RD_B1_UI));
- #endif
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_UI_0_0 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_0 - @4986
- WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[3:0]=4'hb (Mirror: 4'h1)
- WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_0[7:4]=4'hb (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI, P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
- P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_WCK_FS_UI_0_1 ral_reg_DRAMC_blk_SHURK_WCK_FS_UI_0_1 - @4991
- WCK_FS_B0_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[3:0]=4'hb (Mirror: 4'h1)
- WCK_FS_B1_UI uvm_reg_field ... RW SHURK_WCK_FS_UI_0_1[7:4]=4'hb (Mirror: 4'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_WCK_FS_UI+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B0_UI) |
- P_Fld(0xb, SHURK_WCK_FS_UI_WCK_FS_B1_UI));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX WCK auto-generation set Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Enter:
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA1_0 ral_reg_DRAMC_blk_SHU_SELPH_CA1_0 - @5041
- TXDLY_CS uvm_reg_field ... RW SHU_SELPH_CA1_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_CKE uvm_reg_field ... RW SHU_SELPH_CA1_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_ODT uvm_reg_field ... RW SHU_SELPH_CA1_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RESET uvm_reg_field ... RW SHU_SELPH_CA1_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_WE uvm_reg_field ... RW SHU_SELPH_CA1_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_CAS uvm_reg_field ... RW SHU_SELPH_CA1_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RAS uvm_reg_field ... RW SHU_SELPH_CA1_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_CS1 uvm_reg_field ... RW SHU_SELPH_CA1_0[30:28]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CKE) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS) | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS) |
- P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA2_0 ral_reg_DRAMC_blk_SHU_SELPH_CA2_0 - @5052
- TXDLY_BA0 uvm_reg_field ... RW SHU_SELPH_CA2_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_BA1 uvm_reg_field ... RW SHU_SELPH_CA2_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_BA2 uvm_reg_field ... RW SHU_SELPH_CA2_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_CMD uvm_reg_field ... RW SHU_SELPH_CA2_0[20:16]=5'h01
- TXDLY_CKE1 uvm_reg_field ... RW SHU_SELPH_CA2_0[26:24]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0) |
- P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2) |
- P_Fld(0x01, SHU_SELPH_CA2_TXDLY_CMD) | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_CKE1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA3_0 ral_reg_DRAMC_blk_SHU_SELPH_CA3_0 - @5060
- TXDLY_RA0 uvm_reg_field ... RW SHU_SELPH_CA3_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_RA1 uvm_reg_field ... RW SHU_SELPH_CA3_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_RA2 uvm_reg_field ... RW SHU_SELPH_CA3_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RA3 uvm_reg_field ... RW SHU_SELPH_CA3_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_RA4 uvm_reg_field ... RW SHU_SELPH_CA3_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_RA5 uvm_reg_field ... RW SHU_SELPH_CA3_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RA6 uvm_reg_field ... RW SHU_SELPH_CA3_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_RA7 uvm_reg_field ... RW SHU_SELPH_CA3_0[30:28]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5) | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6) |
- P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA4_0 ral_reg_DRAMC_blk_SHU_SELPH_CA4_0 - @5071
- TXDLY_RA8 uvm_reg_field ... RW SHU_SELPH_CA4_0[2:0]=3'h0 (Mirror: 3'h1)
- TXDLY_RA9 uvm_reg_field ... RW SHU_SELPH_CA4_0[6:4]=3'h0 (Mirror: 3'h1)
- TXDLY_RA10 uvm_reg_field ... RW SHU_SELPH_CA4_0[10:8]=3'h0 (Mirror: 3'h1)
- TXDLY_RA11 uvm_reg_field ... RW SHU_SELPH_CA4_0[14:12]=3'h0 (Mirror: 3'h1)
- TXDLY_RA12 uvm_reg_field ... RW SHU_SELPH_CA4_0[18:16]=3'h0 (Mirror: 3'h1)
- TXDLY_RA13 uvm_reg_field ... RW SHU_SELPH_CA4_0[22:20]=3'h0 (Mirror: 3'h1)
- TXDLY_RA14 uvm_reg_field ... RW SHU_SELPH_CA4_0[26:24]=3'h0 (Mirror: 3'h1)
- TXDLY_RA15 uvm_reg_field ... RW SHU_SELPH_CA4_0[30:28]=3'h0 (Mirror: 3'h1)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13) | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14) |
- P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SELPH_CA5_0 ral_reg_DRAMC_blk_SHU_SELPH_CA5_0 - @5082
- dly_CS uvm_reg_field ... RW SHU_SELPH_CA5_0[2:0]=3'h1
- dly_CKE uvm_reg_field ... RW SHU_SELPH_CA5_0[6:4]=3'h1
- dly_ODT uvm_reg_field ... RW SHU_SELPH_CA5_0[10:8]=3'h0 (Mirror: 3'h1)
- dly_RESET uvm_reg_field ... RW SHU_SELPH_CA5_0[14:12]=3'h1
- dly_WE uvm_reg_field ... RW SHU_SELPH_CA5_0[18:16]=3'h1
- dly_CAS uvm_reg_field ... RW SHU_SELPH_CA5_0[22:20]=3'h1
- dly_RAS uvm_reg_field ... RW SHU_SELPH_CA5_0[26:24]=3'h1
- dly_CS1 uvm_reg_field ... RW SHU_SELPH_CA5_0[30:28]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA5, P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CKE) | P_Fld(0x0, SHU_SELPH_CA5_DLY_ODT) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_RESET) | P_Fld(0x1, SHU_SELPH_CA5_DLY_WE) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CAS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_RAS) |
- P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, TX CA golden setting Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Enter:
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SREF_CTRL_0 ral_reg_DRAMC_blk_SHU_SREF_CTRL_0 - @5018
- CKEHCMD uvm_reg_field ... RW SHU_SREF_CTRL_0[5:4]=2'h0 (Mirror: 2'h3)
- SREF_CK_DLY uvm_reg_field ... RW SHU_SREF_CTRL_0[29:28]=2'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_SREF_CTRL, P_Fld(0x0, SHU_SREF_CTRL_CKEHCMD) |
- P_Fld(0x0, SHU_SREF_CTRL_SREF_CK_DLY));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036
- FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h67 (Mirror: 8'h00)
- REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h000
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x67, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x000, SHU_HMR4_DVFS_CTRL0_REFRCNT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_AC_TIME_05T_0 ral_reg_DRAMC_blk_SHU_AC_TIME_05T_0 - @5199
- TRC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[0:0]=1'h1 (Mirror: 1'h0)
- TRFCPB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[1:1]=1'h0
- TRFC_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[2:2]=1'h1 (Mirror: 1'h0)
- TPBR2PBR_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[3:3]=1'h1 (Mirror: 1'h0)
- TXP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[4:4]=1'h1 (Mirror: 1'h0)
- TRTP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[5:5]=1'h0
- TRCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[6:6]=1'h1 (Mirror: 1'h0)
- TRP_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[7:7]=1'h0
- TRPAB_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[8:8]=1'h0
- TRAS_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[9:9]=1'h0
- TWR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[10:10]=1'h1 (Mirror: 1'h0)
- TRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[12:12]=1'h1 (Mirror: 1'h0)
- TFAW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[13:13]=1'h1 (Mirror: 1'h0)
- TCKEPRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[14:14]=1'h0
- TR2PD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[15:15]=1'h0
- TWTPD_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[16:16]=1'h0
- TMRRI_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[17:17]=1'h1 (Mirror: 1'h0)
- TMRWCKEL_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[18:18]=1'h1 (Mirror: 1'h0)
- BGTRRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[19:19]=1'h0
- BGTCCD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[20:20]=1'h0
- BGTWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[21:21]=1'h0
- TR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[22:22]=1'h1 (Mirror: 1'h0)
- TWTR_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[23:23]=1'h0
- XRTR2W_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[24:24]=1'h0
- TMRD_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[25:25]=1'h1 (Mirror: 1'h0)
- TMRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[26:26]=1'h0
- TMRR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[27:27]=1'h1 (Mirror: 1'h0)
- TW2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[28:28]=1'h1 (Mirror: 1'h0)
- TR2MRW_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[29:29]=1'h0
- TPBR2ACT_05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[30:30]=1'h1 (Mirror: 1'h0)
- XRTW2R_M05T uvm_reg_field ... RW SHU_AC_TIME_05T_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(0x1, SHU_AC_TIME_05T_TRC_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRFCPB_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRFC_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TPBR2PBR_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TXP_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRTP_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TRCD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRP_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TRPAB_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TRAS_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TWR_M05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TRRD_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TFAW_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TCKEPRD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2PD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TWTPD_M05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRRI_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TMRWCKEL_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTRRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_BGTCCD_05T) | P_Fld(0x0, SHU_AC_TIME_05T_BGTWTR_M05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TR2W_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TWTR_M05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_XRTR2W_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRD_05T) |
- P_Fld(0x0, SHU_AC_TIME_05T_TMRW_05T) | P_Fld(0x1, SHU_AC_TIME_05T_TMRR2MRW_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TW2MRW_05T) | P_Fld(0x0, SHU_AC_TIME_05T_TR2MRW_05T) |
- P_Fld(0x1, SHU_AC_TIME_05T_TPBR2ACT_05T) | P_Fld(0x1, SHU_AC_TIME_05T_XRTW2R_M05T));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM_XRT_0 ral_reg_DRAMC_blk_SHU_ACTIM_XRT_0 - @5192
- XRTR2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[4:0]=5'h1b (Mirror: 5'h01)
- XRTR2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[13:8]=6'h27 (Mirror: 6'h01)
- XRTW2R uvm_reg_field ... RW SHU_ACTIM_XRT_0[19:16]=4'h8 (Mirror: 4'h1)
- XRTW2W uvm_reg_field ... RW SHU_ACTIM_XRT_0[28:24]=5'h00 (Mirror: 5'h01)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(0x1b, SHU_ACTIM_XRT_XRTR2R) |
- P_Fld(0x27, SHU_ACTIM_XRT_XRTR2W) | P_Fld(0x8, SHU_ACTIM_XRT_XRTW2R) |
- P_Fld(0x00, SHU_ACTIM_XRT_XRTW2W));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM0_0 ral_reg_DRAMC_blk_SHU_ACTIM0_0 - @5138
- TWTR uvm_reg_field ... RW SHU_ACTIM0_0[3:0]=4'h6 (Mirror: 4'h1)
- CKELCKCNT uvm_reg_field ... RW SHU_ACTIM0_0[6:4]=3'h2 (Mirror: 3'h0)
- TWR uvm_reg_field ... RW SHU_ACTIM0_0[15:8]=8'hba (Mirror: 8'h06)
- TRRD uvm_reg_field ... RW SHU_ACTIM0_0[18:16]=3'h0
- TRCD uvm_reg_field ... RW SHU_ACTIM0_0[27:24]=4'ha (Mirror: 4'h2)
- TWTR_L uvm_reg_field ... RW SHU_ACTIM0_0[31:28]=4'hf (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM0, P_Fld(0x6, SHU_ACTIM0_TWTR) |
- P_Fld(0x2, SHU_ACTIM0_CKELCKCNT) | P_Fld(0xba, SHU_ACTIM0_TWR) |
- P_Fld(0x0, SHU_ACTIM0_TRRD) | P_Fld(0xa, SHU_ACTIM0_TRCD) |
- P_Fld(0xf, SHU_ACTIM0_TWTR_L));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM1_0 ral_reg_DRAMC_blk_SHU_ACTIM1_0 - @5147
- TRPAB uvm_reg_field ... RW SHU_ACTIM1_0[3:0]=4'hd (Mirror: 4'ha)
- TMRWCKEL uvm_reg_field ... RW SHU_ACTIM1_0[7:4]=4'h1 (Mirror: 4'h8)
- TRP uvm_reg_field ... RW SHU_ACTIM1_0[11:8]=4'h6 (Mirror: 4'h2)
- TRAS uvm_reg_field ... RW SHU_ACTIM1_0[21:16]=6'h07 (Mirror: 6'h04)
- TRC uvm_reg_field ... RW SHU_ACTIM1_0[28:24]=5'h13 (Mirror: 5'h05)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM1, P_Fld(0xd, SHU_ACTIM1_TRPAB) |
- P_Fld(0x1, SHU_ACTIM1_TMRWCKEL) | P_Fld(0x6, SHU_ACTIM1_TRP) |
- P_Fld(0x07, SHU_ACTIM1_TRAS) | P_Fld(0x13, SHU_ACTIM1_TRC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM2_0 ral_reg_DRAMC_blk_SHU_ACTIM2_0 - @5155
- TXP uvm_reg_field ... RW SHU_ACTIM2_0[3:0]=4'ha (Mirror: 4'h0)
- TMRRI uvm_reg_field ... RW SHU_ACTIM2_0[8:4]=5'h17 (Mirror: 5'h0e)
- TRTP uvm_reg_field ... RW SHU_ACTIM2_0[14:12]=3'h3 (Mirror: 3'h0)
- TR2W uvm_reg_field ... RW SHU_ACTIM2_0[21:16]=6'h33 (Mirror: 6'h00)
- TFAW uvm_reg_field ... RW SHU_ACTIM2_0[28:24]=5'h1c (Mirror: 5'h05)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM2, P_Fld(0xa, SHU_ACTIM2_TXP) |
- P_Fld(0x17, SHU_ACTIM2_TMRRI) | P_Fld(0x3, SHU_ACTIM2_TRTP) |
- P_Fld(0x33, SHU_ACTIM2_TR2W) | P_Fld(0x1c, SHU_ACTIM2_TFAW));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM3_0 ral_reg_DRAMC_blk_SHU_ACTIM3_0 - @5163
- TRFCPB uvm_reg_field ... RW SHU_ACTIM3_0[7:0]=8'h2b (Mirror: 8'h00)
- MANTMRR uvm_reg_field ... RW SHU_ACTIM3_0[11:8]=4'h4 (Mirror: 4'h0)
- TR2MRR uvm_reg_field ... RW SHU_ACTIM3_0[15:12]=4'h4 (Mirror: 4'h0)
- TRFC uvm_reg_field ... RW SHU_ACTIM3_0[23:16]=8'h4c (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM3, P_Fld(0x2b, SHU_ACTIM3_TRFCPB) |
- P_Fld(0x4, SHU_ACTIM3_MANTMRR) | P_Fld(0x4, SHU_ACTIM3_TR2MRR) |
- P_Fld(0x4c, SHU_ACTIM3_TRFC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM4_0 ral_reg_DRAMC_blk_SHU_ACTIM4_0 - @5170
- TXREFCNT uvm_reg_field ... RW SHU_ACTIM4_0[9:0]=10'h197 (Mirror: 10'h028)
- TMRR2MRW uvm_reg_field ... RW SHU_ACTIM4_0[15:10]=6'h0d (Mirror: 6'h00)
- TMRR2W uvm_reg_field ... RW SHU_ACTIM4_0[21:16]=6'h1f (Mirror: 6'h00)
- TZQCS uvm_reg_field ... RW SHU_ACTIM4_0[31:24]=8'h12 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM4, P_Fld(0x197, SHU_ACTIM4_TXREFCNT) |
- P_Fld(0x0d, SHU_ACTIM4_TMRR2MRW) | P_Fld(0x1f, SHU_ACTIM4_TMRR2W) |
- P_Fld(0x12, SHU_ACTIM4_TZQCS));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM5_0 ral_reg_DRAMC_blk_SHU_ACTIM5_0 - @5177
- TR2PD uvm_reg_field ... RW SHU_ACTIM5_0[6:0]=7'h0a (Mirror: 7'h00)
- TWTPD uvm_reg_field ... RW SHU_ACTIM5_0[14:8]=7'h6a (Mirror: 7'h00)
- TPBR2PBR uvm_reg_field ... RW SHU_ACTIM5_0[23:16]=8'h82 (Mirror: 8'h00)
- TPBR2ACT uvm_reg_field ... RW SHU_ACTIM5_0[29:28]=2'h3 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM5, P_Fld(0x0a, SHU_ACTIM5_TR2PD) |
- P_Fld(0x6a, SHU_ACTIM5_TWTPD) | P_Fld(0x82, SHU_ACTIM5_TPBR2PBR) |
- P_Fld(0x3, SHU_ACTIM5_TPBR2ACT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM6_0 ral_reg_DRAMC_blk_SHU_ACTIM6_0 - @5184
- TZQLAT2 uvm_reg_field ... RW SHU_ACTIM6_0[4:0]=5'h04 (Mirror: 5'h1f)
- TMRD uvm_reg_field ... RW SHU_ACTIM6_0[11:8]=4'h7 (Mirror: 4'h0)
- TMRW uvm_reg_field ... RW SHU_ACTIM6_0[15:12]=4'h4 (Mirror: 4'h0)
- TW2MRW uvm_reg_field ... RW SHU_ACTIM6_0[25:20]=6'h30 (Mirror: 6'h00)
- TR2MRW uvm_reg_field ... RW SHU_ACTIM6_0[31:26]=6'h1c (Mirror: 6'h13)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM6, P_Fld(0x04, SHU_ACTIM6_TZQLAT2) |
- P_Fld(0x7, SHU_ACTIM6_TMRD) | P_Fld(0x4, SHU_ACTIM6_TMRW) |
- P_Fld(0x30, SHU_ACTIM6_TW2MRW) | P_Fld(0x1c, SHU_ACTIM6_TR2MRW));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_CKECTRL_0 ral_reg_DRAMC_blk_SHU_CKECTRL_0 - @5262
- TPDE_05T uvm_reg_field ... RW SHU_CKECTRL_0[0:0]=1'h1 (Mirror: 1'h0)
- TPDX_05T uvm_reg_field ... RW SHU_CKECTRL_0[1:1]=1'h0
- TPDE uvm_reg_field ... RW SHU_CKECTRL_0[14:12]=3'h4 (Mirror: 3'h1)
- TPDX uvm_reg_field ... RW SHU_CKECTRL_0[18:16]=3'h0 (Mirror: 3'h1)
- TCKEPRD uvm_reg_field ... RW SHU_CKECTRL_0[22:20]=3'h5 (Mirror: 3'h2)
- TCKESRX uvm_reg_field ... RW SHU_CKECTRL_0[25:24]=2'h1 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x1, SHU_CKECTRL_TPDE_05T) |
- P_Fld(0x0, SHU_CKECTRL_TPDX_05T) | P_Fld(0x4, SHU_CKECTRL_TPDE) |
- P_Fld(0x0, SHU_CKECTRL_TPDX) | P_Fld(0x5, SHU_CKECTRL_TCKEPRD) |
- P_Fld(0x1, SHU_CKECTRL_TCKESRX));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MISC_0 ral_reg_DRAMC_blk_SHU_MISC_0 - @5365
- REQQUE_MAXCNT uvm_reg_field ... RW SHU_MISC_0[3:0]=4'h2
- DCMDLYREF uvm_reg_field ... RW SHU_MISC_0[18:16]=3'h1 (Mirror: 3'h4)
- DAREFEN uvm_reg_field ... RW SHU_MISC_0[30:30]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_MISC, P_Fld(0x2, SHU_MISC_REQQUE_MAXCNT) |
- P_Fld(0x1, SHU_MISC_DCMDLYREF) | P_Fld(0x0, SHU_MISC_DAREFEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_LP5_CMD_0 ral_reg_DRAMC_blk_SHU_LP5_CMD_0 - @5427
- LP5_CMD1TO2EN uvm_reg_field ... RW SHU_LP5_CMD_0[0:0]=1'h0
- TCSH uvm_reg_field ... RW SHU_LP5_CMD_0[7:4]=4'hb (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_LP5_CMD, P_Fld(0x0, SHU_LP5_CMD_LP5_CMD1TO2EN) |
- P_Fld(0xb, SHU_LP5_CMD_TCSH));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIM7_0 ral_reg_DRAMC_blk_SHU_ACTIM7_0 - @5436
- TCSH_CSCAL uvm_reg_field ... RW SHU_ACTIM7_0[3:0]=4'hb (Mirror: 4'h0)
- TCACSH uvm_reg_field ... RW SHU_ACTIM7_0[7:4]=4'h2 (Mirror: 4'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIM7, P_Fld(0xb, SHU_ACTIM7_TCSH_CSCAL) |
- P_Fld(0x2, SHU_ACTIM7_TCACSH));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_WCKCTRL_0 ral_reg_DRAMC_blk_SHU_WCKCTRL_0 - @5407
- WCKRDOFF uvm_reg_field ... RW SHU_WCKCTRL_0[5:0]=6'h18 (Mirror: 6'h00)
- WCKRDOFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[7:7]=1'h1 (Mirror: 1'h0)
- WCKWROFF uvm_reg_field ... RW SHU_WCKCTRL_0[13:8]=6'h02 (Mirror: 6'h00)
- WCKWROFF_05T uvm_reg_field ... RW SHU_WCKCTRL_0[15:15]=1'h1 (Mirror: 1'h0)
- WCKDUAL uvm_reg_field ... RW SHU_WCKCTRL_0[16:16]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_WCKCTRL, P_Fld(0x18, SHU_WCKCTRL_WCKRDOFF) |
- P_Fld(0x1, SHU_WCKCTRL_WCKRDOFF_05T) | P_Fld(0x02, SHU_WCKCTRL_WCKWROFF) |
- P_Fld(0x1, SHU_WCKCTRL_WCKWROFF_05T) | P_Fld(0x0, SHU_WCKCTRL_WCKDUAL));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, AC timing Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Enter.
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX cross-rank improve setting Exit.
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828
- R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0157 (Mirror: 15'h0000)
- R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h0
- R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0157, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231
- R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0157 (Mirror: 15'h0000)
- R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h0
- R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1 (Mirror: 1'h0)
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0157, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ5_0 ral_reg_DDRPHY_blk_SHU_B0_DQ5_0 - @7728
- RG_RX_ARDQ_VREF_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[5:0]=6'h0e
- RG_RX_ARDQ_VREF_BYPASS_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[6:6]=1'h0
- RG_ARPI_FB_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[13:8]=6'h00
- RG_RX_ARDQS0_DQSIEN_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[18:16]=3'h0
- RG_RX_ARDQS_DQSIEN_RB_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[19:19]=1'h0
- RG_RX_ARDQS0_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[23:20]=4'h2 (Mirror: 4'h0)
- RG_RX_ARDQ_FIFO_DQSI_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ5_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ5, P_Fld(0x0e, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0) | P_Fld(0x00, SHU_B0_DQ5_RG_ARPI_FB_B0) |
- P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0) |
- P_Fld(0x2, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0) | P_Fld(0x0, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ5_0 ral_reg_DDRPHY_blk_SHU_B1_DQ5_0 - @9131
- RG_RX_ARDQ_VREF_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[5:0]=6'h0e
- RG_RX_ARDQ_VREF_BYPASS_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[6:6]=1'h0
- RG_ARPI_FB_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[13:8]=6'h00
- RG_RX_ARDQS0_DQSIEN_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[18:16]=3'h0
- RG_RX_ARDQS_DQSIEN_RB_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[19:19]=1'h0
- RG_RX_ARDQS0_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[23:20]=4'h2 (Mirror: 4'h0)
- RG_RX_ARDQ_FIFO_DQSI_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ5_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ5, P_Fld(0x0e, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1) | P_Fld(0x00, SHU_B1_DQ5_RG_ARPI_FB_B1) |
- P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1) |
- P_Fld(0x2, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1) | P_Fld(0x0, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_0 - @7490
- RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0, P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_0 - @7504
- RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1, P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_0 - @7518
- RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2, P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_0 - @7532
- RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3, P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_0 - @7546
- RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_0[15:8]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4, P_Fld(0x53, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x53, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_0 - @7556
- RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[8:0]=9'h00b (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_0[24:16]=9'h00b (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5, P_Fld(0x00b, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x00b, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY0_0_1 - @7497
- RX_ARDQ0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY0_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY1_0_1 - @7511
- RX_ARDQ2_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY1_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY2_0_1 - @7525
- RX_ARDQ4_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY2_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY3_0_1 - @7539
- RX_ARDQ6_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY3_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0) | P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY4_0_1 - @7551
- RX_ARDQM0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY4_0_1[15:8]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) |
- P_Fld(0x52, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B0_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B0_RXDLY5_0_1 - @7561
- RX_ARDQS0_R_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[8:0]=9'h00a (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B0 uvm_reg_field ... RW SHU_R0_B0_RXDLY5_0_1[24:16]=9'h00a (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B0_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00a, SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0) |
- P_Fld(0x00a, SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY0_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_0 - @8893
- RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0, P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY1_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_0 - @8907
- RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1, P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY2_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_0 - @8921
- RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2, P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY3_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_0 - @8935
- RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[15:8]=8'h53 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[23:16]=8'h53 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_0[31:24]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3, P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY4_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_0 - @8949
- RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[7:0]=8'h53 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_0[15:8]=8'h53 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4, P_Fld(0x53, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x53, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY5_0_0 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_0 - @8959
- RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[8:0]=9'h00b (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_0[24:16]=9'h00b (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5, P_Fld(0x00b, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x00b, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY0_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY0_0_1 - @8900
- RX_ARDQ0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ1_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ1_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY0_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY0+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY1_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY1_0_1 - @8914
- RX_ARDQ2_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ2_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ3_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ3_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY1_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY1+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY2_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY2_0_1 - @8928
- RX_ARDQ4_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ4_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ5_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ5_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY2_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY2+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY3_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY3_0_1 - @8942
- RX_ARDQ6_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQ6_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[15:8]=8'h52 (Mirror: 8'h00)
- RX_ARDQ7_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[23:16]=8'h52 (Mirror: 8'h00)
- RX_ARDQ7_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY3_0_1[31:24]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY3+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1) | P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY4_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY4_0_1 - @8954
- RX_ARDQM0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[7:0]=8'h52 (Mirror: 8'h00)
- RX_ARDQM0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY4_0_1[15:8]=8'h52 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY4+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x52, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) |
- P_Fld(0x52, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_R0_B1_RXDLY5_0_1 ral_reg_DDRPHY_blk_SHU_R0_B1_RXDLY5_0_1 - @8964
- RX_ARDQS0_R_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[8:0]=9'h00a (Mirror: 9'h000)
- RX_ARDQS0_F_DLY_B1 uvm_reg_field ... RW SHU_R0_B1_RXDLY5_0_1[24:16]=9'h00a (Mirror: 9'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_R0_B1_RXDLY5+(1*DDRPHY_AO_RANK_OFFSET), P_Fld(0x00a, SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1) |
- P_Fld(0x00a, SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384
- RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h0 (Mirror: 1'h1)
- RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
- P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
- P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
- P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787
- RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h0 (Mirror: 1'h1)
- RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
- P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
- P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
- P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ9 ral_reg_DDRPHY_blk_B0_DQ9 - @7384
- RG_RX_ARDQ_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[0:0]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B0 uvm_reg_field ... RW B0_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B0 uvm_reg_field ... RW B0_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B0 uvm_reg_field ... RW B0_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B0 uvm_reg_field ... RW B0_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B0 uvm_reg_field ... RW B0_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B0 uvm_reg_field ... RW B0_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ9, P_Fld(0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0) |
- P_Fld(0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0) |
- P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0) |
- P_Fld(0x00, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x0, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0) | P_Fld(0x0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0) |
- P_Fld(0x0, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ9 ral_reg_DDRPHY_blk_B1_DQ9 - @8787
- RG_RX_ARDQ_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[0:0]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ9[4:4]=1'h1
- RG_RX_ARDQS0_DQSIENMODE_B1 uvm_reg_field ... RW B1_DQ9[5:5]=1'h0
- R_DMRXDVS_R_F_DLY_RK_OPT_B1 uvm_reg_field ... RW B1_DQ9[6:6]=1'h1
- R_DMRXFIFO_STBENCMP_EN_B1 uvm_reg_field ... RW B1_DQ9[7:7]=1'h0
- R_IN_GATE_EN_LOW_OPT_B1 uvm_reg_field ... RW B1_DQ9[15:8]=8'h00
- R_DMDQSIEN_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[18:16]=3'h0
- R_DMDQSIEN_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[22:20]=3'h0
- R_DMRXDVS_VALID_LAT_B1 uvm_reg_field ... RW B1_DQ9[26:24]=3'h0
- R_DMRXDVS_RDSEL_LAT_B1 uvm_reg_field ... RW B1_DQ9[30:28]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ9, P_Fld(0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1) |
- P_Fld(0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1) |
- P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1) |
- P_Fld(0x00, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x0, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1) | P_Fld(0x0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1) |
- P_Fld(0x0, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ4 ral_reg_DDRPHY_blk_B0_DQ4 - @7313
- RG_RX_ARDQS_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[6:0]=7'h57 (Mirror: 7'h00)
- RG_RX_ARDQS_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[14:8]=7'h57 (Mirror: 7'h00)
- RG_RX_ARDQ_EYE_R_DLY_B0 uvm_reg_field ... RW B0_DQ4[21:16]=6'h13 (Mirror: 6'h00)
- RG_RX_ARDQ_EYE_F_DLY_B0 uvm_reg_field ... RW B0_DQ4[29:24]=6'h13 (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ4, P_Fld(0x57, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0) |
- P_Fld(0x57, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0) | P_Fld(0x13, B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0) |
- P_Fld(0x13, B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ4 ral_reg_DDRPHY_blk_B1_DQ4 - @8716
- RG_RX_ARDQS_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[6:0]=7'h57 (Mirror: 7'h00)
- RG_RX_ARDQS_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[14:8]=7'h57 (Mirror: 7'h00)
- RG_RX_ARDQ_EYE_R_DLY_B1 uvm_reg_field ... RW B1_DQ4[21:16]=6'h13 (Mirror: 6'h00)
- RG_RX_ARDQ_EYE_F_DLY_B1 uvm_reg_field ... RW B1_DQ4[29:24]=6'h13 (Mirror: 6'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ4, P_Fld(0x57, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1) |
- P_Fld(0x57, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1) | P_Fld(0x13, B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1) |
- P_Fld(0x13, B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B0_DQ5 ral_reg_DDRPHY_blk_B0_DQ5 - @7320
- RG_RX_ARDQ_EYE_VREF_SEL_B0 uvm_reg_field ... RW B0_DQ5[13:8]=6'h10
- RG_RX_ARDQ_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[16:16]=1'h1
- RG_RX_ARDQ_EYE_VREF_EN_B0 uvm_reg_field ... RW B0_DQ5[17:17]=1'h1
- RG_RX_ARDQ_EYE_SEL_B0 uvm_reg_field ... RW B0_DQ5[23:20]=4'h0
- RG_RX_ARDQ_EYE_EN_B0 uvm_reg_field ... RW B0_DQ5[24:24]=1'h1
- RG_RX_ARDQ_EYE_STBEN_RESETB_B0 uvm_reg_field ... RW B0_DQ5[25:25]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_DVS_EN_B0 uvm_reg_field ... RW B0_DQ5[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B0_DQ5, P_Fld(0x10, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0) |
- P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0) |
- P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0) | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0) |
- P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0) | P_Fld(0x0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- B1_DQ5 ral_reg_DDRPHY_blk_B1_DQ5 - @8723
- RG_RX_ARDQ_EYE_VREF_SEL_B1 uvm_reg_field ... RW B1_DQ5[13:8]=6'h10
- RG_RX_ARDQ_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[16:16]=1'h1
- RG_RX_ARDQ_EYE_VREF_EN_B1 uvm_reg_field ... RW B1_DQ5[17:17]=1'h1
- RG_RX_ARDQ_EYE_SEL_B1 uvm_reg_field ... RW B1_DQ5[23:20]=4'h0
- RG_RX_ARDQ_EYE_EN_B1 uvm_reg_field ... RW B1_DQ5[24:24]=1'h1
- RG_RX_ARDQ_EYE_STBEN_RESETB_B1 uvm_reg_field ... RW B1_DQ5[25:25]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQS0_DVS_EN_B1 uvm_reg_field ... RW B1_DQ5[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_B1_DQ5, P_Fld(0x10, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1) |
- P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1) |
- P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1) | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1) |
- P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1) | P_Fld(0x0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, RX input delay line set EXIT
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_COMMON0_0 ral_reg_DRAMC_blk_SHU_COMMON0_0 - @5001
- FREQDIV4 uvm_reg_field ... RW SHU_COMMON0_0[0:0]=1'h0
- FDIV2 uvm_reg_field ... RW SHU_COMMON0_0[1:1]=1'h0
- FREQDIV8 uvm_reg_field ... RW SHU_COMMON0_0[2:2]=1'h1 (Mirror: 1'h0)
- DM64BITEN uvm_reg_field ... RW SHU_COMMON0_0[4:4]=1'h0
- DLE256EN uvm_reg_field ... RW SHU_COMMON0_0[5:5]=1'h1 (Mirror: 1'h0)
- LP5BGEN uvm_reg_field ... RW SHU_COMMON0_0[6:6]=1'h1 (Mirror: 1'h0)
- LP5WCKON uvm_reg_field ... RW SHU_COMMON0_0[7:7]=1'h1 (Mirror: 1'h0)
- CL2 uvm_reg_field ... RW SHU_COMMON0_0[8:8]=1'h0
- BL2 uvm_reg_field ... RW SHU_COMMON0_0[9:9]=1'h0
- BL4 uvm_reg_field ... RW SHU_COMMON0_0[10:10]=1'h1 (Mirror: 1'h0)
- LP5BGOTF uvm_reg_field ... RW SHU_COMMON0_0[11:11]=1'h0
- BC4OTF uvm_reg_field ... RW SHU_COMMON0_0[12:12]=1'h1
- LP5HEFF_MODE uvm_reg_field ... RW SHU_COMMON0_0[13:13]=1'h1 (Mirror: 1'h0)
- SHU_COMMON0_RSV uvm_reg_field ... RW SHU_COMMON0_0[31:15]=17'h00000
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_COMMON0, P_Fld(0x0, SHU_COMMON0_FREQDIV4) |
- P_Fld(0x0, SHU_COMMON0_FDIV2) | P_Fld(0x1, SHU_COMMON0_FREQDIV8) |
- P_Fld(0x0, SHU_COMMON0_DM64BITEN) | P_Fld(0x1, SHU_COMMON0_DLE256EN) |
- P_Fld(0x1, SHU_COMMON0_LP5BGEN) | P_Fld(0x1, SHU_COMMON0_LP5WCKON) |
- P_Fld(0x0, SHU_COMMON0_CL2) | P_Fld(0x0, SHU_COMMON0_BL2) |
- P_Fld(0x1, SHU_COMMON0_BL4) | P_Fld(0x0, SHU_COMMON0_LP5BGOTF) |
- P_Fld(0x1, SHU_COMMON0_BC4OTF) | P_Fld(0x1, SHU_COMMON0_LP5HEFF_MODE) |
- P_Fld(0x00000, SHU_COMMON0_SHU_COMMON0_RSV));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ACTIMING_CONF_0 ral_reg_DRAMC_blk_SHU_ACTIMING_CONF_0 - @5255
- SCINTV uvm_reg_field ... RW SHU_ACTIMING_CONF_0[5:0]=6'h26 (Mirror: 6'h2a)
- TRFCPBIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[8:8]=1'h0
- REFBW_FR uvm_reg_field ... RW SHU_ACTIMING_CONF_0[25:16]=10'h000
- TREFBWIG uvm_reg_field ... RW SHU_ACTIMING_CONF_0[31:31]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ACTIMING_CONF, P_Fld(0x26, SHU_ACTIMING_CONF_SCINTV) |
- P_Fld(0x0, SHU_ACTIMING_CONF_TRFCPBIG) | P_Fld(0x000, SHU_ACTIMING_CONF_REFBW_FR) |
- P_Fld(0x1, SHU_ACTIMING_CONF_TREFBWIG));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DCM_CTRL0_0 ral_reg_DRAMC_blk_SHU_DCM_CTRL0_0 - @5027
- DDRPHY_CLK_EN_OPT uvm_reg_field ... RW SHU_DCM_CTRL0_0[7:7]=1'h1
- DPHY_CMDDCM_EXTCNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[11:8]=4'h4
- DDRPHY_CLK_DYN_GATING_SEL uvm_reg_field ... RW SHU_DCM_CTRL0_0[15:12]=4'h5
- CKE_EXTNONPD_CNT uvm_reg_field ... RW SHU_DCM_CTRL0_0[19:16]=4'h0
- FASTWAKE2 uvm_reg_field ... RW SHU_DCM_CTRL0_0[29:29]=1'h1 (Mirror: 1'h0)
- FASTWAKE uvm_reg_field ... RW SHU_DCM_CTRL0_0[31:31]=1'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(0x1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) |
- P_Fld(0x4, SHU_DCM_CTRL0_DPHY_CMDDCM_EXTCNT) | P_Fld(0x5, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL) |
- P_Fld(0x0, SHU_DCM_CTRL0_CKE_EXTNONPD_CNT) | P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE2) |
- P_Fld(0x1, SHU_DCM_CTRL0_FASTWAKE));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_CONF0_0 ral_reg_DRAMC_blk_SHU_CONF0_0 - @5356
- DMPGTIM uvm_reg_field ... RW SHU_CONF0_0[5:0]=6'h3f (Mirror: 6'h08)
- ADVREFEN uvm_reg_field ... RW SHU_CONF0_0[6:6]=1'h0
- ADVPREEN uvm_reg_field ... RW SHU_CONF0_0[7:7]=1'h1 (Mirror: 1'h0)
- PBREFEN uvm_reg_field ... RW SHU_CONF0_0[8:8]=1'h1 (Mirror: 1'h0)
- REFTHD uvm_reg_field ... RW SHU_CONF0_0[15:12]=4'h1 (Mirror: 4'h0)
- REQQUE_DEPTH uvm_reg_field ... RW SHU_CONF0_0[19:16]=4'h8
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x3f, SHU_CONF0_DMPGTIM) |
- P_Fld(0x0, SHU_CONF0_ADVREFEN) | P_Fld(0x1, SHU_CONF0_ADVPREEN) |
- P_Fld(0x1, SHU_CONF0_PBREFEN) | P_Fld(0x1, SHU_CONF0_REFTHD) |
- P_Fld(0x8, SHU_CONF0_REQQUE_DEPTH));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_MATYPE_0 ral_reg_DRAMC_blk_SHU_MATYPE_0 - @4996
- MATYPE uvm_reg_field ... RW SHU_MATYPE_0[1:0]=2'h2 (Mirror: 2'h0)
- NORMPOP_LEN uvm_reg_field ... RW SHU_MATYPE_0[6:4]=3'h1
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_MATYPE, P_Fld(0x2, SHU_MATYPE_MATYPE) |
- P_Fld(0x1, SHU_MATYPE_NORMPOP_LEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_SCHEDULER_0 ral_reg_DRAMC_blk_SHU_SCHEDULER_0 - @5023
- DUALSCHEN uvm_reg_field ... RW SHU_SCHEDULER_0[2:2]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldAlign(DRAMC_REG_SHU_SCHEDULER, 0x1, SHU_SCHEDULER_DUALSCHEN);
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- TX_SET0 ral_reg_DRAMC_blk_TX_SET0 - @3899
- TXRANK uvm_reg_field ... RW TX_SET0[1:0]=2'h0
- TXRANKFIX uvm_reg_field ... RW TX_SET0[2:2]=1'h0
- DDRPHY_COMB_CG_SEL uvm_reg_field ... RW TX_SET0[3:3]=1'h0
- TX_DQM_DEFAULT uvm_reg_field ... RW TX_SET0[4:4]=1'h1
- DQBUS_X32 uvm_reg_field ... RW TX_SET0[5:5]=1'h0
- OE_DOWNGRADE uvm_reg_field ... RW TX_SET0[6:6]=1'h0
- DQ16COM1 uvm_reg_field ... RW TX_SET0[21:21]=1'h0
- WPRE2T uvm_reg_field ... RW TX_SET0[22:22]=1'h1 (Mirror: 1'h0)
- DRSCLR_EN uvm_reg_field ... RW TX_SET0[24:24]=1'h0
- DRSCLR_RK0_EN uvm_reg_field ... RW TX_SET0[25:25]=1'h0
- ARPI_CAL_E2OPT uvm_reg_field ... RW TX_SET0[26:26]=1'h0
- TX_DLY_CAL_E2OPT uvm_reg_field ... RW TX_SET0[27:27]=1'h0
- DQS_OE_OP1_DIS uvm_reg_field ... RW TX_SET0[28:28]=1'h0
- DQS_OE_OP2_EN uvm_reg_field ... RW TX_SET0[29:29]=1'h0
- RK_SCINPUT_OPT uvm_reg_field ... RW TX_SET0[30:30]=1'h0
- DRAMOEN uvm_reg_field ... RW TX_SET0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_TX_SET0, P_Fld(0x0, TX_SET0_TXRANK) |
- P_Fld(0x0, TX_SET0_TXRANKFIX) | P_Fld(0x0, TX_SET0_DDRPHY_COMB_CG_SEL) |
- P_Fld(0x1, TX_SET0_TX_DQM_DEFAULT) | P_Fld(0x0, TX_SET0_DQBUS_X32) |
- P_Fld(0x0, TX_SET0_OE_DOWNGRADE) | P_Fld(0x0, TX_SET0_DQ16COM1) |
- P_Fld(0x1, TX_SET0_WPRE2T) | P_Fld(0x0, TX_SET0_DRSCLR_EN) |
- P_Fld(0x0, TX_SET0_DRSCLR_RK0_EN) | P_Fld(0x0, TX_SET0_ARPI_CAL_E2OPT) |
- P_Fld(0x0, TX_SET0_TX_DLY_CAL_E2OPT) | P_Fld(0x0, TX_SET0_DQS_OE_OP1_DIS) |
- P_Fld(0x0, TX_SET0_DQS_OE_OP2_EN) | P_Fld(0x0, TX_SET0_RK_SCINPUT_OPT) |
- P_Fld(0x0, TX_SET0_DRAMOEN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2 (Mirror: 3'h0)
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h0
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1 (Mirror: 1'h0)
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1 (Mirror: 3'h0)
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x0, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_STBCAL1_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL1_0 - @12514
- DLLFRZRFCOPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[1:0]=2'h0
- DLLFRZWROPT uvm_reg_field ... RW MISC_SHU_STBCAL1_0[5:4]=2'h0
- r_rstbcnt_latch_opt uvm_reg_field ... RW MISC_SHU_STBCAL1_0[10:8]=3'h0
- STB_UPDMASK_EN uvm_reg_field ... RW MISC_SHU_STBCAL1_0[11:11]=1'h1 (Mirror: 1'h0)
- STB_UPDMASKCYC uvm_reg_field ... RW MISC_SHU_STBCAL1_0[15:12]=4'h9 (Mirror: 4'h0)
- DQSINCTL_PRE_SEL uvm_reg_field ... RW MISC_SHU_STBCAL1_0[16:16]=1'h1 (Mirror: 1'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL1, P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZRFCOPT) |
- P_Fld(0x0, MISC_SHU_STBCAL1_DLLFRZWROPT) | P_Fld(0x0, MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT) |
- P_Fld(0x1, MISC_SHU_STBCAL1_STB_UPDMASK_EN) | P_Fld(0x9, MISC_SHU_STBCAL1_STB_UPDMASKCYC) |
- P_Fld(0x1, MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_STBCAL_0 ral_reg_DDRPHY_blk_MISC_SHU_STBCAL_0 - @12499
- DMSTBLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[3:0]=4'h2 (Mirror: 4'h0)
- PICGLAT uvm_reg_field ... RW MISC_SHU_STBCAL_0[6:4]=3'h1 (Mirror: 3'h0)
- DQSG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[8:8]=1'h1 (Mirror: 1'h0)
- DQSIEN_PICG_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[9:9]=1'h1 (Mirror: 1'h0)
- DQSIEN_DQSSTB_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[13:12]=2'h3 (Mirror: 2'h1)
- DQSIEN_BURST_MODE uvm_reg_field ... RW MISC_SHU_STBCAL_0[14:14]=1'h1
- DQSIEN_SELPH_FRUN uvm_reg_field ... RW MISC_SHU_STBCAL_0[15:15]=1'h0
- STBCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[16:16]=1'h1 (Mirror: 1'h0)
- STB_SELPHCALEN uvm_reg_field ... RW MISC_SHU_STBCAL_0[17:17]=1'h1 (Mirror: 1'h0)
- DQSIEN_4TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[20:20]=1'h0
- DQSIEN_8TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[21:21]=1'h0
- DQSIEN_16TO1_EN uvm_reg_field ... RW MISC_SHU_STBCAL_0[22:22]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_STBCAL, P_Fld(0x2, MISC_SHU_STBCAL_DMSTBLAT) |
- P_Fld(0x1, MISC_SHU_STBCAL_PICGLAT) | P_Fld(0x1, MISC_SHU_STBCAL_DQSG_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE) | P_Fld(0x3, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE) |
- P_Fld(0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN) |
- P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) | P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_4TO1_EN) | P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_8TO1_EN) |
- P_Fld(0x0, MISC_SHU_STBCAL_DQSIEN_16TO1_EN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RODTENSTB_0 ral_reg_DDRPHY_blk_MISC_SHU_RODTENSTB_0 - @12562
- RODTENSTB_TRACK_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[0:0]=1'h1 (Mirror: 1'h0)
- RODTEN_P1_ENABLE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[1:1]=1'h0
- RODTENSTB_4BYTE_EN uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[2:2]=1'h0
- RODTENSTB_TRACK_UDFLWCTRL uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[3:3]=1'h1 (Mirror: 1'h0)
- RODTENSTB_SELPH_MODE uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[4:4]=1'h1
- RODTENSTB_SELPH_BY_BITTIME uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[5:5]=1'h0
- RODTENSTB__UI_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[11:8]=4'h4 (Mirror: 4'h0)
- RODTENSTB_MCK_OFFSET uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[15:12]=4'h0
- RODTENSTB_EXT uvm_reg_field ... RW MISC_SHU_RODTENSTB_0[31:16]=16'h0008 (Mirror: 16'h0000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN) |
- P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) | P_Fld(0x1, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME) | P_Fld(0x4, MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET) |
- P_Fld(0x0, MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET) | P_Fld(0x0008, MISC_SHU_RODTENSTB_RODTENSTB_EXT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_RX_SELPH_MODE_0 ral_reg_DDRPHY_blk_MISC_SHU_RX_SELPH_MODE_0 - @12751
- DQSIEN_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[1:0]=2'h3 (Mirror: 2'h0)
- RODT_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[5:4]=2'h2 (Mirror: 2'h0)
- RANK_SELPH_SERMODE uvm_reg_field ... RW MISC_SHU_RX_SELPH_MODE_0[7:6]=2'h2 (Mirror: 2'h0)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE, P_Fld(0x3, MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE) |
- P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE) | P_Fld(0x2, MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DRAMC other fixed register Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1 (Mirror: 1'h0)
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1 (Mirror: 1'h0)
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h0
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1 (Mirror: 1'h0)
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h0e
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x0e, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DBI gen by frequency Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HWSET_MR2_0 ral_reg_DRAMC_blk_SHU_HWSET_MR2_0 - @5122
- HWSET_MR2_MRSMA uvm_reg_field ... RW SHU_HWSET_MR2_0[12:0]=13'h0002
- HWSET_MR2_OP uvm_reg_field ... RW SHU_HWSET_MR2_0[23:16]=8'h09 (Mirror: 8'h12)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HWSET_MR2, P_Fld(0x0002, SHU_HWSET_MR2_HWSET_MR2_MRSMA) |
- P_Fld(0x09, SHU_HWSET_MR2_HWSET_MR2_OP));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, DVFS_WLRL_setting Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_FREQ_RATIO_SET0_0 ral_reg_DRAMC_blk_SHU_FREQ_RATIO_SET0_0 - @5384
- tDQSCK_JUMP_RATIO3 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[7:0]=8'h20 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO2 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[15:8]=8'h93 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO1 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[23:16]=8'h07 (Mirror: 8'h00)
- tDQSCK_JUMP_RATIO0 uvm_reg_field ... RW SHU_FREQ_RATIO_SET0_0[31:24]=8'h20 (Mirror: 8'h00)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3) |
- P_Fld(0x93, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) | P_Fld(0x07, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) |
- P_Fld(0x20, SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, jump_ratio_setting_txrx_SHU_8_group Exit
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Enter
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- MISC_SHU_DVFSDLL_0 ral_reg_DDRPHY_blk_MISC_SHU_DVFSDLL_0 - @12523
- r_bypass_1st_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[0:0]=1'h0
- r_bypass_2nd_dll uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[1:1]=1'h0
- r_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[10:4]=7'h5a (Mirror: 7'h46)
- r_2nd_dll_idle uvm_reg_field ... RW MISC_SHU_DVFSDLL_0[22:16]=7'h5a
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL) |
- P_Fld(0x0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL) | P_Fld(0x5a, MISC_SHU_DVFSDLL_R_DLL_IDLE) |
- P_Fld(0x5a, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, dvfs_config_shuffle_registers Exit
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- /*TINFO=---===BROADCAST OFF!===---*/
- broadcast_off();
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Enter
- mcDELAY_US(1);
-
- mcDELAY_US(1);
-
- /*TINFO=---===BROADCAST ON!===---*/
- broadcast_on();
- // ========>SHUFFLE GROUP: 0, need_fifo: 0, sram_read_timing_option Exit
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DQSOSCR_0 ral_reg_DRAMC_blk_SHU_DQSOSCR_0 - @5338
- DQSOSCRCNT uvm_reg_field ... RW SHU_DQSOSCR_0[7:0]=8'h0e (Mirror: 8'h00)
- DQSOSC_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[9:8]=2'h0
- DQSOSC_DRS_ADV_SEL uvm_reg_field ... RW SHU_DQSOSCR_0[11:10]=2'h0
- DQSOSC_DELTA uvm_reg_field ... RW SHU_DQSOSCR_0[31:16]=16'hffff
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCR, P_Fld(0x0e, SHU_DQSOSCR_DQSOSCRCNT) |
- P_Fld(0x0, SHU_DQSOSCR_DQSOSC_ADV_SEL) | P_Fld(0x0, SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL) |
- P_Fld(0xffff, SHU_DQSOSCR_DQSOSC_DELTA));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_DQSOSC_SET0_0 ral_reg_DRAMC_blk_SHU_DQSOSC_SET0_0 - @5332
- DQSOSCENDIS uvm_reg_field ... RW SHU_DQSOSC_SET0_0[0:0]=1'h1
- DQSOSC_PRDCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[13:4]=10'h009 (Mirror: 10'h00f)
- DQSOSCENCNT uvm_reg_field ... RW SHU_DQSOSC_SET0_0[31:16]=16'h0002
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_SET0, P_Fld(0x1, SHU_DQSOSC_SET0_DQSOSCENDIS) |
- P_Fld(0x009, SHU_DQSOSC_SET0_DQSOSC_PRDCNT) | P_Fld(0x0002, SHU_DQSOSC_SET0_DQSOSCENCNT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_0 - @4906
- DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_0[15:0]=16'h01ca (Mirror: 16'h0000)
- DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_0[31:16]=16'h01ca (Mirror: 16'h0000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC, P_Fld(0x01ca, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x01ca, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_0_1 - @4911
- DQSOSC_BASE_RK0 uvm_reg_field ... RW SHURK_DQSOSC_0_1[15:0]=16'h0106 (Mirror: 16'h0000)
- DQSOSC_BASE_RK0_B1 uvm_reg_field ... RW SHURK_DQSOSC_0_1[31:16]=16'h0106 (Mirror: 16'h0000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x0106, SHURK_DQSOSC_DQSOSC_BASE_RK0) |
- P_Fld(0x0106, SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_THRD_0_0 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_0 - @4916
- DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[11:0]=12'h007 (Mirror: 12'h001)
- DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_0[27:16]=12'h005 (Mirror: 12'h001)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD, P_Fld(0x007, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x005, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHURK_DQSOSC_THRD_0_1 ral_reg_DRAMC_blk_SHURK_DQSOSC_THRD_0_1 - @4921
- DQSOSCTHRD_INC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[11:0]=12'h002 (Mirror: 12'h001)
- DQSOSCTHRD_DEC uvm_reg_field ... RW SHURK_DQSOSC_THRD_0_1[27:16]=12'h001
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHURK_DQSOSC_THRD+(1*DRAMC_REG_AO_RANK_OFFSET), P_Fld(0x002, SHURK_DQSOSC_THRD_DQSOSCTHRD_INC) |
- P_Fld(0x001, SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_TX_SET0_0 ral_reg_DRAMC_blk_SHU_TX_SET0_0 - @5306
- DQOE_CNT uvm_reg_field ... RW SHU_TX_SET0_0[3:0]=4'h0
- DQOE_OPT uvm_reg_field ... RW SHU_TX_SET0_0[4:4]=1'h0
- TXUPD_SEL uvm_reg_field ... RW SHU_TX_SET0_0[7:6]=2'h0
- TXUPD_W2R_SEL uvm_reg_field ... RW SHU_TX_SET0_0[10:8]=3'h2
- WECC_EN uvm_reg_field ... RW SHU_TX_SET0_0[11:11]=1'h0
- DBIWR uvm_reg_field ... RW SHU_TX_SET0_0[12:12]=1'h1
- WDATRGO uvm_reg_field ... RW SHU_TX_SET0_0[13:13]=1'h0
- TWPSTEXT uvm_reg_field ... RW SHU_TX_SET0_0[14:14]=1'h0
- WPST1P5T uvm_reg_field ... RW SHU_TX_SET0_0[15:15]=1'h1
- TXOEN_AUTOSET_OFFSET uvm_reg_field ... RW SHU_TX_SET0_0[19:16]=4'h3
- TWCKPST uvm_reg_field ... RW SHU_TX_SET0_0[21:20]=2'h1
- OE_EXT2UI uvm_reg_field ... RW SHU_TX_SET0_0[24:22]=3'h1
- DQS2DQ_FILT_PITHRD uvm_reg_field ... RW SHU_TX_SET0_0[30:25]=6'h23 (Mirror: 6'h0e)
- TXOEN_AUTOSET_EN uvm_reg_field ... RW SHU_TX_SET0_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(0x0, SHU_TX_SET0_DQOE_CNT) |
- P_Fld(0x0, SHU_TX_SET0_DQOE_OPT) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL) |
- P_Fld(0x2, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_WECC_EN) |
- P_Fld(0x1, SHU_TX_SET0_DBIWR) | P_Fld(0x0, SHU_TX_SET0_WDATRGO) |
- P_Fld(0x0, SHU_TX_SET0_TWPSTEXT) | P_Fld(0x1, SHU_TX_SET0_WPST1P5T) |
- P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | P_Fld(0x1, SHU_TX_SET0_TWCKPST) |
- P_Fld(0x1, SHU_TX_SET0_OE_EXT2UI) | P_Fld(0x23, SHU_TX_SET0_DQS2DQ_FILT_PITHRD) |
- P_Fld(0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_ZQ_SET0_0 ral_reg_DRAMC_blk_SHU_ZQ_SET0_0 - @5351
- ZQCSCNT uvm_reg_field ... RW SHU_ZQ_SET0_0[15:0]=16'h0005 (Mirror: 16'h0000)
- TZQLAT uvm_reg_field ... RW SHU_ZQ_SET0_0[31:27]=5'h1b
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_ZQ_SET0, P_Fld(0x0005, SHU_ZQ_SET0_ZQCSCNT) |
- P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_HMR4_DVFS_CTRL0_0 ral_reg_DRAMC_blk_SHU_HMR4_DVFS_CTRL0_0 - @5036
- FSPCHG_PRDCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[15:8]=8'h67
- REFRCNT uvm_reg_field ... RW SHU_HMR4_DVFS_CTRL0_0[27:16]=12'h005 (Mirror: 12'h000)
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x67, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT) |
- P_Fld(0x005, SHU_HMR4_DVFS_CTRL0_REFRCNT));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ8_0 ral_reg_DDRPHY_blk_SHU_B0_DQ8_0 - @7828
- R_DMRXDVS_UPD_FORCE_CYC_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[14:0]=15'h0157
- R_DMRXDVS_UPD_FORCE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMRANK_RXDLY_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[21:21]=1'h1
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[24:24]=1'h1
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B0 uvm_reg_field ... RW SHU_B0_DQ8_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ8, P_Fld(0x0157, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0) | P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
- P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) | P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
- P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ8_0 ral_reg_DDRPHY_blk_SHU_B1_DQ8_0 - @9231
- R_DMRXDVS_UPD_FORCE_CYC_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[14:0]=15'h0157
- R_DMRXDVS_UPD_FORCE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[15:15]=1'h1 (Mirror: 1'h0)
- R_DMRANK_RXDLY_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[19:19]=1'h0
- R_RMRODTEN_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[20:20]=1'h0
- R_RMRX_TOPHY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[21:21]=1'h1
- R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[22:22]=1'h0
- R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[23:23]=1'h0
- R_DMRXDLY_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[24:24]=1'h1
- R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[26:26]=1'h0
- R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[27:27]=1'h0
- R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[28:28]=1'h0
- R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[29:29]=1'h0
- R_DMRANK_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[30:30]=1'h0
- R_DMRANK_CHG_PIPE_CG_IG_B1 uvm_reg_field ... RW SHU_B1_DQ8_0[31:31]=1'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ8, P_Fld(0x0157, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1) | P_Fld(0x1, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1) |
- P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) | P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
- P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ7_0 ral_reg_DDRPHY_blk_SHU_B0_DQ7_0 - @7808
- R_DMRANKRXDVS_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[6:6]=1'h1
- R_DMDQMDBI_SHU_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[7:7]=1'h1
- R_DMRXDVS_DQM_FLAGSEL_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[11:8]=4'h8 (Mirror: 4'h0)
- R_DMRXDVS_PBYTE_FLAG_OPT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS0 uvm_reg_field ... RW SHU_B0_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[27:25]=3'h1
- R_DMRXRANK_DQS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B0 uvm_reg_field ... RW SHU_B0_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRANKRXDVS_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0) |
- P_Fld(0x8, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRODTEN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0) |
- P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) | P_Fld(0x0, SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0) | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0) |
- P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0) | P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ7_0 ral_reg_DDRPHY_blk_SHU_B1_DQ7_0 - @9211
- R_DMRANKRXDVS_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[3:0]=4'h0
- R_DMDQMDBI_EYE_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[6:6]=1'h1
- R_DMDQMDBI_SHU_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[7:7]=1'h1
- R_DMRXDVS_DQM_FLAGSEL_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[11:8]=4'h8 (Mirror: 4'h0)
- R_DMRXDVS_PBYTE_FLAG_OPT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[12:12]=1'h0
- R_DMRXDVS_PBYTE_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[13:13]=1'h0
- R_DMRXTRACK_DQM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[14:14]=1'h0
- R_DMRODTEN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[15:15]=1'h1
- R_DMARPI_CG_FB2DLL_DCM_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[16:16]=1'h0
- R_DMTX_ARPI_CG_DQ_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[17:17]=1'h0
- R_DMTX_ARPI_CG_DQS_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[18:18]=1'h0
- R_DMTX_ARPI_CG_DQM_NEW_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[19:19]=1'h0
- R_LP4Y_SDN_MODE_DQS1 uvm_reg_field ... RW SHU_B1_DQ7_0[20:20]=1'h0
- R_DMRXRANK_DQ_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[24:24]=1'h1
- R_DMRXRANK_DQ_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[27:25]=3'h1
- R_DMRXRANK_DQS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[28:28]=1'h1
- R_DMRXRANK_DQS_LAT_B1 uvm_reg_field ... RW SHU_B1_DQ7_0[31:29]=3'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRANKRXDVS_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1) |
- P_Fld(0x8, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRODTEN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
- P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) | P_Fld(0x0, SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1) | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1) |
- P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1) | P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B0_DQ11_0 ral_reg_DDRPHY_blk_SHU_B0_DQ11_0 - @7794
- RG_RX_ARDQ_RANK_SEL_SER_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[0:0]=1'h0
- RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[1:1]=1'h0
- RG_RX_ARDQ_OFFSETC_LAT_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[2:2]=1'h0
- RG_RX_ARDQ_OFFSETC_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[3:3]=1'h0
- RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[4:4]=1'h0
- RG_RX_ARDQ_FRATE_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[5:5]=1'h0
- RG_RX_ARDQ_CDR_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[6:6]=1'h0
- RG_RX_ARDQ_DVS_EN_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQ_DVS_DLY_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[11:8]=4'h0
- RG_RX_ARDQ_DES_MODE_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[17:16]=2'h3
- RG_RX_ARDQ_BW_SEL_B0 uvm_reg_field ... RW SHU_B0_DQ11_0[19:18]=2'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ11, P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) |
- P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0) |
- P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0) |
- P_Fld(0x3, SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0) | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0));
- /*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- Name Type Size Value
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- SHU_B1_DQ11_0 ral_reg_DDRPHY_blk_SHU_B1_DQ11_0 - @9197
- RG_RX_ARDQ_RANK_SEL_SER_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[0:0]=1'h0
- RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[1:1]=1'h0
- RG_RX_ARDQ_OFFSETC_LAT_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[2:2]=1'h0
- RG_RX_ARDQ_OFFSETC_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[3:3]=1'h0
- RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[4:4]=1'h0
- RG_RX_ARDQ_FRATE_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[5:5]=1'h0
- RG_RX_ARDQ_CDR_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[6:6]=1'h0
- RG_RX_ARDQ_DVS_EN_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[7:7]=1'h1 (Mirror: 1'h0)
- RG_RX_ARDQ_DVS_DLY_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[11:8]=4'h0
- RG_RX_ARDQ_DES_MODE_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[17:16]=2'h3
- RG_RX_ARDQ_BW_SEL_B1 uvm_reg_field ... RW SHU_B1_DQ11_0[19:18]=2'h0
- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- */
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ11, P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) |
- P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1) |
- P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1) |
- P_Fld(0x3, SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1) | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1));
- // Exit body
-}
-#endif
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
index 14d0068188..3badd6ebb3 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
@@ -146,22 +146,6 @@ const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] =
},
};
-#if (__LP5_COMBO__)
-const U8 uiLPDDR5_MRR_Mapping_POP[CHANNEL_NUM][16] =
-{
- {
- 8, 9, 10, 11, 12, 15, 14, 13,
- 0, 1, 2, 3, 4, 7, 6, 5,
- },
-
-#if (CHANNEL_NUM>1)
- {
- 8, 9, 10, 11, 12, 15, 14, 13,
- 0, 1, 2, 3, 4, 7, 6, 5,
- },
-#endif
-};
-#endif
//MRR DRAM->DRAMC
U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] =
@@ -195,10 +179,6 @@ U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] =
#if (fcFOR_CHIP_ID == fc8195)
static void Set_DRAM_Pinmux_Sel(DRAMC_CTX_T *p)
{
-#if (__LP5_COMBO__)
- if (is_lp5_family(p))
- return;
-#endif
#if !FOR_DV_SIMULATION_USED
if (is_discrete_lpddr4())
@@ -234,11 +214,6 @@ static void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p)
{
vSetPHY2ChannelMapping(p, chIdx);
- #if (__LP5_COMBO__)
- if (is_lp5_family(p))
- uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR5_MRR_Mapping_POP[chIdx];
- else
- #endif
uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR4_MRR_Mapping_POP[chIdx];
//Set MRR pin mux
@@ -276,11 +251,6 @@ static void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p)
{
vSetPHY2ChannelMapping(p, chIdx);
- #if (__LP5_COMBO__)
- if (is_lp5_family(p))
- uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[chIdx];
- else
- #endif
uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[chIdx];
//Set MRR pin mux
@@ -7174,11 +7144,6 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p)
U8 u1DisImpHw;
U32 u4TermFreq;
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- u4TermFreq = LP5_MRFSP_TERM_FREQ;
- else
-#endif
u4TermFreq = LP4_MRFSP_TERM_FREQ;
u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1;
@@ -7282,40 +7247,12 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p)
sv_algorithm_assistance_LP4_400(p);
}
}
- #if __LP5_COMBO__
- else
- {
- if(p->freq_sel==LP5_DDR4266)
- {
- mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_4266 \n"));
- CInit_golden_mini_freq_related_vseq_LP5_4266(p);
- }
- else if(p->freq_sel==LP5_DDR5500)
- {
- mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_5500 \n"));
- CInit_golden_mini_freq_related_vseq_LP5_5500(p);
- }
- else
- {
- mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_3200 \n"));
- CInit_golden_mini_freq_related_vseq_LP5_3200(p);
- CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(p);
- }
- }
- #endif
RESETB_PULL_DN(p);
ANA_init(p);
DIG_STATIC_SETTING(p);
DIG_CONFIG_SHUF(p,0,0); //temp ch0 group 0
-#if __LP5_COMBO__
- if(is_lp5_family(p))
- {
- LP5_UpdateInitialSettings(p);
- }
- else
-#endif
{
LP4_UpdateInitialSettings(p);
}
@@ -7355,9 +7292,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
EnableDramcPhyDCM(p, DCM_OFF); //Let CLK always free-run
vResetDelayChainBeforeCalibration(p);
-#if __LP5_COMBO__
- if(!is_lp5_family(p))
-#endif
+
DVFSSettings(p);
#if REPLACE_DFS_RG_MODE
@@ -7389,13 +7324,6 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
mcSHOW_TIME_MSG(("\tDutyCalibration takes %d us\n", CPU_Cycle));
#endif
-#if __LP5_COMBO__
- if(is_lp5_family(p))
- {
- LP5_DRAM_INIT(p); // Notice: LP5_DRAM_INIT is Broadcast On
- }
- else
-#endif
{
//LP4_DRAM_INIT(p);
DramcModeRegInit_LP4(p);
@@ -7872,16 +7800,7 @@ void DramcHMR4_Presetting(DRAMC_CTX_T *p)
static void SwitchHMR4(DRAMC_CTX_T *p, bool en)
{
-#ifdef __LP5_COMBO__
- if (is_lp5_family(p))
- {
- vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 9, REF_BOUNCE2_PRE_MR4INT_TH);
-
- vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 9, REFCTRL2_MR4INT_TH);
- }
- else
-#endif
{
vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 5, REF_BOUNCE2_PRE_MR4INT_TH);
@@ -8935,20 +8854,10 @@ static void RODTSettings(DRAMC_CTX_T *p)
if(p->odt_onoff==ODT_ON)
{
- #if __LP5_COMBO__
- if (p->dram_type==TYPE_LPDDR5)
- u1VrefSel = 0x46;//term LP5
- else
- #endif
u1VrefSel = 0x2c;//term LP4
}
else
{
- #if __LP5_COMBO__
- if (p->dram_type==TYPE_LPDDR5)
- u1VrefSel = 0x37;//unterm LP5
- else
- #endif
u1VrefSel = 0x37;//unterm LP4
}
@@ -9034,21 +8943,6 @@ static void DQSSTBSettings(DRAMC_CTX_T *p)
unsigned int dqsien_mode = 1;
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
-#if (__LP5_COMBO__)
- U8 rpre_mode = LPDDR5_RPRE_4S_0T;
-
- if (is_lp5_family(p))
- {
- if (p->frequency > 1600)
- rpre_mode = LPDDR5_RPRE_2S_2T;
- }
-
- if (rpre_mode == LPDDR5_RPRE_2S_2T)
- dqsien_mode = 2;
- else if (rpre_mode == LPDDR5_RPRE_XS_4T)
- dqsien_mode = 3;
-#endif
-
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
dqsien_mode, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10),
@@ -9217,58 +9111,6 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p)
SetMck8xLowPwrOption(p);
}
-#if __LP5_COMBO__
-void LP5_UpdateInitialSettings(DRAMC_CTX_T *p)
-{
- U8 u1RankIdx, u1RankIdxBak;
-
- vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //Let CA and CS be independent
- //Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux
-
- //Disable perbyte option
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
- | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
- | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
- vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
- | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
- | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
-
- ///TODO: Temp solution. May need to resolve in init flow
- vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5, /* Will cause PI un-adjustable */
- P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN) |
- P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
- P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
- P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
- P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
- P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN));
-
- DQSSTBSettings(p);
-
- RODTSettings(p);
-
-#if SIMULATION_SW_IMPED
- #if FSP1_CLKCA_TERM
- U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
- #else
- U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
- #endif
- U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
-
- if (p->dram_type == TYPE_LPDDR5)
- DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
-#endif
-
-#if RDSEL_TRACKING_EN
- vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1
-#endif
-
-#if (!XRTRTR_NEW_CROSS_RK_MODE)
- vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN);
-#endif
- SetMck8xLowPwrOption(p);
-}
-#endif
-
#define CKGEN_FMETER 0x0
#define ABIST_FMETER 0x1
/*
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
index 7233f33929..a95546b554 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
@@ -748,22 +748,6 @@ const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] =
//CA DRAM->APHY
#if (CA_PER_BIT_DELAY_CELL || PINMUX_AUTO_TEST_PER_BIT_CA)
-#if __LP5_COMBO__
-const U8 uiLPDDR5_CA_Mapping_POP[CHANNEL_NUM][7] =
-{
- //CH-A
- {
- 0, 1, 2, 3, 4, 5, 6
- },
-
-#if (CHANNEL_NUM>1)
- //CH-B
- {
- 0, 4, 2, 3, 1, 5, 6
- }
-#endif
-};
-#endif
U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] =
{
@@ -791,23 +775,6 @@ U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] =
};
#endif
-#if (__LP5_COMBO__)
-const U8 uiLPDDR5_O1_Mapping_POP[CHANNEL_NUM][16] =
-{
- {
- 8, 9, 10, 11, 12, 15, 14, 13,
- 0, 1, 2, 3, 4, 7, 6, 5,
- },
-
- #if (CHANNEL_NUM>1)
- {
- 8, 9, 10, 11, 12, 15, 14, 13,
- 0, 1, 2, 3, 4, 7, 6, 5,
- },
- #endif
-};
-#endif
-
//O1 DRAM->APHY
U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16] =
{
@@ -837,152 +804,6 @@ U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16] =
#endif
};
-#if 0
-static DRAM_STATUS_T DramcMRInit_LP4(DRAMC_CTX_T *p)
-{
- mcSHOW_DBG_MSG2(("=== LP4 MR Init ===\n"));
-
- U32 u4RankIdx;
- U8 u1MRFsp = FSP_0;
-
- DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
-
- // LP4_HIGHEST_FREQ == 1866
- /* Set MR01 OP[6:4] to 110B = 6 */
- u1MR01Value[FSP_0] |= (0x6 << 4);
- u1MR01Value[FSP_1] |= (0x6 << 4);
- mcSHOW_DBG_MSG2(("(FSP0)MR#1 = 0x%x\n", u1MR01Value[FSP_0]));
-
-// for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
- {
- for (u4RankIdx = 0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
- {
- // FSP_0
- u1MRFsp = FSP_0;
-// DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, TO_MR);
-
- //MR2 set Read/Write Latency
- if ((p->frequency == 800) || (p->frequency == 600) || (p->frequency == 400)) // DDR1600, DDR1200, DDR800
- {
- u1MR02Value[u1MRFsp] = 0x12;
- }
- else if (p->frequency <= 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1)
- {
- u1MR02Value[u1MRFsp] = 0x24;
- }
- else if (p->frequency <= 1333)
- {
- u1MR02Value[u1MRFsp] = 0x24;
- }
- else if (p->frequency <= 1600)
- {
- u1MR02Value[u1MRFsp] = 0x2d;
- }
- else if (p->frequency <= 1866)
- {
- u1MR02Value[u1MRFsp] = 0x36;
- }
- else // if (p->frequency > 1866)
- {
- u1MR02Value[u1MRFsp] = 0x3f;
- }
- DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
- mcSHOW_DBG_MSG2(("(FSP0)MR#2 = 0x%x\n", u1MR02Value[u1MRFsp]));
-
- // FSP_1
- u1MRFsp = FSP_1;
-
- //MR2 set Read/Write Latency
- if ((p->frequency == 800) || (p->frequency == 600) || (p->frequency == 400)) // DDR1600, DDR1200, DDR800
- {
- u1MR02Value[u1MRFsp] = 0x12;
- }
- else if (p->frequency <= 1200) // DDR2280, DDR2400 (DDR2667 uses FSP_1)
- {
- u1MR02Value[u1MRFsp] = 0x24;
- }
- else if (p->frequency <= 1333)
- {
- u1MR02Value[u1MRFsp] = 0x24;
- }
- else if (p->frequency <= 1600)
- {
- u1MR02Value[u1MRFsp] = 0x2d;
- }
- else if (p->frequency <= 1866)
- {
- u1MR02Value[u1MRFsp] = 0x36;
- }
- else // if (p->frequency > 1866)
- {
- u1MR02Value[u1MRFsp] = 0x3f;
- }
- DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
- mcSHOW_DBG_MSG2(("(FSP1)MR#2 = 0x%x\n", u1MR02Value[u1MRFsp]));
-
- // To do...
-
-#if FOR_DV_SIMULATION_USED == 1
- cal_sv_rand_args_t *psra = get_psra(); ;
-
- if (psra) {
- u1MR02Value[p->dram_fsp] = psra->mr2_value & 0x7F;
- DramcModeRegWriteByRank(p, p->rank, 2, u1MR02Value[p->dram_fsp]);
- }
-#endif /* FOR_DV_SIMULATION_USED */
- }
- }
-
- return DRAM_OK;
-}
-#endif
-#if __LP5_COMBO__
-DRAM_STATUS_T DramcMRInit_LP5(DRAMC_CTX_T *p)
-{
- mcSHOW_DBG_MSG2(("=== LP5 MR Init ===\n"));
-
- U32 u4RankIdx;
- U8 u1MRFsp = FSP_0;
-
- DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
-
-// for (u1ChannelIdx = 0; u1ChannelIdx < (p->support_channel_num); u1ChannelIdx++)
- {
- for (u4RankIdx = 0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
- {
- // FSP_0
- u1MRFsp = FSP_0;
-
-// if ((p->frequency == 2133) || (p->frequency == 3200))
- // DV SIM fix DDR6400 <=> Freq 3200
- {
- // u1MR18Value[u1MRFsp] = 0x03;
- // u1MR20Value[u1MRFsp] = 0x02;
- }
- mcSHOW_DBG_MSG2(("(FSP0)MR#18 = 0x%x\n", u1MR18Value[u1MRFsp]));
- mcSHOW_DBG_MSG2(("(FSP0)MR#20 = 0x%x\n", u1MR20Value[u1MRFsp]));
-
- // FSP_1
- u1MRFsp = FSP_1;
- // To do...
-
-
- }
- }
-
-#if FOR_DV_SIMULATION_USED == 1
- cal_sv_rand_args_t *psra = get_psra();
-
- if (psra) {
- u1MR18Value[p->dram_fsp] = psra->mr18_value;
- u1MR20Value[p->dram_fsp] = psra->mr20_value;
- }
-#endif
-
- return DRAM_OK;
-}
-#endif
-
#ifdef IMPEDANCE_TRACKING_ENABLE
static void ImpedanceTracking_DisImpHw_Setting(DRAMC_CTX_T *p, U8 u1DisImpHw)
{
@@ -1024,16 +845,6 @@ static void ImpedanceTracking_DisImpHw_Setting(DRAMC_CTX_T *p, U8 u1DisImpHw)
void vBeforeCalibration(DRAMC_CTX_T *p)
{
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- DramcMRInit_LP5(p);
- }
- else
-#endif
- {
- //DramcMRInit_LP4(p);
- }
#if SIMULATION_RX_DVS || ENABLE_RX_TRACKING
DramcRxInputDelayTrackingInit_byFreq(p);
@@ -1056,11 +867,6 @@ void vBeforeCalibration(DRAMC_CTX_T *p)
U8 u1DisImpHw;
U32 u4TermFreq, u4WbrBackup;
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- u4TermFreq = LP5_MRFSP_TERM_FREQ;
- else
-#endif
u4TermFreq = LP4_MRFSP_TERM_FREQ;
u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1;
@@ -1238,11 +1044,6 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
else
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF), 1, SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA);
- #if (__LP5_COMBO__ == TRUE)
- if (p->dram_type==TYPE_LPDDR5)
- u1VrefSel = 0x37;//unterm LP5
- else
- #endif
u1VrefSel = 0x37;//unterm LP4
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL),
@@ -1304,11 +1105,6 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
static inline u8 get_ca_pi_per_ui(DRAMC_CTX_T *p)
{
-#if __LP5_COMBO__
- if (p->freq_sel == LP5_DDR4266)
- return 64;
- else
-#endif
return 32;
}
@@ -1649,109 +1445,8 @@ static void set_cbt_wlev_intv_lp4(DRAMC_CTX_T *p)
set_cbt_intv_rg(p, pintv);
}
-#if __LP5_COMBO__
-static void set_cbt_wlev_intv_lp5(DRAMC_CTX_T *p)
-{
- struct cbt_intv intv[] = {
- {
- LP5_DDR6400,
- UNKNOWN_MODE,
- 15, /*tcmdo1lat*/
- 15, /* catrain_intv */
- 17, /* new_cbt_pat_intv */
- 17, /* wlev_dqspat_lat */
- }, {
- LP5_DDR6000,
- UNKNOWN_MODE,
- 15, /*tcmdo1lat*/
- 15, /* catrain_intv */
- 17, /* new_cbt_pat_intv */
- 17, /* wlev_dqspat_lat */
- }, {
- LP5_DDR5500,
- UNKNOWN_MODE,
- 14, /*tcmdo1lat*/
- 14, /* catrain_intv */
- 16, /* new_cbt_pat_intv */
- 16, /* wlev_dqspat_lat */
- }, {
- LP5_DDR4800,
- UNKNOWN_MODE,
- 13, /*tcmdo1lat*/
- 13, /* catrain_intv */
- 15, /* new_cbt_pat_intv */
- 15, /* wlev_dqspat_lat */
- }, {
- LP5_DDR4266,
- UNKNOWN_MODE,
- 20, /*tcmdo1lat*/
- 20, /* catrain_intv */
- 22, /* new_cbt_pat_intv */
- 20, /* wlev_dqspat_lat */
- }, {
- LP5_DDR3733,
- UNKNOWN_MODE,
- 19, /*tcmdo1lat*/
- 19, /* catrain_intv */
- 21, /* new_cbt_pat_intv */
- 19, /* wlev_dqspat_lat */
- }, {
- LP5_DDR3200,
- UNKNOWN_MODE,
- 15, /*tcmdo1lat*/
- 15, /* catrain_intv */
- 17, /* new_cbt_pat_intv */
- 17, /* wlev_dqspat_lat */
- }, {
- LP5_DDR2400,
- UNKNOWN_MODE,
- 13, /*tcmdo1lat*/
- 13, /* catrain_intv */
- 15, /* new_cbt_pat_intv */
- 15, /* wlev_dqspat_lat */
- }, {
- LP5_DDR1600,
- UNKNOWN_MODE,
- 17, /*tcmdo1lat*/
- 17, /* catrain_intv */
- 19, /* new_cbt_pat_intv */
- 17, /* wlev_dqspat_lat */
- }, {
- LP5_DDR1200,
- UNKNOWN_MODE,
- 15, /*tcmdo1lat*/
- 15, /* catrain_intv */
- 17, /* new_cbt_pat_intv */
- 15, /* wlev_dqspat_lat */
- }, {
- LP5_DDR800,
- UNKNOWN_MODE,
- 13, /*tcmdo1lat*/
- 13, /* catrain_intv */
- 15, /* new_cbt_pat_intv */
- 13, /* wlev_dqspat_lat */
- },
- };
-
- struct cbt_intv *pintv;
-
- pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv), p->freq_sel, UNKNOWN_MODE);
- if (!pintv) {
- mcSHOW_ERR_MSG(("not found entry!\n"));
- return;
- }
-
- set_cbt_intv_rg(p, pintv);
-}
-#endif /* __LP5_COMBO__ */
-
static void set_cbt_wlev_intv(DRAMC_CTX_T *p)
{
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- set_cbt_wlev_intv_lp5(p);
- else
-#endif
set_cbt_wlev_intv_lp4(p);
}
@@ -2042,11 +1737,6 @@ static u8 get_cbtui_adjustable_maxvalue(DRAMC_CTX_T *p)
* ther are only 0~7 for ui adjust, if ui value is larger than 7, adjust MCK.
*
*/
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- ratio = (get_mck_ck_ratio(p) == 1) ? 1 : 3;
- else
-#endif
ratio = (vGet_Div_Mode(p) == DIV4_MODE) ? 3 : 7;
return ratio;
@@ -2280,477 +1970,6 @@ static u32 get_capi_step(DRAMC_CTX_T *p, int autok)
return step;
}
-#if 0
-static int find_next_bit(u32 *bitmap, u8 bitval, u8 start, u8 end,
- u8 *bit_pos)
-{
- u8 i, base, ofst;
- u32 map;
- int res = 0;
-
- for (i = start; i < end + 1; i++) {
- base = (i >> 5); /* i / 32 */
- ofst = i & 0x1F; /* i % 32 */
- map = bitmap[base];
-
- if ((bitval == 0) && ((map & (1UL << ofst)) == 0UL)) {
- *bit_pos = i;
- res = 1;
- break;
- } else if (bitval && (map & (1UL << ofst))) {
- *bit_pos = i;
- res = 1;
- break;
- }
- }
-
- return res;
-}
-
-static int find_next_zero_bit(u32 *bitmap, u8 start, u8 end, u8 *bit_pos)
-{
- return find_next_bit(bitmap, 0, start, end, bit_pos);
-}
-
-static int find_next_one_bit(u32 *bitmap, u8 start, u8 end, u8 *bit_pos)
-{
- return find_next_bit(bitmap, 1, start, end, bit_pos);
-}
-
-static int find_zero_window(u32 *bitmap, u8 start, u8 end,
- u8 *win_start, u8 *win_end)
-{
- int res;
- u8 win_lsb, win_msb;
-
- if (start > end)
- return 0;
-
- res = find_next_zero_bit(bitmap, start, end, &win_lsb);
- if (!res)
- return 0;
-
- res = find_next_one_bit(bitmap, win_lsb + 1, end, &win_msb);
- if (!res)
- win_msb = end + 1;
-
- *win_start = win_lsb;
- *win_end = win_msb - 1;
-
- return 1;
-}
-#endif
-#if 0
-static int get_new_cbt_pat_cfg(DRAMC_CTX_T *p,
- new_cbt_pat_cfg_t *pncm, U8 u1CATrain)
-{
-#if __LP5_COMBO__
- if (is_lp5_family(p)) {
- /* lp5 */
- pncm->pat_v[0] = 0x04;
- pncm->pat_v[1] = 0x0B;
- pncm->pat_v[2] = 0x0B;
- pncm->pat_v[3] = 0x04;
- pncm->pat_v[4] = 0x04;
- pncm->pat_v[5] = 0x0B;
- pncm->pat_v[6] = 0x0A;
- pncm->pat_v[7] = 0x05;
-
- pncm->pat_a[0] = 0x00;
- pncm->pat_a[1] = 0x0F;
- pncm->pat_a[2] = 0x04;
- pncm->pat_a[3] = 0x0B;
- pncm->pat_a[4] = 0x04;
- pncm->pat_a[5] = 0x0B;
- pncm->pat_a[6] = 0x0A;
- pncm->pat_a[7] = 0x05;
-
- pncm->pat_dmv = 0x55;
- pncm->pat_dma = 0xAA;
-
- pncm->pat_cs0 = 0x0C;
- pncm->pat_cs1 = 0x0C;
- pncm->ca_golden_sel = 0x2;
- pncm->pat_num = 7;
- pncm->ca_num = 6;
- } else
-#endif
- {
- /* lp4 */
- pncm->pat_v[0] = 0x30;
- pncm->pat_v[1] = 0xCF;
- pncm->pat_v[2] = 0xCF;
- pncm->pat_v[3] = 0x30;
- pncm->pat_v[4] = 0x30;
- pncm->pat_v[5] = 0xCF;
- pncm->pat_v[6] = 0xCC;
- pncm->pat_v[7] = 0x33;
-
- pncm->pat_a[0] = 0x00;
- pncm->pat_a[1] = 0xFF;
- pncm->pat_a[2] = 0x30;
- pncm->pat_a[3] = 0xCF;
- pncm->pat_a[4] = 0x30;
- pncm->pat_a[5] = 0xCF;
- pncm->pat_a[6] = 0xCC;
- pncm->pat_a[7] = 0x33;
-
- pncm->pat_dmv = 0x55;
- pncm->pat_dma = 0xAA;
-
- pncm->pat_cs0 = 0x30;
- pncm->pat_cs1 = 0x30;
- pncm->ca_golden_sel = 0x4;
- pncm->pat_num = 7;
- pncm->ca_num = 5;
- }
-
- pncm->invert_num = 1;
-
-#if FOR_DV_SIMULATION_USED == 1
- cal_sv_rand_args_t *psra = get_psra();
-
- if (psra) {
- /*
- * DV's regression
- */
- int i;
-
- for (i = 0; i < 8; i++) {
- pncm->pat_v[i] = psra->pat_v[i] & 0xFF;
- pncm->pat_a[i] = psra->pat_a[i] & 0xFF;
- }
- pncm->pat_dmv = psra->pat_dmv & 0xFF;
- pncm->pat_dma = psra->pat_dma & 0xFF;
- pncm->pat_cs0 = psra->pat_cs & 0xFF;
- pncm->pat_cs1 = pncm->pat_cs0;
- pncm->ca_golden_sel = psra->cagolden_sel & 0xFF;
- pncm->invert_num = psra->invert_num & 0xFF;
- }
-#endif
-
- if (!u1CATrain) {
- pncm->pat_a[0] = pncm->pat_v[0] ^ 0xFF;
- pncm->pat_dmv = 0x00;
- pncm->pat_dma = 0x00;
- pncm->pat_num = 1;
- pncm->ca_num = 0;
- pncm->invert_num = 0;
- }
-
- return 0;
-}
-
-static void cfg_new_cbt_pat(DRAMC_CTX_T *p,
- new_cbt_pat_cfg_t *pncm)
-{
- u32 tmp;
-
- tmp = (pncm->pat_v[3] << 24) | (pncm->pat_v[2] << 16) |
- (pncm->pat_v[1] << 8) | pncm->pat_v[0];
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT0),
- tmp, INITK_PAT0_INITK_PAT0);
-
- tmp = (pncm->pat_v[7] << 24) | (pncm->pat_v[6] << 16) |
- (pncm->pat_v[5] << 8) | pncm->pat_v[4];
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT1),
- tmp, INITK_PAT1_INITK_PAT1);
-
- tmp = (pncm->pat_a[3] << 24) | (pncm->pat_a[2] << 16) |
- (pncm->pat_a[1] << 8) | pncm->pat_a[0];
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT2),
- tmp, INITK_PAT2_INITK_PAT2);
-
- tmp = (pncm->pat_a[7] << 24) | (pncm->pat_a[6] << 16) |
- (pncm->pat_a[5] << 8) | pncm->pat_a[4];
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT3),
- tmp, INITK_PAT3_INITK_PAT3);
-
- tmp = (pncm->pat_cs1 << 24) | (pncm->pat_cs0 << 16) |
- (pncm->pat_dma << 8) | pncm->pat_dmv;
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_INITK_PAT4),
- tmp, INITK_PAT4_INITK_PAT4);
-
-#ifdef CBT_NEW_PAT_DEBUG
- mcSHOW_DBG_MSG(("CBT NEW PAT:\n"));
- mcSHOW_DBG_MSG(("PAT0_V=0x%x, PAT0_A=0x%x\n", pncm->pat_v[0], pncm->pat_a[0]));
- mcSHOW_DBG_MSG(("PAT_DMV=0x%x, PAT_DMA=0x%x\n", pncm->pat_dmv, pncm->pat_dma));
- mcSHOW_DBG_MSG(("PAT_CS0=0x%x, PAT_CS1=0x%x\n", pncm->pat_cs0, pncm->pat_cs1));
-#endif
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5),
- P_Fld(1, CBT_WLEV_CTRL5_CBT_NEW_MODE) |
- P_Fld(p->rank, CBT_WLEV_CTRL5_NEW_CBT_PAT_RKSEL) |
- P_Fld(pncm->ca_num, CBT_WLEV_CTRL5_NEW_CBT_CA_NUM) |
- P_Fld(pncm->pat_num, CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM) |
- P_Fld(pncm->invert_num, CBT_WLEV_CTRL5_NEW_CBT_INVERT_NUM) |
- P_Fld(pncm->ca_golden_sel, CBT_WLEV_CTRL5_NEW_CBT_CAGOLDEN_SEL));
-}
-#endif
-#if CBT_O1_PINMUX_WORKAROUND
-static u32 CBTCompareWordaroundDecodeO1Pinmux(DRAMC_CTX_T *p, u32 o1_value, U8 *uiLPDDR_O1_Mapping)
-{
- U8 u1Idx;
- U32 u4Result;
-
- u4Result = 0;
-
- for (u1Idx = 0;u1Idx < p->data_width;u1Idx++)
- u4Result |= ((o1_value >> uiLPDDR_O1_Mapping[u1Idx]) & 0x1) << u1Idx;
-
- return u4Result;
-}
-
-#if CBT_OLDMODE_SUPPORT
-static u32 CBTDelayCACLKCompareWorkaround(DRAMC_CTX_T *p)
-{
- u8 u1pattern_index, u1ca_index, u1dq_index, u1dq_start, u1dq_end, u1ca_number_per_bit, u1bit_num_per_byte, u1pattern_choose;
- U8 *uiLPDDR_O1_Mapping = NULL;
- u32 u4TimeCnt, rdy, u4dq_o1, u4data_receive, u4ca_pattern, u4Result, u4Ready;
- u8 u1pattern_num;
-
- const U8 u1LP5CBT_Pattern_Mapping[2][7] =
- {
- {
- 1, 2, 4, 8, 16, 32, 64
- },
-
- {
- 126, 125, 123, 119, 111, 95, 63
- },
- };
- const U8 u1LP4CBT_Pattern_Mapping[2][6] =
- {
- {
- 1, 2, 4, 8, 16, 32
- },
-
- {
- 62, 61, 59, 55, 47, 31
- },
- };
-
- u4Result = 0;
- u1bit_num_per_byte = 8;
-
-#if (__LP5_COMBO__)
- if (is_lp5_family(p))
- {
- uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel];
- u1pattern_num = 8;
- u1ca_number_per_bit = CATRAINING_NUM_LP5;
- if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
- {
- u1dq_start = 0;
- u1dq_end = 6;
- }
- else
- {
- u1dq_start = 0;
- u1dq_end = 14;
- }
- }
- else
-#endif
- {
- uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
- u1pattern_num = 4;
- u1ca_number_per_bit = CATRAINING_NUM_LP4;
- if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
- {
- u1dq_start = 8;
- u1dq_end = 13;
- }
- else
- {
- u1dq_start = 0;
- u1dq_end = 13;
- }
- }
-
- vIO32WriteFldMulti(DRAMC_REG_CBT_WLEV_CTRL3, P_Fld(0x1, CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0)
- | P_Fld(0x1, CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1));
-
- for (u1pattern_index = 0; u1pattern_index < u1pattern_num; u1pattern_index++)
- {
- u1pattern_choose = (u1pattern_index > 3) ? (u1pattern_index % 2) : /* LP5 mapping */
- ((u1pattern_index > 1)? (3 - u1pattern_index) : u1pattern_index); /* LP5 & LP4 mapping */
- for (u1ca_index = 0; u1ca_index < u1ca_number_per_bit; u1ca_index++)
- {
- #if (__LP5_COMBO__)
- if (is_lp5_family(p))
- {
- u4ca_pattern = u1LP5CBT_Pattern_Mapping[u1pattern_choose][u1ca_index];
- }
- else
- #endif
- {
- u4ca_pattern = u1LP4CBT_Pattern_Mapping[u1pattern_choose][u1ca_index];
- }
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), P_Fld((u1pattern_index+1), CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0)
- | P_Fld((u1ca_index+1), CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1));
-
- u4TimeCnt = TIME_OUT_CNT;
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_CAPATEN);
-
- //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT)
- do
- {
- u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS1), CBT_WLEV_STATUS1_CATRAIN_CMP_CPT);
- u4TimeCnt --;
- mcDELAY_US(1);
- }while ((u4Ready == 0) && (u4TimeCnt > 0));
-
- if (u4TimeCnt == 0)//time out
- {
- mcSHOW_ERR_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
- mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
- //return DRAM_FAIL;
- }
-
- u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO);
-
- u4dq_o1 = CBTCompareWordaroundDecodeO1Pinmux(p, u4dq_o1, uiLPDDR_O1_Mapping);
-
- if (u1dq_end >= u1ca_number_per_bit)
- u4ca_pattern |= u4ca_pattern << u1bit_num_per_byte;
-
- u4dq_o1 ^= u4ca_pattern;
-
- for(u1dq_index=u1dq_start; u1dq_index<=u1dq_end; u1dq_index++)
- {
- if ((p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) && (u1dq_index == u1ca_number_per_bit))
- u1dq_index = u1bit_num_per_byte;
-
- u4data_receive = (u4dq_o1 >> u1dq_index) & 0x1;
-
- if (u1dq_index < u1bit_num_per_byte)
- u4Result |= u4data_receive << u1dq_index;
- else
- u4Result |= u4data_receive << u1dq_index - u1bit_num_per_byte;
- }
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_CAPATEN);
-
- }
- if (u4Result == ((0x1 << u1ca_number_per_bit) - 1))
- break;
- }
- return u4Result;
-}
-#endif
-
-static u32 new_cbt_pat_compare_workaround(DRAMC_CTX_T *p, new_cbt_pat_cfg_t *ncm)
-{
- u8 u1pattern_index, u1ca_index, u1dq_index, u1dq_start, u1dq_end, u1ca_number_per_bit, u1bit_num_per_byte;
- U8 *uiLPDDR_O1_Mapping = NULL;
- u32 u4TimeCnt, rdy, u4dq_o1, u4data_receive, u4ca_pattern_a, u4ca_pattern, u4Result, u4Ready;
- u8 u1pattern_num;
-
- u4Result = 0;
- u1bit_num_per_byte = 8;
-
-#if (__LP5_COMBO__)
- if (is_lp5_family(p))
- {
- uiLPDDR_O1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[p->channel];
- u1pattern_num = 8;
- u1ca_number_per_bit = 7;
- if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
- {
- u1dq_start = 0;
- u1dq_end = 6;
- }
- else
- {
- u1dq_start = 0;
- u1dq_end = 14;
- }
- }
- else
-#endif
- {
- uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
- u1pattern_num = 4;
- u1ca_number_per_bit = 6;
- if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE)
- {
- u1dq_start = 8;
- u1dq_end = 13;
- }
- else
- {
- u1dq_start = 0;
- u1dq_end = 13;
- }
- }
-
- for (u1pattern_index = 0; u1pattern_index < u1pattern_num; u1pattern_index++)
- {
- u4ca_pattern_a = ((ncm->pat_a[u1pattern_index] >> ncm->ca_golden_sel) & 0x1) ? ((0x1 << u1ca_number_per_bit) - 1) : 0x0;
-
- for (u1ca_index = 0; u1ca_index < u1ca_number_per_bit; u1ca_index++)
- {
- u4ca_pattern = u4ca_pattern_a & ~(0x1 << u1ca_index);
-
- if ((ncm->pat_v[u1pattern_index] >> ncm->ca_golden_sel) & 0x1)
- u4ca_pattern |= 0x1 << u1ca_index;
-
- if (ncm->invert_num)
- u4ca_pattern ^= (0x1 << u1ca_number_per_bit) - 1;
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), P_Fld(u1pattern_index, CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM)
- | P_Fld(u1ca_index, CBT_WLEV_CTRL5_NEW_CBT_CA_NUM));
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 1, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
-
- //Check CA training compare ready (dramc_conf_nao 0x3fc , CATRAIN_CMP_CPT)
- do
- {
- u4Ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS2), CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT);
- u4TimeCnt --;
- mcDELAY_US(1);
- }while ((u4Ready == 0) && (u4TimeCnt > 0));
-
- if (u4TimeCnt == 0)//time out
- {
- mcSHOW_ERR_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
- mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
- //return DRAM_FAIL;
- }
-
- u4dq_o1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQO1), MISC_DQO1_DQO1_RO);
-
- u4dq_o1 = CBTCompareWordaroundDecodeO1Pinmux(p, u4dq_o1, uiLPDDR_O1_Mapping);
-
- if (u1dq_end >= u1ca_number_per_bit)
- u4ca_pattern |= u4ca_pattern << u1bit_num_per_byte;
-
- u4dq_o1 ^= u4ca_pattern;
-
- for(u1dq_index=u1dq_start; u1dq_index<=u1dq_end; u1dq_index++)
- {
- if ((p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) && (u1dq_index == u1ca_number_per_bit))
- u1dq_index = u1bit_num_per_byte;
-
- u4data_receive = (u4dq_o1 >> u1dq_index) & 0x1;
-
- if (u1dq_index < u1bit_num_per_byte)
- u4Result |= u4data_receive << u1dq_index;
- else
- u4Result |= u4data_receive << u1dq_index - u1bit_num_per_byte;
- }
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), 0, CBT_WLEV_CTRL5_NEW_CBT_CAPATEN);
- }
- if (u4Result == ((0x1 << u1ca_number_per_bit) - 1))
- break;
- }
- return u4Result;
-}
-#endif
void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM)
{
@@ -3062,13 +2281,6 @@ static void CATrainingSetPerBitDelayCell(DRAMC_CTX_T *p, S16 *iCAFinalCenter, U8
U8 u1CA;
S8 iCA_PerBit_DelayLine[8] = {0};
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- uiLPDDR_CA_Mapping = (U8 *)uiLPDDR5_CA_Mapping_POP[p->channel];
- }
- else
-#endif
{
uiLPDDR_CA_Mapping = (U8 *)uiLPDDR4_CA_Mapping_POP[p->channel];
}
@@ -3133,36 +2345,6 @@ static void CBTSetCACLKResult(DRAMC_CTX_T *p, U32 u4MCK, U32 u4UI, U8 ca_pin_num
vSetRank(p, backup_rank);
}
-#if (__LP5_COMBO__)
-/* Return (Vref_B0 | (Vref_B1 << 8) to support Byte mode */
-static U8 GetCBTVrefPinMuxValue_lp5(DRAMC_CTX_T *p, U8 u1VrefLevel)
-{
- U8 u2VrefBit, u2Vref_org;
- U16 u2Vref_new;
-
- u2Vref_org = u1VrefLevel & 0x7f;
-
- u2Vref_new = 0;
-
- for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
- {
- //mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]));
- if (u2Vref_org & (1 << u2VrefBit))
- {
- u2Vref_new |= (1 << uiLPDDR5_O1_Mapping_POP[p->channel][u2VrefBit]);
- }
- }
-
- mcSHOW_DBG_MSG4(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
-
- if (lp5_cp[p->channel].dram_dq_b0)
- u2Vref_new >>= 8;
-
- return u2Vref_new;
-}
-
-#endif
-
static U8 GetCBTVrefPinMuxValue(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel)
{
U8 u2VrefBit, u2Vref_org;
@@ -3191,31 +2373,6 @@ static U8 GetCBTVrefPinMuxValue(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel)
return u2Vref_new;
}
-#if 0
-static U8 GetCBTVrefPinMuxRevertValue(DRAMC_CTX_T *p, U8 u1VrefLevel)
-{
- U8 u2VrefBit, u2Vref_new, u2Vref_org;
-
- if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
- return u1VrefLevel;
-
- u2Vref_new = 0;
- u2Vref_org = u1VrefLevel;
- for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
- {
-#if (__LP5_COMBO__)
- if (is_lp5_family(p)) {
- u2Vref_new |= ((u2Vref_org >> uiLPDDR5_O1_Mapping_POP[p->channel][u2VrefBit]) & 1) << u2VrefBit;
- } else
-#endif
- u2Vref_new |= ((u2Vref_org >> uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]) & 1) << u2VrefBit;
- }
-
- mcSHOW_DBG_MSG4(("=== Revert u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
-
- return u2Vref_new;
-}
-#endif
static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 operating_fsp, U8 stateFlag)
{
U32 fld;
@@ -3266,492 +2423,8 @@ static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 ope
}
-#if __LP5_COMBO__
-static inline u8 is_training_mode1(DRAMC_CTX_T *p)
-{
- return is_lp5_family(p) && p->lp5_training_mode == TRAINING_MODE1? 1: 0;
-}
-
-static inline u8 is_training_mode2(DRAMC_CTX_T *p)
-{
- return is_lp5_family(p) && p->lp5_training_mode == TRAINING_MODE2? 1: 0;
-}
-
-static inline u8 is_phase_falling(DRAMC_CTX_T *p)
-{
- return is_lp5_family(p) && p->lp5_cbt_phase == CBT_PHASE_FALLING? 1: 0;
-}
-
-static void force_dq7(DRAMC_CTX_T *p, u8 level)
-{
- u32 fld_b0, fld_b1;
- u8 dq;
- u8 dramc_byte;
- struct cbt_pinmux *cp = &lp5_cp[p->channel];
- /*
- * TODO
- *
- * pinmux to selec dq7
- *
- */
-
- fld_b0 = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0;
- fld_b1 = (cp->dram_dq_b1) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0;
-
- dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- fld_b0);
- dq &= ~(1 << (cp->dram_dq7_b0 % 8));
- dq |= ((level & 1) << (cp->dram_dq7_b0 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- P_Fld(dq, fld_b0));
-
- if (is_byte_mode(p)) {
- dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- fld_b1);
- dq &= ~(1 << (cp->dram_dq7_b1 % 8));
- dq |= ((level & 1) << (cp->dram_dq7_b1 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- P_Fld(dq, fld_b1));
- }
-}
-
-static inline void force_dmi(DRAMC_CTX_T *p, u8 level)
-{
- struct cbt_pinmux *cp = &lp5_cp[p->channel];
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- P_Fld(level, (cp->dram_dmi_b0) ? CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 : CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5));
-
- if (is_byte_mode(p)) {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- P_Fld(level, (cp->dram_dmi_b1 ? CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 : CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5)));
- }
-}
-
-static void toggle_wck(DRAMC_CTX_T *p, u8 toggle)
-{
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- P_Fld(toggle, CBT_WLEV_CTRL0_CBT_WLEV_WCKAO));
-}
-
-static void set_vref_by_mrw(DRAMC_CTX_T *p, u8 vref)
-{
- DramcModeRegWriteByRank(p, p->rank, 12, vref);
-}
-
-static void set_vref_by_dq(DRAMC_CTX_T *p, u16 vref)
-{
- u8 dq;
- struct cbt_pinmux *cp = &lp5_cp[p->channel];
-
- force_dmi(p, 0);
- /* wait tCBTRTW */
- mcDELAY_US(1);
-
- if (is_byte_mode(p)) {
- /* DRAMC B0/B1 as TX */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- 3, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
-
- /* Set DRAM Byte 1 */
- dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- (cp->dram_dq_b1 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0));
-
- /* Shall be carefully processed in case DQ[7] is changed */
- dq &= (1 << (cp->dram_dq7_b1 % 8));
- dq |= ((vref >> 8) & 0xff);
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- P_Fld(dq, (cp->dram_dq_b1 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0)));
- } else {
- /* DRAMC B0 as TX */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- (1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
- }
-
- /* Set DRAM Byte 0 */
- dq = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- (cp->dram_dq_b0 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0));
- dq &= (1 << (cp->dram_dq7_b0 % 8));
- dq |= (vref & 0xff);
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4),
- P_Fld(dq, (cp->dram_dq_b0 ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0)));
-
- /* wait tDQStrain */
- mcDELAY_US(1);
- force_dmi(p, 1);
- mcDELAY_US(1);
- /* DRAMC B0/B1 as RX */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- 0, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
- mcDELAY_US(1);
-}
-
-static void switch_oe_tie(DRAMC_CTX_T *p, u8 sw)
-{
- u8 dq_oe;
- struct cbt_pinmux *cp = &lp5_cp[p->channel];
-
- if (sw) {
- /* Set DRAM Byte 0 */
- if (cp->dram_dq_b0) {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
- dq_oe |= (1 << (cp->dram_dq7_b0 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
- P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
- P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
- } else {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
- dq_oe |= (1 << (cp->dram_dq7_b0 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
- P_Fld(1, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
- P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
- }
-
- /* Set DRAM Byte 1 */
- if (is_byte_mode(p)) {
- /* Set DRAM Byte 0 */
- if (cp->dram_dq_b1) {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
- dq_oe |= (1 << (cp->dram_dq7_b1 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
- P_Fld(1, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
- P_Fld(1, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
- } else {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
- dq_oe |= (1 << (cp->dram_dq7_b1 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
- P_Fld(1, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
- P_Fld(1, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
- }
- }
- } else {
- /* Set DRAM Byte 0 */
- if (cp->dram_dq_b0) {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
- dq_oe &= ~(1 << (cp->dram_dq7_b0 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
- P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
- P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
- } else {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
- dq_oe &= ~(1 << (cp->dram_dq7_b0 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
- P_Fld(0, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
- P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
- }
-
- /* Set DRAM Byte 1 */
- if (is_byte_mode(p)) {
- /* Set DRAM Byte 0 */
- if (cp->dram_dq_b1) {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1);
- dq_oe &= ~(1 << (cp->dram_dq7_b1 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(dq_oe, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) |
- P_Fld(0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2),
- P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) |
- P_Fld(0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1));
- } else {
- dq_oe = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0);
- dq_oe &= ~(0 << (cp->dram_dq7_b1 % 8));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(dq_oe, B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0) |
- P_Fld(0, B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0));
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2),
- P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0) |
- P_Fld(0, B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0));
- }
- }
- }
-}
-
-static void lp5_cbt_entry(DRAMC_CTX_T *p, u8 operating_fsp,
- u16 operation_frequency)
-{
- lp5heff_save_disable(p);
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
- 0, MISC_STBCAL_DQSIENCG_NORMAL_EN);
-
- /* TCMDEN and CATRAINEN use MRSRK */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0),
- p->rank, SWCMD_CTRL0_MRSRK);
-
- #if 0
- if (p->rank == RANK_0) {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- P_Fld(0, CKECTRL_CKEFIXOFF) |
- P_Fld(1, CKECTRL_CKEFIXON));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- P_Fld(1, CKECTRL_CKE1FIXOFF) |
- P_Fld(0, CKECTRL_CKE1FIXON));
- } else if (p->rank == RANK_1) {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- P_Fld(0, CKECTRL_CKE1FIXOFF) |
- P_Fld(1, CKECTRL_CKE1FIXON));
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- P_Fld(1, CKECTRL_CKEFIXOFF) |
- P_Fld(0, CKECTRL_CKEFIXON));
- }
- #else
- if (p->rank == RANK_0) {
- CKEFixOnOff(p, RANK_0, CKE_FIXON, TO_ONE_CHANNEL);
- CKEFixOnOff(p, RANK_1, CKE_FIXOFF, TO_ONE_CHANNEL);
- } else if (p->rank == RANK_1){
- CKEFixOnOff(p, RANK_1, CKE_FIXON, TO_ONE_CHANNEL);
- CKEFixOnOff(p, RANK_0, CKE_FIXOFF, TO_ONE_CHANNEL);
- }
- #endif
-
- /*
- * APHY TX PI Spec mode option
- * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
- */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
- 1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
-
- /*
- * APHY TX PI Spec mode option
- * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
- */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
- 1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
-
- /*
- * APHY TX PI Spec mode option
- * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
- */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
- 1, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- P_Fld(0x1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN));
-
- /*
- * TODO
- * BYTEMODE, PINMUX
- */
- if (is_training_mode1(p)) {
- /* DRAMC B0 as RX */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- 0, CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN);
- }
-
- switch_oe_tie(p, 1);
-
- /*
- * MR13 OP[6], cbt mode
- * 0, training mode 1
- * 1, training mode 2
- *
- * TODO
- * MR13 values??
- */
- DramcModeRegWriteByRank(p, p->rank, 13, p->lp5_training_mode << 6);
-
- if (operating_fsp == FSP_2) {
- /*
- * dram will switch to another FSP_OP automatically
- */
- DramcModeRegWriteByRank(p, p->rank, 16,
- (2 << MR16_FSP_WR_SHIFT) |
- (2 << MR16_FSP_OP_SHIFT) |
- (p->lp5_cbt_phase << MR16_CBT_PHASE) |
- /* CBT enabled fsp[2] */
- (3 << MR16_FSP_CBT) |
- (1 << MR16_VRCG));
- } else if (operating_fsp == FSP_1) {
- /*
- * dram will switch to another FSP_OP automatically
- */
- DramcModeRegWriteByRank(p, p->rank, 16,
- (1 << MR16_FSP_WR_SHIFT) |
- (1<< MR16_FSP_OP_SHIFT) |
- (p->lp5_cbt_phase << MR16_CBT_PHASE) |
- /* CBT enabled fsp[1] */
- (2 << MR16_FSP_CBT) |
- (1 << MR16_VRCG));
- } else {
- /* FSP_0 */
- DramcModeRegWriteByRank(p, p->rank, 16,
- (0 << MR16_FSP_WR_SHIFT) |
- (0 << MR16_FSP_OP_SHIFT) |
- (p->lp5_cbt_phase << MR16_CBT_PHASE) |
- /* CBT enabled fsp[0] */
- (1 << MR16_FSP_CBT) |
- (1 << MR16_VRCG));
- }
-
- /* wait tCBTWCKPRE_static */
- mcDELAY_US(1);
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3),
- P_Fld(0x5, CBT_WLEV_CTRL3_DQSBX_G) |
- P_Fld(0x5, CBT_WLEV_CTRL3_DQSBY_G) |
- P_Fld(0x5, CBT_WLEV_CTRL3_DQSBX1_G) |
- P_Fld(0x5, CBT_WLEV_CTRL3_DQSBY1_G));
-
- if (is_byte_mode(p)) {
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 3, CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL);
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) |
- P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1
- } else {
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), (1 << lp5_cp[p->channel].dram_dq_b0),
- CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL);
- }
-
- /* toggle WCK */
- toggle_wck(p, 1);
-
- /* wait tWCK2DQ7H */
- mcDELAY_US(1);
-
- /* DQ[7] = High */
- force_dq7(p, 1);
-
- /* wait tDQ7HWCK to switch FSP */
- mcDELAY_US(1);
-
- /* stop toggle WCK */
- toggle_wck(p, 0);
-
- /* wait tDQ72DQ */
- mcDELAY_US(1);
-
- O1PathOnOff(p, 1);
-
- /* start toggle WCK */
- toggle_wck(p, 1);
-
- /* Wait tCAENT */
- mcDELAY_US(1);
-}
-
-static void lp5_cbt_exit(DRAMC_CTX_T *p, u8 operating_fsp,
- u8 operation_frequency)
-{
- /* drive dq7 low */
- force_dq7(p, 0);
-
- /* wait tDQ7WCK */
- mcDELAY_US(1);
-
- /* stop wck toggle */
- toggle_wck(p, 0);
-
- /* wait tVREFCA_LOGNG */
- mcDELAY_US(1);
-
- if (operating_fsp == FSP_2) {
- DramcModeRegWriteByRank(p, p->rank, 16,
- (2 << MR16_FSP_WR_SHIFT) |
- (2 << MR16_FSP_OP_SHIFT) |
- (0 << MR16_CBT_PHASE) |
- /* normal operation */
- (0 << MR16_FSP_CBT) |
- (1 << MR16_VRCG));
- } else if (operating_fsp == FSP_1) {
- DramcModeRegWriteByRank(p, p->rank, 16,
- (1 << MR16_FSP_WR_SHIFT) |
- (1 << MR16_FSP_OP_SHIFT) |
- (0 << MR16_CBT_PHASE) |
- /* normal operation */
- (0 << MR16_FSP_CBT) |
- (1 << MR16_VRCG));
- } else {
- DramcModeRegWriteByRank(p, p->rank, 16,
- (0 << MR16_FSP_WR_SHIFT) |
- (0 << MR16_FSP_OP_SHIFT) |
- (0 << MR16_CBT_PHASE) |
- /* normal operation */
- (0 << MR16_FSP_CBT) |
- (1 << MR16_VRCG));
- }
-
- /* wait tMRD */
- mcDELAY_US(1);
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0),
- P_Fld(0x0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN));
- switch_oe_tie(p, 0);
-
- /*
- * APHY TX PI Spec mode option
- * for K RK1, if RK0/1 DQ UI setting is not the same, it will fail
- */
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL),
- 0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE);
-
- /* Disable O1 path output */
- O1PathOnOff(p, 0);
-
- if (is_byte_mode(p)) {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) |
- P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); //BYTEMODECBTEN=1
- }
-
- #if 0
- if (p->rank == RANK_0) {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- P_Fld(0, CKECTRL_CKEFIXOFF) |
- P_Fld(0, CKECTRL_CKEFIXON));
- } else if (p->rank == RANK_1) {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- P_Fld(0, CKECTRL_CKE1FIXOFF) |
- P_Fld(0, CKECTRL_CKE1FIXON));
- }
- #else
- CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL);
- #endif
-
- lp5heff_restore(p);
-}
-#endif
-
static void CBTEntryLP45(DRAMC_CTX_T *p, U8 u1FSP, U16 u2Freq)
{
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- lp5_cbt_entry(p, u1FSP, u2Freq);
- }
- else
-#endif
{
if(p->dram_fsp == FSP_1)
{
@@ -3778,16 +2451,6 @@ static void CBTExitLP45(DRAMC_CTX_T *p, U8 u1FSP, U8 u2Freq, U8 stateFlag)
* if stateFlag == IN_CBT, it means we are trying to setup vref by MRW
* IN_CBT case, only for LP5 mode 1 and LP4 byte mode
*/
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- if (stateFlag == OUT_CBT || is_training_mode1(p))
- {
- lp5_cbt_exit(p, u1FSP, u2Freq);
- }
- }
- else
-#endif
{
if (stateFlag == OUT_CBT || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
{
@@ -3802,40 +2465,6 @@ static void CBTExitLP45(DRAMC_CTX_T *p, U8 u1FSP, U8 u2Freq, U8 stateFlag)
static void CBTSetVrefLP45(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 u1FSP, U16 u2Freq, U8 stateFlag)
{
- /* by yirong.wang
- * if stateFlag == OUT_CBT, it means we are not in CBT, setup vref by MRW
- * if stateFlag == IN_CBT, it means we are doing CBT
- * LP5 training mode 1 and LP4 byte mode, exit CBT and setup vref by MRW, then re-enter CBT
- * LP5 training mode 2 and LP4 normal mode, setup vref by DQ
- */
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- if (stateFlag == IN_CBT && is_training_mode2(p))
- {
- /*
- * training mode2
- * TODO, according to pinmux to adjust u1VrefLevel
- */
- set_vref_by_dq(p, GetCBTVrefPinMuxValue_lp5(p, u1VrefLevel));
- }
- else
- {
- if (stateFlag == IN_CBT && is_training_mode1(p))
- {
- lp5_cbt_exit(p, u1FSP, u2Freq);
- }
-
- set_vref_by_mrw(p, u1VrefLevel);
-
- if (stateFlag == IN_CBT && is_training_mode1(p))
- {
- lp5_cbt_entry(p, u1FSP, u2Freq);
- }
- }
- }
- else
-#endif
{
if (stateFlag == IN_CBT && p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
{
@@ -3870,9 +2499,6 @@ static void CBTScanPI(DRAMC_CTX_T *p, S16 *s2PIStart, S16 *s2PIEnd, S16 *s2PISte
*s2PIStart = 0;
*s2PIEnd = p2u * 3 - 1;
-#if __LP5_COMBO__
- if (!is_lp5_family(p))
-#endif
{
/* LPDDR4 */
#if !CBT_MOVE_CA_INSTEAD_OF_CLK
@@ -3969,14 +2595,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type)
mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
#endif
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp];
- ca_pin_num = CATRAINING_NUM_LP5;
- }
- else
-#endif
{
u1FinalRange = u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6;
u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp] & 0x3f;
@@ -4018,13 +2636,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type)
mcSHOW_DBG_MSG(("[CmdBusTrainingLP45] new_cbt_mode=%d, autok=%d\n", p->new_cbt_mode, autok));
mcSHOW_DBG_MSG2(("pi_start=%d, pi_end=%d, pi_step=%d\n", pi_start, pi_end, pi_step));
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- mcSHOW_DBG_MSG2(("lp5_training_mode=%d, lp5_cbt_phase=%d\n", p->lp5_training_mode, p->lp5_cbt_phase));
- }
-#endif
-
//Back up dramC register
DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress));
@@ -4160,38 +2771,16 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type)
/* ------------- CS and CLK ---------- */
/* delay ca 1UI before K CS */
-#if __LP5_COMBO__
- if (is_phase_falling(p)) {
- ca_mck = get_ca_mck(p);
- ca_ui = get_ca_ui(p);
- xlate_ca_mck_ui(p, 1,
- ca_mck, ca_ui,
- &ca_mck_tmp, &ca_ui_tmp);
- put_ca_mck(p, ca_mck_tmp);
- put_ca_ui(p, ca_ui_tmp);
- }
-#endif
if (u1CBTEyeScanEnable == DISABLE)
{
CBTAdjustCS(p, autok);
}
- /* restore ca mck and ui */
-#if __LP5_COMBO__
- if (is_phase_falling(p)) {
- put_ca_mck(p, ca_mck);
- put_ca_ui(p, ca_ui);
- }
-#endif
-
//------- Going to exit Command bus training(CBT) mode.-------------
CBTExitLP45(p, operating_fsp, operation_frequency, OUT_CBT);
CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, OUT_CBT);
-#if __LP5_COMBO__
- if (!is_lp5_family(p))
-#endif
{
if (p->dram_fsp == FSP_1)
{
@@ -4232,25 +2821,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type)
U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p)
{
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- //in LP4 1:8 mode, 8 small UI = 1 large UI
- if (vGet_Div_Mode(p) == DIV4_MODE)
- {
- return MCK_TO_4UI_SHIFT;
- }
- else if (vGet_Div_Mode(p) == DIV16_MODE)
- {
- return MCK_TO_16UI_SHIFT;
- }
- else
- {
- return MCK_TO_8UI_SHIFT;
- }
- }
- else
-#endif
{
//in LP4 1:8 mode, 8 small UI = 1 large UI
if (vGet_Div_Mode(p) == DIV4_MODE)
@@ -4421,35 +2991,8 @@ void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
// LP4_ShiftDQUI(p, iShiftUI, ALL_BYTES);
//}
-#if __LP5_COMBO__
-static void LP5_ShiftWCKUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
-{
- REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_WCK_WR_UI, SHURK_WCK_WR_UI_WCK_WR_B0_UI}, // Byte0
- {DRAMC_REG_SHURK_WCK_WR_UI, SHURK_WCK_WR_UI_WCK_WR_B1_UI}, // Byte1
- {DRAMC_REG_SHURK_WCK_RD_UI, SHURK_WCK_RD_UI_WCK_RD_B0_UI}, // Byte0
- {DRAMC_REG_SHURK_WCK_RD_UI, SHURK_WCK_RD_UI_WCK_RD_B1_UI}, // Byte1
- {DRAMC_REG_SHURK_WCK_FS_UI, SHURK_WCK_FS_UI_WCK_FS_B0_UI}, // Byte0
- {DRAMC_REG_SHURK_WCK_FS_UI, SHURK_WCK_FS_UI_WCK_FS_B1_UI}}; // Byte1
- REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK},
- {DRAMC_REG_SHURK_WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK},
- {DRAMC_REG_SHURK_WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK},
- {DRAMC_REG_SHURK_WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK},
- {DRAMC_REG_SHURK_WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK},
- {DRAMC_REG_SHURK_WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK}};
-
- _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs,
- sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T),
- iShiftUI, eByteIdx);
-}
-#endif
-
static void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx)
{
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- LP5_ShiftWCKUI(p, iShiftUI, eByteIdx);
- else
-#endif
{
LP4_ShiftDQSUI(p, iShiftUI, eByteIdx);
LP4_ShiftDQS_OENUI(p, iShiftUI, eByteIdx);
@@ -4483,18 +3026,7 @@ U8 u1IsPhaseMode(DRAMC_CTX_T *p)
else // DDR800_CLOSE_LOOP and NORMAL_CLOSE_LOOP
return FALSE;
}
-#if __LP5_COMBO__
-static void vSetLP5Dram_WCK2CK_WlevOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
-{
- // MR18 OP[6] to enable/disable WCK2CK leveling
- if (u1OnOff)
- u1MR18Value[p->dram_fsp] |= 0x40; // OP[6] WCK2CK Leveling = 1
- else
- u1MR18Value[p->dram_fsp] &= 0xBF; // OP[6] WCK2CK Leveling = 0
- DramcModeRegWriteByRank(p, p->rank, 18, u1MR18Value[p->dram_fsp]);
-}
-#endif
#if 0
static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg)
{
@@ -4736,20 +3268,6 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
ShiftDQ_OENUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES);
ShiftDQSWCK_UI(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES);
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- // For DLY based WCK leveling
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), 0, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), 0, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
-
- // Set DQS DLY-based delay to 16
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), STORAGED_DLY_UNIT, SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1);
- }
-#endif
// Set DQS PI-based delay to 0
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); //rank0, byte0, DQS delay
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); //rank0, byte1, DQS delay
@@ -4817,12 +3335,6 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
#endif
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
-
- vSetLP5Dram_WCK2CK_WlevOnOff(p, DISABLE);
- else
-#endif
vSetDramMRWriteLevelingOnOff(p, DISABLE); // Disable DDR write leveling mode: issue MR2[7] to enable write leveling
@@ -5950,45 +4462,6 @@ U8 __wa__gating_swk_for_autok = 0;
U8 __wa__gating_autok_init_ui[RANK_MAX] = { 0 };
#endif
-#if (__LP5_COMBO__)
-static U8 u1GetLp5ReadLatency(DRAMC_CTX_T *p)
-{
- U8 read_latency;
- U8 rl, ckr, dvfsc;
-
- const U8 au1MR2MappingToRL_wo_dvfsc[2][12] = {
- {3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 15, 17}, /* CKR = 4:1 */
- {6, 8, 10, 12, 16, 18}, /* CKR = 2:1 */
- };
-
- ///TODO: Spec has not specify these values
- const U8 au1MR2MappingToRL_wi_dvfsc[2][6] = {
- {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, /* CKR = 4:1 */
- {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, /* CKR = 2:1 */
- };
-
- ckr = (u1MR18Value[p->dram_fsp] >> 7) & 0x1;
- dvfsc = !!(u1MR19Value[p->dram_fsp] & 0x3);
- rl = (u1MR02Value[p->dram_fsp] & 0xf);
-
- if (dvfsc)
- read_latency = au1MR2MappingToRL_wi_dvfsc[ckr][rl];
- else
- read_latency = au1MR2MappingToRL_wo_dvfsc[ckr][rl];
-
- /* note that the uint of RL is nCK, convert to nWCK */
- if (ckr == 0)
- read_latency *= 4;
- else
- read_latency *= 2;
-
- mcSHOW_DBG_MSG2(("ckr = %d, dvfsc = %d, rl = %d, read_latency = %d\n",
- ckr, dvfsc, rl, read_latency));
-
- return read_latency;
-}
-#endif
-
static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK)
{
const U8 au1MR2MappingToRL[2][8] = {{6, 10, 14, 20, 24, 28, 32, 36}, //normal mode
@@ -6013,12 +4486,6 @@ static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK)
u1MR0_LatencyMode = (gu2MR0_Value[p->rank]>>1) & 0x1; //MR0 OP[1], 0:normal mode, 1:byte mode
}
-#if (__LP5_COMBO__)
- if (is_lp5_family(p)) {
- u4TDQSCK_UI_min = 500 * DDRPhyGetRealFreq(p) *2/ 1000000;
- u1RealRL = u1GetLp5ReadLatency(p);
- } else
-#endif
{
u4TDQSCK_UI_min = 1500 * DDRPhyGetRealFreq(p) *2/ 1000000;
u1RealRL = au1MR2MappingToRL[u1MR0_LatencyMode][u1MR2RLValue];
@@ -6035,16 +4502,6 @@ static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK)
{
u1MCK2CK_UI = 8;
u1ExtraMCKfor1_4mode = 0;
-#if (__LP5_COMBO__)
- if (is_lp5_family(p)) {
- if (p->frequency <= 1600)
- u1GatingAheadDQS_UI = 1 * u1MCK2CK_UI;
- else if (p->frequency == 1866)
- u1GatingAheadDQS_UI = 4;
- else
- u1GatingAheadDQS_UI = 8;
- } else
-#endif
u1GatingAheadDQS_UI = 5;
}
else
@@ -6332,14 +4789,6 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p,
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE);
-#if (__LP5_COMBO__)
- if (is_lp5_family(p)) {
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
- 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
- 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
- } else
-#endif
{
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
@@ -6859,14 +5308,6 @@ static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE);
-#if (__LP5_COMBO__)
- if (is_lp5_family(p)) {
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
- 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9),
- 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
- } else
-#endif
{
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9),
0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
@@ -7178,11 +5619,6 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p,
rxdqs_trans->dqs_lead[1], rxdqs_trans->dqs_lag[1],
rxdqs_trans->dqs_lead[0], rxdqs_trans->dqs_lag[0]));
-#if (__LP5_COMBO__)
- if((is_lp5_family(p)) && (vGet_Div_Mode(p) == DIV16_MODE))
- debug_pass_cnt = (GATING_GOLDEND_DQSCNT_LP5 >> 1);
- else
-#endif
debug_pass_cnt = GATING_GOLDEND_DQSCNT_LP5;
/* Decide the window center */
@@ -7320,30 +5756,12 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p,
else
dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32;
#else
- #if __LP5_COMBO__
- if((is_lp5_family(p)) && ((p->frequency == 2133) || (p->frequency == 2750)))
- dly_ui_start = 5;
- else
- #endif
dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF);//7; //12;ly_ui_start + 32;
#endif
dly_ui_end = dly_ui_start+ 32;
pass_byte_count = 0;
#else
- #if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- if (p->frequency == 1600)
- dly_ui_start = 7; //12;
- else
- dly_ui_start = 8; //12;
-
- dly_ui_end = dly_ui_start + 32;
- pass_byte_count = 0;
- }
- else
- #endif
{
dly_ui_start = 9; //12; Eddie change to 9 for Hynix Normal Mode
if(p->freq_sel==LP4_DDR4266)
@@ -7828,68 +6246,10 @@ void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p)
}
#endif
-#if __LP5_COMBO__
-static void vSetLP5DramRDDQC_DQandDMI(DRAMC_CTX_T *p, U8 eDQMode, U8 eDMIMode)
-{
- // Set DQ
- if (eDQMode == 0) // Invert
- u1MR20Value[p->dram_fsp] &= ~0x80;
- else // low-fixed
- u1MR20Value[p->dram_fsp] |= 0x80;
-
- // Set DMI
- if (eDMIMode == 0) // By pattern
- u1MR20Value[p->dram_fsp] &= ~0x40;
- else // low-fixed
- u1MR20Value[p->dram_fsp] |= 0x40;
-
- DramcModeRegWriteByRank(p, p->rank, 20, u1MR20Value[p->dram_fsp]);
-}
-
-static void vSetLP5Dram_WCKON_OnOff(DRAMC_CTX_T *p, U8 u1OnOff)
-{
- U8 rk;
- U8 backup_mrsrk;
-
- // Issue MR18 OP[4] to enable/disable WCK always ON mode
- if (u1OnOff == ON)
- u1MR18Value[p->dram_fsp] |= 0x10; // OP[4] WCK ON = 1
- else
- u1MR18Value[p->dram_fsp] &= 0xEF; // OP[4] WCK ON = 0
-
- backup_mrsrk = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0),
- SWCMD_CTRL0_MRSRK);
-
- //zj DramcModeRegWriteByRank(p, p->rank, 18, u1MR18Value[p->dram_fsp]);
- for (rk = RANK_0; rk < p->support_rank_num; rk++) {
- DramcModeRegWriteByRank(p, rk, 18, u1MR18Value[p->dram_fsp]);
- }
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), backup_mrsrk,
- SWCMD_CTRL0_MRSRK);
-}
-#endif
-
#if RDDQC_PINMUX_WORKAROUND
static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p)
{
U8 *uiLPDDR_RDDQC_Mapping;
-#if (__LP5_COMBO__)
- const U8 uiLPDDR5_RDDQC_Mapping_POP[CHANNEL_NUM][16] =
- {
- {
- 8, 9, 10, 11, 12, 15, 14, 13,
- 0, 1, 2, 3, 4, 7, 6, 5,
- },
- #if (CHANNEL_NUM>1)
- {
- 8, 9, 10, 11, 12, 15, 14, 13,
- 0, 1, 2, 3, 4, 7, 6, 5,
- },
- #endif
- };
-
-#endif
const U8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_NUM][16] =
{
{
@@ -8002,13 +6362,6 @@ static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p)
}
};
- #if (__LP5_COMBO__)
- if (is_lp5_family(p))
- {
- uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR5_RDDQC_Mapping_POP[p->channel];
- }
- else
- #endif
{
uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR4_RDDQC_Mapping_POP[p->DRAMPinmux][p->channel];
}
@@ -8071,16 +6424,6 @@ static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p)
#endif
// Set golden values into dram MR
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- DramcModeRegWriteByRank(p, p->rank, 31, RDDQC_Bit_Ctrl_Lower);
- DramcModeRegWriteByRank(p, p->rank, 32, RDDQC_Bit_Ctrl_Upper);
- DramcModeRegWriteByRank(p, p->rank, 33, RDDQC_Pattern_A);
- DramcModeRegWriteByRank(p, p->rank, 34, RDDQC_Pattern_B);
- }
- else
-#endif
{
DramcModeRegWriteByRank(p, p->rank, 15, RDDQC_Bit_Ctrl_Lower);
DramcModeRegWriteByRank(p, p->rank, 20, RDDQC_Bit_Ctrl_Upper);
@@ -8101,52 +6444,14 @@ static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8),
P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1));
-#if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- // Set function mode applied to DQ & DMI
-// U8 RDDQC_RDC_DQ_mode = 0;
-// U8 RDDQC_RDC_DMI_mode = 0;
-
-// vSetLP5DramRDDQC_DQandDMI(p, RDDQC_RDC_DQ_mode, RDDQC_RDC_DMI_mode);
-
-// vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN1),
-// P_Fld(RDDQC_RDC_DQ_mode, RDDQCGOLDEN1_LP5_MR20_7_GOLDEN) |
-// P_Fld(RDDQC_RDC_DMI_mode, RDDQCGOLDEN1_LP5_MR20_6_GOLDEN));
-
- if (is_heff_mode(p) == FALSE)
- {
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), 1, SHU_COMMON0_LP5WCKON);
-
- // Enable MR18 "WCK always ON mode"
- vSetLP5Dram_WCKON_OnOff(p, ON);
- }
-
- RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_FS);
- }
-#endif
return 0;
}
-#if 0
+#if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK
static U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p)
{
// Recover MPC Rank
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRSRK);
-#if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF);
-
- if (is_heff_mode(p) == FALSE)
- {
- // Disable MR18 "WCK always ON mode"
- vSetLP5Dram_WCKON_OnOff(p, OFF);
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0), 0, SHU_COMMON0_LP5WCKON);
- }
- }
-#endif
return 0;
}
#endif
@@ -8838,21 +7143,6 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT);
#endif
-
-#if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- // 1 step = 1/4 delay cell
- // Adjust step = 1/2/4(precision adjustment) by data-rate
- if (p->frequency <= GetFreqBySel(p,LP5_DDR3200))
- u16DelayStep = 4;
- else if (p->frequency <= GetFreqBySel(p,LP5_DDR4800)) // 3733, 4266, 4800
- u16DelayStep = 2;
- else // 5500, 6000, 6400
- u16DelayStep = 1;
- }
- else
-#endif
{
u16DelayStep = 4;
}
@@ -9328,13 +7618,6 @@ void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter
*pu1UILarge_DQ = (u2TmpValue >> u1Small_ui_to_large);
#endif
// calculate DQ OE according to DQ UI
- #if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- u2TmpValue -= TX_DQ_OE_SHIFT_LP5;
- }
- else
- #endif
{
u2TmpValue -= u1TxDQOEShift;
}
@@ -9468,14 +7751,6 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca
U16 u2TempVirtualDelay, u2SmallestVirtualDelay = 0xffff;
U16 u2DQDelayBegin = 0, u2DQDelayEnd = 0;
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK));
- u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI));
- }
- else
-#endif
{
u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0));
u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1));
@@ -9531,18 +7806,6 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca
}
#endif
- #if (__LP5_COMBO__)
- if (is_lp5_family(p)) {
- /* For DDR3200, +1.5 MCK */
- if (p->frequency == 1600)
- u2DQDelayBegin += (((1 << u1MCK2UI) + ((1 << u1MCK2UI) >> 1)) << u1UI2PI);
- else if (p->frequency == 2133)
- u2DQDelayBegin += ((1 << u1MCK2UI) << u1UI2PI);
- else if (p->frequency == 2750)
- u2DQDelayBegin += (9 << u1UI2PI);
- }
- #endif
-
#if TX_K_DQM_WITH_WDBI
if (calType == TX_DQ_DQS_MOVE_DQM_ONLY)
{
@@ -9683,21 +7946,12 @@ static void DramcTXSetVref(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefValue)
{
U8 u1TempOPValue;
-#ifdef __LP5_COMBO__
- if (is_lp5_family(p))
- u1TempOPValue = ((u1VrefValue & 0x7f));
- else
-#endif
u1TempOPValue = ((u1VrefValue & 0x3f) | (u1VrefRange << 6));
u1MR14Value[p->channel][p->rank][p->dram_fsp] = u1TempOPValue;
//For TX VREF of different byte
DramcModeRegWriteByRank(p, p->rank, 14, u1TempOPValue);
-#ifdef __LP5_COMBO__
- if (is_lp5_family(p))
- DramcModeRegWriteByRank(p, p->rank, 15, u1TempOPValue);
-#endif
#if CALIBRATION_SPEED_UP_DEBUG
mcSHOW_DBG_MSG2(("Yulia TX Vref : CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u1VrefRange, (u1VrefValue & 0x3f)));
@@ -9879,15 +8133,6 @@ static void Tx_Auto_K_Init(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), early_break, TX_ATK_SET1_TX_ATK_EARLY_BREAK); //Enable early break
#endif
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0),
- P_Fld(0x5, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) |
- P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN)); //Enable OE auto adjust
- }
- else
-#endif
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0),
P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) |
@@ -10218,10 +8463,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
u2DQDelayStep = 2;
else
u2DQDelayStep = 1;
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- u2DQDelayStep = 4; /* To speed up simulation */
-#endif
+
#if (FOR_DV_SIMULATION_USED == 1)
u2DQDelayStep = (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) ? 16 : 8;
#endif
@@ -11258,14 +9500,6 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p)
DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
//restore Vref
- #if __LP5_COMBO__
- if (is_lp5_family(p))
- {
- u2VrefRange = 0;
- u2VrefLevel = backup_u1MR14Value;
- }
- else
- #endif
{
u2VrefRange = backup_u1MR14Value>>6;
u2VrefLevel = backup_u1MR14Value & 0x3f;
@@ -12630,11 +10864,7 @@ DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_regi
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), P_Fld(0, MISC_IMPCAL_IMPCAL_CALI_ENN) | P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDP) | \
P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDN)); //RG_RIMP_BIAS_EN and RG_RIMP_VREF_EN move to IMPPDP and IMPPDN
-#if __LP5_COMBO__
- if (is_lp5_family(p))
- u1DDR4 = 0;
- else //LPDDR4
-#endif
+
u1DDR4 = 1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), P_Fld(1, MISC_IMP_CTRL1_RG_IMP_EN) | \
@@ -12896,34 +11126,6 @@ static void DQSDutyScan_SetDqsDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay)
}
}
-#if __LP5_COMBO__
-static void WCKDutyScan_SetWCKDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay)
-{
- U8 u1ShuffleIdx = 0, u1DQSIdx, u1RankIdx = 0;
- U32 save_offset;
- U8 tDelay[2];
-
- for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++)
- {
- DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx]));
- }
-
-#if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ
- for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
-#endif
- {
- {
- for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++)
- {
- save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET;
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset,
- P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0));
- }
- }
- }
-}
-#endif
-
#if APPLY_DQDQM_DUTY_CALIBRATION
static void DQDQMDutyScan_SetDQDQMDelayCell(DRAMC_CTX_T *p, U8 u1ChannelIdx, S8 *scDutyDelay, U8 k_type)
{
@@ -13057,9 +11259,6 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p)
DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
- #if __LP5_COMBO__
- WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]);
- #endif
#if APPLY_DQDQM_DUTY_CALIBRATION
DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index 501f9d3785..02ba357664 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -2337,27 +2337,6 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args
#endif // (SIMULATION_RX_RDDQC == 1)
-#if (__LP5_COMBO__ == TRUE)
-#if (SIMULATION_DUTY_CYC_MONITOR == 1)
- if (is_lp5_family(DramConfig) && DramConfig->frequency >= GetFreqBySel(DramConfig,LP5_DDR4266))
- {
- if (!psra) {
- mcSHOW_DBG_MSG6(("\n----->DramcDutyCycleMonitor begin...\n"));
- timestamp_show();
- DramcDutyCycleMonitor(DramConfig);
- timestamp_show();
- mcSHOW_DBG_MSG6(("DramcDutyCycleMonitor end<-----\n\n"));
-
- mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(DLY) begin...\n"));
- timestamp_show();
- DramcWriteLeveling(DramConfig, psra->wl_autok, DLY_BASED);
- timestamp_show();
- mcSHOW_DBG_MSG6(("DramcWriteLeveling(DLY)end<-----\n\n"));
- }
- }
-#endif /* (SIMULATION_DUTY_CYC_MONITOR == 1) */
-#endif // (__LP5_COMBO__ == TRUE)
-
#if (SIMULATION_TX_PERBIT == 1)
if (!psra || psra->tx_perbit) {
mcSHOW_DBG_MSG6(("\n----->DramcTxWindowPerbitCal begin...\n"));
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
index 3880f9a79a..63384cf4f8 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
@@ -47,35 +47,6 @@ u8 is_heff_mode(DRAMC_CTX_T *p)
return res? TRUE: FALSE;
}
-#if __LP5_COMBO__
-static u8 lp5heff;
-
-u8 lp5heff_save_disable(DRAMC_CTX_T *p)
-{
- /* save it */
- lp5heff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
- SHU_COMMON0_LP5HEFF_MODE);
-
- /* disable it */
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
- P_Fld(0, SHU_COMMON0_LP5HEFF_MODE));
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG),
- 0, RKCFG_CKE2RANK);
-
-
- return lp5heff;
-}
-
-void lp5heff_restore(DRAMC_CTX_T *p)
-{
- /* restore it */
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
- P_Fld(lp5heff, SHU_COMMON0_LP5HEFF_MODE));
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG),
- lp5heff, RKCFG_CKE2RANK);
-}
-#endif
-
#if FOR_DV_SIMULATION_USED
U8 u1BroadcastOnOff = 0;
#endif
@@ -290,11 +261,6 @@ void vSetRankNumber(DRAMC_CTX_T *p)
void vSetFSPNumber(DRAMC_CTX_T *p)
{
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- p->support_fsp_num = 3;
- else
-#endif
p->support_fsp_num = 2;
}
@@ -304,60 +270,7 @@ static void setFreqGroup(DRAMC_CTX_T *p)
/* Below listed conditions represent freqs that exist in ACTimingTable
* -> Should cover freqGroup settings for all real freq values
*/
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- if (p->frequency <= 400) // DDR800
- {
- p->freqGroup = 400;
- }
- else if (p->frequency <= 600) // DDR1200
- {
- p->freqGroup = 600;
- }
- else if (p->frequency <= 800) // DDR1600
- {
- p->freqGroup = 800;
- }
- else if (p->frequency <= 933) //DDR1866
- {
- p->freqGroup = 933;
- }
- else if (p->frequency <= 1200) //DDR2400, DDR2280
- {
- p->freqGroup = 1200;
- }
- else if (p->frequency <= 1600) // DDR3200
- {
- p->freqGroup = 1600;
- }
- else if (p->frequency <= 1866) // DDR3733
- {
- p->freqGroup = 1866;
- }
- else if (p->frequency <= 2133) // DDR4266
- {
- p->freqGroup = 2133;
- }
- else if (p->frequency <= 2400) // DDR4800
- {
- p->freqGroup = 2400;
- }
- else if (p->frequency <= 2750) // DDR5500
- {
- p->freqGroup = 2750;
- }
- else if (p->frequency <= 3000) // DDR6000
- {
- p->freqGroup = 3000;
- }
- else // DDR6600
- {
- p->freqGroup = 3300;
- }
- }
- else
-#endif
+
{
if (p->frequency <= 200) // DDR400
{
@@ -719,20 +632,7 @@ void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
{
p->freq_sel = sel;
p->frequency = GetFreqBySel(p, sel);
-#if __LP5_COMBO__
- if(is_lp5_family(p))
- {
- ///TODO: Dennis
- //p->dram_fsp = (p->frequency < LP5_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
- p->dram_fsp = FSP_0;
- #if LP5_DDR4266_RDBI_WORKAROUND
- if(p->frequency >= 2133)
- p->DBI_R_onoff[FSP_0] = DBI_ON;
- #endif
- p->odt_onoff = (p->frequency < LP5_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
- }
- else
-#endif
+
{
p->dram_fsp = (p->frequency < LP4_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
p->odt_onoff = (p->frequency < LP4_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
@@ -1370,15 +1270,6 @@ DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1Te
P_Fld(test2_1 >> 24, TEST2_A0_TEST2_PAT0) |
P_Fld(test2_2 >> 24, TEST2_A0_TEST2_PAT1));
-#if (__LP5_COMBO__ == TRUE)
- if (TRUE == is_lp5_family(p))
- {
- // LP5 TA2 base: 0x0
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
- test2_1 & 0x00ffffff, RK_TEST2_A1_TEST2_BASE);
- }
- else
-#endif
{
// LP4 TA2 base: 0x10000. It's only TBA constrain, but not HW.
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
@@ -1984,32 +1875,6 @@ U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank)
u1Fsp = FSP_0;
-#if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- switch (u1MRIdx)
- {
- case 1:
- case 2:
- case 3:
- case 10:
- case 11:
- case 12:
- case 14:
- case 15:
- case 17:
- case 18:
- case 19:
- case 20:
- case 24:
- case 30:
- case 41:
- u1Fsp = gFSPWR_Flag[u1Rank];
- break;
- }
- }
- else
-#endif
{
switch (u1MRIdx)
{
@@ -2392,17 +2257,6 @@ void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
1, SWCMD_EN_RTMRWEN);
-#if __LP5_COMBO__
-#if WORKAROUND_LP5_HEFF
- if (is_heff_mode(p))
- {
- mcDELAY_US(1);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- 1, CKECTRL_CKE2RANK_OPT6);
- }
-#endif
-#endif
-
u4TimeCnt = TIME_OUT_CNT;
do {
@@ -2417,81 +2271,10 @@ void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *
mcSHOW_ERR_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0]));
}
-#if __LP5_COMBO__
-#if WORKAROUND_LP5_HEFF
- if (is_heff_mode(p))
- {
- mcDELAY_US(1);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- 0, CKECTRL_CKE2RANK_OPT6);
- }
-#endif
-#endif
-
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
0, SWCMD_EN_RTMRWEN);
}
-#if 0
-static void DramcModeRegWriteByRank_RTSWCMD_MRW(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
-{
- U32 u4Response, u4TimeCnt;
-
- vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
- P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
- P_Fld(u1Rank, SWCMD_CTRL2_RTSWCMD_RK) |
- P_Fld(u1MRIdx, SWCMD_CTRL2_RTSWCMD_MA) |
- P_Fld(u1Value, SWCMD_CTRL2_RTSWCMD_OP));
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
- 1, MPC_CTRL_RTSWCMD_HPRI_EN);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT),
- 0x2a, RTSWCMD_CNT_RTSWCMD_CNT);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
- 4, SWCMD_EN_RTSWCMD_SEL);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
- 1, SWCMD_EN_RTSWCMDEN);
-
-#if __LP5_COMBO__
-#if WORKAROUND_LP5_HEFF
- if (is_heff_mode(p))
- {
- mcDELAY_US(1);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- 1, CKECTRL_CKE2RANK_OPT6);
- }
-#endif
-#endif
-
- u4TimeCnt = TIME_OUT_CNT;
-
- do {
- u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3),
- SPCMDRESP3_RTSWCMD_RESPONSE);
- u4TimeCnt--;
- mcDELAY_US(5);
- } while ((u4Response == 0) && (u4TimeCnt > 0));
- if (u4TimeCnt == 0)//time out
- {
- mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank, u1MRIdx, u1Value));
- }
-
-#if __LP5_COMBO__
-#if WORKAROUND_LP5_HEFF
- if (is_heff_mode(p))
- {
- mcDELAY_US(1);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
- 0, CKECTRL_CKE2RANK_OPT6);
- }
-#endif
-#endif
-
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
- 0, SWCMD_EN_RTSWCMDEN);
- vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
- 0, MPC_CTRL_RTSWCMD_HPRI_EN);
-}
-#endif
static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
{
U32 counter = 0;
@@ -2548,17 +2331,6 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
else
#endif
{
- #if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- #if ENABLE_RUNTIME_MRW_FOR_LP5
- DramcModeRegWriteByRank_RTMRW(p, &u1Rank, &u1MRIdx, &u1Value, 1);
- #else
- DramcModeRegWriteByRank_RTSWCMD_MRW(p, u1Rank, u1MRIdx, u1Value);
- #endif
- }
- else
- #endif
{
DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value);
}
@@ -2583,11 +2355,6 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
u1RankStart = u1Rank;
}
- #if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- u1FSPMRIdx=16;
- else
- #endif
u1FSPMRIdx=13;
for (u1RankIdx=u1RankStart;u1RankIdx<u1RankStart+u1RankNum;u1RankIdx++)
@@ -2620,14 +2387,6 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
mcSHOW_MRW_MSG((" [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL")));
#endif
- #if (__LP5_COMBO__ == TRUE)
- if (is_lp5_family(p))
- {
- if (u1MRIdx==u1FSPMRIdx)
- gFSPWR_Flag[u1RankIdx] = u1Value & 0x3;
- }
- else
- #endif
{
if (u1MRIdx==u1FSPMRIdx)
gFSPWR_Flag[u1RankIdx] = (u1Value>> 6) & 0x1;
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h b/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h
index 2e82326d36..0e3966daf2 100644
--- a/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_actiming.h
@@ -122,49 +122,7 @@ typedef enum
AC_TIMING_NUMBER_LP4
} AC_TIMING_LP4_COUNT_TYPE_T;
-#if (__LP5_COMBO__)
-/* Used to keep track the total number of LP5 ACTimings */
-typedef enum
-{
-#if SUPPORT_LP5_DDR6400_ACTIM
-#if ENABLE_READ_DBI
- AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0,
- AC_TIME_LP5_NORM_DDR6400_RDBI_ON,
-#else //(ENABLE_READ_DBI == 0)
- AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF,
- AC_TIME_LP5_NORM_DDR6400_RDBI_OFF,
-#endif //ENABLE_READ_DBI
-#endif
-
-#if SUPPORT_LP5_DDR5500_ACTIM
-#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
- AC_TIME_LP5_BYTE_DDR5500_RDBI_ON,
- AC_TIME_LP5_NORM_DDR5500_RDBI_ON,
-#else
- AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF,
- AC_TIME_LP5_NORM_DDR5500_RDBI_OFF,
-#endif
-#endif
-
-#if SUPPORT_LP5_DDR4266_ACTIM
-#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
- AC_TIME_LP5_BYTE_DDR4266_RDBI_ON,
- AC_TIME_LP5_NORM_DDR4266_RDBI_ON,
-#else //(ENABLE_READ_DBI == 0)
- AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF,
- AC_TIME_LP5_NORM_DDR4266_RDBI_OFF,
-#endif //ENABLE_READ_DBI
-#endif
-
-#if SUPPORT_LP5_DDR3200_ACTIM
- AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF,
- AC_TIME_LP5_NORM_DDR3200_RDBI_OFF,
-#endif
- AC_TIMING_NUMBER_LP5
-} AC_TIMING_LP5_COUNT_TYPE_T;
-#else
#define AC_TIMING_NUMBER_LP5 0
-#endif
/* ACTiming struct declaration (declared here due Fld_wid for each register type)
* Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg()
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h b/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h
index b228130b7f..c3585852eb 100644
--- a/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h
@@ -323,9 +323,6 @@ extern void get_top_configuration_from_DV_random(DV_new_config_T * tr);
extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr);
extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra);
extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr);
-#if __LP5_COMBO__
-extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr);
-#endif
extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate);
extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs);
extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 04:49:05 +0000