diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-10-06 20:26:58 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-10-08 03:41:37 +0000 |
| commit | 1259da13e37434a3a6d606a7dd55d4b23c8063a8 (patch) | |
| tree | 70cbd2d29c38c020d9c74b7ae6750115574cf659 /src/vendorcode/mediatek | |
| parent | dc9abea4fc3f2b0028e083817b4b148596c6e744 (diff) | |
vc/mediatek/mt8195: fix misleading-indentation error
Fix misleading-indentation error in dramc_pi_calibration_api.c.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode/mediatek')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index a95546b554..e73e6e5358 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -1040,11 +1040,11 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) // VREF_UNTERM_EN vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF), 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); if (!isLP4_DSC) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF), 1, SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA); - u1VrefSel = 0x37;//unterm LP4 + u1VrefSel = 0x37;//unterm LP4 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | |