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author | Johnny Lin <johnny_lin@wiwynn.com> | 2022-06-13 14:05:43 +0800 |
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committer | David Hendricks <david.hendricks@gmail.com> | 2023-01-29 18:40:34 +0000 |
commit | 55bc2d3e1491017e5640153fe7b7992a20a1a76d (patch) | |
tree | f54563f65c33101e0f319fcc3a7f11cc4fadc4e8 /src/vendorcode/intel | |
parent | 7a7cdf8efbd93f3fa935b0386ad5529c8d6d4960 (diff) |
drivers/intel/fsp2_0: Add saving MRC data after FSP-S option
When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training
data after FSP-S instead of FSP-M. For now only SPR-SP server
FSP supports this.
This issue surfaces with SPR-SP, because of the memory type
(DDR5 support) and memory capacity (more memory controllers, bigger
DRAM capacity). Therefore Intel decided to save MRC training data after
FSP-S with SPR-SP FSP.
Change-Id: I3bab0c5004e717e842b484c89187e8c0b9c2b3eb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71950
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel')
0 files changed, 0 insertions, 0 deletions