diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-03-06 14:45:51 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 08:07:21 +0000 |
| commit | 7b6a82dc1a6ca7157ba95793ae03afc542cff42f (patch) | |
| tree | 4ecf4d575a209acfd931b1f632a3f001843d8066 /src/vendorcode/intel | |
| parent | b3bfb2a1a7ffc190dc37905b073da8d1d3b054ba (diff) | |
vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform
version 2457.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 24cbd6e9ef..8ab5878f83 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -635,7 +635,18 @@ typedef struct { /** Offset 0x091A - Reserved **/ - UINT8 Reserved33[438]; + UINT8 Reserved33[3]; + +/** Offset 0x091D - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x091E - Reserved +**/ + UINT8 Reserved34[434]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -643,7 +654,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved34[101]; + UINT8 Reserved35[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -661,7 +672,7 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved35[264]; + UINT8 Reserved36[264]; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -675,7 +686,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved36[269]; + UINT8 Reserved37[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -683,7 +694,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved37[80]; + UINT8 Reserved38[80]; } FSP_S_CONFIG; /** Fsp S UPD Configuration |