diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-08-28 13:13:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:31:16 +0000 |
| commit | 6727276a659968b509b79bf559dc25a71305bc6e (patch) | |
| tree | a6f774c0c5906f4bb2a54a7a50088621502bcd35 /src/vendorcode/intel | |
| parent | aab188174f7fa349ef395ecb38a41d5b6cf45e92 (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333
Update FSP headers for Tiger Lake platform generated based FSP
version 3333. Previous version was 3313.
Changes Include:
1. Update comments
2. Add new UPD for Gpio Override support
BUG=b:166790597
BRANCH=none
TEST=build and boot volteer proto2
Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 15 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 4 |
2 files changed, 15 insertions, 4 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 32b6a327b5..0b3fe7d64c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2487,7 +2487,18 @@ typedef struct { /** Offset 0x089F - Reserved **/ - UINT8 Reserved44[129]; + UINT8 Reserved44[124]; + +/** Offset 0x091B - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level + 2 - skips GpioSetNativePadByFunction and GpioSetPadMode +**/ + UINT8 GpioOverride; + +/** Offset 0x091C - Reserved +**/ + UINT8 Reserved45[4]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2508,7 +2519,7 @@ typedef struct { /** Offset 0x0920 **/ - UINT8 UnusedUpdSpace26[6]; + UINT8 UnusedUpdSpace25[6]; /** Offset 0x0926 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index b0d9ca9f80..315a0a7a8c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -828,8 +828,8 @@ typedef struct { **/ UINT8 AmtKvmEnabled; -/** Offset 0x040E - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. +/** Offset 0x040E - Force MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. $EN_DIS **/ UINT8 ForcMebxSyncUp; |