diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-03-16 15:28:06 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-03-17 07:44:07 +0000 |
| commit | 9a035ede17a23127ec4fc451ab84283e79636e75 (patch) | |
| tree | 314591a9da7ba307a502a8b264a37e5f852e4d6f /src/vendorcode/intel | |
| parent | 0533867a08cd587eb075e01290c788235d44be3f (diff) | |
vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064
This patch updates the Memory Hob Info data structure as per FSP
v3064 source code change.
BUG=b:273894357
TEST=Able to see `smbios type 17` table while booting google/rex.
Without this patch:
[DEBUG] 0 DIMM found
With this patch:
[DEBUG] 8 DIMM found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h index 804644180d..e980f9ac56 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h @@ -192,6 +192,7 @@ typedef struct { UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. } MRC_CH_TIMING; typedef struct { |