aboutsummaryrefslogtreecommitdiff
path: root/src/vendorcode/intel/fsp
diff options
context:
space:
mode:
authorEdward O'Callaghan <quasisec@google.com>2020-02-21 16:08:04 +1100
committerEdward O'Callaghan <quasisec@chromium.org>2020-02-28 03:28:30 +0000
commitfa043c4e9d8ee07aba02eb9c7bdbe41e4848f5a9 (patch)
tree9198da9d5c3006256a53e22be84662851b3f5969 /src/vendorcode/intel/fsp
parentd51665600e0ddbd4e1ae7144e29d179287ec285f (diff)
soc/intel/cannonlake: Plumb TetonGlacierMode into dt
The following plumbs through the enabling of Intel's TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives to be accessable via devicetree. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp')
0 files changed, 0 insertions, 0 deletions