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| author | John Su <john_su@compal.corp-partner.google.com> | 2018-10-16 14:50:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-24 09:57:58 +0000 |
| commit | 75a7862c472e5a38d4c767f67ffbb669122a3054 (patch) | |
| tree | f1f394af32f686f4ac4ba49f4678869e77b84d5a /src/vendorcode/intel/fsp | |
| parent | 6d2f7d24efc22b055d15f430f4c595d812eeb6a5 (diff) | |
mb/google/octopus/variants/fleex: Update DPTF parameters
1. Update PSV values for cpu and sensers.
2. Change PL1 min value from 3w to 4.5w.
3. Change TSR2 TRT source from charger to CPU.
Refer to 112448519#comment31.
BUG=b:112448519
TEST=Build coreboot for Octopus board
Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/vendorcode/intel/fsp')
0 files changed, 0 insertions, 0 deletions