diff options
| author | Derek Huang <derek.huang@intel.corp-partner.google.com> | 2021-01-27 17:01:00 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-03 20:11:06 +0000 |
| commit | ed6bda2818a8ce79a36f9e5a2e30f1be6299724a (patch) | |
| tree | 41d88e803d52ea6d0b50339a2cccf06d14b05d81 /src/vendorcode/intel/fsp | |
| parent | e65e9dd6b12255b94547fa8aeb2195def0bfb76b (diff) | |
soc/intel/tgl: Add configurable value for ConfigTdpLevel
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level
Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 35cc43bcbb..909ba36708 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -1304,9 +1304,14 @@ typedef struct { **/ UINT8 IsTPMPresence; -/** Offset 0x0389 - Reserved +/** Offset 0x0389 - ConfigTdpLevel + Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ - UINT8 Reserved17[6]; + UINT8 ConfigTdpLevel; + +/** Offset 0x038A - Reserved +**/ + UINT8 Reserved17[5]; /** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. |