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author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-07-10 12:43:26 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 15:01:02 +0000 |
commit | 3e52d7955f8741e4645d183e20f648d4523eb4c6 (patch) | |
tree | 33c99996b6b2fd491d9182c563c9804df692c5b5 /src/vendorcode/intel/fsp | |
parent | ce3c77c30536649ba2a6ab81979a7fa371128c31 (diff) |
mb/ibm/sbp1: Disable SIO Uarts
Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.
TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.
Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/vendorcode/intel/fsp')
0 files changed, 0 insertions, 0 deletions