diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:37:28 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:45 +0000 |
| commit | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (patch) | |
| tree | 042e376cee473f72f143ed76768f50536ab323ef /src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h | |
| parent | 298619f6d9adde49b4279c906b0d20a41f919a61 (diff) | |
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h')
| -rw-r--r-- | src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h deleted file mode 100644 index 16cddf073d..0000000000 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h +++ /dev/null @@ -1,54 +0,0 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef __PI_BOOT_MODE_H__ -#define __PI_BOOT_MODE_H__ - -/// -/// EFI boot mode -/// -typedef UINT32 EFI_BOOT_MODE; - -// -// 0x21 - 0xf..f are reserved. -// -#define BOOT_WITH_FULL_CONFIGURATION 0x00 -#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 -#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 -#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 -#define BOOT_WITH_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 - -#endif |