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| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2020-09-03 06:40:46 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:30:08 +0000 |
| commit | 9440c5356762b94c019d2399d6cddbd61fba96c9 (patch) | |
| tree | d9239a6a642c0144929238afaa9b5cdd39e235fb /src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | |
| parent | 70a2ddc5ac6c8f7d49b9bc2075373772286faf7b (diff) | |
soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table
1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c
2. Add additional EHL SA DID in pci_ids.h
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h')
0 files changed, 0 insertions, 0 deletions