vendor/intel/skykabylake: Update FSP header files to version 2.9.2

There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to
configure clock source(s) of PCIe Root Ports. This UPD is used
to disable clock source(s) of disabled PCIe Root Port which
has active device connected.

CQ-DEPEND=CL:*520658,CL:*520659
BUG=b:
BRANCH=None
TEST= Build and boot soraka

Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/22692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

1 files changed, 9 insertions, 2 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index f4f4badf47..0209245151 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -451,9 +451,16 @@ typedef struct {
 **/
   UINT8                       AmtSolEnabled;
 
-/** Offset 0x015D
+/** Offset 0x015D - Configure CLKSRC Number
+  Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid
+  clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for
+  port1, byte1 for port2, and so on.
 **/
-  UINT8                       UnusedUpdSpace6[163];
+  UINT8                       PcieRpClkSrcNumber[24];
+
+/** Offset 0x0175
+**/
+  UINT8                       UnusedUpdSpace6[139];
 
 /** Offset 0x0200 - Subsystem Vendor ID for SA devices
   Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086