vendor/intel/skykabylake: Update FSP header files to version 2.7.2

Update FSP header files to version 2.7.2.

New UPDs added
	FspmUpd.h:
	 *CleanMemory

	FspsUpd.h:
	 *IslVrCmd
	 *ThreeStrikeCounterDisable

Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.

CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.

Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 30 insertions, 15 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index b3c7698857..f4f4badf47 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -167,7 +167,7 @@ typedef struct {
 
 /** Offset 0x0036 - Flash Configuration Lock Down
   Enable/disable flash lock down. If platform decides to skip this programming, it
-  must lock SPI flash register before end of post.
+  must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
   $EN_DIS
 **/
   UINT8                       SpiFlashCfgLockDown;
@@ -484,7 +484,7 @@ typedef struct {
 
 /** Offset 0x020C - PCIe DeEmphasis control per root port
   0: -6dB, 1(Default): -3.5dB
-  0:Disable, 2:L1
+  0:-6dB, 1:-3.5dB
 **/
   UINT8                       PegDeEmphasis[3];
 
@@ -2060,9 +2060,15 @@ typedef struct {
 **/
   UINT8                       MeUnconfigIsValid;
 
-/** Offset 0x077A
+/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.
+  Intersil VR mailbox command. <b>0 - no mailbox command sent.</b>  1 - VR mailbox
+  command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
+**/
+  UINT8                       IslVrCmd;
+
+/** Offset 0x077B
 **/
-  UINT8                       ReservedFspsUpd[6];
+  UINT8                       ReservedFspsUpd[5];
 } FSP_S_CONFIG;
 
 /** Fsp S Test Configuration
@@ -2107,7 +2113,7 @@ typedef struct {
   UINT8                       DmiIot;
 
 /** Offset 0x0789 - PEG Max Payload size per root port
-  0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B
+  0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
   0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
 **/
   UINT8                       PegMaxPayload[3];
@@ -2520,25 +2526,25 @@ typedef struct {
 /** Offset 0x07DA - Enable or Disable Package C-State Demotion
   Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b>
   (Auto: Enabled for Skylake; Disabled for Kabylake)
-  $EN_DIS
+  0:Disable, 1:Enable, 2:Auto
 **/
   UINT8                       PkgCStateDemotion;
 
 /** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
   Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b>
   (Auto: Enabled for Skylake; Disabled for Kabylake)
-  $EN_DIS
+  0:Disable, 1:Enable, 2:Auto
 **/
   UINT8                       PkgCStateUnDemotion;
 
 /** Offset 0x07DC - Enable or Disable CState-Pre wake
-  Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
+  Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
   $EN_DIS
 **/
   UINT8                       CStatePreWake;
 
 /** Offset 0x07DD - Enable or Disable TimedMwait Support.
-  Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
+  Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
   $EN_DIS
 **/
   UINT8                       TimedMwait;
@@ -2606,7 +2612,7 @@ typedef struct {
 
 /** Offset 0x07E8 - Configuration for boot TDP selection
   Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
-  Up;0xFF : Deactivate
+  Up; 0xFF: Deactivate
   0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate
 **/
   UINT8                       ConfigTdpLevel;
@@ -2632,12 +2638,14 @@ typedef struct {
   UINT16                      StateRatio[40];
 
 /** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
-  Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF
+  Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF,
+  Default is 0x4E, Server Platform is 0x4B
 **/
   UINT16                      CstateLatencyControl0Irtl;
 
 /** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
-  Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
+  Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF,
+  Default is 0x76, Server Platform is 0x6B
 **/
   UINT16                      CstateLatencyControl1Irtl;
 
@@ -2783,11 +2791,18 @@ typedef struct {
 **/
   UINT8                       EightCoreRatioLimit;
 
-/** Offset 0x0888 - ReservedCpuPostMemTest
+/** Offset 0x0888 - Set Three Strike Counter Disable
+  False (default): Three Strike counter will be incremented and True: Prevents Three
+  Strike counter from incrementing; <b>0: False</b>; 1: True.
+  0: False, 1: True
+**/
+  UINT8                       ThreeStrikeCounterDisable;
+
+/** Offset 0x0889 - ReservedCpuPostMemTest
   Reserved for CPU Post-Mem Test
   $EN_DIS
 **/
-  UINT8                       ReservedCpuPostMemTest[2];
+  UINT8                       ReservedCpuPostMemTest[1];
 
 /** Offset 0x088A - SgxSinitDataFromTpm
   SgxSinitDataFromTpm default values
@@ -2923,7 +2938,7 @@ typedef struct {
   UINT8                       PchPmDisableEnergyReport;
 
 /** Offset 0x0A2F - PCH Pm Pmc Read Disable
-  When set to true, this bit disallows host reads to PMC XRAM.
+  Deprecated
   $EN_DIS
 **/
   UINT8                       PchPmPmcReadDisable;