vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release

Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter,
and adds some fields to HOBs.

Update FspmUpd.h and HOB header files.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
index 1229f1b427..7baa11a480 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
@@ -124,7 +124,7 @@ struct ChannelDevice {
 };
 
 typedef struct socket {
-	UINT8    reserved1[1110];
+	UINT8    reserved1[1114];
 	struct   ChannelDevice ChannelInfo[MAX_CH];
 } MEMMAP_SOCKET;
 
@@ -154,7 +154,7 @@ typedef struct SystemMemoryMapHob {
 
   UINT32   MmiohBase;                                   // MMIOH base in 64MB granularity
 
-  UINT8    reserved6[4];
+  UINT8    reserved6[5];
 
 } SYSTEM_MEMORY_MAP_HOB;